1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/Analysis/TargetTransformInfo.h"
11 #include "llvm/Analysis/TargetTransformInfoImpl.h"
12 #include "llvm/IR/CallSite.h"
13 #include "llvm/IR/DataLayout.h"
14 #include "llvm/IR/Instruction.h"
15 #include "llvm/IR/Instructions.h"
16 #include "llvm/IR/IntrinsicInst.h"
17 #include "llvm/IR/Module.h"
18 #include "llvm/IR/Operator.h"
19 #include "llvm/IR/PatternMatch.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <utility>
23 
24 using namespace llvm;
25 using namespace PatternMatch;
26 
27 #define DEBUG_TYPE "tti"
28 
29 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
30                                      cl::Hidden,
31                                      cl::desc("Recognize reduction patterns."));
32 
33 namespace {
34 /// No-op implementation of the TTI interface using the utility base
35 /// classes.
36 ///
37 /// This is used when no target specific information is available.
38 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
39   explicit NoTTIImpl(const DataLayout &DL)
40       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
41 };
42 }
43 
44 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
45     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
46 
47 TargetTransformInfo::~TargetTransformInfo() {}
48 
49 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
50     : TTIImpl(std::move(Arg.TTIImpl)) {}
51 
52 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
53   TTIImpl = std::move(RHS.TTIImpl);
54   return *this;
55 }
56 
57 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
58                                           Type *OpTy) const {
59   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
60   assert(Cost >= 0 && "TTI should not produce negative costs!");
61   return Cost;
62 }
63 
64 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs) const {
65   int Cost = TTIImpl->getCallCost(FTy, NumArgs);
66   assert(Cost >= 0 && "TTI should not produce negative costs!");
67   return Cost;
68 }
69 
70 int TargetTransformInfo::getCallCost(const Function *F,
71                                      ArrayRef<const Value *> Arguments) const {
72   int Cost = TTIImpl->getCallCost(F, Arguments);
73   assert(Cost >= 0 && "TTI should not produce negative costs!");
74   return Cost;
75 }
76 
77 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
78   return TTIImpl->getInliningThresholdMultiplier();
79 }
80 
81 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
82                                     ArrayRef<const Value *> Operands) const {
83   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
84 }
85 
86 int TargetTransformInfo::getExtCost(const Instruction *I,
87                                     const Value *Src) const {
88   return TTIImpl->getExtCost(I, Src);
89 }
90 
91 int TargetTransformInfo::getIntrinsicCost(
92     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments) const {
93   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments);
94   assert(Cost >= 0 && "TTI should not produce negative costs!");
95   return Cost;
96 }
97 
98 unsigned
99 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
100                                                       unsigned &JTSize) const {
101   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
102 }
103 
104 int TargetTransformInfo::getUserCost(const User *U,
105     ArrayRef<const Value *> Operands) const {
106   int Cost = TTIImpl->getUserCost(U, Operands);
107   assert(Cost >= 0 && "TTI should not produce negative costs!");
108   return Cost;
109 }
110 
111 bool TargetTransformInfo::hasBranchDivergence() const {
112   return TTIImpl->hasBranchDivergence();
113 }
114 
115 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
116   return TTIImpl->isSourceOfDivergence(V);
117 }
118 
119 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
120   return TTIImpl->isAlwaysUniform(V);
121 }
122 
123 unsigned TargetTransformInfo::getFlatAddressSpace() const {
124   return TTIImpl->getFlatAddressSpace();
125 }
126 
127 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
128   return TTIImpl->isLoweredToCall(F);
129 }
130 
131 void TargetTransformInfo::getUnrollingPreferences(
132     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
133   return TTIImpl->getUnrollingPreferences(L, SE, UP);
134 }
135 
136 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
137   return TTIImpl->isLegalAddImmediate(Imm);
138 }
139 
140 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
141   return TTIImpl->isLegalICmpImmediate(Imm);
142 }
143 
144 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
145                                                 int64_t BaseOffset,
146                                                 bool HasBaseReg,
147                                                 int64_t Scale,
148                                                 unsigned AddrSpace,
149                                                 Instruction *I) const {
150   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
151                                         Scale, AddrSpace, I);
152 }
153 
154 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
155   return TTIImpl->isLSRCostLess(C1, C2);
156 }
157 
158 bool TargetTransformInfo::canMacroFuseCmp() const {
159   return TTIImpl->canMacroFuseCmp();
160 }
161 
162 bool TargetTransformInfo::shouldFavorPostInc() const {
163   return TTIImpl->shouldFavorPostInc();
164 }
165 
166 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
167   return TTIImpl->isLegalMaskedStore(DataType);
168 }
169 
170 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
171   return TTIImpl->isLegalMaskedLoad(DataType);
172 }
173 
174 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
175   return TTIImpl->isLegalMaskedGather(DataType);
176 }
177 
178 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
179   return TTIImpl->isLegalMaskedScatter(DataType);
180 }
181 
182 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
183   return TTIImpl->hasDivRemOp(DataType, IsSigned);
184 }
185 
186 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
187                                              unsigned AddrSpace) const {
188   return TTIImpl->hasVolatileVariant(I, AddrSpace);
189 }
190 
191 bool TargetTransformInfo::prefersVectorizedAddressing() const {
192   return TTIImpl->prefersVectorizedAddressing();
193 }
194 
195 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
196                                               int64_t BaseOffset,
197                                               bool HasBaseReg,
198                                               int64_t Scale,
199                                               unsigned AddrSpace) const {
200   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
201                                            Scale, AddrSpace);
202   assert(Cost >= 0 && "TTI should not produce negative costs!");
203   return Cost;
204 }
205 
206 bool TargetTransformInfo::LSRWithInstrQueries() const {
207   return TTIImpl->LSRWithInstrQueries();
208 }
209 
210 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
211   return TTIImpl->isTruncateFree(Ty1, Ty2);
212 }
213 
214 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
215   return TTIImpl->isProfitableToHoist(I);
216 }
217 
218 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
219 
220 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
221   return TTIImpl->isTypeLegal(Ty);
222 }
223 
224 unsigned TargetTransformInfo::getJumpBufAlignment() const {
225   return TTIImpl->getJumpBufAlignment();
226 }
227 
228 unsigned TargetTransformInfo::getJumpBufSize() const {
229   return TTIImpl->getJumpBufSize();
230 }
231 
232 bool TargetTransformInfo::shouldBuildLookupTables() const {
233   return TTIImpl->shouldBuildLookupTables();
234 }
235 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
236   return TTIImpl->shouldBuildLookupTablesForConstant(C);
237 }
238 
239 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
240   return TTIImpl->useColdCCForColdCall(F);
241 }
242 
243 unsigned TargetTransformInfo::
244 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
245   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
246 }
247 
248 unsigned TargetTransformInfo::
249 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
250                                  unsigned VF) const {
251   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
252 }
253 
254 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
255   return TTIImpl->supportsEfficientVectorElementLoadStore();
256 }
257 
258 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
259   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
260 }
261 
262 const TargetTransformInfo::MemCmpExpansionOptions *
263 TargetTransformInfo::enableMemCmpExpansion(bool IsZeroCmp) const {
264   return TTIImpl->enableMemCmpExpansion(IsZeroCmp);
265 }
266 
267 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
268   return TTIImpl->enableInterleavedAccessVectorization();
269 }
270 
271 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
272   return TTIImpl->enableMaskedInterleavedAccessVectorization();
273 }
274 
275 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
276   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
277 }
278 
279 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
280                                                          unsigned BitWidth,
281                                                          unsigned AddressSpace,
282                                                          unsigned Alignment,
283                                                          bool *Fast) const {
284   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
285                                                  Alignment, Fast);
286 }
287 
288 TargetTransformInfo::PopcntSupportKind
289 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
290   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
291 }
292 
293 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
294   return TTIImpl->haveFastSqrt(Ty);
295 }
296 
297 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
298   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
299 }
300 
301 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
302   int Cost = TTIImpl->getFPOpCost(Ty);
303   assert(Cost >= 0 && "TTI should not produce negative costs!");
304   return Cost;
305 }
306 
307 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
308                                                const APInt &Imm,
309                                                Type *Ty) const {
310   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
311   assert(Cost >= 0 && "TTI should not produce negative costs!");
312   return Cost;
313 }
314 
315 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
316   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
317   assert(Cost >= 0 && "TTI should not produce negative costs!");
318   return Cost;
319 }
320 
321 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
322                                        const APInt &Imm, Type *Ty) const {
323   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
324   assert(Cost >= 0 && "TTI should not produce negative costs!");
325   return Cost;
326 }
327 
328 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
329                                        const APInt &Imm, Type *Ty) const {
330   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
331   assert(Cost >= 0 && "TTI should not produce negative costs!");
332   return Cost;
333 }
334 
335 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
336   return TTIImpl->getNumberOfRegisters(Vector);
337 }
338 
339 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
340   return TTIImpl->getRegisterBitWidth(Vector);
341 }
342 
343 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
344   return TTIImpl->getMinVectorRegisterBitWidth();
345 }
346 
347 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
348   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
349 }
350 
351 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
352   return TTIImpl->getMinimumVF(ElemWidth);
353 }
354 
355 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
356     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
357   return TTIImpl->shouldConsiderAddressTypePromotion(
358       I, AllowPromotionWithoutCommonHeader);
359 }
360 
361 unsigned TargetTransformInfo::getCacheLineSize() const {
362   return TTIImpl->getCacheLineSize();
363 }
364 
365 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
366   const {
367   return TTIImpl->getCacheSize(Level);
368 }
369 
370 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
371   CacheLevel Level) const {
372   return TTIImpl->getCacheAssociativity(Level);
373 }
374 
375 unsigned TargetTransformInfo::getPrefetchDistance() const {
376   return TTIImpl->getPrefetchDistance();
377 }
378 
379 unsigned TargetTransformInfo::getMinPrefetchStride() const {
380   return TTIImpl->getMinPrefetchStride();
381 }
382 
383 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
384   return TTIImpl->getMaxPrefetchIterationsAhead();
385 }
386 
387 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
388   return TTIImpl->getMaxInterleaveFactor(VF);
389 }
390 
391 TargetTransformInfo::OperandValueKind
392 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
393   OperandValueKind OpInfo = OK_AnyValue;
394   OpProps = OP_None;
395 
396   if (auto *CI = dyn_cast<ConstantInt>(V)) {
397     if (CI->getValue().isPowerOf2())
398       OpProps = OP_PowerOf2;
399     return OK_UniformConstantValue;
400   }
401 
402   // A broadcast shuffle creates a uniform value.
403   // TODO: Add support for non-zero index broadcasts.
404   // TODO: Add support for different source vector width.
405   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
406     if (ShuffleInst->isZeroEltSplat())
407       OpInfo = OK_UniformValue;
408 
409   const Value *Splat = getSplatValue(V);
410 
411   // Check for a splat of a constant or for a non uniform vector of constants
412   // and check if the constant(s) are all powers of two.
413   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
414     OpInfo = OK_NonUniformConstantValue;
415     if (Splat) {
416       OpInfo = OK_UniformConstantValue;
417       if (auto *CI = dyn_cast<ConstantInt>(Splat))
418         if (CI->getValue().isPowerOf2())
419           OpProps = OP_PowerOf2;
420     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
421       OpProps = OP_PowerOf2;
422       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
423         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
424           if (CI->getValue().isPowerOf2())
425             continue;
426         OpProps = OP_None;
427         break;
428       }
429     }
430   }
431 
432   // Check for a splat of a uniform value. This is not loop aware, so return
433   // true only for the obviously uniform cases (argument, globalvalue)
434   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
435     OpInfo = OK_UniformValue;
436 
437   return OpInfo;
438 }
439 
440 int TargetTransformInfo::getArithmeticInstrCost(
441     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
442     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
443     OperandValueProperties Opd2PropInfo,
444     ArrayRef<const Value *> Args) const {
445   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
446                                              Opd1PropInfo, Opd2PropInfo, Args);
447   assert(Cost >= 0 && "TTI should not produce negative costs!");
448   return Cost;
449 }
450 
451 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
452                                         Type *SubTp) const {
453   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
454   assert(Cost >= 0 && "TTI should not produce negative costs!");
455   return Cost;
456 }
457 
458 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
459                                  Type *Src, const Instruction *I) const {
460   assert ((I == nullptr || I->getOpcode() == Opcode) &&
461           "Opcode should reflect passed instruction.");
462   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
463   assert(Cost >= 0 && "TTI should not produce negative costs!");
464   return Cost;
465 }
466 
467 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
468                                                   VectorType *VecTy,
469                                                   unsigned Index) const {
470   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
471   assert(Cost >= 0 && "TTI should not produce negative costs!");
472   return Cost;
473 }
474 
475 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
476   int Cost = TTIImpl->getCFInstrCost(Opcode);
477   assert(Cost >= 0 && "TTI should not produce negative costs!");
478   return Cost;
479 }
480 
481 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
482                                  Type *CondTy, const Instruction *I) const {
483   assert ((I == nullptr || I->getOpcode() == Opcode) &&
484           "Opcode should reflect passed instruction.");
485   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
486   assert(Cost >= 0 && "TTI should not produce negative costs!");
487   return Cost;
488 }
489 
490 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
491                                             unsigned Index) const {
492   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
493   assert(Cost >= 0 && "TTI should not produce negative costs!");
494   return Cost;
495 }
496 
497 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
498                                          unsigned Alignment,
499                                          unsigned AddressSpace,
500                                          const Instruction *I) const {
501   assert ((I == nullptr || I->getOpcode() == Opcode) &&
502           "Opcode should reflect passed instruction.");
503   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
504   assert(Cost >= 0 && "TTI should not produce negative costs!");
505   return Cost;
506 }
507 
508 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
509                                                unsigned Alignment,
510                                                unsigned AddressSpace) const {
511   int Cost =
512       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
513   assert(Cost >= 0 && "TTI should not produce negative costs!");
514   return Cost;
515 }
516 
517 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
518                                                 Value *Ptr, bool VariableMask,
519                                                 unsigned Alignment) const {
520   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
521                                              Alignment);
522   assert(Cost >= 0 && "TTI should not produce negative costs!");
523   return Cost;
524 }
525 
526 int TargetTransformInfo::getInterleavedMemoryOpCost(
527     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
528     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
529     bool UseMaskForGaps) const {
530   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
531                                                  Alignment, AddressSpace,
532                                                  UseMaskForCond,
533                                                  UseMaskForGaps);
534   assert(Cost >= 0 && "TTI should not produce negative costs!");
535   return Cost;
536 }
537 
538 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
539                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
540                                     unsigned ScalarizationCostPassed) const {
541   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
542                                             ScalarizationCostPassed);
543   assert(Cost >= 0 && "TTI should not produce negative costs!");
544   return Cost;
545 }
546 
547 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
548            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
549   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
550   assert(Cost >= 0 && "TTI should not produce negative costs!");
551   return Cost;
552 }
553 
554 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
555                                           ArrayRef<Type *> Tys) const {
556   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
557   assert(Cost >= 0 && "TTI should not produce negative costs!");
558   return Cost;
559 }
560 
561 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
562   return TTIImpl->getNumberOfParts(Tp);
563 }
564 
565 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
566                                                    ScalarEvolution *SE,
567                                                    const SCEV *Ptr) const {
568   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
569   assert(Cost >= 0 && "TTI should not produce negative costs!");
570   return Cost;
571 }
572 
573 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
574                                                     bool IsPairwiseForm) const {
575   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
576   assert(Cost >= 0 && "TTI should not produce negative costs!");
577   return Cost;
578 }
579 
580 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
581                                                 bool IsPairwiseForm,
582                                                 bool IsUnsigned) const {
583   int Cost =
584       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
585   assert(Cost >= 0 && "TTI should not produce negative costs!");
586   return Cost;
587 }
588 
589 unsigned
590 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
591   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
592 }
593 
594 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
595                                              MemIntrinsicInfo &Info) const {
596   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
597 }
598 
599 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
600   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
601 }
602 
603 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
604     IntrinsicInst *Inst, Type *ExpectedType) const {
605   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
606 }
607 
608 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
609                                                      Value *Length,
610                                                      unsigned SrcAlign,
611                                                      unsigned DestAlign) const {
612   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
613                                             DestAlign);
614 }
615 
616 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
617     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
618     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
619   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
620                                              SrcAlign, DestAlign);
621 }
622 
623 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
624                                               const Function *Callee) const {
625   return TTIImpl->areInlineCompatible(Caller, Callee);
626 }
627 
628 bool TargetTransformInfo::areFunctionArgsABICompatible(
629     const Function *Caller, const Function *Callee,
630     SmallPtrSetImpl<Argument *> &Args) const {
631   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
632 }
633 
634 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
635                                              Type *Ty) const {
636   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
637 }
638 
639 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
640                                               Type *Ty) const {
641   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
642 }
643 
644 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
645   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
646 }
647 
648 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
649   return TTIImpl->isLegalToVectorizeLoad(LI);
650 }
651 
652 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
653   return TTIImpl->isLegalToVectorizeStore(SI);
654 }
655 
656 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
657     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
658   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
659                                               AddrSpace);
660 }
661 
662 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
663     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
664   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
665                                                AddrSpace);
666 }
667 
668 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
669                                                   unsigned LoadSize,
670                                                   unsigned ChainSizeInBytes,
671                                                   VectorType *VecTy) const {
672   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
673 }
674 
675 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
676                                                    unsigned StoreSize,
677                                                    unsigned ChainSizeInBytes,
678                                                    VectorType *VecTy) const {
679   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
680 }
681 
682 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
683                                                 Type *Ty, ReductionFlags Flags) const {
684   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
685 }
686 
687 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
688   return TTIImpl->shouldExpandReduction(II);
689 }
690 
691 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
692   return TTIImpl->getInstructionLatency(I);
693 }
694 
695 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
696                                      unsigned Level) {
697   // We don't need a shuffle if we just want to have element 0 in position 0 of
698   // the vector.
699   if (!SI && Level == 0 && IsLeft)
700     return true;
701   else if (!SI)
702     return false;
703 
704   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
705 
706   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
707   // we look at the left or right side.
708   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
709     Mask[i] = val;
710 
711   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
712   return Mask == ActualMask;
713 }
714 
715 namespace {
716 /// Kind of the reduction data.
717 enum ReductionKind {
718   RK_None,           /// Not a reduction.
719   RK_Arithmetic,     /// Binary reduction data.
720   RK_MinMax,         /// Min/max reduction data.
721   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
722 };
723 /// Contains opcode + LHS/RHS parts of the reduction operations.
724 struct ReductionData {
725   ReductionData() = delete;
726   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
727       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
728     assert(Kind != RK_None && "expected binary or min/max reduction only.");
729   }
730   unsigned Opcode = 0;
731   Value *LHS = nullptr;
732   Value *RHS = nullptr;
733   ReductionKind Kind = RK_None;
734   bool hasSameData(ReductionData &RD) const {
735     return Kind == RD.Kind && Opcode == RD.Opcode;
736   }
737 };
738 } // namespace
739 
740 static Optional<ReductionData> getReductionData(Instruction *I) {
741   Value *L, *R;
742   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
743     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
744   if (auto *SI = dyn_cast<SelectInst>(I)) {
745     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
746         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
747         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
748         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
749         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
750         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
751       auto *CI = cast<CmpInst>(SI->getCondition());
752       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
753     }
754     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
755         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
756       auto *CI = cast<CmpInst>(SI->getCondition());
757       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
758     }
759   }
760   return llvm::None;
761 }
762 
763 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
764                                                    unsigned Level,
765                                                    unsigned NumLevels) {
766   // Match one level of pairwise operations.
767   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
768   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
769   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
770   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
771   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
772   if (!I)
773     return RK_None;
774 
775   assert(I->getType()->isVectorTy() && "Expecting a vector type");
776 
777   Optional<ReductionData> RD = getReductionData(I);
778   if (!RD)
779     return RK_None;
780 
781   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
782   if (!LS && Level)
783     return RK_None;
784   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
785   if (!RS && Level)
786     return RK_None;
787 
788   // On level 0 we can omit one shufflevector instruction.
789   if (!Level && !RS && !LS)
790     return RK_None;
791 
792   // Shuffle inputs must match.
793   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
794   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
795   Value *NextLevelOp = nullptr;
796   if (NextLevelOpR && NextLevelOpL) {
797     // If we have two shuffles their operands must match.
798     if (NextLevelOpL != NextLevelOpR)
799       return RK_None;
800 
801     NextLevelOp = NextLevelOpL;
802   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
803     // On the first level we can omit the shufflevector <0, undef,...>. So the
804     // input to the other shufflevector <1, undef> must match with one of the
805     // inputs to the current binary operation.
806     // Example:
807     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
808     //  %BinOp        = fadd          %NextLevelOpL, %R
809     if (NextLevelOpL && NextLevelOpL != RD->RHS)
810       return RK_None;
811     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
812       return RK_None;
813 
814     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
815   } else
816     return RK_None;
817 
818   // Check that the next levels binary operation exists and matches with the
819   // current one.
820   if (Level + 1 != NumLevels) {
821     Optional<ReductionData> NextLevelRD =
822         getReductionData(cast<Instruction>(NextLevelOp));
823     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
824       return RK_None;
825   }
826 
827   // Shuffle mask for pairwise operation must match.
828   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
829     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
830       return RK_None;
831   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
832     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
833       return RK_None;
834   } else {
835     return RK_None;
836   }
837 
838   if (++Level == NumLevels)
839     return RD->Kind;
840 
841   // Match next level.
842   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
843                                        NumLevels);
844 }
845 
846 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
847                                             unsigned &Opcode, Type *&Ty) {
848   if (!EnableReduxCost)
849     return RK_None;
850 
851   // Need to extract the first element.
852   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
853   unsigned Idx = ~0u;
854   if (CI)
855     Idx = CI->getZExtValue();
856   if (Idx != 0)
857     return RK_None;
858 
859   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
860   if (!RdxStart)
861     return RK_None;
862   Optional<ReductionData> RD = getReductionData(RdxStart);
863   if (!RD)
864     return RK_None;
865 
866   Type *VecTy = RdxStart->getType();
867   unsigned NumVecElems = VecTy->getVectorNumElements();
868   if (!isPowerOf2_32(NumVecElems))
869     return RK_None;
870 
871   // We look for a sequence of shuffle,shuffle,add triples like the following
872   // that builds a pairwise reduction tree.
873   //
874   //  (X0, X1, X2, X3)
875   //   (X0 + X1, X2 + X3, undef, undef)
876   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
877   //
878   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
879   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
880   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
881   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
882   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
883   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
884   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
885   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
886   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
887   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
888   // %r = extractelement <4 x float> %bin.rdx8, i32 0
889   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
890       RK_None)
891     return RK_None;
892 
893   Opcode = RD->Opcode;
894   Ty = VecTy;
895 
896   return RD->Kind;
897 }
898 
899 static std::pair<Value *, ShuffleVectorInst *>
900 getShuffleAndOtherOprd(Value *L, Value *R) {
901   ShuffleVectorInst *S = nullptr;
902 
903   if ((S = dyn_cast<ShuffleVectorInst>(L)))
904     return std::make_pair(R, S);
905 
906   S = dyn_cast<ShuffleVectorInst>(R);
907   return std::make_pair(L, S);
908 }
909 
910 static ReductionKind
911 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
912                               unsigned &Opcode, Type *&Ty) {
913   if (!EnableReduxCost)
914     return RK_None;
915 
916   // Need to extract the first element.
917   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
918   unsigned Idx = ~0u;
919   if (CI)
920     Idx = CI->getZExtValue();
921   if (Idx != 0)
922     return RK_None;
923 
924   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
925   if (!RdxStart)
926     return RK_None;
927   Optional<ReductionData> RD = getReductionData(RdxStart);
928   if (!RD)
929     return RK_None;
930 
931   Type *VecTy = ReduxRoot->getOperand(0)->getType();
932   unsigned NumVecElems = VecTy->getVectorNumElements();
933   if (!isPowerOf2_32(NumVecElems))
934     return RK_None;
935 
936   // We look for a sequence of shuffles and adds like the following matching one
937   // fadd, shuffle vector pair at a time.
938   //
939   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
940   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
941   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
942   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
943   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
944   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
945   // %r = extractelement <4 x float> %bin.rdx8, i32 0
946 
947   unsigned MaskStart = 1;
948   Instruction *RdxOp = RdxStart;
949   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
950   unsigned NumVecElemsRemain = NumVecElems;
951   while (NumVecElemsRemain - 1) {
952     // Check for the right reduction operation.
953     if (!RdxOp)
954       return RK_None;
955     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
956     if (!RDLevel || !RDLevel->hasSameData(*RD))
957       return RK_None;
958 
959     Value *NextRdxOp;
960     ShuffleVectorInst *Shuffle;
961     std::tie(NextRdxOp, Shuffle) =
962         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
963 
964     // Check the current reduction operation and the shuffle use the same value.
965     if (Shuffle == nullptr)
966       return RK_None;
967     if (Shuffle->getOperand(0) != NextRdxOp)
968       return RK_None;
969 
970     // Check that shuffle masks matches.
971     for (unsigned j = 0; j != MaskStart; ++j)
972       ShuffleMask[j] = MaskStart + j;
973     // Fill the rest of the mask with -1 for undef.
974     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
975 
976     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
977     if (ShuffleMask != Mask)
978       return RK_None;
979 
980     RdxOp = dyn_cast<Instruction>(NextRdxOp);
981     NumVecElemsRemain /= 2;
982     MaskStart *= 2;
983   }
984 
985   Opcode = RD->Opcode;
986   Ty = VecTy;
987   return RD->Kind;
988 }
989 
990 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
991   switch (I->getOpcode()) {
992   case Instruction::GetElementPtr:
993     return getUserCost(I);
994 
995   case Instruction::Ret:
996   case Instruction::PHI:
997   case Instruction::Br: {
998     return getCFInstrCost(I->getOpcode());
999   }
1000   case Instruction::Add:
1001   case Instruction::FAdd:
1002   case Instruction::Sub:
1003   case Instruction::FSub:
1004   case Instruction::Mul:
1005   case Instruction::FMul:
1006   case Instruction::UDiv:
1007   case Instruction::SDiv:
1008   case Instruction::FDiv:
1009   case Instruction::URem:
1010   case Instruction::SRem:
1011   case Instruction::FRem:
1012   case Instruction::Shl:
1013   case Instruction::LShr:
1014   case Instruction::AShr:
1015   case Instruction::And:
1016   case Instruction::Or:
1017   case Instruction::Xor: {
1018     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1019     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1020     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1021     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1022     SmallVector<const Value *, 2> Operands(I->operand_values());
1023     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1024                                   Op1VP, Op2VP, Operands);
1025   }
1026   case Instruction::Select: {
1027     const SelectInst *SI = cast<SelectInst>(I);
1028     Type *CondTy = SI->getCondition()->getType();
1029     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1030   }
1031   case Instruction::ICmp:
1032   case Instruction::FCmp: {
1033     Type *ValTy = I->getOperand(0)->getType();
1034     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1035   }
1036   case Instruction::Store: {
1037     const StoreInst *SI = cast<StoreInst>(I);
1038     Type *ValTy = SI->getValueOperand()->getType();
1039     return getMemoryOpCost(I->getOpcode(), ValTy,
1040                                 SI->getAlignment(),
1041                                 SI->getPointerAddressSpace(), I);
1042   }
1043   case Instruction::Load: {
1044     const LoadInst *LI = cast<LoadInst>(I);
1045     return getMemoryOpCost(I->getOpcode(), I->getType(),
1046                                 LI->getAlignment(),
1047                                 LI->getPointerAddressSpace(), I);
1048   }
1049   case Instruction::ZExt:
1050   case Instruction::SExt:
1051   case Instruction::FPToUI:
1052   case Instruction::FPToSI:
1053   case Instruction::FPExt:
1054   case Instruction::PtrToInt:
1055   case Instruction::IntToPtr:
1056   case Instruction::SIToFP:
1057   case Instruction::UIToFP:
1058   case Instruction::Trunc:
1059   case Instruction::FPTrunc:
1060   case Instruction::BitCast:
1061   case Instruction::AddrSpaceCast: {
1062     Type *SrcTy = I->getOperand(0)->getType();
1063     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1064   }
1065   case Instruction::ExtractElement: {
1066     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1067     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1068     unsigned Idx = -1;
1069     if (CI)
1070       Idx = CI->getZExtValue();
1071 
1072     // Try to match a reduction sequence (series of shufflevector and vector
1073     // adds followed by a extractelement).
1074     unsigned ReduxOpCode;
1075     Type *ReduxType;
1076 
1077     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1078     case RK_Arithmetic:
1079       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1080                                              /*IsPairwiseForm=*/false);
1081     case RK_MinMax:
1082       return getMinMaxReductionCost(
1083           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1084           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1085     case RK_UnsignedMinMax:
1086       return getMinMaxReductionCost(
1087           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1088           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1089     case RK_None:
1090       break;
1091     }
1092 
1093     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1094     case RK_Arithmetic:
1095       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1096                                              /*IsPairwiseForm=*/true);
1097     case RK_MinMax:
1098       return getMinMaxReductionCost(
1099           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1100           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1101     case RK_UnsignedMinMax:
1102       return getMinMaxReductionCost(
1103           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1104           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1105     case RK_None:
1106       break;
1107     }
1108 
1109     return getVectorInstrCost(I->getOpcode(),
1110                                    EEI->getOperand(0)->getType(), Idx);
1111   }
1112   case Instruction::InsertElement: {
1113     const InsertElementInst * IE = cast<InsertElementInst>(I);
1114     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1115     unsigned Idx = -1;
1116     if (CI)
1117       Idx = CI->getZExtValue();
1118     return getVectorInstrCost(I->getOpcode(),
1119                                    IE->getType(), Idx);
1120   }
1121   case Instruction::ShuffleVector: {
1122     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1123     Type *Ty = Shuffle->getType();
1124     Type *SrcTy = Shuffle->getOperand(0)->getType();
1125 
1126     // TODO: Identify and add costs for insert subvector, etc.
1127     int SubIndex;
1128     if (Shuffle->isExtractSubvectorMask(SubIndex))
1129       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1130 
1131     if (Shuffle->changesLength())
1132       return -1;
1133 
1134     if (Shuffle->isIdentity())
1135       return 0;
1136 
1137     if (Shuffle->isReverse())
1138       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1139 
1140     if (Shuffle->isSelect())
1141       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1142 
1143     if (Shuffle->isTranspose())
1144       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1145 
1146     if (Shuffle->isZeroEltSplat())
1147       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1148 
1149     if (Shuffle->isSingleSource())
1150       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1151 
1152     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1153   }
1154   case Instruction::Call:
1155     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1156       SmallVector<Value *, 4> Args(II->arg_operands());
1157 
1158       FastMathFlags FMF;
1159       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1160         FMF = FPMO->getFastMathFlags();
1161 
1162       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1163                                         Args, FMF);
1164     }
1165     return -1;
1166   default:
1167     // We don't have any information on this instruction.
1168     return -1;
1169   }
1170 }
1171 
1172 TargetTransformInfo::Concept::~Concept() {}
1173 
1174 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1175 
1176 TargetIRAnalysis::TargetIRAnalysis(
1177     std::function<Result(const Function &)> TTICallback)
1178     : TTICallback(std::move(TTICallback)) {}
1179 
1180 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1181                                                FunctionAnalysisManager &) {
1182   return TTICallback(F);
1183 }
1184 
1185 AnalysisKey TargetIRAnalysis::Key;
1186 
1187 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1188   return Result(F.getParent()->getDataLayout());
1189 }
1190 
1191 // Register the basic pass.
1192 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1193                 "Target Transform Information", false, true)
1194 char TargetTransformInfoWrapperPass::ID = 0;
1195 
1196 void TargetTransformInfoWrapperPass::anchor() {}
1197 
1198 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1199     : ImmutablePass(ID) {
1200   initializeTargetTransformInfoWrapperPassPass(
1201       *PassRegistry::getPassRegistry());
1202 }
1203 
1204 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1205     TargetIRAnalysis TIRA)
1206     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1207   initializeTargetTransformInfoWrapperPassPass(
1208       *PassRegistry::getPassRegistry());
1209 }
1210 
1211 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1212   FunctionAnalysisManager DummyFAM;
1213   TTI = TIRA.run(F, DummyFAM);
1214   return *TTI;
1215 }
1216 
1217 ImmutablePass *
1218 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1219   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1220 }
1221