1 //===---------------------------- libunwind.h -----------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is dual licensed under the MIT and the University of Illinois Open
6 // Source Licenses. See LICENSE.TXT for details.
7 //
8 //
9 // Compatible with libunwind API documented at:
10 //   http://www.nongnu.org/libunwind/man/libunwind(3).html
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef __LIBUNWIND__
15 #define __LIBUNWIND__
16 
17 #include <__libunwind_config.h>
18 
19 #include <stdint.h>
20 #include <stddef.h>
21 
22 #ifdef __APPLE__
23   #if __clang__
24     #if __has_include(<Availability.h>)
25       #include <Availability.h>
26     #endif
27   #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050
28     #include <Availability.h>
29   #endif
30 
31   #ifdef __arm__
32      #define LIBUNWIND_AVAIL __attribute__((unavailable))
33   #elif defined(__OSX_AVAILABLE_STARTING)
34     #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0)
35   #else
36     #include <AvailabilityMacros.h>
37     #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
38       #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
39     #else
40       #define LIBUNWIND_AVAIL __attribute__((unavailable))
41     #endif
42   #endif
43 #else
44   #define LIBUNWIND_AVAIL
45 #endif
46 
47 /* error codes */
48 enum {
49   UNW_ESUCCESS      = 0,     /* no error */
50   UNW_EUNSPEC       = -6540, /* unspecified (general) error */
51   UNW_ENOMEM        = -6541, /* out of memory */
52   UNW_EBADREG       = -6542, /* bad register number */
53   UNW_EREADONLYREG  = -6543, /* attempt to write read-only register */
54   UNW_ESTOPUNWIND   = -6544, /* stop unwinding */
55   UNW_EINVALIDIP    = -6545, /* invalid IP */
56   UNW_EBADFRAME     = -6546, /* bad frame */
57   UNW_EINVAL        = -6547, /* unsupported operation or bad value */
58   UNW_EBADVERSION   = -6548, /* unwind info has unsupported version */
59   UNW_ENOINFO       = -6549  /* no unwind info found */
60 #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
61   , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
62 #endif
63 };
64 
65 struct unw_context_t {
66   uint64_t data[_LIBUNWIND_CONTEXT_SIZE];
67 };
68 typedef struct unw_context_t unw_context_t;
69 
70 struct unw_cursor_t {
71   uint64_t data[_LIBUNWIND_CURSOR_SIZE];
72 };
73 typedef struct unw_cursor_t unw_cursor_t;
74 
75 typedef struct unw_addr_space *unw_addr_space_t;
76 
77 typedef int unw_regnum_t;
78 typedef uintptr_t unw_word_t;
79 #if defined(__arm__)
80 typedef uint64_t unw_fpreg_t;
81 #else
82 typedef double unw_fpreg_t;
83 #endif
84 
85 struct unw_proc_info_t {
86   unw_word_t  start_ip;         /* start address of function */
87   unw_word_t  end_ip;           /* address after end of function */
88   unw_word_t  lsda;             /* address of language specific data area, */
89                                 /*  or zero if not used */
90   unw_word_t  handler;          /* personality routine, or zero if not used */
91   unw_word_t  gp;               /* not used */
92   unw_word_t  flags;            /* not used */
93   uint32_t    format;           /* compact unwind encoding, or zero if none */
94   uint32_t    unwind_info_size; /* size of DWARF unwind info, or zero if none */
95   unw_word_t  unwind_info;      /* address of DWARF unwind info, or zero */
96   unw_word_t  extra;            /* mach_header of mach-o image containing func */
97 };
98 typedef struct unw_proc_info_t unw_proc_info_t;
99 
100 #ifdef __cplusplus
101 extern "C" {
102 #endif
103 
104 extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL;
105 extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL;
106 extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL;
107 extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL;
108 extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL;
109 extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL;
110 extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t)  LIBUNWIND_AVAIL;
111 extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL;
112 
113 #ifdef __arm__
114 /* Save VFP registers in FSTMX format (instead of FSTMD). */
115 extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL;
116 #endif
117 
118 
119 extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
120 extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL;
121 extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
122 extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL;
123 extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL;
124 //extern int       unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*);
125 
126 extern unw_addr_space_t unw_local_addr_space;
127 
128 #ifdef UNW_REMOTE
129 /*
130  * Mac OS X "remote" API for unwinding other processes on same machine
131  *
132  */
133 extern unw_addr_space_t unw_create_addr_space_for_task(task_t);
134 extern void unw_destroy_addr_space(unw_addr_space_t);
135 extern int unw_init_remote_thread(unw_cursor_t *, unw_addr_space_t, thread_t *);
136 #endif /* UNW_REMOTE */
137 
138 /*
139  * traditional libunwind "remote" API
140  *   NOT IMPLEMENTED on Mac OS X
141  *
142  * extern int               unw_init_remote(unw_cursor_t*, unw_addr_space_t,
143  *                                          thread_t*);
144  * extern unw_accessors_t   unw_get_accessors(unw_addr_space_t);
145  * extern unw_addr_space_t  unw_create_addr_space(unw_accessors_t, int);
146  * extern void              unw_flush_cache(unw_addr_space_t, unw_word_t,
147  *                                          unw_word_t);
148  * extern int               unw_set_caching_policy(unw_addr_space_t,
149  *                                                 unw_caching_policy_t);
150  * extern void              _U_dyn_register(unw_dyn_info_t*);
151  * extern void              _U_dyn_cancel(unw_dyn_info_t*);
152  */
153 
154 #ifdef __cplusplus
155 }
156 #endif
157 
158 // architecture independent register numbers
159 enum {
160   UNW_REG_IP = -1, // instruction pointer
161   UNW_REG_SP = -2, // stack pointer
162 };
163 
164 // 32-bit x86 registers
165 enum {
166   UNW_X86_EAX = 0,
167   UNW_X86_ECX = 1,
168   UNW_X86_EDX = 2,
169   UNW_X86_EBX = 3,
170   UNW_X86_EBP = 4,
171   UNW_X86_ESP = 5,
172   UNW_X86_ESI = 6,
173   UNW_X86_EDI = 7
174 };
175 
176 // 64-bit x86_64 registers
177 enum {
178   UNW_X86_64_RAX = 0,
179   UNW_X86_64_RDX = 1,
180   UNW_X86_64_RCX = 2,
181   UNW_X86_64_RBX = 3,
182   UNW_X86_64_RSI = 4,
183   UNW_X86_64_RDI = 5,
184   UNW_X86_64_RBP = 6,
185   UNW_X86_64_RSP = 7,
186   UNW_X86_64_R8  = 8,
187   UNW_X86_64_R9  = 9,
188   UNW_X86_64_R10 = 10,
189   UNW_X86_64_R11 = 11,
190   UNW_X86_64_R12 = 12,
191   UNW_X86_64_R13 = 13,
192   UNW_X86_64_R14 = 14,
193   UNW_X86_64_R15 = 15,
194   UNW_X86_64_RIP = 16,
195   UNW_X86_64_XMM0 = 17,
196   UNW_X86_64_XMM1 = 18,
197   UNW_X86_64_XMM2 = 19,
198   UNW_X86_64_XMM3 = 20,
199   UNW_X86_64_XMM4 = 21,
200   UNW_X86_64_XMM5 = 22,
201   UNW_X86_64_XMM6 = 23,
202   UNW_X86_64_XMM7 = 24,
203   UNW_X86_64_XMM8 = 25,
204   UNW_X86_64_XMM9 = 26,
205   UNW_X86_64_XMM10 = 27,
206   UNW_X86_64_XMM11 = 28,
207   UNW_X86_64_XMM12 = 29,
208   UNW_X86_64_XMM13 = 30,
209   UNW_X86_64_XMM14 = 31,
210   UNW_X86_64_XMM15 = 32,
211 };
212 
213 
214 // 32-bit ppc register numbers
215 enum {
216   UNW_PPC_R0  = 0,
217   UNW_PPC_R1  = 1,
218   UNW_PPC_R2  = 2,
219   UNW_PPC_R3  = 3,
220   UNW_PPC_R4  = 4,
221   UNW_PPC_R5  = 5,
222   UNW_PPC_R6  = 6,
223   UNW_PPC_R7  = 7,
224   UNW_PPC_R8  = 8,
225   UNW_PPC_R9  = 9,
226   UNW_PPC_R10 = 10,
227   UNW_PPC_R11 = 11,
228   UNW_PPC_R12 = 12,
229   UNW_PPC_R13 = 13,
230   UNW_PPC_R14 = 14,
231   UNW_PPC_R15 = 15,
232   UNW_PPC_R16 = 16,
233   UNW_PPC_R17 = 17,
234   UNW_PPC_R18 = 18,
235   UNW_PPC_R19 = 19,
236   UNW_PPC_R20 = 20,
237   UNW_PPC_R21 = 21,
238   UNW_PPC_R22 = 22,
239   UNW_PPC_R23 = 23,
240   UNW_PPC_R24 = 24,
241   UNW_PPC_R25 = 25,
242   UNW_PPC_R26 = 26,
243   UNW_PPC_R27 = 27,
244   UNW_PPC_R28 = 28,
245   UNW_PPC_R29 = 29,
246   UNW_PPC_R30 = 30,
247   UNW_PPC_R31 = 31,
248   UNW_PPC_F0  = 32,
249   UNW_PPC_F1  = 33,
250   UNW_PPC_F2  = 34,
251   UNW_PPC_F3  = 35,
252   UNW_PPC_F4  = 36,
253   UNW_PPC_F5  = 37,
254   UNW_PPC_F6  = 38,
255   UNW_PPC_F7  = 39,
256   UNW_PPC_F8  = 40,
257   UNW_PPC_F9  = 41,
258   UNW_PPC_F10 = 42,
259   UNW_PPC_F11 = 43,
260   UNW_PPC_F12 = 44,
261   UNW_PPC_F13 = 45,
262   UNW_PPC_F14 = 46,
263   UNW_PPC_F15 = 47,
264   UNW_PPC_F16 = 48,
265   UNW_PPC_F17 = 49,
266   UNW_PPC_F18 = 50,
267   UNW_PPC_F19 = 51,
268   UNW_PPC_F20 = 52,
269   UNW_PPC_F21 = 53,
270   UNW_PPC_F22 = 54,
271   UNW_PPC_F23 = 55,
272   UNW_PPC_F24 = 56,
273   UNW_PPC_F25 = 57,
274   UNW_PPC_F26 = 58,
275   UNW_PPC_F27 = 59,
276   UNW_PPC_F28 = 60,
277   UNW_PPC_F29 = 61,
278   UNW_PPC_F30 = 62,
279   UNW_PPC_F31 = 63,
280   UNW_PPC_MQ  = 64,
281   UNW_PPC_LR  = 65,
282   UNW_PPC_CTR = 66,
283   UNW_PPC_AP  = 67,
284   UNW_PPC_CR0 = 68,
285   UNW_PPC_CR1 = 69,
286   UNW_PPC_CR2 = 70,
287   UNW_PPC_CR3 = 71,
288   UNW_PPC_CR4 = 72,
289   UNW_PPC_CR5 = 73,
290   UNW_PPC_CR6 = 74,
291   UNW_PPC_CR7 = 75,
292   UNW_PPC_XER = 76,
293   UNW_PPC_V0  = 77,
294   UNW_PPC_V1  = 78,
295   UNW_PPC_V2  = 79,
296   UNW_PPC_V3  = 80,
297   UNW_PPC_V4  = 81,
298   UNW_PPC_V5  = 82,
299   UNW_PPC_V6  = 83,
300   UNW_PPC_V7  = 84,
301   UNW_PPC_V8  = 85,
302   UNW_PPC_V9  = 86,
303   UNW_PPC_V10 = 87,
304   UNW_PPC_V11 = 88,
305   UNW_PPC_V12 = 89,
306   UNW_PPC_V13 = 90,
307   UNW_PPC_V14 = 91,
308   UNW_PPC_V15 = 92,
309   UNW_PPC_V16 = 93,
310   UNW_PPC_V17 = 94,
311   UNW_PPC_V18 = 95,
312   UNW_PPC_V19 = 96,
313   UNW_PPC_V20 = 97,
314   UNW_PPC_V21 = 98,
315   UNW_PPC_V22 = 99,
316   UNW_PPC_V23 = 100,
317   UNW_PPC_V24 = 101,
318   UNW_PPC_V25 = 102,
319   UNW_PPC_V26 = 103,
320   UNW_PPC_V27 = 104,
321   UNW_PPC_V28 = 105,
322   UNW_PPC_V29 = 106,
323   UNW_PPC_V30 = 107,
324   UNW_PPC_V31 = 108,
325   UNW_PPC_VRSAVE  = 109,
326   UNW_PPC_VSCR    = 110,
327   UNW_PPC_SPE_ACC = 111,
328   UNW_PPC_SPEFSCR = 112
329 };
330 
331 // 64-bit ppc register numbers
332 enum {
333   UNW_PPC64_R0      = 0,
334   UNW_PPC64_R1      = 1,
335   UNW_PPC64_R2      = 2,
336   UNW_PPC64_R3      = 3,
337   UNW_PPC64_R4      = 4,
338   UNW_PPC64_R5      = 5,
339   UNW_PPC64_R6      = 6,
340   UNW_PPC64_R7      = 7,
341   UNW_PPC64_R8      = 8,
342   UNW_PPC64_R9      = 9,
343   UNW_PPC64_R10     = 10,
344   UNW_PPC64_R11     = 11,
345   UNW_PPC64_R12     = 12,
346   UNW_PPC64_R13     = 13,
347   UNW_PPC64_R14     = 14,
348   UNW_PPC64_R15     = 15,
349   UNW_PPC64_R16     = 16,
350   UNW_PPC64_R17     = 17,
351   UNW_PPC64_R18     = 18,
352   UNW_PPC64_R19     = 19,
353   UNW_PPC64_R20     = 20,
354   UNW_PPC64_R21     = 21,
355   UNW_PPC64_R22     = 22,
356   UNW_PPC64_R23     = 23,
357   UNW_PPC64_R24     = 24,
358   UNW_PPC64_R25     = 25,
359   UNW_PPC64_R26     = 26,
360   UNW_PPC64_R27     = 27,
361   UNW_PPC64_R28     = 28,
362   UNW_PPC64_R29     = 29,
363   UNW_PPC64_R30     = 30,
364   UNW_PPC64_R31     = 31,
365   UNW_PPC64_F0      = 32,
366   UNW_PPC64_F1      = 33,
367   UNW_PPC64_F2      = 34,
368   UNW_PPC64_F3      = 35,
369   UNW_PPC64_F4      = 36,
370   UNW_PPC64_F5      = 37,
371   UNW_PPC64_F6      = 38,
372   UNW_PPC64_F7      = 39,
373   UNW_PPC64_F8      = 40,
374   UNW_PPC64_F9      = 41,
375   UNW_PPC64_F10     = 42,
376   UNW_PPC64_F11     = 43,
377   UNW_PPC64_F12     = 44,
378   UNW_PPC64_F13     = 45,
379   UNW_PPC64_F14     = 46,
380   UNW_PPC64_F15     = 47,
381   UNW_PPC64_F16     = 48,
382   UNW_PPC64_F17     = 49,
383   UNW_PPC64_F18     = 50,
384   UNW_PPC64_F19     = 51,
385   UNW_PPC64_F20     = 52,
386   UNW_PPC64_F21     = 53,
387   UNW_PPC64_F22     = 54,
388   UNW_PPC64_F23     = 55,
389   UNW_PPC64_F24     = 56,
390   UNW_PPC64_F25     = 57,
391   UNW_PPC64_F26     = 58,
392   UNW_PPC64_F27     = 59,
393   UNW_PPC64_F28     = 60,
394   UNW_PPC64_F29     = 61,
395   UNW_PPC64_F30     = 62,
396   UNW_PPC64_F31     = 63,
397   // 64: reserved
398   UNW_PPC64_LR      = 65,
399   UNW_PPC64_CTR     = 66,
400   // 67: reserved
401   UNW_PPC64_CR0     = 68,
402   UNW_PPC64_CR1     = 69,
403   UNW_PPC64_CR2     = 70,
404   UNW_PPC64_CR3     = 71,
405   UNW_PPC64_CR4     = 72,
406   UNW_PPC64_CR5     = 73,
407   UNW_PPC64_CR6     = 74,
408   UNW_PPC64_CR7     = 75,
409   UNW_PPC64_XER     = 76,
410   UNW_PPC64_V0      = 77,
411   UNW_PPC64_V1      = 78,
412   UNW_PPC64_V2      = 79,
413   UNW_PPC64_V3      = 80,
414   UNW_PPC64_V4      = 81,
415   UNW_PPC64_V5      = 82,
416   UNW_PPC64_V6      = 83,
417   UNW_PPC64_V7      = 84,
418   UNW_PPC64_V8      = 85,
419   UNW_PPC64_V9      = 86,
420   UNW_PPC64_V10     = 87,
421   UNW_PPC64_V11     = 88,
422   UNW_PPC64_V12     = 89,
423   UNW_PPC64_V13     = 90,
424   UNW_PPC64_V14     = 91,
425   UNW_PPC64_V15     = 92,
426   UNW_PPC64_V16     = 93,
427   UNW_PPC64_V17     = 94,
428   UNW_PPC64_V18     = 95,
429   UNW_PPC64_V19     = 96,
430   UNW_PPC64_V20     = 97,
431   UNW_PPC64_V21     = 98,
432   UNW_PPC64_V22     = 99,
433   UNW_PPC64_V23     = 100,
434   UNW_PPC64_V24     = 101,
435   UNW_PPC64_V25     = 102,
436   UNW_PPC64_V26     = 103,
437   UNW_PPC64_V27     = 104,
438   UNW_PPC64_V28     = 105,
439   UNW_PPC64_V29     = 106,
440   UNW_PPC64_V30     = 107,
441   UNW_PPC64_V31     = 108,
442   // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
443   // Borrowing VRSAVE number from PPC32.
444   UNW_PPC64_VRSAVE  = 109,
445   UNW_PPC64_VSCR    = 110,
446   UNW_PPC64_TFHAR   = 114,
447   UNW_PPC64_TFIAR   = 115,
448   UNW_PPC64_TEXASR  = 116,
449   UNW_PPC64_VS0     = UNW_PPC64_F0,
450   UNW_PPC64_VS1     = UNW_PPC64_F1,
451   UNW_PPC64_VS2     = UNW_PPC64_F2,
452   UNW_PPC64_VS3     = UNW_PPC64_F3,
453   UNW_PPC64_VS4     = UNW_PPC64_F4,
454   UNW_PPC64_VS5     = UNW_PPC64_F5,
455   UNW_PPC64_VS6     = UNW_PPC64_F6,
456   UNW_PPC64_VS7     = UNW_PPC64_F7,
457   UNW_PPC64_VS8     = UNW_PPC64_F8,
458   UNW_PPC64_VS9     = UNW_PPC64_F9,
459   UNW_PPC64_VS10    = UNW_PPC64_F10,
460   UNW_PPC64_VS11    = UNW_PPC64_F11,
461   UNW_PPC64_VS12    = UNW_PPC64_F12,
462   UNW_PPC64_VS13    = UNW_PPC64_F13,
463   UNW_PPC64_VS14    = UNW_PPC64_F14,
464   UNW_PPC64_VS15    = UNW_PPC64_F15,
465   UNW_PPC64_VS16    = UNW_PPC64_F16,
466   UNW_PPC64_VS17    = UNW_PPC64_F17,
467   UNW_PPC64_VS18    = UNW_PPC64_F18,
468   UNW_PPC64_VS19    = UNW_PPC64_F19,
469   UNW_PPC64_VS20    = UNW_PPC64_F20,
470   UNW_PPC64_VS21    = UNW_PPC64_F21,
471   UNW_PPC64_VS22    = UNW_PPC64_F22,
472   UNW_PPC64_VS23    = UNW_PPC64_F23,
473   UNW_PPC64_VS24    = UNW_PPC64_F24,
474   UNW_PPC64_VS25    = UNW_PPC64_F25,
475   UNW_PPC64_VS26    = UNW_PPC64_F26,
476   UNW_PPC64_VS27    = UNW_PPC64_F27,
477   UNW_PPC64_VS28    = UNW_PPC64_F28,
478   UNW_PPC64_VS29    = UNW_PPC64_F29,
479   UNW_PPC64_VS30    = UNW_PPC64_F30,
480   UNW_PPC64_VS31    = UNW_PPC64_F31,
481   UNW_PPC64_VS32    = UNW_PPC64_V0,
482   UNW_PPC64_VS33    = UNW_PPC64_V1,
483   UNW_PPC64_VS34    = UNW_PPC64_V2,
484   UNW_PPC64_VS35    = UNW_PPC64_V3,
485   UNW_PPC64_VS36    = UNW_PPC64_V4,
486   UNW_PPC64_VS37    = UNW_PPC64_V5,
487   UNW_PPC64_VS38    = UNW_PPC64_V6,
488   UNW_PPC64_VS39    = UNW_PPC64_V7,
489   UNW_PPC64_VS40    = UNW_PPC64_V8,
490   UNW_PPC64_VS41    = UNW_PPC64_V9,
491   UNW_PPC64_VS42    = UNW_PPC64_V10,
492   UNW_PPC64_VS43    = UNW_PPC64_V11,
493   UNW_PPC64_VS44    = UNW_PPC64_V12,
494   UNW_PPC64_VS45    = UNW_PPC64_V13,
495   UNW_PPC64_VS46    = UNW_PPC64_V14,
496   UNW_PPC64_VS47    = UNW_PPC64_V15,
497   UNW_PPC64_VS48    = UNW_PPC64_V16,
498   UNW_PPC64_VS49    = UNW_PPC64_V17,
499   UNW_PPC64_VS50    = UNW_PPC64_V18,
500   UNW_PPC64_VS51    = UNW_PPC64_V19,
501   UNW_PPC64_VS52    = UNW_PPC64_V20,
502   UNW_PPC64_VS53    = UNW_PPC64_V21,
503   UNW_PPC64_VS54    = UNW_PPC64_V22,
504   UNW_PPC64_VS55    = UNW_PPC64_V23,
505   UNW_PPC64_VS56    = UNW_PPC64_V24,
506   UNW_PPC64_VS57    = UNW_PPC64_V25,
507   UNW_PPC64_VS58    = UNW_PPC64_V26,
508   UNW_PPC64_VS59    = UNW_PPC64_V27,
509   UNW_PPC64_VS60    = UNW_PPC64_V28,
510   UNW_PPC64_VS61    = UNW_PPC64_V29,
511   UNW_PPC64_VS62    = UNW_PPC64_V30,
512   UNW_PPC64_VS63    = UNW_PPC64_V31
513 };
514 
515 // 64-bit ARM64 registers
516 enum {
517   UNW_ARM64_X0  = 0,
518   UNW_ARM64_X1  = 1,
519   UNW_ARM64_X2  = 2,
520   UNW_ARM64_X3  = 3,
521   UNW_ARM64_X4  = 4,
522   UNW_ARM64_X5  = 5,
523   UNW_ARM64_X6  = 6,
524   UNW_ARM64_X7  = 7,
525   UNW_ARM64_X8  = 8,
526   UNW_ARM64_X9  = 9,
527   UNW_ARM64_X10 = 10,
528   UNW_ARM64_X11 = 11,
529   UNW_ARM64_X12 = 12,
530   UNW_ARM64_X13 = 13,
531   UNW_ARM64_X14 = 14,
532   UNW_ARM64_X15 = 15,
533   UNW_ARM64_X16 = 16,
534   UNW_ARM64_X17 = 17,
535   UNW_ARM64_X18 = 18,
536   UNW_ARM64_X19 = 19,
537   UNW_ARM64_X20 = 20,
538   UNW_ARM64_X21 = 21,
539   UNW_ARM64_X22 = 22,
540   UNW_ARM64_X23 = 23,
541   UNW_ARM64_X24 = 24,
542   UNW_ARM64_X25 = 25,
543   UNW_ARM64_X26 = 26,
544   UNW_ARM64_X27 = 27,
545   UNW_ARM64_X28 = 28,
546   UNW_ARM64_X29 = 29,
547   UNW_ARM64_FP  = 29,
548   UNW_ARM64_X30 = 30,
549   UNW_ARM64_LR  = 30,
550   UNW_ARM64_X31 = 31,
551   UNW_ARM64_SP  = 31,
552   // reserved block
553   UNW_ARM64_RA_SIGN_STATE = 34,
554   // reserved block
555   UNW_ARM64_D0  = 64,
556   UNW_ARM64_D1  = 65,
557   UNW_ARM64_D2  = 66,
558   UNW_ARM64_D3  = 67,
559   UNW_ARM64_D4  = 68,
560   UNW_ARM64_D5  = 69,
561   UNW_ARM64_D6  = 70,
562   UNW_ARM64_D7  = 71,
563   UNW_ARM64_D8  = 72,
564   UNW_ARM64_D9  = 73,
565   UNW_ARM64_D10 = 74,
566   UNW_ARM64_D11 = 75,
567   UNW_ARM64_D12 = 76,
568   UNW_ARM64_D13 = 77,
569   UNW_ARM64_D14 = 78,
570   UNW_ARM64_D15 = 79,
571   UNW_ARM64_D16 = 80,
572   UNW_ARM64_D17 = 81,
573   UNW_ARM64_D18 = 82,
574   UNW_ARM64_D19 = 83,
575   UNW_ARM64_D20 = 84,
576   UNW_ARM64_D21 = 85,
577   UNW_ARM64_D22 = 86,
578   UNW_ARM64_D23 = 87,
579   UNW_ARM64_D24 = 88,
580   UNW_ARM64_D25 = 89,
581   UNW_ARM64_D26 = 90,
582   UNW_ARM64_D27 = 91,
583   UNW_ARM64_D28 = 92,
584   UNW_ARM64_D29 = 93,
585   UNW_ARM64_D30 = 94,
586   UNW_ARM64_D31 = 95,
587 };
588 
589 // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
590 // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
591 // In this scheme, even though the 64-bit floating point registers D0-D31
592 // overlap physically with the 32-bit floating pointer registers S0-S31,
593 // they are given a non-overlapping range of register numbers.
594 //
595 // Commented out ranges are not preserved during unwinding.
596 enum {
597   UNW_ARM_R0  = 0,
598   UNW_ARM_R1  = 1,
599   UNW_ARM_R2  = 2,
600   UNW_ARM_R3  = 3,
601   UNW_ARM_R4  = 4,
602   UNW_ARM_R5  = 5,
603   UNW_ARM_R6  = 6,
604   UNW_ARM_R7  = 7,
605   UNW_ARM_R8  = 8,
606   UNW_ARM_R9  = 9,
607   UNW_ARM_R10 = 10,
608   UNW_ARM_R11 = 11,
609   UNW_ARM_R12 = 12,
610   UNW_ARM_SP  = 13,  // Logical alias for UNW_REG_SP
611   UNW_ARM_R13 = 13,
612   UNW_ARM_LR  = 14,
613   UNW_ARM_R14 = 14,
614   UNW_ARM_IP  = 15,  // Logical alias for UNW_REG_IP
615   UNW_ARM_R15 = 15,
616   // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
617   UNW_ARM_S0  = 64,
618   UNW_ARM_S1  = 65,
619   UNW_ARM_S2  = 66,
620   UNW_ARM_S3  = 67,
621   UNW_ARM_S4  = 68,
622   UNW_ARM_S5  = 69,
623   UNW_ARM_S6  = 70,
624   UNW_ARM_S7  = 71,
625   UNW_ARM_S8  = 72,
626   UNW_ARM_S9  = 73,
627   UNW_ARM_S10 = 74,
628   UNW_ARM_S11 = 75,
629   UNW_ARM_S12 = 76,
630   UNW_ARM_S13 = 77,
631   UNW_ARM_S14 = 78,
632   UNW_ARM_S15 = 79,
633   UNW_ARM_S16 = 80,
634   UNW_ARM_S17 = 81,
635   UNW_ARM_S18 = 82,
636   UNW_ARM_S19 = 83,
637   UNW_ARM_S20 = 84,
638   UNW_ARM_S21 = 85,
639   UNW_ARM_S22 = 86,
640   UNW_ARM_S23 = 87,
641   UNW_ARM_S24 = 88,
642   UNW_ARM_S25 = 89,
643   UNW_ARM_S26 = 90,
644   UNW_ARM_S27 = 91,
645   UNW_ARM_S28 = 92,
646   UNW_ARM_S29 = 93,
647   UNW_ARM_S30 = 94,
648   UNW_ARM_S31 = 95,
649   //  96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
650   // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
651   UNW_ARM_WR0 = 112,
652   UNW_ARM_WR1 = 113,
653   UNW_ARM_WR2 = 114,
654   UNW_ARM_WR3 = 115,
655   UNW_ARM_WR4 = 116,
656   UNW_ARM_WR5 = 117,
657   UNW_ARM_WR6 = 118,
658   UNW_ARM_WR7 = 119,
659   UNW_ARM_WR8 = 120,
660   UNW_ARM_WR9 = 121,
661   UNW_ARM_WR10 = 122,
662   UNW_ARM_WR11 = 123,
663   UNW_ARM_WR12 = 124,
664   UNW_ARM_WR13 = 125,
665   UNW_ARM_WR14 = 126,
666   UNW_ARM_WR15 = 127,
667   // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
668   // 134-143 -- Reserved
669   // 144-150 -- R8_USR-R14_USR
670   // 151-157 -- R8_FIQ-R14_FIQ
671   // 158-159 -- R13_IRQ-R14_IRQ
672   // 160-161 -- R13_ABT-R14_ABT
673   // 162-163 -- R13_UND-R14_UND
674   // 164-165 -- R13_SVC-R14_SVC
675   // 166-191 -- Reserved
676   UNW_ARM_WC0 = 192,
677   UNW_ARM_WC1 = 193,
678   UNW_ARM_WC2 = 194,
679   UNW_ARM_WC3 = 195,
680   // 196-199 -- wC4-wC7 (Intel wireless MMX control)
681   // 200-255 -- Reserved
682   UNW_ARM_D0  = 256,
683   UNW_ARM_D1  = 257,
684   UNW_ARM_D2  = 258,
685   UNW_ARM_D3  = 259,
686   UNW_ARM_D4  = 260,
687   UNW_ARM_D5  = 261,
688   UNW_ARM_D6  = 262,
689   UNW_ARM_D7  = 263,
690   UNW_ARM_D8  = 264,
691   UNW_ARM_D9  = 265,
692   UNW_ARM_D10 = 266,
693   UNW_ARM_D11 = 267,
694   UNW_ARM_D12 = 268,
695   UNW_ARM_D13 = 269,
696   UNW_ARM_D14 = 270,
697   UNW_ARM_D15 = 271,
698   UNW_ARM_D16 = 272,
699   UNW_ARM_D17 = 273,
700   UNW_ARM_D18 = 274,
701   UNW_ARM_D19 = 275,
702   UNW_ARM_D20 = 276,
703   UNW_ARM_D21 = 277,
704   UNW_ARM_D22 = 278,
705   UNW_ARM_D23 = 279,
706   UNW_ARM_D24 = 280,
707   UNW_ARM_D25 = 281,
708   UNW_ARM_D26 = 282,
709   UNW_ARM_D27 = 283,
710   UNW_ARM_D28 = 284,
711   UNW_ARM_D29 = 285,
712   UNW_ARM_D30 = 286,
713   UNW_ARM_D31 = 287,
714   // 288-319 -- Reserved for VFP/Neon
715   // 320-8191 -- Reserved
716   // 8192-16383 -- Unspecified vendor co-processor register.
717 };
718 
719 // OpenRISC1000 register numbers
720 enum {
721   UNW_OR1K_R0  = 0,
722   UNW_OR1K_R1  = 1,
723   UNW_OR1K_R2  = 2,
724   UNW_OR1K_R3  = 3,
725   UNW_OR1K_R4  = 4,
726   UNW_OR1K_R5  = 5,
727   UNW_OR1K_R6  = 6,
728   UNW_OR1K_R7  = 7,
729   UNW_OR1K_R8  = 8,
730   UNW_OR1K_R9  = 9,
731   UNW_OR1K_R10 = 10,
732   UNW_OR1K_R11 = 11,
733   UNW_OR1K_R12 = 12,
734   UNW_OR1K_R13 = 13,
735   UNW_OR1K_R14 = 14,
736   UNW_OR1K_R15 = 15,
737   UNW_OR1K_R16 = 16,
738   UNW_OR1K_R17 = 17,
739   UNW_OR1K_R18 = 18,
740   UNW_OR1K_R19 = 19,
741   UNW_OR1K_R20 = 20,
742   UNW_OR1K_R21 = 21,
743   UNW_OR1K_R22 = 22,
744   UNW_OR1K_R23 = 23,
745   UNW_OR1K_R24 = 24,
746   UNW_OR1K_R25 = 25,
747   UNW_OR1K_R26 = 26,
748   UNW_OR1K_R27 = 27,
749   UNW_OR1K_R28 = 28,
750   UNW_OR1K_R29 = 29,
751   UNW_OR1K_R30 = 30,
752   UNW_OR1K_R31 = 31,
753   UNW_OR1K_EPCR = 32,
754 };
755 
756 // 64-bit RISC-V registers
757 enum {
758   UNW_RISCV_X0  = 0,
759   UNW_RISCV_X1  = 1,
760   UNW_RISCV_RA  = 1,
761   UNW_RISCV_X2  = 2,
762   UNW_RISCV_SP  = 2,
763   UNW_RISCV_X3  = 3,
764   UNW_RISCV_X4  = 4,
765   UNW_RISCV_X5  = 5,
766   UNW_RISCV_X6  = 6,
767   UNW_RISCV_X7  = 7,
768   UNW_RISCV_X8  = 8,
769   UNW_RISCV_X9  = 9,
770   UNW_RISCV_X10 = 10,
771   UNW_RISCV_X11 = 11,
772   UNW_RISCV_X12 = 12,
773   UNW_RISCV_X13 = 13,
774   UNW_RISCV_X14 = 14,
775   UNW_RISCV_X15 = 15,
776   UNW_RISCV_X16 = 16,
777   UNW_RISCV_X17 = 17,
778   UNW_RISCV_X18 = 18,
779   UNW_RISCV_X19 = 19,
780   UNW_RISCV_X20 = 20,
781   UNW_RISCV_X21 = 21,
782   UNW_RISCV_X22 = 22,
783   UNW_RISCV_X23 = 23,
784   UNW_RISCV_X24 = 24,
785   UNW_RISCV_X25 = 25,
786   UNW_RISCV_X26 = 26,
787   UNW_RISCV_X27 = 27,
788   UNW_RISCV_X28 = 28,
789   UNW_RISCV_X29 = 29,
790   UNW_RISCV_X30 = 30,
791   UNW_RISCV_X31 = 31,
792   // reserved block
793   UNW_RISCV_D0  = 64,
794   UNW_RISCV_D1  = 65,
795   UNW_RISCV_D2  = 66,
796   UNW_RISCV_D3  = 67,
797   UNW_RISCV_D4  = 68,
798   UNW_RISCV_D5  = 69,
799   UNW_RISCV_D6  = 70,
800   UNW_RISCV_D7  = 71,
801   UNW_RISCV_D8  = 72,
802   UNW_RISCV_D9  = 73,
803   UNW_RISCV_D10 = 74,
804   UNW_RISCV_D11 = 75,
805   UNW_RISCV_D12 = 76,
806   UNW_RISCV_D13 = 77,
807   UNW_RISCV_D14 = 78,
808   UNW_RISCV_D15 = 79,
809   UNW_RISCV_D16 = 80,
810   UNW_RISCV_D17 = 81,
811   UNW_RISCV_D18 = 82,
812   UNW_RISCV_D19 = 83,
813   UNW_RISCV_D20 = 84,
814   UNW_RISCV_D21 = 85,
815   UNW_RISCV_D22 = 86,
816   UNW_RISCV_D23 = 87,
817   UNW_RISCV_D24 = 88,
818   UNW_RISCV_D25 = 89,
819   UNW_RISCV_D26 = 90,
820   UNW_RISCV_D27 = 91,
821   UNW_RISCV_D28 = 92,
822   UNW_RISCV_D29 = 93,
823   UNW_RISCV_D30 = 94,
824   UNW_RISCV_D31 = 95,
825 };
826 
827 // MIPS registers
828 enum {
829   UNW_MIPS_R0  = 0,
830   UNW_MIPS_R1  = 1,
831   UNW_MIPS_R2  = 2,
832   UNW_MIPS_R3  = 3,
833   UNW_MIPS_R4  = 4,
834   UNW_MIPS_R5  = 5,
835   UNW_MIPS_R6  = 6,
836   UNW_MIPS_R7  = 7,
837   UNW_MIPS_R8  = 8,
838   UNW_MIPS_R9  = 9,
839   UNW_MIPS_R10 = 10,
840   UNW_MIPS_R11 = 11,
841   UNW_MIPS_R12 = 12,
842   UNW_MIPS_R13 = 13,
843   UNW_MIPS_R14 = 14,
844   UNW_MIPS_R15 = 15,
845   UNW_MIPS_R16 = 16,
846   UNW_MIPS_R17 = 17,
847   UNW_MIPS_R18 = 18,
848   UNW_MIPS_R19 = 19,
849   UNW_MIPS_R20 = 20,
850   UNW_MIPS_R21 = 21,
851   UNW_MIPS_R22 = 22,
852   UNW_MIPS_R23 = 23,
853   UNW_MIPS_R24 = 24,
854   UNW_MIPS_R25 = 25,
855   UNW_MIPS_R26 = 26,
856   UNW_MIPS_R27 = 27,
857   UNW_MIPS_R28 = 28,
858   UNW_MIPS_R29 = 29,
859   UNW_MIPS_R30 = 30,
860   UNW_MIPS_R31 = 31,
861   UNW_MIPS_F0  = 32,
862   UNW_MIPS_F1  = 33,
863   UNW_MIPS_F2  = 34,
864   UNW_MIPS_F3  = 35,
865   UNW_MIPS_F4  = 36,
866   UNW_MIPS_F5  = 37,
867   UNW_MIPS_F6  = 38,
868   UNW_MIPS_F7  = 39,
869   UNW_MIPS_F8  = 40,
870   UNW_MIPS_F9  = 41,
871   UNW_MIPS_F10 = 42,
872   UNW_MIPS_F11 = 43,
873   UNW_MIPS_F12 = 44,
874   UNW_MIPS_F13 = 45,
875   UNW_MIPS_F14 = 46,
876   UNW_MIPS_F15 = 47,
877   UNW_MIPS_F16 = 48,
878   UNW_MIPS_F17 = 49,
879   UNW_MIPS_F18 = 50,
880   UNW_MIPS_F19 = 51,
881   UNW_MIPS_F20 = 52,
882   UNW_MIPS_F21 = 53,
883   UNW_MIPS_F22 = 54,
884   UNW_MIPS_F23 = 55,
885   UNW_MIPS_F24 = 56,
886   UNW_MIPS_F25 = 57,
887   UNW_MIPS_F26 = 58,
888   UNW_MIPS_F27 = 59,
889   UNW_MIPS_F28 = 60,
890   UNW_MIPS_F29 = 61,
891   UNW_MIPS_F30 = 62,
892   UNW_MIPS_F31 = 63,
893   UNW_MIPS_HI = 64,
894   UNW_MIPS_LO = 65,
895 };
896 
897 // SPARC registers
898 enum {
899   UNW_SPARC_G0 = 0,
900   UNW_SPARC_G1 = 1,
901   UNW_SPARC_G2 = 2,
902   UNW_SPARC_G3 = 3,
903   UNW_SPARC_G4 = 4,
904   UNW_SPARC_G5 = 5,
905   UNW_SPARC_G6 = 6,
906   UNW_SPARC_G7 = 7,
907   UNW_SPARC_O0 = 8,
908   UNW_SPARC_O1 = 9,
909   UNW_SPARC_O2 = 10,
910   UNW_SPARC_O3 = 11,
911   UNW_SPARC_O4 = 12,
912   UNW_SPARC_O5 = 13,
913   UNW_SPARC_O6 = 14,
914   UNW_SPARC_O7 = 15,
915   UNW_SPARC_L0 = 16,
916   UNW_SPARC_L1 = 17,
917   UNW_SPARC_L2 = 18,
918   UNW_SPARC_L3 = 19,
919   UNW_SPARC_L4 = 20,
920   UNW_SPARC_L5 = 21,
921   UNW_SPARC_L6 = 22,
922   UNW_SPARC_L7 = 23,
923   UNW_SPARC_I0 = 24,
924   UNW_SPARC_I1 = 25,
925   UNW_SPARC_I2 = 26,
926   UNW_SPARC_I3 = 27,
927   UNW_SPARC_I4 = 28,
928   UNW_SPARC_I5 = 29,
929   UNW_SPARC_I6 = 30,
930   UNW_SPARC_I7 = 31,
931 };
932 
933 #endif
934