1 /* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc. 3 Contributed by Ralph Campbell and OSF 4 Commented and modified by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 1, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 21 22 #ifndef _MIPS_H_ 23 #define _MIPS_H_ 24 25 /* These are bit masks and shift counts to use to access the various 26 fields of an instruction. To retrieve the X field of an 27 instruction, use the expression 28 (i >> OP_SH_X) & OP_MASK_X 29 To set the same field (to j), use 30 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 31 32 Make sure you use fields that are appropriate for the instruction, 33 of course. 34 35 The 'i' format uses OP, RS, RT and IMMEDIATE. 36 37 The 'j' format uses OP and TARGET. 38 39 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 40 41 The 'b' format uses OP, RS, RT and DELTA. 42 43 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 44 45 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 46 47 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 48 breakpoint instruction are not defined; Kane says the breakpoint 49 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 50 only use ten bits). 51 52 The syscall instruction uses SYSCALL. 53 54 The general coprocessor instructions use COPZ. */ 55 56 #define OP_MASK_OP 0x3f 57 #define OP_SH_OP 26 58 #define OP_MASK_RS 0x1f 59 #define OP_SH_RS 21 60 #define OP_MASK_FR 0x1f 61 #define OP_SH_FR 21 62 #define OP_MASK_FMT 0x1f 63 #define OP_SH_FMT 21 64 #define OP_MASK_BCC 0x7 65 #define OP_SH_BCC 18 66 #define OP_MASK_CODE 0x3ff 67 #define OP_SH_CODE 16 68 #define OP_MASK_RT 0x1f 69 #define OP_SH_RT 16 70 #define OP_MASK_FT 0x1f 71 #define OP_SH_FT 16 72 #define OP_MASK_CACHE 0x1f 73 #define OP_SH_CACHE 16 74 #define OP_MASK_RD 0x1f 75 #define OP_SH_RD 11 76 #define OP_MASK_FS 0x1f 77 #define OP_SH_FS 11 78 #define OP_MASK_PREFX 0x1f 79 #define OP_SH_PREFX 11 80 #define OP_MASK_CCC 0x7 81 #define OP_SH_CCC 8 82 #define OP_MASK_SYSCALL 0xfffff 83 #define OP_SH_SYSCALL 6 84 #define OP_MASK_SHAMT 0x1f 85 #define OP_SH_SHAMT 6 86 #define OP_MASK_FD 0x1f 87 #define OP_SH_FD 6 88 #define OP_MASK_TARGET 0x3ffffff 89 #define OP_SH_TARGET 0 90 #define OP_MASK_COPZ 0x1ffffff 91 #define OP_SH_COPZ 0 92 #define OP_MASK_IMMEDIATE 0xffff 93 #define OP_SH_IMMEDIATE 0 94 #define OP_MASK_DELTA 0xffff 95 #define OP_SH_DELTA 0 96 #define OP_MASK_FUNCT 0x3f 97 #define OP_SH_FUNCT 0 98 #define OP_MASK_SPEC 0x3f 99 #define OP_SH_SPEC 0 100 #define OP_SH_LOCC 8 /* FP condition code */ 101 #define OP_SH_HICC 18 /* FP condition code */ 102 #define OP_MASK_CC 0x7 103 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding */ 104 #define OP_MASK_COP1NORM 0x1 /* a single bit */ 105 #define OP_SH_COP1SPEC 21 /* COP1 encodings */ 106 #define OP_MASK_COP1SPEC 0xf 107 #define OP_MASK_COP1SCLR 0x4 108 #define OP_MASK_COP1CMP 0x3 109 #define OP_SH_COP1CMP 4 110 #define OP_SH_FORMAT 21 /* FP short format field */ 111 #define OP_MASK_FORMAT 0x7 112 #define OP_SH_TRUE 16 113 #define OP_MASK_TRUE 0x1 114 #define OP_SH_GE 17 115 #define OP_MASK_GE 0x01 116 #define OP_SH_UNSIGNED 16 117 #define OP_MASK_UNSIGNED 0x1 118 #define OP_SH_HINT 16 119 #define OP_MASK_HINT 0x1f 120 #define OP_SH_MMI 0 /* Multimedia (parallel) op */ 121 #define OP_MASK_MMI 0x3f 122 #define OP_SH_MMISUB 6 123 #define OP_MASK_MMISUB 0x1f 124 #define OP_MASK_PERFREG 0x1f /* Performance monitoring */ 125 #define OP_SH_PERFREG 1 126 127 /* This structure holds information for a particular instruction. */ 128 129 struct mips_opcode 130 { 131 /* The name of the instruction. */ 132 const char *name; 133 /* A string describing the arguments for this instruction. */ 134 const char *args; 135 /* The basic opcode for the instruction. When assembling, this 136 opcode is modified by the arguments to produce the actual opcode 137 that is used. If pinfo is INSN_MACRO, then this is 0. */ 138 unsigned long match; 139 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 140 relevant portions of the opcode when disassembling. If the 141 actual opcode anded with the match field equals the opcode field, 142 then we have found the correct instruction. If pinfo is 143 INSN_MACRO, then this field is the macro identifier. */ 144 unsigned long mask; 145 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 146 of bits describing the instruction, notably any relevant hazard 147 information. */ 148 unsigned long pinfo; 149 /* A collection of bits describing the instruction sets of which this 150 instruction or macro is a member. */ 151 unsigned long membership; 152 }; 153 154 /* These are the characters which may appears in the args field of an 155 instruction. They appear in the order in which the fields appear 156 when the instruction is used. Commas and parentheses in the args 157 string are ignored when assembling, and written into the output 158 when disassembling. 159 160 Each of these characters corresponds to a mask field defined above. 161 162 "<" 5 bit shift amount (OP_*_SHAMT) 163 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 164 "a" 26 bit target address (OP_*_TARGET) 165 "b" 5 bit base register (OP_*_RS) 166 "c" 10 bit breakpoint code (OP_*_CODE) 167 "d" 5 bit destination register specifier (OP_*_RD) 168 "h" 5 bit prefx hint (OP_*_PREFX) 169 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 170 "j" 16 bit signed immediate (OP_*_DELTA) 171 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 172 "o" 16 bit signed offset (OP_*_DELTA) 173 "p" 16 bit PC relative branch target address (OP_*_DELTA) 174 "r" 5 bit same register used as both source and target (OP_*_RS) 175 "s" 5 bit source register specifier (OP_*_RS) 176 "t" 5 bit target register (OP_*_RT) 177 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 178 "v" 5 bit same register used as both source and destination (OP_*_RS) 179 "w" 5 bit same register used as both target and destination (OP_*_RT) 180 "C" 25 bit coprocessor function code (OP_*_COPZ) 181 "B" 20 bit syscall function code (OP_*_SYSCALL) 182 "x" accept and ignore register name 183 "z" must be zero register 184 185 Floating point instructions: 186 "D" 5 bit destination register (OP_*_FD) 187 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 188 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 189 "S" 5 bit fs source 1 register (OP_*_FS) 190 "T" 5 bit ft source 2 register (OP_*_FT) 191 "R" 5 bit fr source 3 register (OP_*_FR) 192 "V" 5 bit same register used as floating source and destination (OP_*_FS) 193 "W" 5 bit same register used as floating target and destination (OP_*_FT) 194 195 Coprocessor instructions: 196 "E" 5 bit target register (OP_*_RT) 197 "G" 5 bit destination register (OP_*_RD) 198 "P" 5 bit performance-monitor register (OP_*_PERFREG) 199 200 Macro instructions: 201 "A" General 32 bit expression 202 "I" 32 bit immediate 203 "F" 64 bit floating point constant in .rdata 204 "L" 64 bit floating point constant in .lit8 205 "f" 32 bit floating point constant 206 "l" 32 bit floating point constant in .lit4 207 208 Other: 209 "()" parens surrounding optional value 210 "," separates operands 211 212 Characters used so far, for quick reference when adding more: 213 "<>()," 214 "ABCDEFGILMNSTRVW" 215 "abcdfhijkloprstuvwxz" 216 */ 217 218 /* These are the bits which may be set in the pinfo field of an 219 instructions, if it is not equal to INSN_MACRO. */ 220 221 /* Modifies the general purpose register in OP_*_RD. */ 222 #define INSN_WRITE_GPR_D 0x00000001 223 /* Modifies the general purpose register in OP_*_RT. */ 224 #define INSN_WRITE_GPR_T 0x00000002 225 /* Modifies general purpose register 31. */ 226 #define INSN_WRITE_GPR_31 0x00000004 227 /* Modifies the floating point register in OP_*_FD. */ 228 #define INSN_WRITE_FPR_D 0x00000008 229 /* Modifies the floating point register in OP_*_FS. */ 230 #define INSN_WRITE_FPR_S 0x00000010 231 /* Modifies the floating point register in OP_*_FT. */ 232 #define INSN_WRITE_FPR_T 0x00000020 233 /* Reads the general purpose register in OP_*_RS. */ 234 #define INSN_READ_GPR_S 0x00000040 235 /* Reads the general purpose register in OP_*_RT. */ 236 #define INSN_READ_GPR_T 0x00000080 237 /* Reads the floating point register in OP_*_FS. */ 238 #define INSN_READ_FPR_S 0x00000100 239 /* Reads the floating point register in OP_*_FT. */ 240 #define INSN_READ_FPR_T 0x00000200 241 /* Reads the floating point register in OP_*_FR. */ 242 #define INSN_READ_FPR_R 0x00000400 243 /* Modifies coprocessor condition code. */ 244 #define INSN_WRITE_COND_CODE 0x00000800 245 /* Reads coprocessor condition code. */ 246 #define INSN_READ_COND_CODE 0x00001000 247 /* TLB operation. */ 248 #define INSN_TLB 0x00002000 249 /* Reads coprocessor register other than floating point register. */ 250 #define INSN_COP 0x00004000 251 /* Instruction loads value from memory, requiring delay. */ 252 #define INSN_LOAD_MEMORY_DELAY 0x00008000 253 /* Instruction loads value from coprocessor, requiring delay. */ 254 #define INSN_LOAD_COPROC_DELAY 0x00010000 255 /* Instruction has unconditional branch delay slot. */ 256 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 257 /* Instruction has conditional branch delay slot. */ 258 #define INSN_COND_BRANCH_DELAY 0x00040000 259 /* Conditional branch likely: if branch not taken, insn nullified. */ 260 #define INSN_COND_BRANCH_LIKELY 0x00080000 261 /* Moves to coprocessor register, requiring delay. */ 262 #define INSN_COPROC_MOVE_DELAY 0x00100000 263 /* Loads coprocessor register from memory, requiring delay. */ 264 #define INSN_COPROC_MEMORY_DELAY 0x00200000 265 /* Reads the HI register. */ 266 #define INSN_READ_HI 0x00400000 267 /* Reads the LO register. */ 268 #define INSN_READ_LO 0x00800000 269 /* Modifies the HI register. */ 270 #define INSN_WRITE_HI 0x01000000 271 /* Modifies the LO register. */ 272 #define INSN_WRITE_LO 0x02000000 273 /* Takes a trap (easier to keep out of delay slot). */ 274 #define INSN_TRAP 0x04000000 275 /* Instruction stores value into memory. */ 276 #define INSN_STORE_MEMORY 0x08000000 277 /* Instruction uses single precision floating point. */ 278 #define FP_S 0x10000000 279 /* Instruction uses double precision floating point. */ 280 #define FP_D 0x20000000 281 282 /* As yet unused bits: 0x40000000 */ 283 284 /* Instruction is actually a macro. It should be ignored by the 285 disassembler, and requires special treatment by the assembler. */ 286 #define INSN_MACRO 0xffffffff 287 288 289 290 291 292 /* MIPS ISA field--CPU level at which insn is supported. */ 293 #define INSN_ISA 0x0000000F 294 /* An instruction which is not part of any basic MIPS ISA. 295 (ie it is a chip specific instruction) */ 296 #define INSN_NO_ISA 0x00000000 297 /* MIPS ISA 1 instruction. */ 298 #define INSN_ISA1 0x00000001 299 /* MIPS ISA 2 instruction (R6000 or R4000). */ 300 #define INSN_ISA2 0x00000002 301 /* MIPS ISA 3 instruction (R4000). */ 302 #define INSN_ISA3 0x00000003 303 /* MIPS ISA 4 instruction (R8000). */ 304 #define INSN_ISA4 0x00000004 305 306 /* Chip specific instructions. These are bitmasks. */ 307 /* MIPS R4650 instruction. */ 308 #define INSN_4650 0x00000010 309 /* LSI R4010 instruction. */ 310 #define INSN_4010 0x00000020 311 /* NEC VR4100 instruction. */ 312 #define INSN_4100 0x00000040 313 /* Toshiba R3900 instruction. */ 314 #define INSN_3900 0x00000080 315 316 317 /* This is a list of macro expanded instructions. 318 * 319 * _I appended means immediate 320 * _A appended means address 321 * _AB appended means address with base register 322 * _D appended means 64 bit floating point constant 323 * _S appended means 32 bit floating point constant 324 */ 325 enum { 326 M_ABS, 327 M_ADD_I, 328 M_ADDU_I, 329 M_AND_I, 330 M_BEQ, 331 M_BEQ_I, 332 M_BEQL_I, 333 M_BGE, 334 M_BGEL, 335 M_BGE_I, 336 M_BGEL_I, 337 M_BGEU, 338 M_BGEUL, 339 M_BGEU_I, 340 M_BGEUL_I, 341 M_BGT, 342 M_BGTL, 343 M_BGT_I, 344 M_BGTL_I, 345 M_BGTU, 346 M_BGTUL, 347 M_BGTU_I, 348 M_BGTUL_I, 349 M_BLE, 350 M_BLEL, 351 M_BLE_I, 352 M_BLEL_I, 353 M_BLEU, 354 M_BLEUL, 355 M_BLEU_I, 356 M_BLEUL_I, 357 M_BLT, 358 M_BLTL, 359 M_BLT_I, 360 M_BLTL_I, 361 M_BLTU, 362 M_BLTUL, 363 M_BLTU_I, 364 M_BLTUL_I, 365 M_BNE, 366 M_BNE_I, 367 M_BNEL_I, 368 M_DABS, 369 M_DADD_I, 370 M_DADDU_I, 371 M_DDIV_3, 372 M_DDIV_3I, 373 M_DDIVU_3, 374 M_DDIVU_3I, 375 M_DIV_3, 376 M_DIV_3I, 377 M_DIVU_3, 378 M_DIVU_3I, 379 M_DLA_AB, 380 M_DLI, 381 M_DMUL, 382 M_DMUL_I, 383 M_DMULO, 384 M_DMULO_I, 385 M_DMULOU, 386 M_DMULOU_I, 387 M_DREM_3, 388 M_DREM_3I, 389 M_DREMU_3, 390 M_DREMU_3I, 391 M_DSUB_I, 392 M_DSUBU_I, 393 M_DSUBU_I_2, 394 M_J_A, 395 M_JAL_1, 396 M_JAL_2, 397 M_JAL_A, 398 M_L_DOB, 399 M_L_DAB, 400 M_LA_AB, 401 M_LB_A, 402 M_LB_AB, 403 M_LBU_A, 404 M_LBU_AB, 405 M_LD_A, 406 M_LD_OB, 407 M_LD_AB, 408 M_LDC1_AB, 409 M_LDC2_AB, 410 M_LDC3_AB, 411 M_LDL_AB, 412 M_LDR_AB, 413 M_LH_A, 414 M_LH_AB, 415 M_LHU_A, 416 M_LHU_AB, 417 M_LI, 418 M_LI_D, 419 M_LI_DD, 420 M_LI_S, 421 M_LI_SS, 422 M_LL_AB, 423 M_LLD_AB, 424 M_LS_A, 425 M_LW_A, 426 M_LW_AB, 427 M_LWC0_A, 428 M_LWC0_AB, 429 M_LWC1_A, 430 M_LWC1_AB, 431 M_LWC2_A, 432 M_LWC2_AB, 433 M_LWC3_A, 434 M_LWC3_AB, 435 M_LWL_A, 436 M_LWL_AB, 437 M_LWR_A, 438 M_LWR_AB, 439 M_LWU_AB, 440 M_MUL, 441 M_MUL_I, 442 M_MULO, 443 M_MULO_I, 444 M_MULOU, 445 M_MULOU_I, 446 M_NOR_I, 447 M_OR_I, 448 M_REM_3, 449 M_REM_3I, 450 M_REMU_3, 451 M_REMU_3I, 452 M_ROL, 453 M_ROL_I, 454 M_ROR, 455 M_ROR_I, 456 M_S_DA, 457 M_S_DOB, 458 M_S_DAB, 459 M_S_S, 460 M_SC_AB, 461 M_SCD_AB, 462 M_SD_A, 463 M_SD_OB, 464 M_SD_AB, 465 M_SDC1_AB, 466 M_SDC2_AB, 467 M_SDC3_AB, 468 M_SDL_AB, 469 M_SDR_AB, 470 M_SEQ, 471 M_SEQ_I, 472 M_SGE, 473 M_SGE_I, 474 M_SGEU, 475 M_SGEU_I, 476 M_SGT, 477 M_SGT_I, 478 M_SGTU, 479 M_SGTU_I, 480 M_SLE, 481 M_SLE_I, 482 M_SLEU, 483 M_SLEU_I, 484 M_SLT_I, 485 M_SLTU_I, 486 M_SNE, 487 M_SNE_I, 488 M_SB_A, 489 M_SB_AB, 490 M_SH_A, 491 M_SH_AB, 492 M_SW_A, 493 M_SW_AB, 494 M_SWC0_A, 495 M_SWC0_AB, 496 M_SWC1_A, 497 M_SWC1_AB, 498 M_SWC2_A, 499 M_SWC2_AB, 500 M_SWC3_A, 501 M_SWC3_AB, 502 M_SWL_A, 503 M_SWL_AB, 504 M_SWR_A, 505 M_SWR_AB, 506 M_SUB_I, 507 M_SUBU_I, 508 M_SUBU_I_2, 509 M_TEQ_I, 510 M_TGE_I, 511 M_TGEU_I, 512 M_TLT_I, 513 M_TLTU_I, 514 M_TNE_I, 515 M_TRUNCWD, 516 M_TRUNCWS, 517 M_ULD, 518 M_ULD_A, 519 M_ULH, 520 M_ULH_A, 521 M_ULHU, 522 M_ULHU_A, 523 M_ULW, 524 M_ULW_A, 525 M_USH, 526 M_USH_A, 527 M_USW, 528 M_USW_A, 529 M_USD, 530 M_USD_A, 531 M_XOR_I, 532 M_COP0, 533 M_COP1, 534 M_COP2, 535 M_COP3, 536 M_NUM_MACROS 537 }; 538 539 540 /* The order of overloaded instructions matters. Label arguments and 541 register arguments look the same. Instructions that can have either 542 for arguments must apear in the correct order in this table for the 543 assembler to pick the right one. In other words, entries with 544 immediate operands must apear after the same instruction with 545 registers. 546 547 Many instructions are short hand for other instructions (i.e., The 548 jal <register> instruction is short for jalr <register>). */ 549 550 extern const struct mips_opcode mips_builtin_opcodes[]; 551 extern const int bfd_mips_num_builtin_opcodes; 552 extern struct mips_opcode *mips_opcodes; 553 extern int bfd_mips_num_opcodes; 554 #define NUMOPCODES bfd_mips_num_opcodes 555 556 557 /* The rest of this file adds definitions for the mips16 TinyRISC 558 processor. */ 559 560 /* These are the bitmasks and shift counts used for the different 561 fields in the instruction formats. Other than OP, no masks are 562 provided for the fixed portions of an instruction, since they are 563 not needed. 564 565 The I format uses IMM11. 566 567 The RI format uses RX and IMM8. 568 569 The RR format uses RX, and RY. 570 571 The RRI format uses RX, RY, and IMM5. 572 573 The RRR format uses RX, RY, and RZ. 574 575 The RRI_A format uses RX, RY, and IMM4. 576 577 The SHIFT format uses RX, RY, and SHAMT. 578 579 The I8 format uses IMM8. 580 581 The I8_MOVR32 format uses RY and REGR32. 582 583 The IR_MOV32R format uses REG32R and MOV32Z. 584 585 The I64 format uses IMM8. 586 587 The RI64 format uses RY and IMM5. 588 */ 589 590 #define MIPS16OP_MASK_OP 0x1f 591 #define MIPS16OP_SH_OP 11 592 #define MIPS16OP_MASK_IMM11 0x7ff 593 #define MIPS16OP_SH_IMM11 0 594 #define MIPS16OP_MASK_RX 0x7 595 #define MIPS16OP_SH_RX 8 596 #define MIPS16OP_MASK_IMM8 0xff 597 #define MIPS16OP_SH_IMM8 0 598 #define MIPS16OP_MASK_RY 0x7 599 #define MIPS16OP_SH_RY 5 600 #define MIPS16OP_MASK_IMM5 0x1f 601 #define MIPS16OP_SH_IMM5 0 602 #define MIPS16OP_MASK_RZ 0x7 603 #define MIPS16OP_SH_RZ 2 604 #define MIPS16OP_MASK_IMM4 0xf 605 #define MIPS16OP_SH_IMM4 0 606 #define MIPS16OP_MASK_REGR32 0x1f 607 #define MIPS16OP_SH_REGR32 0 608 #define MIPS16OP_MASK_REG32R 0x1f 609 #define MIPS16OP_SH_REG32R 3 610 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 611 #define MIPS16OP_MASK_MOVE32Z 0x7 612 #define MIPS16OP_SH_MOVE32Z 0 613 #define MIPS16OP_MASK_IMM6 0x3f 614 #define MIPS16OP_SH_IMM6 5 615 616 /* These are the characters which may appears in the args field of an 617 instruction. They appear in the order in which the fields appear 618 when the instruction is used. Commas and parentheses in the args 619 string are ignored when assembling, and written into the output 620 when disassembling. 621 622 "y" 3 bit register (MIPS16OP_*_RY) 623 "x" 3 bit register (MIPS16OP_*_RX) 624 "z" 3 bit register (MIPS16OP_*_RZ) 625 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 626 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 627 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 628 "0" zero register ($0) 629 "S" stack pointer ($sp or $29) 630 "P" program counter 631 "R" return address register ($ra or $31) 632 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 633 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 634 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 635 "a" 26 bit jump address 636 "e" 11 bit extension value 637 "l" register list for entry instruction 638 "L" register list for exit instruction 639 640 The remaining codes may be extended. Except as otherwise noted, 641 the full extended operand is a 16 bit signed value. 642 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 643 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 644 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 645 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 646 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 647 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 648 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 649 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 650 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 651 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 652 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 653 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 654 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 655 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 656 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 657 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 658 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 659 "q" 11 bit branch address (MIPS16OP_*_IMM11) 660 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 661 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 662 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 663 */ 664 665 /* For the mips16, we use the same opcode table format and a few of 666 the same flags. However, most of the flags are different. */ 667 668 /* Modifies the register in MIPS16OP_*_RX. */ 669 #define MIPS16_INSN_WRITE_X 0x00000001 670 /* Modifies the register in MIPS16OP_*_RY. */ 671 #define MIPS16_INSN_WRITE_Y 0x00000002 672 /* Modifies the register in MIPS16OP_*_RZ. */ 673 #define MIPS16_INSN_WRITE_Z 0x00000004 674 /* Modifies the T ($24) register. */ 675 #define MIPS16_INSN_WRITE_T 0x00000008 676 /* Modifies the SP ($29) register. */ 677 #define MIPS16_INSN_WRITE_SP 0x00000010 678 /* Modifies the RA ($31) register. */ 679 #define MIPS16_INSN_WRITE_31 0x00000020 680 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 681 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 682 /* Reads the register in MIPS16OP_*_RX. */ 683 #define MIPS16_INSN_READ_X 0x00000080 684 /* Reads the register in MIPS16OP_*_RY. */ 685 #define MIPS16_INSN_READ_Y 0x00000100 686 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 687 #define MIPS16_INSN_READ_Z 0x00000200 688 /* Reads the T ($24) register. */ 689 #define MIPS16_INSN_READ_T 0x00000400 690 /* Reads the SP ($29) register. */ 691 #define MIPS16_INSN_READ_SP 0x00000800 692 /* Reads the RA ($31) register. */ 693 #define MIPS16_INSN_READ_31 0x00001000 694 /* Reads the program counter. */ 695 #define MIPS16_INSN_READ_PC 0x00002000 696 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 697 #define MIPS16_INSN_READ_GPR_X 0x00004000 698 699 /* The following flags have the same value for the mips16 opcode 700 table: 701 INSN_UNCOND_BRANCH_DELAY 702 INSN_COND_BRANCH_DELAY 703 INSN_COND_BRANCH_LIKELY (never used) 704 INSN_READ_HI 705 INSN_READ_LO 706 INSN_WRITE_HI 707 INSN_WRITE_LO 708 INSN_TRAP 709 INSN_ISA3 710 */ 711 712 extern const struct mips_opcode mips16_opcodes[]; 713 extern const int bfd_mips16_num_opcodes; 714 715 #endif /* _MIPS_H_ */ 716