1 /* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003, 2004, 2005 4 Free Software Foundation, Inc. 5 Contributed by Ralph Campbell and OSF 6 Commented and modified by Ian Lance Taylor, Cygnus Support 7 8 This file is part of GDB, GAS, and the GNU binutils. 9 10 GDB, GAS, and the GNU binutils are free software; you can redistribute 11 them and/or modify them under the terms of the GNU General Public 12 License as published by the Free Software Foundation; either version 13 1, or (at your option) any later version. 14 15 GDB, GAS, and the GNU binutils are distributed in the hope that they 16 will be useful, but WITHOUT ANY WARRANTY; without even the implied 17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 18 the GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this file; see the file COPYING. If not, write to the Free 22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23 24 #ifndef _MIPS_H_ 25 #define _MIPS_H_ 26 27 /* These are bit masks and shift counts to use to access the various 28 fields of an instruction. To retrieve the X field of an 29 instruction, use the expression 30 (i >> OP_SH_X) & OP_MASK_X 31 To set the same field (to j), use 32 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 33 34 Make sure you use fields that are appropriate for the instruction, 35 of course. 36 37 The 'i' format uses OP, RS, RT and IMMEDIATE. 38 39 The 'j' format uses OP and TARGET. 40 41 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 42 43 The 'b' format uses OP, RS, RT and DELTA. 44 45 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 46 47 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 48 49 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 50 breakpoint instruction are not defined; Kane says the breakpoint 51 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 52 only use ten bits). An optional two-operand form of break/sdbbp 53 allows the lower ten bits to be set too, and MIPS32 and later 54 architectures allow 20 bits to be set with a signal operand 55 (using CODE20). 56 57 The syscall instruction uses CODE20. 58 59 The general coprocessor instructions use COPZ. */ 60 61 #define OP_MASK_OP 0x3f 62 #define OP_SH_OP 26 63 #define OP_MASK_RS 0x1f 64 #define OP_SH_RS 21 65 #define OP_MASK_FR 0x1f 66 #define OP_SH_FR 21 67 #define OP_MASK_FMT 0x1f 68 #define OP_SH_FMT 21 69 #define OP_MASK_BCC 0x7 70 #define OP_SH_BCC 18 71 #define OP_MASK_CODE 0x3ff 72 #define OP_SH_CODE 16 73 #define OP_MASK_CODE2 0x3ff 74 #define OP_SH_CODE2 6 75 #define OP_MASK_RT 0x1f 76 #define OP_SH_RT 16 77 #define OP_MASK_FT 0x1f 78 #define OP_SH_FT 16 79 #define OP_MASK_CACHE 0x1f 80 #define OP_SH_CACHE 16 81 #define OP_MASK_RD 0x1f 82 #define OP_SH_RD 11 83 #define OP_MASK_FS 0x1f 84 #define OP_SH_FS 11 85 #define OP_MASK_PREFX 0x1f 86 #define OP_SH_PREFX 11 87 #define OP_MASK_CCC 0x7 88 #define OP_SH_CCC 8 89 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 90 #define OP_SH_CODE20 6 91 #define OP_MASK_SHAMT 0x1f 92 #define OP_SH_SHAMT 6 93 #define OP_MASK_BITIND OP_MASK_RT 94 #define OP_SH_BITIND OP_SH_RT 95 #define OP_MASK_FD 0x1f 96 #define OP_SH_FD 6 97 #define OP_MASK_TARGET 0x3ffffff 98 #define OP_SH_TARGET 0 99 #define OP_MASK_COPZ 0x1ffffff 100 #define OP_SH_COPZ 0 101 #define OP_MASK_IMMEDIATE 0xffff 102 #define OP_SH_IMMEDIATE 0 103 #define OP_MASK_DELTA 0xffff 104 #define OP_SH_DELTA 0 105 #define OP_MASK_FUNCT 0x3f 106 #define OP_SH_FUNCT 0 107 #define OP_MASK_SPEC 0x3f 108 #define OP_SH_SPEC 0 109 #define OP_SH_LOCC 8 /* FP condition code. */ 110 #define OP_SH_HICC 18 /* FP condition code. */ 111 #define OP_MASK_CC 0x7 112 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 113 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 114 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 115 #define OP_MASK_COP1SPEC 0xf 116 #define OP_MASK_COP1SCLR 0x4 117 #define OP_MASK_COP1CMP 0x3 118 #define OP_SH_COP1CMP 4 119 #define OP_SH_FORMAT 21 /* FP short format field. */ 120 #define OP_MASK_FORMAT 0x7 121 #define OP_SH_TRUE 16 122 #define OP_MASK_TRUE 0x1 123 #define OP_SH_GE 17 124 #define OP_MASK_GE 0x01 125 #define OP_SH_UNSIGNED 16 126 #define OP_MASK_UNSIGNED 0x1 127 #define OP_SH_HINT 16 128 #define OP_MASK_HINT 0x1f 129 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 130 #define OP_MASK_MMI 0x3f 131 #define OP_SH_MMISUB 6 132 #define OP_MASK_MMISUB 0x1f 133 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 134 #define OP_SH_PERFREG 1 135 #define OP_SH_SEL 0 /* Coprocessor select field. */ 136 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 137 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 138 #define OP_MASK_CODE19 0x7ffff 139 #define OP_SH_ALN 21 140 #define OP_MASK_ALN 0x7 141 #define OP_SH_VSEL 21 142 #define OP_MASK_VSEL 0x1f 143 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 144 but 0x8-0xf don't select bytes. */ 145 #define OP_SH_VECBYTE 22 146 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 147 #define OP_SH_VECALIGN 21 148 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 149 #define OP_SH_INSMSB 11 150 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 151 #define OP_SH_EXTMSBD 11 152 153 /* MIPS DSP ASE */ 154 #define OP_SH_DSPACC 11 155 #define OP_MASK_DSPACC 0x3 156 #define OP_SH_DSPACC_S 21 157 #define OP_MASK_DSPACC_S 0x3 158 #define OP_SH_DSPSFT 20 159 #define OP_MASK_DSPSFT 0x3f 160 #define OP_SH_DSPSFT_7 19 161 #define OP_MASK_DSPSFT_7 0x7f 162 #define OP_SH_SA3 21 163 #define OP_MASK_SA3 0x7 164 #define OP_SH_SA4 21 165 #define OP_MASK_SA4 0xf 166 #define OP_SH_IMM8 16 167 #define OP_MASK_IMM8 0xff 168 #define OP_SH_IMM10 16 169 #define OP_MASK_IMM10 0x3ff 170 #define OP_SH_WRDSP 11 171 #define OP_MASK_WRDSP 0x3f 172 #define OP_SH_RDDSP 16 173 #define OP_MASK_RDDSP 0x3f 174 #define OP_SH_BP 11 175 #define OP_MASK_BP 0x3 176 177 /* MIPS MT ASE */ 178 #define OP_SH_MT_U 5 179 #define OP_MASK_MT_U 0x1 180 #define OP_SH_MT_H 4 181 #define OP_MASK_MT_H 0x1 182 #define OP_SH_MTACC_T 18 183 #define OP_MASK_MTACC_T 0x3 184 #define OP_SH_MTACC_D 13 185 #define OP_MASK_MTACC_D 0x3 186 187 #define OP_OP_COP0 0x10 188 #define OP_OP_COP1 0x11 189 #define OP_OP_COP2 0x12 190 #define OP_OP_COP3 0x13 191 #define OP_OP_LWC1 0x31 192 #define OP_OP_LWC2 0x32 193 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 194 #define OP_OP_LDC1 0x35 195 #define OP_OP_LDC2 0x36 196 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 197 #define OP_OP_SWC1 0x39 198 #define OP_OP_SWC2 0x3a 199 #define OP_OP_SWC3 0x3b 200 #define OP_OP_SDC1 0x3d 201 #define OP_OP_SDC2 0x3e 202 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 203 204 /* Values in the 'VSEL' field. */ 205 #define MDMX_FMTSEL_IMM_QH 0x1d 206 #define MDMX_FMTSEL_IMM_OB 0x1e 207 #define MDMX_FMTSEL_VEC_QH 0x15 208 #define MDMX_FMTSEL_VEC_OB 0x16 209 210 /* UDI */ 211 #define OP_SH_UDI1 6 212 #define OP_MASK_UDI1 0x1f 213 #define OP_SH_UDI2 6 214 #define OP_MASK_UDI2 0x3ff 215 #define OP_SH_UDI3 6 216 #define OP_MASK_UDI3 0x7fff 217 #define OP_SH_UDI4 6 218 #define OP_MASK_UDI4 0xfffff 219 220 /* This structure holds information for a particular instruction. */ 221 222 struct mips_opcode 223 { 224 /* The name of the instruction. */ 225 const char *name; 226 /* A string describing the arguments for this instruction. */ 227 const char *args; 228 /* The basic opcode for the instruction. When assembling, this 229 opcode is modified by the arguments to produce the actual opcode 230 that is used. If pinfo is INSN_MACRO, then this is 0. */ 231 unsigned long match; 232 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 233 relevant portions of the opcode when disassembling. If the 234 actual opcode anded with the match field equals the opcode field, 235 then we have found the correct instruction. If pinfo is 236 INSN_MACRO, then this field is the macro identifier. */ 237 unsigned long mask; 238 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 239 of bits describing the instruction, notably any relevant hazard 240 information. */ 241 unsigned long pinfo; 242 /* A collection of additional bits describing the instruction. */ 243 unsigned long pinfo2; 244 /* A collection of bits describing the instruction sets of which this 245 instruction or macro is a member. */ 246 unsigned long membership; 247 }; 248 249 /* These are the characters which may appear in the args field of an 250 instruction. They appear in the order in which the fields appear 251 when the instruction is used. Commas and parentheses in the args 252 string are ignored when assembling, and written into the output 253 when disassembling. 254 255 Each of these characters corresponds to a mask field defined above. 256 257 "<" 5 bit shift amount (OP_*_SHAMT) 258 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 259 "^" 5 bit bit index amount (OP_*_BITIND) 260 "~" bit index between 32 and 63, stored after subtracting 32 (OP_*_BITIND) 261 "a" 26 bit target address (OP_*_TARGET) 262 "b" 5 bit base register (OP_*_RS) 263 "c" 10 bit breakpoint code (OP_*_CODE) 264 "d" 5 bit destination register specifier (OP_*_RD) 265 "h" 5 bit prefx hint (OP_*_PREFX) 266 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 267 "j" 16 bit signed immediate (OP_*_DELTA) 268 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 269 Also used for immediate operands in vr5400 vector insns. 270 "o" 16 bit signed offset (OP_*_DELTA) 271 "p" 16 bit PC relative branch target address (OP_*_DELTA) 272 "q" 10 bit extra breakpoint code (OP_*_CODE2) 273 "r" 5 bit same register used as both source and target (OP_*_RS) 274 "s" 5 bit source register specifier (OP_*_RS) 275 "t" 5 bit target register (OP_*_RT) 276 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 277 "v" 5 bit same register used as both source and destination (OP_*_RS) 278 "w" 5 bit same register used as both target and destination (OP_*_RT) 279 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 280 (used by clo and clz) 281 "C" 25 bit coprocessor function code (OP_*_COPZ) 282 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 283 "J" 19 bit wait function code (OP_*_CODE19) 284 "x" accept and ignore register name 285 "y" 10 bit signed const (OP_*_CODE2) 286 "z" must be zero register 287 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 288 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 289 LSB (OP_*_SHAMT). 290 Enforces: 0 <= pos < 32. 291 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 292 Requires that "+A" or "+E" occur first to set position. 293 Enforces: 0 < (pos+size) <= 32. 294 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 295 Requires that "+A" or "+E" occur first to set position. 296 Enforces: 0 < (pos+size) <= 32. 297 (Also used by "dext" w/ different limits, but limits for 298 that are checked by the M_DEXT macro.) 299 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 300 Enforces: 32 <= pos < 64. 301 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 302 Requires that "+A" or "+E" occur first to set position. 303 Enforces: 32 < (pos+size) <= 64. 304 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 305 Requires that "+A" or "+E" occur first to set position. 306 Enforces: 32 < (pos+size) <= 64. 307 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 308 Requires that "+A" or "+E" occur first to set position. 309 Enforces: 32 < (pos+size) <= 64. 310 311 Floating point instructions: 312 "D" 5 bit destination register (OP_*_FD) 313 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 314 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 315 "S" 5 bit fs source 1 register (OP_*_FS) 316 "T" 5 bit ft source 2 register (OP_*_FT) 317 "R" 5 bit fr source 3 register (OP_*_FR) 318 "V" 5 bit same register used as floating source and destination (OP_*_FS) 319 "W" 5 bit same register used as floating target and destination (OP_*_FT) 320 321 Coprocessor instructions: 322 "E" 5 bit target register (OP_*_RT) 323 "G" 5 bit destination register (OP_*_RD) 324 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 325 "P" 5 bit performance-monitor register (OP_*_PERFREG) 326 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 327 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 328 see also "k" above 329 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 330 for pretty-printing in disassembly only. 331 332 Macro instructions: 333 "A" General 32 bit expression 334 "I" 32 bit immediate (value placed in imm_expr). 335 "+I" 32 bit immediate (value placed in imm2_expr). 336 "F" 64 bit floating point constant in .rdata 337 "L" 64 bit floating point constant in .lit8 338 "f" 32 bit floating point constant 339 "l" 32 bit floating point constant in .lit4 340 341 MDMX instruction operands (note that while these use the FP register 342 fields, they accept both $fN and $vN names for the registers): 343 "O" MDMX alignment offset (OP_*_ALN) 344 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 345 "X" MDMX destination register (OP_*_FD) 346 "Y" MDMX source register (OP_*_FS) 347 "Z" MDMX source register (OP_*_FT) 348 349 DSP ASE usage: 350 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 351 "3" 3 bit unsigned immediate (OP_*_SA3) 352 "4" 4 bit unsigned immediate (OP_*_SA4) 353 "5" 8 bit unsigned immediate (OP_*_IMM8) 354 "6" 5 bit unsigned immediate (OP_*_RS) 355 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 356 "8" 6 bit unsigned immediate (OP_*_WRDSP) 357 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 358 "0" 6 bit signed immediate (OP_*_DSPSFT) 359 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 360 "'" 6 bit unsigned immediate (OP_*_RDDSP) 361 "@" 10 bit signed immediate (OP_*_IMM10) 362 363 MT ASE usage: 364 "!" 1 bit usermode flag (OP_*_MT_U) 365 "$" 1 bit load high flag (OP_*_MT_H) 366 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 367 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 368 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 369 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 370 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only 371 372 UDI immediates: 373 "+1" UDI immediate bits 6-10 374 "+2" UDI immediate bits 6-15 375 "+3" UDI immediate bits 6-20 376 "+4" UDI immediate bits 6-25 377 378 Other: 379 "()" parens surrounding optional value 380 "," separates operands 381 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 382 "+" Start of extension sequence. 383 384 Characters used so far, for quick reference when adding more: 385 "234567890" 386 "%[]<>(),+:'@!$*&^~" 387 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 388 "abcdefghijklopqrstuvwxyz" 389 390 Extension character sequences used so far ("+" followed by the 391 following), for quick reference when adding more: 392 "1234" 393 "ABCDEFGHIT" 394 "t" 395 */ 396 397 /* These are the bits which may be set in the pinfo field of an 398 instructions, if it is not equal to INSN_MACRO. */ 399 400 /* Modifies the general purpose register in OP_*_RD. */ 401 #define INSN_WRITE_GPR_D 0x00000001 402 /* Modifies the general purpose register in OP_*_RT. */ 403 #define INSN_WRITE_GPR_T 0x00000002 404 /* Modifies general purpose register 31. */ 405 #define INSN_WRITE_GPR_31 0x00000004 406 /* Modifies the floating point register in OP_*_FD. */ 407 #define INSN_WRITE_FPR_D 0x00000008 408 /* Modifies the floating point register in OP_*_FS. */ 409 #define INSN_WRITE_FPR_S 0x00000010 410 /* Modifies the floating point register in OP_*_FT. */ 411 #define INSN_WRITE_FPR_T 0x00000020 412 /* Reads the general purpose register in OP_*_RS. */ 413 #define INSN_READ_GPR_S 0x00000040 414 /* Reads the general purpose register in OP_*_RT. */ 415 #define INSN_READ_GPR_T 0x00000080 416 /* Reads the floating point register in OP_*_FS. */ 417 #define INSN_READ_FPR_S 0x00000100 418 /* Reads the floating point register in OP_*_FT. */ 419 #define INSN_READ_FPR_T 0x00000200 420 /* Reads the floating point register in OP_*_FR. */ 421 #define INSN_READ_FPR_R 0x00000400 422 /* Modifies coprocessor condition code. */ 423 #define INSN_WRITE_COND_CODE 0x00000800 424 /* Reads coprocessor condition code. */ 425 #define INSN_READ_COND_CODE 0x00001000 426 /* TLB operation. */ 427 #define INSN_TLB 0x00002000 428 /* Reads coprocessor register other than floating point register. */ 429 #define INSN_COP 0x00004000 430 /* Instruction loads value from memory, requiring delay. */ 431 #define INSN_LOAD_MEMORY_DELAY 0x00008000 432 /* Instruction loads value from coprocessor, requiring delay. */ 433 #define INSN_LOAD_COPROC_DELAY 0x00010000 434 /* Instruction has unconditional branch delay slot. */ 435 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 436 /* Instruction has conditional branch delay slot. */ 437 #define INSN_COND_BRANCH_DELAY 0x00040000 438 /* Conditional branch likely: if branch not taken, insn nullified. */ 439 #define INSN_COND_BRANCH_LIKELY 0x00080000 440 /* Moves to coprocessor register, requiring delay. */ 441 #define INSN_COPROC_MOVE_DELAY 0x00100000 442 /* Loads coprocessor register from memory, requiring delay. */ 443 #define INSN_COPROC_MEMORY_DELAY 0x00200000 444 /* Reads the HI register. */ 445 #define INSN_READ_HI 0x00400000 446 /* Reads the LO register. */ 447 #define INSN_READ_LO 0x00800000 448 /* Modifies the HI register. */ 449 #define INSN_WRITE_HI 0x01000000 450 /* Modifies the LO register. */ 451 #define INSN_WRITE_LO 0x02000000 452 /* Takes a trap (easier to keep out of delay slot). */ 453 #define INSN_TRAP 0x04000000 454 /* Instruction stores value into memory. */ 455 #define INSN_STORE_MEMORY 0x08000000 456 /* Instruction uses single precision floating point. */ 457 #define FP_S 0x10000000 458 /* Instruction uses double precision floating point. */ 459 #define FP_D 0x20000000 460 /* Instruction is part of the tx39's integer multiply family. */ 461 #define INSN_MULT 0x40000000 462 /* Instruction synchronize shared memory. */ 463 #define INSN_SYNC 0x80000000 464 465 /* These are the bits which may be set in the pinfo2 field of an 466 instruction. */ 467 468 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 469 #define INSN2_ALIAS 0x00000001 470 /* Instruction reads MDMX accumulator. */ 471 #define INSN2_READ_MDMX_ACC 0x00000002 472 /* Instruction writes MDMX accumulator. */ 473 #define INSN2_WRITE_MDMX_ACC 0x00000004 474 475 /* Instruction is actually a macro. It should be ignored by the 476 disassembler, and requires special treatment by the assembler. */ 477 #define INSN_MACRO 0xffffffff 478 479 /* Masks used to mark instructions to indicate which MIPS ISA level 480 they were introduced in. ISAs, as defined below, are logical 481 ORs of these bits, indicating that they support the instructions 482 defined at the given level. */ 483 484 #define INSN_ISA_MASK 0x00000fff 485 #define INSN_ISA1 0x00000001 486 #define INSN_ISA2 0x00000002 487 #define INSN_ISA3 0x00000004 488 #define INSN_ISA4 0x00000008 489 #define INSN_ISA5 0x00000010 490 #define INSN_ISA32 0x00000020 491 #define INSN_ISA64 0x00000040 492 #define INSN_ISA32R2 0x00000080 493 #define INSN_ISA64R2 0x00000100 494 495 /* Masks used for MIPS-defined ASEs. */ 496 #define INSN_ASE_MASK 0x3c00f000 497 498 /* DSP ASE */ 499 #define INSN_DSP 0x00001000 500 #define INSN_DSP64 0x00002000 501 /* MIPS 16 ASE */ 502 #define INSN_MIPS16 0x00004000 503 /* MIPS-3D ASE */ 504 #define INSN_MIPS3D 0x00008000 505 506 /* Chip specific instructions. These are bitmasks. */ 507 508 /* MIPS R4650 instruction. */ 509 #define INSN_4650 0x00010000 510 /* LSI R4010 instruction. */ 511 #define INSN_4010 0x00020000 512 /* NEC VR4100 instruction. */ 513 #define INSN_4100 0x00040000 514 /* Toshiba R3900 instruction. */ 515 #define INSN_3900 0x00080000 516 /* MIPS R10000 instruction. */ 517 #define INSN_10000 0x00100000 518 /* Broadcom SB-1 instruction. */ 519 #define INSN_SB1 0x00200000 520 /* NEC VR4111/VR4181 instruction. */ 521 #define INSN_4111 0x00400000 522 /* NEC VR4120 instruction. */ 523 #define INSN_4120 0x00800000 524 /* NEC VR5400 instruction. */ 525 #define INSN_5400 0x01000000 526 /* NEC VR5500 instruction. */ 527 #define INSN_5500 0x02000000 528 529 /* MDMX ASE */ 530 #define INSN_MDMX 0x04000000 531 /* MT ASE */ 532 #define INSN_MT 0x08000000 533 /* SmartMIPS ASE */ 534 #define INSN_SMARTMIPS 0x10000000 535 /* DSP R2 ASE */ 536 #define INSN_DSPR2 0x20000000 537 /* Cavium Networks Octeon instruction. */ 538 #define INSN_OCTEON 0x08000000 539 540 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 541 542 #define ISA_UNKNOWN 0 /* Gas internal use. */ 543 #define ISA_MIPS1 (INSN_ISA1) 544 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) 545 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) 546 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) 547 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) 548 549 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) 550 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) 551 552 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) 553 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) 554 555 556 /* CPU defines, use instead of hardcoding processor number. Keep this 557 in sync with bfd/archures.c in order for machine selection to work. */ 558 #define CPU_UNKNOWN 0 /* Gas internal use. */ 559 #define CPU_R3000 3000 560 #define CPU_R3900 3900 561 #define CPU_R4000 4000 562 #define CPU_R4010 4010 563 #define CPU_VR4100 4100 564 #define CPU_R4111 4111 565 #define CPU_VR4120 4120 566 #define CPU_R4300 4300 567 #define CPU_R4400 4400 568 #define CPU_R4600 4600 569 #define CPU_R4650 4650 570 #define CPU_R5000 5000 571 #define CPU_VR5400 5400 572 #define CPU_VR5500 5500 573 #define CPU_R6000 6000 574 #define CPU_RM7000 7000 575 #define CPU_R8000 8000 576 #define CPU_RM9000 9000 577 #define CPU_R10000 10000 578 #define CPU_R12000 12000 579 #define CPU_MIPS16 16 580 #define CPU_MIPS32 32 581 #define CPU_MIPS32R2 33 582 #define CPU_MIPS5 5 583 #define CPU_MIPS64 64 584 #define CPU_MIPS64R2 65 585 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 586 #define CPU_OCTEON 6502 587 588 /* Test for membership in an ISA including chip specific ISAs. INSN 589 is pointer to an element of the opcode table; ISA is the specified 590 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 591 test, or zero if no CPU specific ISA test is desired. */ 592 593 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 594 (((insn)->membership & isa) != 0 \ 595 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 596 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 597 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ 598 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 599 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 600 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 601 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 602 && ((insn)->membership & INSN_10000) != 0) \ 603 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 604 || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \ 605 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 606 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 607 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 608 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 609 || 0) /* Please keep this term for easier source merging. */ 610 611 /* This is a list of macro expanded instructions. 612 613 _I appended means immediate 614 _A appended means address 615 _AB appended means address with base register 616 _D appended means 64 bit floating point constant 617 _S appended means 32 bit floating point constant. */ 618 619 enum 620 { 621 M_ABS, 622 M_ADD_I, 623 M_ADDU_I, 624 M_AND_I, 625 M_BALIGN, 626 M_BEQ, 627 M_BEQ_I, 628 M_BEQL_I, 629 M_BGE, 630 M_BGEL, 631 M_BGE_I, 632 M_BGEL_I, 633 M_BGEU, 634 M_BGEUL, 635 M_BGEU_I, 636 M_BGEUL_I, 637 M_BGT, 638 M_BGTL, 639 M_BGT_I, 640 M_BGTL_I, 641 M_BGTU, 642 M_BGTUL, 643 M_BGTU_I, 644 M_BGTUL_I, 645 M_BLE, 646 M_BLEL, 647 M_BLE_I, 648 M_BLEL_I, 649 M_BLEU, 650 M_BLEUL, 651 M_BLEU_I, 652 M_BLEUL_I, 653 M_BLT, 654 M_BLTL, 655 M_BLT_I, 656 M_BLTL_I, 657 M_BLTU, 658 M_BLTUL, 659 M_BLTU_I, 660 M_BLTUL_I, 661 M_BNE, 662 M_BNE_I, 663 M_BNEL_I, 664 M_CACHE_AB, 665 M_DABS, 666 M_DADD_I, 667 M_DADDU_I, 668 M_DDIV_3, 669 M_DDIV_3I, 670 M_DDIVU_3, 671 M_DDIVU_3I, 672 M_DEXT, 673 M_DINS, 674 M_DIV_3, 675 M_DIV_3I, 676 M_DIVU_3, 677 M_DIVU_3I, 678 M_DLA_AB, 679 M_DLCA_AB, 680 M_DLI, 681 M_DMUL, 682 M_DMUL_I, 683 M_DMULO, 684 M_DMULO_I, 685 M_DMULOU, 686 M_DMULOU_I, 687 M_DREM_3, 688 M_DREM_3I, 689 M_DREMU_3, 690 M_DREMU_3I, 691 M_DSUB_I, 692 M_DSUBU_I, 693 M_DSUBU_I_2, 694 M_J_A, 695 M_JAL_1, 696 M_JAL_2, 697 M_JAL_A, 698 M_L_DOB, 699 M_L_DAB, 700 M_LA_AB, 701 M_LB_A, 702 M_LB_AB, 703 M_LBU_A, 704 M_LBU_AB, 705 M_LCA_AB, 706 M_LD_A, 707 M_LD_OB, 708 M_LD_AB, 709 M_LDC1_AB, 710 M_LDC2_AB, 711 M_LDC3_AB, 712 M_LDL_AB, 713 M_LDR_AB, 714 M_LH_A, 715 M_LH_AB, 716 M_LHU_A, 717 M_LHU_AB, 718 M_LI, 719 M_LI_D, 720 M_LI_DD, 721 M_LI_S, 722 M_LI_SS, 723 M_LL_AB, 724 M_LLD_AB, 725 M_LS_A, 726 M_LW_A, 727 M_LW_AB, 728 M_LWC0_A, 729 M_LWC0_AB, 730 M_LWC1_A, 731 M_LWC1_AB, 732 M_LWC2_A, 733 M_LWC2_AB, 734 M_LWC3_A, 735 M_LWC3_AB, 736 M_LWL_A, 737 M_LWL_AB, 738 M_LWR_A, 739 M_LWR_AB, 740 M_LWU_AB, 741 M_MOVE, 742 M_MUL, 743 M_MUL_I, 744 M_MULO, 745 M_MULO_I, 746 M_MULOU, 747 M_MULOU_I, 748 M_NOR_I, 749 M_OR_I, 750 M_REM_3, 751 M_REM_3I, 752 M_REMU_3, 753 M_REMU_3I, 754 M_DROL, 755 M_ROL, 756 M_DROL_I, 757 M_ROL_I, 758 M_DROR, 759 M_ROR, 760 M_DROR_I, 761 M_ROR_I, 762 M_S_DA, 763 M_S_DOB, 764 M_S_DAB, 765 M_S_S, 766 M_SAA_AB, 767 M_SAAD_AB, 768 M_SC_AB, 769 M_SCD_AB, 770 M_SD_A, 771 M_SD_OB, 772 M_SD_AB, 773 M_SDC1_AB, 774 M_SDC2_AB, 775 M_SDC3_AB, 776 M_SDL_AB, 777 M_SDR_AB, 778 M_SEQ, 779 M_SEQ_I, 780 M_SGE, 781 M_SGE_I, 782 M_SGEU, 783 M_SGEU_I, 784 M_SGT, 785 M_SGT_I, 786 M_SGTU, 787 M_SGTU_I, 788 M_SLE, 789 M_SLE_I, 790 M_SLEU, 791 M_SLEU_I, 792 M_SLT_I, 793 M_SLTU_I, 794 M_SNE, 795 M_SNE_I, 796 M_SB_A, 797 M_SB_AB, 798 M_SH_A, 799 M_SH_AB, 800 M_SW_A, 801 M_SW_AB, 802 M_SWC0_A, 803 M_SWC0_AB, 804 M_SWC1_A, 805 M_SWC1_AB, 806 M_SWC2_A, 807 M_SWC2_AB, 808 M_SWC3_A, 809 M_SWC3_AB, 810 M_SWL_A, 811 M_SWL_AB, 812 M_SWR_A, 813 M_SWR_AB, 814 M_SUB_I, 815 M_SUBU_I, 816 M_SUBU_I_2, 817 M_TEQ_I, 818 M_TGE_I, 819 M_TGEU_I, 820 M_TLT_I, 821 M_TLTU_I, 822 M_TNE_I, 823 M_TRUNCWD, 824 M_TRUNCWS, 825 M_ULD, 826 M_ULD_A, 827 M_ULH, 828 M_ULH_A, 829 M_ULHU, 830 M_ULHU_A, 831 M_ULW, 832 M_ULW_A, 833 M_USH, 834 M_USH_A, 835 M_USW, 836 M_USW_A, 837 M_USD, 838 M_USD_A, 839 M_XOR_I, 840 M_COP0, 841 M_COP1, 842 M_COP2, 843 M_COP3, 844 M_NUM_MACROS 845 }; 846 847 848 /* The order of overloaded instructions matters. Label arguments and 849 register arguments look the same. Instructions that can have either 850 for arguments must apear in the correct order in this table for the 851 assembler to pick the right one. In other words, entries with 852 immediate operands must apear after the same instruction with 853 registers. 854 855 Many instructions are short hand for other instructions (i.e., The 856 jal <register> instruction is short for jalr <register>). */ 857 858 extern const struct mips_opcode mips_builtin_opcodes[]; 859 extern const int bfd_mips_num_builtin_opcodes; 860 extern struct mips_opcode *mips_opcodes; 861 extern int bfd_mips_num_opcodes; 862 #define NUMOPCODES bfd_mips_num_opcodes 863 864 865 /* The rest of this file adds definitions for the mips16 TinyRISC 866 processor. */ 867 868 /* These are the bitmasks and shift counts used for the different 869 fields in the instruction formats. Other than OP, no masks are 870 provided for the fixed portions of an instruction, since they are 871 not needed. 872 873 The I format uses IMM11. 874 875 The RI format uses RX and IMM8. 876 877 The RR format uses RX, and RY. 878 879 The RRI format uses RX, RY, and IMM5. 880 881 The RRR format uses RX, RY, and RZ. 882 883 The RRI_A format uses RX, RY, and IMM4. 884 885 The SHIFT format uses RX, RY, and SHAMT. 886 887 The I8 format uses IMM8. 888 889 The I8_MOVR32 format uses RY and REGR32. 890 891 The IR_MOV32R format uses REG32R and MOV32Z. 892 893 The I64 format uses IMM8. 894 895 The RI64 format uses RY and IMM5. 896 */ 897 898 #define MIPS16OP_MASK_OP 0x1f 899 #define MIPS16OP_SH_OP 11 900 #define MIPS16OP_MASK_IMM11 0x7ff 901 #define MIPS16OP_SH_IMM11 0 902 #define MIPS16OP_MASK_RX 0x7 903 #define MIPS16OP_SH_RX 8 904 #define MIPS16OP_MASK_IMM8 0xff 905 #define MIPS16OP_SH_IMM8 0 906 #define MIPS16OP_MASK_RY 0x7 907 #define MIPS16OP_SH_RY 5 908 #define MIPS16OP_MASK_IMM5 0x1f 909 #define MIPS16OP_SH_IMM5 0 910 #define MIPS16OP_MASK_RZ 0x7 911 #define MIPS16OP_SH_RZ 2 912 #define MIPS16OP_MASK_IMM4 0xf 913 #define MIPS16OP_SH_IMM4 0 914 #define MIPS16OP_MASK_REGR32 0x1f 915 #define MIPS16OP_SH_REGR32 0 916 #define MIPS16OP_MASK_REG32R 0x1f 917 #define MIPS16OP_SH_REG32R 3 918 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 919 #define MIPS16OP_MASK_MOVE32Z 0x7 920 #define MIPS16OP_SH_MOVE32Z 0 921 #define MIPS16OP_MASK_IMM6 0x3f 922 #define MIPS16OP_SH_IMM6 5 923 924 /* These are the characters which may appears in the args field of an 925 instruction. They appear in the order in which the fields appear 926 when the instruction is used. Commas and parentheses in the args 927 string are ignored when assembling, and written into the output 928 when disassembling. 929 930 "y" 3 bit register (MIPS16OP_*_RY) 931 "x" 3 bit register (MIPS16OP_*_RX) 932 "z" 3 bit register (MIPS16OP_*_RZ) 933 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 934 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 935 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 936 "0" zero register ($0) 937 "S" stack pointer ($sp or $29) 938 "P" program counter 939 "R" return address register ($ra or $31) 940 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 941 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 942 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 943 "a" 26 bit jump address 944 "e" 11 bit extension value 945 "l" register list for entry instruction 946 "L" register list for exit instruction 947 948 The remaining codes may be extended. Except as otherwise noted, 949 the full extended operand is a 16 bit signed value. 950 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 951 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 952 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 953 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 954 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 955 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 956 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 957 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 958 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 959 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 960 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 961 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 962 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 963 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 964 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 965 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 966 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 967 "q" 11 bit branch address (MIPS16OP_*_IMM11) 968 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 969 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 970 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 971 "m" 7 bit register list for save instruction (18 bit extended) 972 "M" 7 bit register list for restore instruction (18 bit extended) 973 */ 974 975 /* Save/restore encoding for the args field when all 4 registers are 976 either saved as arguments or saved/restored as statics. */ 977 #define MIPS16_ALL_ARGS 0xe 978 #define MIPS16_ALL_STATICS 0xb 979 980 /* For the mips16, we use the same opcode table format and a few of 981 the same flags. However, most of the flags are different. */ 982 983 /* Modifies the register in MIPS16OP_*_RX. */ 984 #define MIPS16_INSN_WRITE_X 0x00000001 985 /* Modifies the register in MIPS16OP_*_RY. */ 986 #define MIPS16_INSN_WRITE_Y 0x00000002 987 /* Modifies the register in MIPS16OP_*_RZ. */ 988 #define MIPS16_INSN_WRITE_Z 0x00000004 989 /* Modifies the T ($24) register. */ 990 #define MIPS16_INSN_WRITE_T 0x00000008 991 /* Modifies the SP ($29) register. */ 992 #define MIPS16_INSN_WRITE_SP 0x00000010 993 /* Modifies the RA ($31) register. */ 994 #define MIPS16_INSN_WRITE_31 0x00000020 995 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 996 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 997 /* Reads the register in MIPS16OP_*_RX. */ 998 #define MIPS16_INSN_READ_X 0x00000080 999 /* Reads the register in MIPS16OP_*_RY. */ 1000 #define MIPS16_INSN_READ_Y 0x00000100 1001 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 1002 #define MIPS16_INSN_READ_Z 0x00000200 1003 /* Reads the T ($24) register. */ 1004 #define MIPS16_INSN_READ_T 0x00000400 1005 /* Reads the SP ($29) register. */ 1006 #define MIPS16_INSN_READ_SP 0x00000800 1007 /* Reads the RA ($31) register. */ 1008 #define MIPS16_INSN_READ_31 0x00001000 1009 /* Reads the program counter. */ 1010 #define MIPS16_INSN_READ_PC 0x00002000 1011 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 1012 #define MIPS16_INSN_READ_GPR_X 0x00004000 1013 /* Is a branch insn. */ 1014 #define MIPS16_INSN_BRANCH 0x00010000 1015 1016 /* The following flags have the same value for the mips16 opcode 1017 table: 1018 INSN_UNCOND_BRANCH_DELAY 1019 INSN_COND_BRANCH_DELAY 1020 INSN_COND_BRANCH_LIKELY (never used) 1021 INSN_READ_HI 1022 INSN_READ_LO 1023 INSN_WRITE_HI 1024 INSN_WRITE_LO 1025 INSN_TRAP 1026 INSN_ISA3 1027 */ 1028 1029 extern const struct mips_opcode mips16_opcodes[]; 1030 extern const int bfd_mips16_num_opcodes; 1031 1032 #endif /* _MIPS_H_ */ 1033