1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
5 * reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * NETLOGIC_BSD */
31
32 /*
33 * Simple driver for the 32-bit interval counter built in to all
34 * MIPS32 CPUs.
35 */
36
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/sysctl.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/rman.h>
47 #include <sys/power.h>
48 #include <sys/smp.h>
49 #include <sys/time.h>
50 #include <sys/timeet.h>
51 #include <sys/timetc.h>
52
53 #include <machine/hwfunc.h>
54 #include <machine/clock.h>
55 #include <machine/locore.h>
56 #include <machine/md_var.h>
57 #include <machine/intr_machdep.h>
58
59 #include <mips/nlm/interrupt.h>
60
61 uint64_t counter_freq;
62
63 struct timecounter *platform_timecounter;
64
65 DPCPU_DEFINE_STATIC(uint32_t, cycles_per_tick);
66 static uint32_t cycles_per_usec;
67
68 DPCPU_DEFINE_STATIC(volatile uint32_t, counter_upper);
69 DPCPU_DEFINE_STATIC(volatile uint32_t, counter_lower_last);
70 DPCPU_DEFINE_STATIC(uint32_t, compare_ticks);
71 DPCPU_DEFINE_STATIC(uint32_t, lost_ticks);
72
73 struct clock_softc {
74 int intr_rid;
75 struct resource *intr_res;
76 void *intr_handler;
77 struct timecounter tc;
78 struct eventtimer et;
79 };
80 static struct clock_softc *softc;
81
82 /*
83 * Device methods
84 */
85 static int clock_probe(device_t);
86 static void clock_identify(driver_t *, device_t);
87 static int clock_attach(device_t);
88 static unsigned counter_get_timecount(struct timecounter *tc);
89
90 void
mips_timer_early_init(uint64_t clock_hz)91 mips_timer_early_init(uint64_t clock_hz)
92 {
93 /* Initialize clock early so that we can use DELAY sooner */
94 counter_freq = clock_hz;
95 cycles_per_usec = (clock_hz / (1000 * 1000));
96 }
97
98 void
platform_initclocks(void)99 platform_initclocks(void)
100 {
101
102 if (platform_timecounter != NULL)
103 tc_init(platform_timecounter);
104 }
105
106 static uint64_t
tick_ticker(void)107 tick_ticker(void)
108 {
109 uint64_t ret;
110 uint32_t ticktock;
111 uint32_t t_lower_last, t_upper;
112
113 /*
114 * Disable preemption because we are working with cpu specific data.
115 */
116 critical_enter();
117
118 /*
119 * Note that even though preemption is disabled, interrupts are
120 * still enabled. In particular there is a race with clock_intr()
121 * reading the values of 'counter_upper' and 'counter_lower_last'.
122 *
123 * XXX this depends on clock_intr() being executed periodically
124 * so that 'counter_upper' and 'counter_lower_last' are not stale.
125 */
126 do {
127 t_upper = DPCPU_GET(counter_upper);
128 t_lower_last = DPCPU_GET(counter_lower_last);
129 } while (t_upper != DPCPU_GET(counter_upper));
130
131 ticktock = mips_rd_count();
132
133 critical_exit();
134
135 /* COUNT register wrapped around */
136 if (ticktock < t_lower_last)
137 t_upper++;
138
139 ret = ((uint64_t)t_upper << 32) | ticktock;
140 return (ret);
141 }
142
143 void
mips_timer_init_params(uint64_t platform_counter_freq,int double_count)144 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
145 {
146
147 /*
148 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
149 * function should be called before cninit.
150 */
151 counter_freq = platform_counter_freq;
152 /*
153 * XXX: Some MIPS32 cores update the Count register only every two
154 * pipeline cycles.
155 * We know this because of status registers in CP0, make it automatic.
156 */
157 if (double_count != 0)
158 counter_freq /= 2;
159
160 cycles_per_usec = counter_freq / (1 * 1000 * 1000);
161 set_cputicker(tick_ticker, counter_freq, 1);
162 }
163
164 static int
sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)165 sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
166 {
167 int error;
168 uint64_t freq;
169
170 if (softc == NULL)
171 return (EOPNOTSUPP);
172 freq = counter_freq;
173 error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
174 if (error == 0 && req->newptr != NULL) {
175 counter_freq = freq;
176 softc->et.et_frequency = counter_freq;
177 softc->tc.tc_frequency = counter_freq;
178 }
179 return (error);
180 }
181
182 SYSCTL_PROC(_machdep, OID_AUTO, counter_freq,
183 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, NULL, 0,
184 sysctl_machdep_counter_freq, "QU",
185 "Timecounter frequency in Hz");
186
187 static unsigned
counter_get_timecount(struct timecounter * tc)188 counter_get_timecount(struct timecounter *tc)
189 {
190
191 return (mips_rd_count());
192 }
193
194 /*
195 * Wait for about n microseconds (at least!).
196 */
197 void
DELAY(int n)198 DELAY(int n)
199 {
200 uint32_t cur, last, delta, usecs;
201
202 TSENTER();
203 /*
204 * This works by polling the timer and counting the number of
205 * microseconds that go by.
206 */
207 last = mips_rd_count();
208 delta = usecs = 0;
209
210 while (n > usecs) {
211 cur = mips_rd_count();
212
213 /* Check to see if the timer has wrapped around. */
214 if (cur < last)
215 delta += cur + (0xffffffff - last) + 1;
216 else
217 delta += cur - last;
218
219 last = cur;
220
221 if (delta >= cycles_per_usec) {
222 usecs += delta / cycles_per_usec;
223 delta %= cycles_per_usec;
224 }
225 }
226 TSEXIT();
227 }
228
229 static int
clock_start(struct eventtimer * et,sbintime_t first,sbintime_t period)230 clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
231 {
232 uint32_t fdiv, div, next;
233
234 if (period != 0)
235 div = (et->et_frequency * period) >> 32;
236 else
237 div = 0;
238 if (first != 0)
239 fdiv = (et->et_frequency * first) >> 32;
240 else
241 fdiv = div;
242 DPCPU_SET(cycles_per_tick, div);
243 next = mips_rd_count() + fdiv;
244 DPCPU_SET(compare_ticks, next);
245 mips_wr_compare(next);
246 return (0);
247 }
248
249 static int
clock_stop(struct eventtimer * et)250 clock_stop(struct eventtimer *et)
251 {
252
253 DPCPU_SET(cycles_per_tick, 0);
254 mips_wr_compare(0xffffffff);
255 return (0);
256 }
257
258 /*
259 * Device section of file below
260 */
261 static int
clock_intr(void * arg)262 clock_intr(void *arg)
263 {
264 struct clock_softc *sc = (struct clock_softc *)arg;
265 uint32_t cycles_per_tick;
266 uint32_t count, compare_last, compare_next, lost_ticks;
267
268 cycles_per_tick = DPCPU_GET(cycles_per_tick);
269 /*
270 * Set next clock edge.
271 */
272 count = mips_rd_count();
273 compare_last = DPCPU_GET(compare_ticks);
274 if (cycles_per_tick > 0) {
275 compare_next = count + cycles_per_tick;
276 DPCPU_SET(compare_ticks, compare_next);
277 mips_wr_compare(compare_next);
278 } else /* In one-shot mode timer should be stopped after the event. */
279 mips_wr_compare(0xffffffff);
280
281 /* COUNT register wrapped around */
282 if (count < DPCPU_GET(counter_lower_last)) {
283 DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
284 }
285 DPCPU_SET(counter_lower_last, count);
286
287 if (cycles_per_tick > 0) {
288 /*
289 * Account for the "lost time" between when the timer interrupt
290 * fired and when 'clock_intr' actually started executing.
291 */
292 lost_ticks = DPCPU_GET(lost_ticks);
293 lost_ticks += count - compare_last;
294
295 /*
296 * If the COUNT and COMPARE registers are no longer in sync
297 * then make up some reasonable value for the 'lost_ticks'.
298 *
299 * This could happen, for e.g., after we resume normal
300 * operations after exiting the debugger.
301 */
302 if (lost_ticks > 2 * cycles_per_tick)
303 lost_ticks = cycles_per_tick;
304
305 while (lost_ticks >= cycles_per_tick) {
306 if (sc->et.et_active)
307 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
308 lost_ticks -= cycles_per_tick;
309 }
310 DPCPU_SET(lost_ticks, lost_ticks);
311 }
312 if (sc->et.et_active)
313 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
314 return (FILTER_HANDLED);
315 }
316
317 static int
clock_probe(device_t dev)318 clock_probe(device_t dev)
319 {
320
321 device_set_desc(dev, "Generic MIPS32 ticker");
322 return (BUS_PROBE_NOWILDCARD);
323 }
324
325 static void
clock_identify(driver_t * drv,device_t parent)326 clock_identify(driver_t * drv, device_t parent)
327 {
328
329 BUS_ADD_CHILD(parent, 0, "clock", 0);
330 }
331
332 static int
clock_attach(device_t dev)333 clock_attach(device_t dev)
334 {
335 struct clock_softc *sc;
336
337 if (device_get_unit(dev) != 0)
338 panic("can't attach more clocks");
339
340 softc = sc = device_get_softc(dev);
341 cpu_establish_hardintr("compare", clock_intr, NULL,
342 sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
343
344 sc->tc.tc_get_timecount = counter_get_timecount;
345 sc->tc.tc_counter_mask = 0xffffffff;
346 sc->tc.tc_frequency = counter_freq;
347 sc->tc.tc_name = "MIPS32";
348 sc->tc.tc_quality = 800;
349 sc->tc.tc_priv = sc;
350 tc_init(&sc->tc);
351 sc->et.et_name = "MIPS32";
352 #if 0
353 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
354 ET_FLAGS_PERCPU;
355 #endif
356 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_PERCPU;
357 sc->et.et_quality = 800;
358 sc->et.et_frequency = counter_freq;
359 sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
360 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
361 sc->et.et_start = clock_start;
362 sc->et.et_stop = clock_stop;
363 sc->et.et_priv = sc;
364 et_register(&sc->et);
365 return (0);
366 }
367
368 static device_method_t clock_methods[] = {
369 /* Device interface */
370 DEVMETHOD(device_probe, clock_probe),
371 DEVMETHOD(device_identify, clock_identify),
372 DEVMETHOD(device_attach, clock_attach),
373 DEVMETHOD(device_detach, bus_generic_detach),
374 DEVMETHOD(device_shutdown, bus_generic_shutdown),
375 {0, 0}
376 };
377
378 static driver_t clock_driver = {
379 "clock",
380 clock_methods,
381 sizeof(struct clock_softc),
382 };
383
384 static devclass_t clock_devclass;
385
386 DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
387