1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-2-Clause
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * uart_dev_oct16550.c
31 *
32 * Derived from uart_dev_ns8250.c
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 *
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 *
56 */
57
58 #include <sys/cdefs.h>
59 __FBSDID("$FreeBSD$");
60
61 #include <sys/param.h>
62 #include <sys/systm.h>
63 #include <sys/bus.h>
64 #include <sys/conf.h>
65 #include <machine/bus.h>
66 #include <machine/pcpu.h>
67
68 #include <dev/uart/uart.h>
69 #include <dev/uart/uart_cpu.h>
70 #include <dev/uart/uart_bus.h>
71
72 #include <dev/ic/ns16550.h>
73
74 #include <mips/cavium/octeon_pcmap_regs.h>
75
76 #include <contrib/octeon-sdk/cvmx.h>
77
78 #include "uart_if.h"
79
80 /*
81 * Clear pending interrupts. THRE is cleared by reading IIR. Data
82 * that may have been received gets lost here.
83 */
84 static void
oct16550_clrint(struct uart_bas * bas)85 oct16550_clrint (struct uart_bas *bas)
86 {
87 uint8_t iir;
88
89 iir = uart_getreg(bas, REG_IIR);
90 while ((iir & IIR_NOPEND) == 0) {
91 iir &= IIR_IMASK;
92 if (iir == IIR_RLS)
93 (void)uart_getreg(bas, REG_LSR);
94 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
95 (void)uart_getreg(bas, REG_DATA);
96 else if (iir == IIR_MLSC)
97 (void)uart_getreg(bas, REG_MSR);
98 else if (iir == IIR_BUSY)
99 (void) uart_getreg(bas, REG_USR);
100 uart_barrier(bas);
101 iir = uart_getreg(bas, REG_IIR);
102 }
103 }
104
105 static int delay_changed = 1;
106
107 static int
oct16550_delay(struct uart_bas * bas)108 oct16550_delay (struct uart_bas *bas)
109 {
110 int divisor;
111 u_char lcr;
112 static int delay = 0;
113
114 if (!delay_changed) return delay;
115 delay_changed = 0;
116 lcr = uart_getreg(bas, REG_LCR);
117 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
118 uart_barrier(bas);
119 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
120 uart_barrier(bas);
121 uart_setreg(bas, REG_LCR, lcr);
122 uart_barrier(bas);
123
124 if(!bas->rclk)
125 return 10; /* return an approx delay value */
126
127 /* 1/10th the time to transmit 1 character (estimate). */
128 if (divisor <= 134)
129 return (16000000 * divisor / bas->rclk);
130 return (16000 * divisor / (bas->rclk / 1000));
131
132 }
133
134 static int
oct16550_divisor(int rclk,int baudrate)135 oct16550_divisor (int rclk, int baudrate)
136 {
137 int actual_baud, divisor;
138 int error;
139
140 if (baudrate == 0)
141 return (0);
142
143 divisor = (rclk / (baudrate << 3) + 1) >> 1;
144 if (divisor == 0 || divisor >= 65536)
145 return (0);
146 actual_baud = rclk / (divisor << 4);
147
148 /* 10 times error in percent: */
149 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
150
151 /* 3.0% maximum error tolerance: */
152 if (error < -30 || error > 30)
153 return (0);
154
155 return (divisor);
156 }
157
158 static int
oct16550_drain(struct uart_bas * bas,int what)159 oct16550_drain (struct uart_bas *bas, int what)
160 {
161 int delay, limit;
162
163 delay = oct16550_delay(bas);
164
165 if (what & UART_DRAIN_TRANSMITTER) {
166 /*
167 * Pick an arbitrary high limit to avoid getting stuck in
168 * an infinite loop when the hardware is broken. Make the
169 * limit high enough to handle large FIFOs.
170 */
171 limit = 10*10*10*1024;
172 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
173 DELAY(delay);
174 if (limit == 0) {
175 /* printf("oct16550: transmitter appears stuck... "); */
176 return (0);
177 }
178 }
179
180 if (what & UART_DRAIN_RECEIVER) {
181 /*
182 * Pick an arbitrary high limit to avoid getting stuck in
183 * an infinite loop when the hardware is broken. Make the
184 * limit high enough to handle large FIFOs and integrated
185 * UARTs. The HP rx2600 for example has 3 UARTs on the
186 * management board that tend to get a lot of data send
187 * to it when the UART is first activated.
188 */
189 limit=10*4096;
190 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
191 (void)uart_getreg(bas, REG_DATA);
192 uart_barrier(bas);
193 DELAY(delay << 2);
194 }
195 if (limit == 0) {
196 /* printf("oct16550: receiver appears broken... "); */
197 return (EIO);
198 }
199 }
200
201 return (0);
202 }
203
204 /*
205 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
206 * drained. WARNING: this function clobbers the FIFO setting!
207 */
208 static void
oct16550_flush(struct uart_bas * bas,int what)209 oct16550_flush (struct uart_bas *bas, int what)
210 {
211 uint8_t fcr;
212
213 fcr = FCR_ENABLE;
214 if (what & UART_FLUSH_TRANSMITTER)
215 fcr |= FCR_XMT_RST;
216 if (what & UART_FLUSH_RECEIVER)
217 fcr |= FCR_RCV_RST;
218 uart_setreg(bas, REG_FCR, fcr);
219 uart_barrier(bas);
220 }
221
222 static int
oct16550_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)223 oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits,
224 int parity)
225 {
226 int divisor;
227 uint8_t lcr;
228
229 lcr = 0;
230 if (databits >= 8)
231 lcr |= LCR_8BITS;
232 else if (databits == 7)
233 lcr |= LCR_7BITS;
234 else if (databits == 6)
235 lcr |= LCR_6BITS;
236 else
237 lcr |= LCR_5BITS;
238 if (stopbits > 1)
239 lcr |= LCR_STOPB;
240 lcr |= parity << 3;
241
242 /* Set baudrate. */
243 if (baudrate > 0) {
244 divisor = oct16550_divisor(bas->rclk, baudrate);
245 if (divisor == 0)
246 return (EINVAL);
247 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
248 uart_barrier(bas);
249 uart_setreg(bas, REG_DLL, divisor & 0xff);
250 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
251 uart_barrier(bas);
252 delay_changed = 1;
253 }
254
255 /* Set LCR and clear DLAB. */
256 uart_setreg(bas, REG_LCR, lcr);
257 uart_barrier(bas);
258 return (0);
259 }
260
261 /*
262 * Low-level UART interface.
263 */
264 static int oct16550_probe(struct uart_bas *bas);
265 static void oct16550_init(struct uart_bas *bas, int, int, int, int);
266 static void oct16550_term(struct uart_bas *bas);
267 static void oct16550_putc(struct uart_bas *bas, int);
268 static int oct16550_rxready(struct uart_bas *bas);
269 static int oct16550_getc(struct uart_bas *bas, struct mtx *);
270
271 struct uart_ops uart_oct16550_ops = {
272 .probe = oct16550_probe,
273 .init = oct16550_init,
274 .term = oct16550_term,
275 .putc = oct16550_putc,
276 .rxready = oct16550_rxready,
277 .getc = oct16550_getc,
278 };
279
280 static int
oct16550_probe(struct uart_bas * bas)281 oct16550_probe (struct uart_bas *bas)
282 {
283 u_char val;
284
285 /* Check known 0 bits that don't depend on DLAB. */
286 val = uart_getreg(bas, REG_IIR);
287 if (val & 0x30)
288 return (ENXIO);
289 val = uart_getreg(bas, REG_MCR);
290 if (val & 0xc0)
291 return (ENXIO);
292 val = uart_getreg(bas, REG_USR);
293 if (val & 0xe0)
294 return (ENXIO);
295 return (0);
296 }
297
298 static void
oct16550_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)299 oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits,
300 int parity)
301 {
302 u_char ier;
303
304 oct16550_param(bas, baudrate, databits, stopbits, parity);
305
306 /* Disable all interrupt sources. */
307 ier = uart_getreg(bas, REG_IER) & 0x0;
308 uart_setreg(bas, REG_IER, ier);
309 uart_barrier(bas);
310
311 /* Disable the FIFO (if present). */
312 // uart_setreg(bas, REG_FCR, 0);
313 uart_barrier(bas);
314
315 /* Set RTS & DTR. */
316 uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR);
317 uart_barrier(bas);
318
319 oct16550_clrint(bas);
320 }
321
322 static void
oct16550_term(struct uart_bas * bas)323 oct16550_term (struct uart_bas *bas)
324 {
325
326 /* Clear RTS & DTR. */
327 uart_setreg(bas, REG_MCR, 0);
328 uart_barrier(bas);
329 }
330
oct16550_wait_txhr_empty(struct uart_bas * bas,int limit,int delay)331 static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay)
332 {
333 while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) &&
334 ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0))
335 DELAY(delay);
336 }
337
338 static void
oct16550_putc(struct uart_bas * bas,int c)339 oct16550_putc (struct uart_bas *bas, int c)
340 {
341 int delay;
342
343 /* 1/10th the time to transmit 1 character (estimate). */
344 delay = oct16550_delay(bas);
345 oct16550_wait_txhr_empty(bas, 100, delay);
346 uart_setreg(bas, REG_DATA, c);
347 uart_barrier(bas);
348 oct16550_wait_txhr_empty(bas, 100, delay);
349 }
350
351 static int
oct16550_rxready(struct uart_bas * bas)352 oct16550_rxready (struct uart_bas *bas)
353 {
354
355 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
356 }
357
358 static int
oct16550_getc(struct uart_bas * bas,struct mtx * hwmtx)359 oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx)
360 {
361 int c, delay;
362
363 uart_lock(hwmtx);
364
365 /* 1/10th the time to transmit 1 character (estimate). */
366 delay = oct16550_delay(bas);
367
368 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
369 uart_unlock(hwmtx);
370 DELAY(delay);
371 uart_lock(hwmtx);
372 }
373
374 c = uart_getreg(bas, REG_DATA);
375
376 uart_unlock(hwmtx);
377
378 return (c);
379 }
380
381 /*
382 * High-level UART interface.
383 */
384 struct oct16550_softc {
385 struct uart_softc base;
386 uint8_t fcr;
387 uint8_t ier;
388 uint8_t mcr;
389 };
390
391 static int oct16550_bus_attach(struct uart_softc *);
392 static int oct16550_bus_detach(struct uart_softc *);
393 static int oct16550_bus_flush(struct uart_softc *, int);
394 static int oct16550_bus_getsig(struct uart_softc *);
395 static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t);
396 static int oct16550_bus_ipend(struct uart_softc *);
397 static int oct16550_bus_param(struct uart_softc *, int, int, int, int);
398 static int oct16550_bus_probe(struct uart_softc *);
399 static int oct16550_bus_receive(struct uart_softc *);
400 static int oct16550_bus_setsig(struct uart_softc *, int);
401 static int oct16550_bus_transmit(struct uart_softc *);
402 static void oct16550_bus_grab(struct uart_softc *);
403 static void oct16550_bus_ungrab(struct uart_softc *);
404
405 static kobj_method_t oct16550_methods[] = {
406 KOBJMETHOD(uart_attach, oct16550_bus_attach),
407 KOBJMETHOD(uart_detach, oct16550_bus_detach),
408 KOBJMETHOD(uart_flush, oct16550_bus_flush),
409 KOBJMETHOD(uart_getsig, oct16550_bus_getsig),
410 KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl),
411 KOBJMETHOD(uart_ipend, oct16550_bus_ipend),
412 KOBJMETHOD(uart_param, oct16550_bus_param),
413 KOBJMETHOD(uart_probe, oct16550_bus_probe),
414 KOBJMETHOD(uart_receive, oct16550_bus_receive),
415 KOBJMETHOD(uart_setsig, oct16550_bus_setsig),
416 KOBJMETHOD(uart_transmit, oct16550_bus_transmit),
417 KOBJMETHOD(uart_grab, oct16550_bus_grab),
418 KOBJMETHOD(uart_ungrab, oct16550_bus_ungrab),
419 { 0, 0 }
420 };
421
422 struct uart_class uart_oct16550_class = {
423 "oct16550 class",
424 oct16550_methods,
425 sizeof(struct oct16550_softc),
426 .uc_ops = &uart_oct16550_ops,
427 .uc_range = 8 << 3,
428 .uc_rclk = 0,
429 .uc_rshift = 0
430 };
431
432 #define SIGCHG(c, i, s, d) \
433 if (c) { \
434 i |= (i & s) ? s : s | d; \
435 } else { \
436 i = (i & s) ? (i & ~s) | d : i; \
437 }
438
439 static int
oct16550_bus_attach(struct uart_softc * sc)440 oct16550_bus_attach (struct uart_softc *sc)
441 {
442 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
443 struct uart_bas *bas;
444 int unit;
445
446 unit = device_get_unit(sc->sc_dev);
447 bas = &sc->sc_bas;
448
449 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
450 oct16550->mcr = uart_getreg(bas, REG_MCR);
451 oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH;
452 uart_setreg(bas, REG_FCR, oct16550->fcr);
453 uart_barrier(bas);
454 oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
455
456 if (oct16550->mcr & MCR_DTR)
457 sc->sc_hwsig |= SER_DTR;
458 if (oct16550->mcr & MCR_RTS)
459 sc->sc_hwsig |= SER_RTS;
460 oct16550_bus_getsig(sc);
461
462 oct16550_clrint(bas);
463 oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0;
464 oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
465 uart_setreg(bas, REG_IER, oct16550->ier);
466 uart_barrier(bas);
467
468 return (0);
469 }
470
471 static int
oct16550_bus_detach(struct uart_softc * sc)472 oct16550_bus_detach (struct uart_softc *sc)
473 {
474 struct uart_bas *bas;
475 u_char ier;
476
477 bas = &sc->sc_bas;
478 ier = uart_getreg(bas, REG_IER) & 0xf0;
479 uart_setreg(bas, REG_IER, ier);
480 uart_barrier(bas);
481 oct16550_clrint(bas);
482 return (0);
483 }
484
485 static int
oct16550_bus_flush(struct uart_softc * sc,int what)486 oct16550_bus_flush (struct uart_softc *sc, int what)
487 {
488 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
489 struct uart_bas *bas;
490 int error;
491
492 bas = &sc->sc_bas;
493 uart_lock(sc->sc_hwmtx);
494 if (sc->sc_rxfifosz > 1) {
495 oct16550_flush(bas, what);
496 uart_setreg(bas, REG_FCR, oct16550->fcr);
497 uart_barrier(bas);
498 error = 0;
499 } else
500 error = oct16550_drain(bas, what);
501 uart_unlock(sc->sc_hwmtx);
502 return (error);
503 }
504
505 static int
oct16550_bus_getsig(struct uart_softc * sc)506 oct16550_bus_getsig (struct uart_softc *sc)
507 {
508 uint32_t new, old, sig;
509 uint8_t msr;
510
511 do {
512 old = sc->sc_hwsig;
513 sig = old;
514 uart_lock(sc->sc_hwmtx);
515 msr = uart_getreg(&sc->sc_bas, REG_MSR);
516 uart_unlock(sc->sc_hwmtx);
517 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
518 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
519 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
520 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
521 new = sig & ~SER_MASK_DELTA;
522 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
523 return (sig);
524 }
525
526 static int
oct16550_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)527 oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
528 {
529 struct uart_bas *bas;
530 int baudrate, divisor, error;
531 uint8_t efr, lcr;
532
533 bas = &sc->sc_bas;
534 error = 0;
535 uart_lock(sc->sc_hwmtx);
536 switch (request) {
537 case UART_IOCTL_BREAK:
538 lcr = uart_getreg(bas, REG_LCR);
539 if (data)
540 lcr |= LCR_SBREAK;
541 else
542 lcr &= ~LCR_SBREAK;
543 uart_setreg(bas, REG_LCR, lcr);
544 uart_barrier(bas);
545 break;
546 case UART_IOCTL_IFLOW:
547 lcr = uart_getreg(bas, REG_LCR);
548 uart_barrier(bas);
549 uart_setreg(bas, REG_LCR, 0xbf);
550 uart_barrier(bas);
551 efr = uart_getreg(bas, REG_EFR);
552 if (data)
553 efr |= EFR_RTS;
554 else
555 efr &= ~EFR_RTS;
556 uart_setreg(bas, REG_EFR, efr);
557 uart_barrier(bas);
558 uart_setreg(bas, REG_LCR, lcr);
559 uart_barrier(bas);
560 break;
561 case UART_IOCTL_OFLOW:
562 lcr = uart_getreg(bas, REG_LCR);
563 uart_barrier(bas);
564 uart_setreg(bas, REG_LCR, 0xbf);
565 uart_barrier(bas);
566 efr = uart_getreg(bas, REG_EFR);
567 if (data)
568 efr |= EFR_CTS;
569 else
570 efr &= ~EFR_CTS;
571 uart_setreg(bas, REG_EFR, efr);
572 uart_barrier(bas);
573 uart_setreg(bas, REG_LCR, lcr);
574 uart_barrier(bas);
575 break;
576 case UART_IOCTL_BAUD:
577 lcr = uart_getreg(bas, REG_LCR);
578 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
579 uart_barrier(bas);
580 divisor = uart_getreg(bas, REG_DLL) |
581 (uart_getreg(bas, REG_DLH) << 8);
582 uart_barrier(bas);
583 uart_setreg(bas, REG_LCR, lcr);
584 uart_barrier(bas);
585 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
586 delay_changed = 1;
587 if (baudrate > 0)
588 *(int*)data = baudrate;
589 else
590 error = ENXIO;
591 break;
592 default:
593 error = EINVAL;
594 break;
595 }
596 uart_unlock(sc->sc_hwmtx);
597 return (error);
598 }
599
600 static int
oct16550_bus_ipend(struct uart_softc * sc)601 oct16550_bus_ipend(struct uart_softc *sc)
602 {
603 struct uart_bas *bas;
604 int ipend = 0;
605 uint8_t iir, lsr;
606
607 bas = &sc->sc_bas;
608 uart_lock(sc->sc_hwmtx);
609
610 iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
611 if (iir != IIR_NOPEND) {
612 if (iir == IIR_RLS) {
613 lsr = uart_getreg(bas, REG_LSR);
614 if (lsr & LSR_OE)
615 ipend |= SER_INT_OVERRUN;
616 if (lsr & LSR_BI)
617 ipend |= SER_INT_BREAK;
618 if (lsr & LSR_RXRDY)
619 ipend |= SER_INT_RXREADY;
620
621 } else if (iir == IIR_RXRDY) {
622 ipend |= SER_INT_RXREADY;
623
624 } else if (iir == IIR_RXTOUT) {
625 ipend |= SER_INT_RXREADY;
626
627 } else if (iir == IIR_TXRDY) {
628 ipend |= SER_INT_TXIDLE;
629
630 } else if (iir == IIR_MLSC) {
631 ipend |= SER_INT_SIGCHG;
632
633 } else if (iir == IIR_BUSY) {
634 (void) uart_getreg(bas, REG_USR);
635 }
636 }
637 uart_unlock(sc->sc_hwmtx);
638
639 return (ipend);
640 }
641
642 static int
oct16550_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)643 oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits,
644 int stopbits, int parity)
645 {
646 struct uart_bas *bas;
647 int error;
648
649 bas = &sc->sc_bas;
650 uart_lock(sc->sc_hwmtx);
651 error = oct16550_param(bas, baudrate, databits, stopbits, parity);
652 uart_unlock(sc->sc_hwmtx);
653 return (error);
654 }
655
656 static int
oct16550_bus_probe(struct uart_softc * sc)657 oct16550_bus_probe (struct uart_softc *sc)
658 {
659 struct uart_bas *bas;
660 int error;
661
662 bas = &sc->sc_bas;
663 bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
664
665 error = oct16550_probe(bas);
666 if (error) {
667 return (error);
668 }
669
670 uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS));
671
672 /*
673 * Enable FIFOs. And check that the UART has them. If not, we're
674 * done. Since this is the first time we enable the FIFOs, we reset
675 * them.
676 */
677 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
678 #define ENABLE_OCTEON_FIFO 1
679 #ifdef ENABLE_OCTEON_FIFO
680 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
681 #endif
682 uart_barrier(bas);
683
684 oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
685
686 if (device_get_unit(sc->sc_dev)) {
687 device_set_desc(sc->sc_dev, "Octeon-16550 channel 1");
688 } else {
689 device_set_desc(sc->sc_dev, "Octeon-16550 channel 0");
690 }
691 #ifdef ENABLE_OCTEON_FIFO
692 sc->sc_rxfifosz = 64;
693 sc->sc_txfifosz = 64;
694 #else
695 sc->sc_rxfifosz = 1;
696 sc->sc_txfifosz = 1;
697 #endif
698
699 #if 0
700 /*
701 * XXX there are some issues related to hardware flow control and
702 * it's likely that uart(4) is the cause. This basicly needs more
703 * investigation, but we avoid using for hardware flow control
704 * until then.
705 */
706 /* 16650s or higher have automatic flow control. */
707 if (sc->sc_rxfifosz > 16) {
708 sc->sc_hwiflow = 1;
709 sc->sc_hwoflow = 1;
710 }
711 #endif
712
713 return (0);
714 }
715
716 static int
oct16550_bus_receive(struct uart_softc * sc)717 oct16550_bus_receive (struct uart_softc *sc)
718 {
719 struct uart_bas *bas;
720 int xc;
721 uint8_t lsr;
722
723 bas = &sc->sc_bas;
724 uart_lock(sc->sc_hwmtx);
725 lsr = uart_getreg(bas, REG_LSR);
726
727 while (lsr & LSR_RXRDY) {
728 if (uart_rx_full(sc)) {
729 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
730 break;
731 }
732 xc = uart_getreg(bas, REG_DATA);
733 if (lsr & LSR_FE)
734 xc |= UART_STAT_FRAMERR;
735 if (lsr & LSR_PE)
736 xc |= UART_STAT_PARERR;
737 uart_rx_put(sc, xc);
738 lsr = uart_getreg(bas, REG_LSR);
739 }
740 /* Discard everything left in the Rx FIFO. */
741 /*
742 * First do a dummy read/discard anyway, in case the UART was lying to us.
743 * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY
744 * Results in a stuck ipend loop.
745 */
746 (void)uart_getreg(bas, REG_DATA);
747 while (lsr & LSR_RXRDY) {
748 (void)uart_getreg(bas, REG_DATA);
749 uart_barrier(bas);
750 lsr = uart_getreg(bas, REG_LSR);
751 }
752 uart_unlock(sc->sc_hwmtx);
753 return (0);
754 }
755
756 static int
oct16550_bus_setsig(struct uart_softc * sc,int sig)757 oct16550_bus_setsig (struct uart_softc *sc, int sig)
758 {
759 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
760 struct uart_bas *bas;
761 uint32_t new, old;
762
763 bas = &sc->sc_bas;
764 do {
765 old = sc->sc_hwsig;
766 new = old;
767 if (sig & SER_DDTR) {
768 SIGCHG(sig & SER_DTR, new, SER_DTR,
769 SER_DDTR);
770 }
771 if (sig & SER_DRTS) {
772 SIGCHG(sig & SER_RTS, new, SER_RTS,
773 SER_DRTS);
774 }
775 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
776 uart_lock(sc->sc_hwmtx);
777 oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
778 if (new & SER_DTR)
779 oct16550->mcr |= MCR_DTR;
780 if (new & SER_RTS)
781 oct16550->mcr |= MCR_RTS;
782 uart_setreg(bas, REG_MCR, oct16550->mcr);
783 uart_barrier(bas);
784 uart_unlock(sc->sc_hwmtx);
785 return (0);
786 }
787
788 static int
oct16550_bus_transmit(struct uart_softc * sc)789 oct16550_bus_transmit (struct uart_softc *sc)
790 {
791 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
792 struct uart_bas *bas;
793 int i;
794
795 bas = &sc->sc_bas;
796 uart_lock(sc->sc_hwmtx);
797 #ifdef NO_UART_INTERRUPTS
798 for (i = 0; i < sc->sc_txdatasz; i++) {
799 oct16550_putc(bas, sc->sc_txbuf[i]);
800 }
801 #else
802
803 oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
804 uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY);
805 uart_barrier(bas);
806
807 for (i = 0; i < sc->sc_txdatasz; i++) {
808 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
809 uart_barrier(bas);
810 }
811 sc->sc_txbusy = 1;
812 #endif
813 uart_unlock(sc->sc_hwmtx);
814 return (0);
815 }
816
817 static void
oct16550_bus_grab(struct uart_softc * sc)818 oct16550_bus_grab(struct uart_softc *sc)
819 {
820 struct uart_bas *bas = &sc->sc_bas;
821
822 /*
823 * turn off all interrupts to enter polling mode. Leave the
824 * saved mask alone. We'll restore whatever it was in ungrab.
825 * All pending interupt signals are reset when IER is set to 0.
826 */
827 uart_lock(sc->sc_hwmtx);
828 uart_setreg(bas, REG_IER, 0);
829 uart_barrier(bas);
830 uart_unlock(sc->sc_hwmtx);
831 }
832
833 static void
oct16550_bus_ungrab(struct uart_softc * sc)834 oct16550_bus_ungrab(struct uart_softc *sc)
835 {
836 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
837 struct uart_bas *bas = &sc->sc_bas;
838
839 /*
840 * Restore previous interrupt mask
841 */
842 uart_lock(sc->sc_hwmtx);
843 uart_setreg(bas, REG_IER, oct16550->ier);
844 uart_barrier(bas);
845 uart_unlock(sc->sc_hwmtx);
846 }
847