1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010 Adrian Chadd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include "opt_ddb.h"
33
34 #include <sys/param.h>
35 #include <sys/conf.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/cons.h>
40 #include <sys/kdb.h>
41 #include <sys/reboot.h>
42
43 #include <vm/vm.h>
44 #include <vm/vm_page.h>
45
46 #include <net/ethernet.h>
47
48 #include <machine/clock.h>
49 #include <machine/cpu.h>
50 #include <machine/cpuregs.h>
51 #include <machine/hwfunc.h>
52 #include <machine/md_var.h>
53 #include <machine/trap.h>
54 #include <machine/vmparam.h>
55
56 #include <mips/atheros/ar71xxreg.h>
57 #include <mips/atheros/ar933xreg.h>
58 #include <mips/atheros/ar934xreg.h>
59 #include <mips/atheros/qca955xreg.h>
60 #include <mips/atheros/qca953xreg.h>
61
62 #include <mips/atheros/ar71xx_setup.h>
63
64 #include <mips/atheros/ar71xx_cpudef.h>
65
66 #include <mips/atheros/ar71xx_chip.h>
67 #include <mips/atheros/ar724x_chip.h>
68 #include <mips/atheros/ar91xx_chip.h>
69 #include <mips/atheros/ar933x_chip.h>
70 #include <mips/atheros/ar934x_chip.h>
71 #include <mips/atheros/qca953x_chip.h>
72 #include <mips/atheros/qca955x_chip.h>
73
74 #define AR71XX_SYS_TYPE_LEN 128
75
76 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
77 enum ar71xx_soc_type ar71xx_soc;
78 struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
79
80 void
ar71xx_detect_sys_type(void)81 ar71xx_detect_sys_type(void)
82 {
83 char *chip = "????";
84 uint32_t id;
85 uint32_t major;
86 uint32_t minor;
87 uint32_t rev = 0;
88
89 id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
90 major = id & REV_ID_MAJOR_MASK;
91
92 switch (major) {
93 case REV_ID_MAJOR_AR71XX:
94 minor = id & AR71XX_REV_ID_MINOR_MASK;
95 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
96 rev &= AR71XX_REV_ID_REVISION_MASK;
97 ar71xx_cpu_ops = &ar71xx_chip_def;
98 switch (minor) {
99 case AR71XX_REV_ID_MINOR_AR7130:
100 ar71xx_soc = AR71XX_SOC_AR7130;
101 chip = "7130";
102 break;
103
104 case AR71XX_REV_ID_MINOR_AR7141:
105 ar71xx_soc = AR71XX_SOC_AR7141;
106 chip = "7141";
107 break;
108
109 case AR71XX_REV_ID_MINOR_AR7161:
110 ar71xx_soc = AR71XX_SOC_AR7161;
111 chip = "7161";
112 break;
113 }
114 break;
115
116 case REV_ID_MAJOR_AR7240:
117 ar71xx_soc = AR71XX_SOC_AR7240;
118 chip = "7240";
119 ar71xx_cpu_ops = &ar724x_chip_def;
120 rev = (id & AR724X_REV_ID_REVISION_MASK);
121 break;
122
123 case REV_ID_MAJOR_AR7241:
124 ar71xx_soc = AR71XX_SOC_AR7241;
125 chip = "7241";
126 ar71xx_cpu_ops = &ar724x_chip_def;
127 rev = (id & AR724X_REV_ID_REVISION_MASK);
128 break;
129
130 case REV_ID_MAJOR_AR7242:
131 ar71xx_soc = AR71XX_SOC_AR7242;
132 chip = "7242";
133 ar71xx_cpu_ops = &ar724x_chip_def;
134 rev = (id & AR724X_REV_ID_REVISION_MASK);
135 break;
136
137 case REV_ID_MAJOR_AR913X:
138 minor = id & AR91XX_REV_ID_MINOR_MASK;
139 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
140 rev &= AR91XX_REV_ID_REVISION_MASK;
141 ar71xx_cpu_ops = &ar91xx_chip_def;
142 switch (minor) {
143 case AR91XX_REV_ID_MINOR_AR9130:
144 ar71xx_soc = AR71XX_SOC_AR9130;
145 chip = "9130";
146 break;
147
148 case AR91XX_REV_ID_MINOR_AR9132:
149 ar71xx_soc = AR71XX_SOC_AR9132;
150 chip = "9132";
151 break;
152 }
153 break;
154 case REV_ID_MAJOR_AR9330:
155 minor = 0;
156 rev = (id & AR933X_REV_ID_REVISION_MASK);
157 chip = "9330";
158 ar71xx_cpu_ops = &ar933x_chip_def;
159 ar71xx_soc = AR71XX_SOC_AR9330;
160 break;
161 case REV_ID_MAJOR_AR9331:
162 minor = 1;
163 rev = (id & AR933X_REV_ID_REVISION_MASK);
164 chip = "9331";
165 ar71xx_soc = AR71XX_SOC_AR9331;
166 ar71xx_cpu_ops = &ar933x_chip_def;
167 break;
168
169 case REV_ID_MAJOR_AR9341:
170 minor = 0;
171 rev = (id & AR934X_REV_ID_REVISION_MASK);
172 chip = "9341";
173 ar71xx_soc = AR71XX_SOC_AR9341;
174 ar71xx_cpu_ops = &ar934x_chip_def;
175 break;
176
177 case REV_ID_MAJOR_AR9342:
178 minor = 0;
179 rev = (id & AR934X_REV_ID_REVISION_MASK);
180 chip = "9342";
181 ar71xx_soc = AR71XX_SOC_AR9342;
182 ar71xx_cpu_ops = &ar934x_chip_def;
183 break;
184
185 case REV_ID_MAJOR_AR9344:
186 minor = 0;
187 rev = (id & AR934X_REV_ID_REVISION_MASK);
188 chip = "9344";
189 ar71xx_soc = AR71XX_SOC_AR9344;
190 ar71xx_cpu_ops = &ar934x_chip_def;
191 break;
192
193 case REV_ID_MAJOR_QCA9533:
194 minor = 0;
195 rev = (id & QCA953X_REV_ID_REVISION_MASK);
196 chip = "9533";
197 ar71xx_soc = AR71XX_SOC_QCA9533;
198 ar71xx_cpu_ops = &qca953x_chip_def;
199 break;
200
201 case REV_ID_MAJOR_QCA9533_V2:
202 minor = 0;
203 rev = (id & QCA953X_REV_ID_REVISION_MASK);
204 chip = "9533v2";
205 ar71xx_soc = AR71XX_SOC_QCA9533_V2;
206 ar71xx_cpu_ops = &qca953x_chip_def;
207 break;
208
209 case REV_ID_MAJOR_QCA9556:
210 minor = 0;
211 rev = (id & QCA955X_REV_ID_REVISION_MASK);
212 chip = "9556";
213 ar71xx_soc = AR71XX_SOC_QCA9556;
214 ar71xx_cpu_ops = &qca955x_chip_def;
215 break;
216
217 case REV_ID_MAJOR_QCA9558:
218 minor = 0;
219 rev = (id & QCA955X_REV_ID_REVISION_MASK);
220 chip = "9558";
221 ar71xx_soc = AR71XX_SOC_QCA9558;
222 ar71xx_cpu_ops = &qca955x_chip_def;
223 break;
224
225 default:
226 panic("ar71xx: unknown chip id:0x%08x\n", id);
227 }
228
229 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
230 }
231
232 const char *
ar71xx_get_system_type(void)233 ar71xx_get_system_type(void)
234 {
235 return ar71xx_sys_type;
236 }
237