1 /*-
2 * Copyright (c) 2016 Stormshield
3 * Copyright (c) 2016 Semihalf
4 * All rights reserved.
5 *
6 * Developed by Semihalf.
7 *
8 * Portions of this software were developed by Semihalf
9 * under sponsorship from the FreeBSD Foundation.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of MARVELL nor the names of contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 /*
37 * Marvell integrated PCI/PCI-Express Bus Controller Driver.
38 */
39
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/lock.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/bus.h>
50 #include <sys/rman.h>
51
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 static int mv_pcib_ctrl_probe(device_t);
56 static int mv_pcib_ctrl_attach(device_t);
57 static device_t mv_pcib_ctrl_add_child(device_t, u_int, const char *, int);
58 static const struct ofw_bus_devinfo * mv_pcib_ctrl_get_devinfo(device_t, device_t);
59 static struct resource * mv_pcib_ctrl_alloc_resource(device_t, device_t, int,
60 int *, rman_res_t, rman_res_t, rman_res_t, u_int);
61 void mv_pcib_ctrl_init(device_t, phandle_t);
62 static int mv_pcib_ofw_bus_attach(device_t);
63
64 struct mv_pcib_ctrl_range {
65 uint64_t bus;
66 uint64_t host;
67 uint64_t size;
68 };
69
70 typedef int (*get_rl_t)(device_t dev, phandle_t node, pcell_t acells,
71 pcell_t scells, struct resource_list *rl);
72
73 struct mv_pcib_ctrl_softc {
74 pcell_t addr_cells;
75 pcell_t size_cells;
76 int nranges;
77 struct mv_pcib_ctrl_range *ranges;
78 };
79
80 struct mv_pcib_ctrl_devinfo {
81 struct ofw_bus_devinfo di_dinfo;
82 struct resource_list di_rl;
83 };
84
85 static int mv_pcib_ctrl_fill_ranges(phandle_t, struct mv_pcib_ctrl_softc *);
86
87 /*
88 * Bus interface definitions
89 */
90 static device_method_t mv_pcib_ctrl_methods[] = {
91 /* Device interface */
92 DEVMETHOD(device_probe, mv_pcib_ctrl_probe),
93 DEVMETHOD(device_attach, mv_pcib_ctrl_attach),
94
95 /* Bus interface */
96 DEVMETHOD(bus_add_child, mv_pcib_ctrl_add_child),
97 DEVMETHOD(bus_alloc_resource, mv_pcib_ctrl_alloc_resource),
98 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
99 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
100 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
101 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
102
103 /* ofw_bus interface */
104 DEVMETHOD(ofw_bus_get_devinfo, mv_pcib_ctrl_get_devinfo),
105 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
106 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
107 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
108 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
109 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
110
111 DEVMETHOD_END
112 };
113
114 static struct ofw_compat_data mv_pcib_ctrl_compat[] = {
115 {"mrvl,pcie-ctrl", (uintptr_t)&ofw_bus_reg_to_rl},
116 {"marvell,armada-370-pcie",
117 (uintptr_t)&ofw_bus_assigned_addresses_to_rl},
118 {NULL, (uintptr_t)NULL},
119 };
120
121 static driver_t mv_pcib_ctrl_driver = {
122 "pcib_ctrl",
123 mv_pcib_ctrl_methods,
124 sizeof(struct mv_pcib_ctrl_softc),
125 };
126
127 devclass_t pcib_ctrl_devclass;
128
129 DRIVER_MODULE(pcib_ctrl, simplebus, mv_pcib_ctrl_driver, pcib_ctrl_devclass, 0, 0);
130
131 MALLOC_DEFINE(M_PCIB_CTRL, "PCIe Bus Controller",
132 "Marvell Integrated PCIe Bus Controller");
133
134 static int
mv_pcib_ctrl_probe(device_t dev)135 mv_pcib_ctrl_probe(device_t dev)
136 {
137
138 if (!ofw_bus_status_okay(dev))
139 return (ENXIO);
140
141 if (!ofw_bus_search_compatible(dev, mv_pcib_ctrl_compat)->ocd_data)
142 return (ENXIO);
143
144 device_set_desc(dev, "Marvell Integrated PCIe Bus Controller");
145 return (BUS_PROBE_DEFAULT);
146 }
147
148 static int
mv_pcib_ctrl_attach(device_t dev)149 mv_pcib_ctrl_attach(device_t dev)
150 {
151 int err;
152
153 err = mv_pcib_ofw_bus_attach(dev);
154 if (err != 0)
155 return (err);
156
157 return (bus_generic_attach(dev));
158 }
159
160 static int
mv_pcib_ofw_bus_attach(device_t dev)161 mv_pcib_ofw_bus_attach(device_t dev)
162 {
163 struct mv_pcib_ctrl_devinfo *di;
164 struct mv_pcib_ctrl_softc *sc;
165 device_t child;
166 phandle_t parent, node;
167 get_rl_t get_rl;
168
169 parent = ofw_bus_get_node(dev);
170 sc = device_get_softc(dev);
171 if (parent > 0) {
172 sc->addr_cells = 1;
173 if (OF_getencprop(parent, "#address-cells", &(sc->addr_cells),
174 sizeof(sc->addr_cells)) <= 0)
175 return(ENXIO);
176
177 sc->size_cells = 1;
178 if (OF_getencprop(parent, "#size-cells", &(sc->size_cells),
179 sizeof(sc->size_cells)) <= 0)
180 return(ENXIO);
181
182 for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
183 di = malloc(sizeof(*di), M_PCIB_CTRL, M_WAITOK | M_ZERO);
184 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node)) {
185 if (bootverbose) {
186 device_printf(dev,
187 "Could not set up devinfo for PCI\n");
188 }
189 free(di, M_PCIB_CTRL);
190 continue;
191 }
192
193 child = device_add_child(dev, NULL, -1);
194 if (child == NULL) {
195 if (bootverbose) {
196 device_printf(dev,
197 "Could not add child: %s\n",
198 di->di_dinfo.obd_name);
199 }
200 ofw_bus_gen_destroy_devinfo(&di->di_dinfo);
201 free(di, M_PCIB_CTRL);
202 continue;
203 }
204
205 resource_list_init(&di->di_rl);
206 get_rl = (get_rl_t) ofw_bus_search_compatible(dev,
207 mv_pcib_ctrl_compat)->ocd_data;
208 if (get_rl != NULL)
209 get_rl(child, node, sc->addr_cells,
210 sc->size_cells, &di->di_rl);
211
212 device_set_ivars(child, di);
213 }
214 }
215
216 if (mv_pcib_ctrl_fill_ranges(parent, sc) < 0) {
217 device_printf(dev, "could not get ranges\n");
218 return (ENXIO);
219 }
220
221 return (0);
222 }
223
224 static device_t
mv_pcib_ctrl_add_child(device_t dev,u_int order,const char * name,int unit)225 mv_pcib_ctrl_add_child(device_t dev, u_int order, const char *name, int unit)
226 {
227 device_t cdev;
228 struct mv_pcib_ctrl_devinfo *di;
229
230 cdev = device_add_child_ordered(dev, order, name, unit);
231 if (cdev == NULL)
232 return (NULL);
233
234 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
235 di->di_dinfo.obd_node = -1;
236 resource_list_init(&di->di_rl);
237 device_set_ivars(cdev, di);
238
239 return (cdev);
240 }
241
242 static struct resource *
mv_pcib_ctrl_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)243 mv_pcib_ctrl_alloc_resource(device_t bus, device_t child, int type, int *rid,
244 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
245 {
246 struct mv_pcib_ctrl_devinfo *di;
247 struct resource_list_entry *rle;
248 struct mv_pcib_ctrl_softc *sc;
249 int i;
250
251 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
252 if ((di = device_get_ivars(child)) == NULL)
253 return (NULL);
254 if (type != SYS_RES_MEMORY)
255 return (NULL);
256
257 /* Find defaults for this rid */
258 rle = resource_list_find(&di->di_rl, type, *rid);
259
260 if (rle == NULL)
261 return (NULL);
262
263 start = rle->start;
264 end = rle->end;
265 count = rle->count;
266 }
267
268 sc = device_get_softc(bus);
269 if (type == SYS_RES_MEMORY) {
270 /* Remap through ranges property */
271 for (i = 0; i < sc->nranges; i++) {
272 if (start >= sc->ranges[i].bus && end <
273 sc->ranges[i].bus + sc->ranges[i].size) {
274 start -= sc->ranges[i].bus;
275 start += sc->ranges[i].host;
276 end -= sc->ranges[i].bus;
277 end += sc->ranges[i].host;
278 break;
279 }
280 }
281
282 if (i == sc->nranges && sc->nranges != 0) {
283 device_printf(bus, "Could not map resource "
284 "%#llx-%#llx\n", start, end);
285 return (NULL);
286 }
287 }
288
289 return (bus_generic_alloc_resource(bus, child, type, rid, start, end,
290 count, flags));
291 }
292
293 static int
mv_pcib_ctrl_fill_ranges(phandle_t node,struct mv_pcib_ctrl_softc * sc)294 mv_pcib_ctrl_fill_ranges(phandle_t node, struct mv_pcib_ctrl_softc *sc)
295 {
296 int host_address_cells;
297 cell_t *base_ranges;
298 ssize_t nbase_ranges;
299 int err;
300 int i, j, k;
301
302 err = OF_searchencprop(OF_parent(node), "#address-cells",
303 &host_address_cells, sizeof(host_address_cells));
304 if (err <= 0)
305 return (-1);
306
307 nbase_ranges = OF_getproplen(node, "ranges");
308 if (nbase_ranges < 0)
309 return (-1);
310 sc->nranges = nbase_ranges / sizeof(cell_t) /
311 (sc->addr_cells + host_address_cells + sc->size_cells);
312 if (sc->nranges == 0)
313 return (0);
314
315 sc->ranges = malloc(sc->nranges * sizeof(sc->ranges[0]),
316 M_DEVBUF, M_WAITOK);
317 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK);
318 OF_getencprop(node, "ranges", base_ranges, nbase_ranges);
319
320 for (i = 0, j = 0; i < sc->nranges; i++) {
321 sc->ranges[i].bus = 0;
322 for (k = 0; k < sc->addr_cells; k++) {
323 sc->ranges[i].bus <<= 32;
324 sc->ranges[i].bus |= base_ranges[j++];
325 }
326 sc->ranges[i].host = 0;
327 for (k = 0; k < host_address_cells; k++) {
328 sc->ranges[i].host <<= 32;
329 sc->ranges[i].host |= base_ranges[j++];
330 }
331 sc->ranges[i].size = 0;
332 for (k = 0; k < sc->size_cells; k++) {
333 sc->ranges[i].size <<= 32;
334 sc->ranges[i].size |= base_ranges[j++];
335 }
336 }
337
338 free(base_ranges, M_DEVBUF);
339 return (sc->nranges);
340 }
341
342 static const struct ofw_bus_devinfo *
mv_pcib_ctrl_get_devinfo(device_t bus __unused,device_t child)343 mv_pcib_ctrl_get_devinfo(device_t bus __unused, device_t child)
344 {
345 struct mv_pcib_ctrl_devinfo *di;
346
347 di = device_get_ivars(child);
348 return (&di->di_dinfo);
349 }
350