1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
3 * All rights reserved.
4 * www.cavium.com
5 */
6
7 #include "qede_ethdev.h"
8 #include <rte_string_fns.h>
9 #include <rte_alarm.h>
10 #include <rte_kvargs.h>
11
12 static const struct qed_eth_ops *qed_ops;
13 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
14 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
15
16 #define QEDE_SP_TIMER_PERIOD 10000 /* 100ms */
17
18 struct rte_qede_xstats_name_off {
19 char name[RTE_ETH_XSTATS_NAME_SIZE];
20 uint64_t offset;
21 };
22
23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
24 {"rx_unicast_bytes",
25 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
26 {"rx_multicast_bytes",
27 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
28 {"rx_broadcast_bytes",
29 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
30 {"rx_unicast_packets",
31 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
32 {"rx_multicast_packets",
33 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
34 {"rx_broadcast_packets",
35 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
36
37 {"tx_unicast_bytes",
38 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
39 {"tx_multicast_bytes",
40 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
41 {"tx_broadcast_bytes",
42 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
43 {"tx_unicast_packets",
44 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
45 {"tx_multicast_packets",
46 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
47 {"tx_broadcast_packets",
48 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
49
50 {"rx_64_byte_packets",
51 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
52 {"rx_65_to_127_byte_packets",
53 offsetof(struct ecore_eth_stats_common,
54 rx_65_to_127_byte_packets)},
55 {"rx_128_to_255_byte_packets",
56 offsetof(struct ecore_eth_stats_common,
57 rx_128_to_255_byte_packets)},
58 {"rx_256_to_511_byte_packets",
59 offsetof(struct ecore_eth_stats_common,
60 rx_256_to_511_byte_packets)},
61 {"rx_512_to_1023_byte_packets",
62 offsetof(struct ecore_eth_stats_common,
63 rx_512_to_1023_byte_packets)},
64 {"rx_1024_to_1518_byte_packets",
65 offsetof(struct ecore_eth_stats_common,
66 rx_1024_to_1518_byte_packets)},
67 {"tx_64_byte_packets",
68 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
69 {"tx_65_to_127_byte_packets",
70 offsetof(struct ecore_eth_stats_common,
71 tx_65_to_127_byte_packets)},
72 {"tx_128_to_255_byte_packets",
73 offsetof(struct ecore_eth_stats_common,
74 tx_128_to_255_byte_packets)},
75 {"tx_256_to_511_byte_packets",
76 offsetof(struct ecore_eth_stats_common,
77 tx_256_to_511_byte_packets)},
78 {"tx_512_to_1023_byte_packets",
79 offsetof(struct ecore_eth_stats_common,
80 tx_512_to_1023_byte_packets)},
81 {"tx_1024_to_1518_byte_packets",
82 offsetof(struct ecore_eth_stats_common,
83 tx_1024_to_1518_byte_packets)},
84
85 {"rx_mac_crtl_frames",
86 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
87 {"tx_mac_control_frames",
88 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
89 {"rx_pause_frames",
90 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
91 {"tx_pause_frames",
92 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
93 {"rx_priority_flow_control_frames",
94 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
95 {"tx_priority_flow_control_frames",
96 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
97
98 {"rx_crc_errors",
99 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
100 {"rx_align_errors",
101 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
102 {"rx_carrier_errors",
103 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
104 {"rx_oversize_packet_errors",
105 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
106 {"rx_jabber_errors",
107 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
108 {"rx_undersize_packet_errors",
109 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
110 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
111 {"rx_host_buffer_not_available",
112 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
113 /* Number of packets discarded because they are bigger than MTU */
114 {"rx_packet_too_big_discards",
115 offsetof(struct ecore_eth_stats_common,
116 packet_too_big_discard)},
117 {"rx_ttl_zero_discards",
118 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
119 {"rx_multi_function_tag_filter_discards",
120 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
121 {"rx_mac_filter_discards",
122 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
123 {"rx_gft_filter_drop",
124 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
125 {"rx_hw_buffer_truncates",
126 offsetof(struct ecore_eth_stats_common, brb_truncates)},
127 {"rx_hw_buffer_discards",
128 offsetof(struct ecore_eth_stats_common, brb_discards)},
129 {"tx_error_drop_packets",
130 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
131
132 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
133 {"rx_mac_unicast_packets",
134 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
135 {"rx_mac_multicast_packets",
136 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
137 {"rx_mac_broadcast_packets",
138 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
139 {"rx_mac_frames_ok",
140 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
141 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
142 {"tx_mac_unicast_packets",
143 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
144 {"tx_mac_multicast_packets",
145 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
146 {"tx_mac_broadcast_packets",
147 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
148
149 {"lro_coalesced_packets",
150 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
151 {"lro_coalesced_events",
152 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
153 {"lro_aborts_num",
154 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
155 {"lro_not_coalesced_packets",
156 offsetof(struct ecore_eth_stats_common,
157 tpa_not_coalesced_pkts)},
158 {"lro_coalesced_bytes",
159 offsetof(struct ecore_eth_stats_common,
160 tpa_coalesced_bytes)},
161 };
162
163 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
164 {"rx_1519_to_1522_byte_packets",
165 offsetof(struct ecore_eth_stats, bb) +
166 offsetof(struct ecore_eth_stats_bb,
167 rx_1519_to_1522_byte_packets)},
168 {"rx_1519_to_2047_byte_packets",
169 offsetof(struct ecore_eth_stats, bb) +
170 offsetof(struct ecore_eth_stats_bb,
171 rx_1519_to_2047_byte_packets)},
172 {"rx_2048_to_4095_byte_packets",
173 offsetof(struct ecore_eth_stats, bb) +
174 offsetof(struct ecore_eth_stats_bb,
175 rx_2048_to_4095_byte_packets)},
176 {"rx_4096_to_9216_byte_packets",
177 offsetof(struct ecore_eth_stats, bb) +
178 offsetof(struct ecore_eth_stats_bb,
179 rx_4096_to_9216_byte_packets)},
180 {"rx_9217_to_16383_byte_packets",
181 offsetof(struct ecore_eth_stats, bb) +
182 offsetof(struct ecore_eth_stats_bb,
183 rx_9217_to_16383_byte_packets)},
184
185 {"tx_1519_to_2047_byte_packets",
186 offsetof(struct ecore_eth_stats, bb) +
187 offsetof(struct ecore_eth_stats_bb,
188 tx_1519_to_2047_byte_packets)},
189 {"tx_2048_to_4095_byte_packets",
190 offsetof(struct ecore_eth_stats, bb) +
191 offsetof(struct ecore_eth_stats_bb,
192 tx_2048_to_4095_byte_packets)},
193 {"tx_4096_to_9216_byte_packets",
194 offsetof(struct ecore_eth_stats, bb) +
195 offsetof(struct ecore_eth_stats_bb,
196 tx_4096_to_9216_byte_packets)},
197 {"tx_9217_to_16383_byte_packets",
198 offsetof(struct ecore_eth_stats, bb) +
199 offsetof(struct ecore_eth_stats_bb,
200 tx_9217_to_16383_byte_packets)},
201
202 {"tx_lpi_entry_count",
203 offsetof(struct ecore_eth_stats, bb) +
204 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
205 {"tx_total_collisions",
206 offsetof(struct ecore_eth_stats, bb) +
207 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
208 };
209
210 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
211 {"rx_1519_to_max_byte_packets",
212 offsetof(struct ecore_eth_stats, ah) +
213 offsetof(struct ecore_eth_stats_ah,
214 rx_1519_to_max_byte_packets)},
215 {"tx_1519_to_max_byte_packets",
216 offsetof(struct ecore_eth_stats, ah) +
217 offsetof(struct ecore_eth_stats_ah,
218 tx_1519_to_max_byte_packets)},
219 };
220
221 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
222 {"rx_q_segments",
223 offsetof(struct qede_rx_queue, rx_segs)},
224 {"rx_q_hw_errors",
225 offsetof(struct qede_rx_queue, rx_hw_errors)},
226 {"rx_q_allocation_errors",
227 offsetof(struct qede_rx_queue, rx_alloc_errors)}
228 };
229
230 /* Get FW version string based on fw_size */
231 static int
qede_fw_version_get(struct rte_eth_dev * dev,char * fw_ver,size_t fw_size)232 qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
233 {
234 struct qede_dev *qdev = dev->data->dev_private;
235 struct ecore_dev *edev = &qdev->edev;
236 struct qed_dev_info *info = &qdev->dev_info.common;
237 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
238 size_t size;
239
240 if (fw_ver == NULL)
241 return 0;
242
243 if (IS_PF(edev))
244 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
245 QEDE_PMD_FW_VERSION);
246 else
247 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
248 info->fw_major, info->fw_minor,
249 info->fw_rev, info->fw_eng);
250 size = strlen(ver_str);
251 if (size + 1 <= fw_size) /* Add 1 byte for "\0" */
252 strlcpy(fw_ver, ver_str, fw_size);
253 else
254 return (size + 1);
255
256 snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
257 " MFW: %d.%d.%d.%d",
258 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_3),
259 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_2),
260 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_1),
261 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_0));
262 size = strlen(ver_str);
263 if (size + 1 <= fw_size)
264 strlcpy(fw_ver, ver_str, fw_size);
265
266 if (fw_size <= 32)
267 goto out;
268
269 snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
270 " MBI: %d.%d.%d",
271 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_2),
272 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_1),
273 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_0));
274 size = strlen(ver_str);
275 if (size + 1 <= fw_size)
276 strlcpy(fw_ver, ver_str, fw_size);
277
278 out:
279 return 0;
280 }
281
qede_interrupt_action(struct ecore_hwfn * p_hwfn)282 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
283 {
284 OSAL_SPIN_LOCK(&p_hwfn->spq_lock);
285 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
286 OSAL_SPIN_UNLOCK(&p_hwfn->spq_lock);
287 }
288
289 static void
qede_interrupt_handler_intx(void * param)290 qede_interrupt_handler_intx(void *param)
291 {
292 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
293 struct qede_dev *qdev = eth_dev->data->dev_private;
294 struct ecore_dev *edev = &qdev->edev;
295 u64 status;
296
297 /* Check if our device actually raised an interrupt */
298 status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
299 if (status & 0x1) {
300 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
301
302 if (rte_intr_ack(eth_dev->intr_handle))
303 DP_ERR(edev, "rte_intr_ack failed\n");
304 }
305 }
306
307 static void
qede_interrupt_handler(void * param)308 qede_interrupt_handler(void *param)
309 {
310 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
311 struct qede_dev *qdev = eth_dev->data->dev_private;
312 struct ecore_dev *edev = &qdev->edev;
313
314 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
315 if (rte_intr_ack(eth_dev->intr_handle))
316 DP_ERR(edev, "rte_intr_ack failed\n");
317 }
318
319 static void
qede_assign_rxtx_handlers(struct rte_eth_dev * dev,bool is_dummy)320 qede_assign_rxtx_handlers(struct rte_eth_dev *dev, bool is_dummy)
321 {
322 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
323 struct qede_dev *qdev = dev->data->dev_private;
324 struct ecore_dev *edev = &qdev->edev;
325 bool use_tx_offload = false;
326
327 if (is_dummy) {
328 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
329 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
330 return;
331 }
332
333 if (ECORE_IS_CMT(edev)) {
334 dev->rx_pkt_burst = qede_recv_pkts_cmt;
335 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
336 return;
337 }
338
339 if (dev->data->lro || dev->data->scattered_rx) {
340 DP_INFO(edev, "Assigning qede_recv_pkts\n");
341 dev->rx_pkt_burst = qede_recv_pkts;
342 } else {
343 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
344 dev->rx_pkt_burst = qede_recv_pkts_regular;
345 }
346
347 use_tx_offload = !!(tx_offloads &
348 (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */
349 DEV_TX_OFFLOAD_TCP_TSO | /* tso */
350 DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */
351
352 if (use_tx_offload) {
353 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
354 dev->tx_pkt_burst = qede_xmit_pkts;
355 } else {
356 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
357 dev->tx_pkt_burst = qede_xmit_pkts_regular;
358 }
359 }
360
361 static void
qede_alloc_etherdev(struct qede_dev * qdev,struct qed_dev_eth_info * info)362 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
363 {
364 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
365 qdev->ops = qed_ops;
366 }
367
qede_print_adapter_info(struct rte_eth_dev * dev)368 static void qede_print_adapter_info(struct rte_eth_dev *dev)
369 {
370 struct qede_dev *qdev = dev->data->dev_private;
371 struct ecore_dev *edev = &qdev->edev;
372 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
373
374 DP_INFO(edev, "**************************************************\n");
375 DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version());
376 DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details",
377 ECORE_IS_BB(edev) ? "BB" : "AH",
378 'A' + edev->chip_rev,
379 (int)edev->chip_metal);
380 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
381 QEDE_PMD_DRV_VERSION);
382 DP_INFO(edev, " %-20s: %s\n", "Driver version", ver_str);
383 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
384 QEDE_PMD_BASE_VERSION);
385 DP_INFO(edev, " %-20s: %s\n", "Base version", ver_str);
386 qede_fw_version_get(dev, ver_str, sizeof(ver_str));
387 DP_INFO(edev, " %-20s: %s\n", "Firmware version", ver_str);
388 DP_INFO(edev, " %-20s: %s\n", "Firmware file", qede_fw_file);
389 DP_INFO(edev, "**************************************************\n");
390 }
391
qede_reset_queue_stats(struct qede_dev * qdev,bool xstats)392 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
393 {
394 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
395 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
396 unsigned int i = 0, j = 0, qid;
397 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
398 struct qede_tx_queue *txq;
399
400 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
401
402 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
403 RTE_ETHDEV_QUEUE_STAT_CNTRS);
404 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
405 RTE_ETHDEV_QUEUE_STAT_CNTRS);
406
407 for (qid = 0; qid < qdev->num_rx_queues; qid++) {
408 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
409 offsetof(struct qede_rx_queue, rcv_pkts), 0,
410 sizeof(uint64_t));
411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
412 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
413 sizeof(uint64_t));
414 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
415 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
416 sizeof(uint64_t));
417
418 if (xstats)
419 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
420 OSAL_MEMSET((((char *)
421 (qdev->fp_array[qid].rxq)) +
422 qede_rxq_xstats_strings[j].offset),
423 0,
424 sizeof(uint64_t));
425
426 i++;
427 if (i == rxq_stat_cntrs)
428 break;
429 }
430
431 i = 0;
432
433 for (qid = 0; qid < qdev->num_tx_queues; qid++) {
434 txq = qdev->fp_array[qid].txq;
435
436 OSAL_MEMSET((uint64_t *)(uintptr_t)
437 (((uint64_t)(uintptr_t)(txq)) +
438 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
439 sizeof(uint64_t));
440
441 i++;
442 if (i == txq_stat_cntrs)
443 break;
444 }
445 }
446
447 static int
qede_stop_vport(struct ecore_dev * edev)448 qede_stop_vport(struct ecore_dev *edev)
449 {
450 struct ecore_hwfn *p_hwfn;
451 uint8_t vport_id;
452 int rc;
453 int i;
454
455 vport_id = 0;
456 for_each_hwfn(edev, i) {
457 p_hwfn = &edev->hwfns[i];
458 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
459 vport_id);
460 if (rc != ECORE_SUCCESS) {
461 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
462 return rc;
463 }
464 }
465
466 DP_INFO(edev, "vport stopped\n");
467
468 return 0;
469 }
470
471 static int
qede_start_vport(struct qede_dev * qdev,uint16_t mtu)472 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
473 {
474 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
475 struct ecore_sp_vport_start_params params;
476 struct ecore_hwfn *p_hwfn;
477 int rc;
478 int i;
479
480 if (qdev->vport_started)
481 qede_stop_vport(edev);
482
483 memset(¶ms, 0, sizeof(params));
484 params.vport_id = 0;
485 params.mtu = mtu;
486 /* @DPDK - Disable FW placement */
487 params.zero_placement_offset = 1;
488 for_each_hwfn(edev, i) {
489 p_hwfn = &edev->hwfns[i];
490 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
491 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
492 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
493 if (rc != ECORE_SUCCESS) {
494 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
495 return rc;
496 }
497 }
498 ecore_reset_vport_stats(edev);
499 qdev->vport_started = true;
500 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
501
502 return 0;
503 }
504
505 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching"
506 #define QEDE_VF_TX_SWITCHING "vf_tx_switching"
507
508 /* Activate or deactivate vport via vport-update */
qede_activate_vport(struct rte_eth_dev * eth_dev,bool flg)509 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
510 {
511 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
512 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
513 struct ecore_sp_vport_update_params params;
514 struct ecore_hwfn *p_hwfn;
515 uint8_t i;
516 int rc = -1;
517
518 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
519 params.vport_id = 0;
520 params.update_vport_active_rx_flg = 1;
521 params.update_vport_active_tx_flg = 1;
522 params.vport_active_rx_flg = flg;
523 params.vport_active_tx_flg = flg;
524 if ((qdev->enable_tx_switching == false) && (flg == true)) {
525 params.update_tx_switching_flg = 1;
526 params.tx_switching_flg = !flg;
527 }
528 for_each_hwfn(edev, i) {
529 p_hwfn = &edev->hwfns[i];
530 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
531 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
532 ECORE_SPQ_MODE_EBLOCK, NULL);
533 if (rc != ECORE_SUCCESS) {
534 DP_ERR(edev, "Failed to update vport\n");
535 break;
536 }
537 }
538 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
539
540 return rc;
541 }
542
543 static void
qede_update_sge_tpa_params(struct ecore_sge_tpa_params * sge_tpa_params,uint16_t mtu,bool enable)544 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
545 uint16_t mtu, bool enable)
546 {
547 /* Enable LRO in split mode */
548 sge_tpa_params->tpa_ipv4_en_flg = enable;
549 sge_tpa_params->tpa_ipv6_en_flg = enable;
550 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
551 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
552 /* set if tpa enable changes */
553 sge_tpa_params->update_tpa_en_flg = 1;
554 /* set if tpa parameters should be handled */
555 sge_tpa_params->update_tpa_param_flg = enable;
556
557 sge_tpa_params->max_buffers_per_cqe = 20;
558 /* Enable TPA in split mode. In this mode each TPA segment
559 * starts on the new BD, so there is one BD per segment.
560 */
561 sge_tpa_params->tpa_pkt_split_flg = 1;
562 sge_tpa_params->tpa_hdr_data_split_flg = 0;
563 sge_tpa_params->tpa_gro_consistent_flg = 0;
564 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
565 sge_tpa_params->tpa_max_size = 0x7FFF;
566 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
567 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
568 }
569
570 /* Enable/disable LRO via vport-update */
qede_enable_tpa(struct rte_eth_dev * eth_dev,bool flg)571 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
572 {
573 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
574 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
575 struct ecore_sp_vport_update_params params;
576 struct ecore_sge_tpa_params tpa_params;
577 struct ecore_hwfn *p_hwfn;
578 int rc;
579 int i;
580
581 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
582 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
583 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
584 params.vport_id = 0;
585 params.sge_tpa_params = &tpa_params;
586 for_each_hwfn(edev, i) {
587 p_hwfn = &edev->hwfns[i];
588 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
589 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
590 ECORE_SPQ_MODE_EBLOCK, NULL);
591 if (rc != ECORE_SUCCESS) {
592 DP_ERR(edev, "Failed to update LRO\n");
593 return -1;
594 }
595 }
596 qdev->enable_lro = flg;
597 eth_dev->data->lro = flg;
598
599 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
600
601 return 0;
602 }
603
604 static int
qed_configure_filter_rx_mode(struct rte_eth_dev * eth_dev,enum qed_filter_rx_mode_type type)605 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
606 enum qed_filter_rx_mode_type type)
607 {
608 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
609 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
610 struct ecore_filter_accept_flags flags;
611
612 memset(&flags, 0, sizeof(flags));
613
614 flags.update_rx_mode_config = 1;
615 flags.update_tx_mode_config = 1;
616 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
617 ECORE_ACCEPT_MCAST_MATCHED |
618 ECORE_ACCEPT_BCAST;
619
620 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
621 ECORE_ACCEPT_MCAST_MATCHED |
622 ECORE_ACCEPT_BCAST;
623
624 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
625 flags.rx_accept_filter |= (ECORE_ACCEPT_UCAST_UNMATCHED |
626 ECORE_ACCEPT_MCAST_UNMATCHED);
627 if (IS_VF(edev)) {
628 flags.tx_accept_filter |=
629 (ECORE_ACCEPT_UCAST_UNMATCHED |
630 ECORE_ACCEPT_MCAST_UNMATCHED);
631 DP_INFO(edev, "Enabling Tx unmatched flags for VF\n");
632 }
633 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
634 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
635 }
636
637 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
638 ECORE_SPQ_MODE_CB, NULL);
639 }
640
641 int
qede_ucast_filter(struct rte_eth_dev * eth_dev,struct ecore_filter_ucast * ucast,bool add)642 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
643 bool add)
644 {
645 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
646 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
647 struct qede_ucast_entry *tmp = NULL;
648 struct qede_ucast_entry *u;
649 struct rte_ether_addr *mac_addr;
650
651 mac_addr = (struct rte_ether_addr *)ucast->mac;
652 if (add) {
653 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
654 if ((memcmp(mac_addr, &tmp->mac,
655 RTE_ETHER_ADDR_LEN) == 0) &&
656 ucast->vni == tmp->vni &&
657 ucast->vlan == tmp->vlan) {
658 DP_INFO(edev, "Unicast MAC is already added"
659 " with vlan = %u, vni = %u\n",
660 ucast->vlan, ucast->vni);
661 return 0;
662 }
663 }
664 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
665 RTE_CACHE_LINE_SIZE);
666 if (!u) {
667 DP_ERR(edev, "Did not allocate memory for ucast\n");
668 return -ENOMEM;
669 }
670 rte_ether_addr_copy(mac_addr, &u->mac);
671 u->vlan = ucast->vlan;
672 u->vni = ucast->vni;
673 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
674 qdev->num_uc_addr++;
675 } else {
676 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
677 if ((memcmp(mac_addr, &tmp->mac,
678 RTE_ETHER_ADDR_LEN) == 0) &&
679 ucast->vlan == tmp->vlan &&
680 ucast->vni == tmp->vni)
681 break;
682 }
683 if (tmp == NULL) {
684 DP_INFO(edev, "Unicast MAC is not found\n");
685 return -EINVAL;
686 }
687 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
688 qdev->num_uc_addr--;
689 }
690
691 return 0;
692 }
693
694 static int
qede_add_mcast_filters(struct rte_eth_dev * eth_dev,struct rte_ether_addr * mc_addrs,uint32_t mc_addrs_num)695 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
696 struct rte_ether_addr *mc_addrs,
697 uint32_t mc_addrs_num)
698 {
699 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
700 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
701 struct ecore_filter_mcast mcast;
702 struct qede_mcast_entry *m = NULL;
703 uint8_t i;
704 int rc;
705
706 for (i = 0; i < mc_addrs_num; i++) {
707 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
708 RTE_CACHE_LINE_SIZE);
709 if (!m) {
710 DP_ERR(edev, "Did not allocate memory for mcast\n");
711 return -ENOMEM;
712 }
713 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
714 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
715 }
716 memset(&mcast, 0, sizeof(mcast));
717 mcast.num_mc_addrs = mc_addrs_num;
718 mcast.opcode = ECORE_FILTER_ADD;
719 for (i = 0; i < mc_addrs_num; i++)
720 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
721 &mcast.mac[i]);
722 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
723 if (rc != ECORE_SUCCESS) {
724 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
725 return -1;
726 }
727
728 return 0;
729 }
730
qede_del_mcast_filters(struct rte_eth_dev * eth_dev)731 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
732 {
733 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
734 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
735 struct qede_mcast_entry *tmp = NULL;
736 struct ecore_filter_mcast mcast;
737 int j;
738 int rc;
739
740 memset(&mcast, 0, sizeof(mcast));
741 mcast.num_mc_addrs = qdev->num_mc_addr;
742 mcast.opcode = ECORE_FILTER_REMOVE;
743 j = 0;
744 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
745 rte_ether_addr_copy(&tmp->mac,
746 (struct rte_ether_addr *)&mcast.mac[j]);
747 j++;
748 }
749 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
750 if (rc != ECORE_SUCCESS) {
751 DP_ERR(edev, "Failed to delete multicast filter\n");
752 return -1;
753 }
754 /* Init the list */
755 while (!SLIST_EMPTY(&qdev->mc_list_head)) {
756 tmp = SLIST_FIRST(&qdev->mc_list_head);
757 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
758 }
759 SLIST_INIT(&qdev->mc_list_head);
760
761 return 0;
762 }
763
764 enum _ecore_status_t
qede_mac_int_ops(struct rte_eth_dev * eth_dev,struct ecore_filter_ucast * ucast,bool add)765 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
766 bool add)
767 {
768 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
769 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
770 enum _ecore_status_t rc = ECORE_INVAL;
771
772 if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
773 DP_ERR(edev, "Ucast filter table limit exceeded,"
774 " Please enable promisc mode\n");
775 return ECORE_INVAL;
776 }
777
778 rc = qede_ucast_filter(eth_dev, ucast, add);
779 if (rc == 0)
780 rc = ecore_filter_ucast_cmd(edev, ucast,
781 ECORE_SPQ_MODE_CB, NULL);
782 /* Indicate error only for add filter operation.
783 * Delete filter operations are not severe.
784 */
785 if ((rc != ECORE_SUCCESS) && add)
786 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
787 rc, add);
788
789 return rc;
790 }
791
792 static int
qede_mac_addr_add(struct rte_eth_dev * eth_dev,struct rte_ether_addr * mac_addr,__rte_unused uint32_t index,__rte_unused uint32_t pool)793 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
794 __rte_unused uint32_t index, __rte_unused uint32_t pool)
795 {
796 struct ecore_filter_ucast ucast;
797 int re;
798
799 if (!rte_is_valid_assigned_ether_addr(mac_addr))
800 return -EINVAL;
801
802 qede_set_ucast_cmn_params(&ucast);
803 ucast.opcode = ECORE_FILTER_ADD;
804 ucast.type = ECORE_FILTER_MAC;
805 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
806 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
807 return re;
808 }
809
810 static void
qede_mac_addr_remove(struct rte_eth_dev * eth_dev,uint32_t index)811 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
812 {
813 struct qede_dev *qdev = eth_dev->data->dev_private;
814 struct ecore_dev *edev = &qdev->edev;
815 struct ecore_filter_ucast ucast;
816
817 PMD_INIT_FUNC_TRACE(edev);
818
819 if (index >= qdev->dev_info.num_mac_filters) {
820 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
821 index, qdev->dev_info.num_mac_filters);
822 return;
823 }
824
825 if (!rte_is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index]))
826 return;
827
828 qede_set_ucast_cmn_params(&ucast);
829 ucast.opcode = ECORE_FILTER_REMOVE;
830 ucast.type = ECORE_FILTER_MAC;
831
832 /* Use the index maintained by rte */
833 rte_ether_addr_copy(ð_dev->data->mac_addrs[index],
834 (struct rte_ether_addr *)&ucast.mac);
835
836 qede_mac_int_ops(eth_dev, &ucast, false);
837 }
838
839 static int
qede_mac_addr_set(struct rte_eth_dev * eth_dev,struct rte_ether_addr * mac_addr)840 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
841 {
842 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
843 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
844
845 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
846 mac_addr->addr_bytes)) {
847 DP_ERR(edev, "Setting MAC address is not allowed\n");
848 return -EPERM;
849 }
850
851 qede_mac_addr_remove(eth_dev, 0);
852
853 return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
854 }
855
qede_config_accept_any_vlan(struct qede_dev * qdev,bool flg)856 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
857 {
858 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
859 struct ecore_sp_vport_update_params params;
860 struct ecore_hwfn *p_hwfn;
861 uint8_t i;
862 int rc;
863
864 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
865 params.vport_id = 0;
866 params.update_accept_any_vlan_flg = 1;
867 params.accept_any_vlan = flg;
868 for_each_hwfn(edev, i) {
869 p_hwfn = &edev->hwfns[i];
870 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
871 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
872 ECORE_SPQ_MODE_EBLOCK, NULL);
873 if (rc != ECORE_SUCCESS) {
874 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
875 return;
876 }
877 }
878
879 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
880 }
881
qede_vlan_stripping(struct rte_eth_dev * eth_dev,bool flg)882 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
883 {
884 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
885 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
886 struct ecore_sp_vport_update_params params;
887 struct ecore_hwfn *p_hwfn;
888 uint8_t i;
889 int rc;
890
891 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
892 params.vport_id = 0;
893 params.update_inner_vlan_removal_flg = 1;
894 params.inner_vlan_removal_flg = flg;
895 for_each_hwfn(edev, i) {
896 p_hwfn = &edev->hwfns[i];
897 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
898 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
899 ECORE_SPQ_MODE_EBLOCK, NULL);
900 if (rc != ECORE_SUCCESS) {
901 DP_ERR(edev, "Failed to update vport\n");
902 return -1;
903 }
904 }
905
906 qdev->vlan_strip_flg = flg;
907
908 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
909 return 0;
910 }
911
qede_vlan_filter_set(struct rte_eth_dev * eth_dev,uint16_t vlan_id,int on)912 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
913 uint16_t vlan_id, int on)
914 {
915 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
916 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
917 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
918 struct qede_vlan_entry *tmp = NULL;
919 struct qede_vlan_entry *vlan;
920 struct ecore_filter_ucast ucast;
921 int rc;
922
923 if (on) {
924 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
925 DP_ERR(edev, "Reached max VLAN filter limit"
926 " enabling accept_any_vlan\n");
927 qede_config_accept_any_vlan(qdev, true);
928 return 0;
929 }
930
931 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
932 if (tmp->vid == vlan_id) {
933 DP_INFO(edev, "VLAN %u already configured\n",
934 vlan_id);
935 return 0;
936 }
937 }
938
939 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
940 RTE_CACHE_LINE_SIZE);
941
942 if (!vlan) {
943 DP_ERR(edev, "Did not allocate memory for VLAN\n");
944 return -ENOMEM;
945 }
946
947 qede_set_ucast_cmn_params(&ucast);
948 ucast.opcode = ECORE_FILTER_ADD;
949 ucast.type = ECORE_FILTER_VLAN;
950 ucast.vlan = vlan_id;
951 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
952 NULL);
953 if (rc != 0) {
954 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
955 rc);
956 rte_free(vlan);
957 } else {
958 vlan->vid = vlan_id;
959 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
960 qdev->configured_vlans++;
961 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
962 vlan_id, qdev->configured_vlans);
963 }
964 } else {
965 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
966 if (tmp->vid == vlan_id)
967 break;
968 }
969
970 if (!tmp) {
971 if (qdev->configured_vlans == 0) {
972 DP_INFO(edev,
973 "No VLAN filters configured yet\n");
974 return 0;
975 }
976
977 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
978 return -EINVAL;
979 }
980
981 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
982
983 qede_set_ucast_cmn_params(&ucast);
984 ucast.opcode = ECORE_FILTER_REMOVE;
985 ucast.type = ECORE_FILTER_VLAN;
986 ucast.vlan = vlan_id;
987 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
988 NULL);
989 if (rc != 0) {
990 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
991 vlan_id, rc);
992 } else {
993 qdev->configured_vlans--;
994 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
995 vlan_id, qdev->configured_vlans);
996 }
997 }
998
999 return rc;
1000 }
1001
qede_vlan_offload_set(struct rte_eth_dev * eth_dev,int mask)1002 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1003 {
1004 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1005 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1006 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1007
1008 if (mask & ETH_VLAN_STRIP_MASK) {
1009 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1010 (void)qede_vlan_stripping(eth_dev, 1);
1011 else
1012 (void)qede_vlan_stripping(eth_dev, 0);
1013 }
1014
1015 if (mask & ETH_VLAN_FILTER_MASK) {
1016 /* VLAN filtering kicks in when a VLAN is added */
1017 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1018 qede_vlan_filter_set(eth_dev, 0, 1);
1019 } else {
1020 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1021 DP_ERR(edev,
1022 " Please remove existing VLAN filters"
1023 " before disabling VLAN filtering\n");
1024 /* Signal app that VLAN filtering is still
1025 * enabled
1026 */
1027 eth_dev->data->dev_conf.rxmode.offloads |=
1028 DEV_RX_OFFLOAD_VLAN_FILTER;
1029 } else {
1030 qede_vlan_filter_set(eth_dev, 0, 0);
1031 }
1032 }
1033 }
1034
1035 qdev->vlan_offload_mask = mask;
1036
1037 DP_INFO(edev, "VLAN offload mask %d\n", mask);
1038
1039 return 0;
1040 }
1041
qede_prandom_bytes(uint32_t * buff)1042 static void qede_prandom_bytes(uint32_t *buff)
1043 {
1044 uint8_t i;
1045
1046 srand((unsigned int)time(NULL));
1047 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1048 buff[i] = rand();
1049 }
1050
qede_config_rss(struct rte_eth_dev * eth_dev)1051 int qede_config_rss(struct rte_eth_dev *eth_dev)
1052 {
1053 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1054 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1055 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1056 struct rte_eth_rss_reta_entry64 reta_conf[2];
1057 struct rte_eth_rss_conf rss_conf;
1058 uint32_t i, id, pos, q;
1059
1060 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1061 if (!rss_conf.rss_key) {
1062 DP_INFO(edev, "Applying driver default key\n");
1063 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1064 qede_prandom_bytes(&def_rss_key[0]);
1065 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1066 }
1067
1068 /* Configure RSS hash */
1069 if (qede_rss_hash_update(eth_dev, &rss_conf))
1070 return -EINVAL;
1071
1072 /* Configure default RETA */
1073 memset(reta_conf, 0, sizeof(reta_conf));
1074 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1075 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1076
1077 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1078 id = i / RTE_RETA_GROUP_SIZE;
1079 pos = i % RTE_RETA_GROUP_SIZE;
1080 q = i % QEDE_RSS_COUNT(eth_dev);
1081 reta_conf[id].reta[pos] = q;
1082 }
1083 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1084 ECORE_RSS_IND_TABLE_SIZE))
1085 return -EINVAL;
1086
1087 return 0;
1088 }
1089
qede_fastpath_start(struct ecore_dev * edev)1090 static void qede_fastpath_start(struct ecore_dev *edev)
1091 {
1092 struct ecore_hwfn *p_hwfn;
1093 int i;
1094
1095 for_each_hwfn(edev, i) {
1096 p_hwfn = &edev->hwfns[i];
1097 ecore_hw_start_fastpath(p_hwfn);
1098 }
1099 }
1100
qede_dev_start(struct rte_eth_dev * eth_dev)1101 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1102 {
1103 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1104 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1105 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1106
1107 PMD_INIT_FUNC_TRACE(edev);
1108
1109 /* Update MTU only if it has changed */
1110 if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1111 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1112 goto err;
1113 qdev->mtu = qdev->new_mtu;
1114 qdev->new_mtu = 0;
1115 }
1116
1117 /* Configure TPA parameters */
1118 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1119 if (qede_enable_tpa(eth_dev, true))
1120 return -EINVAL;
1121 /* Enable scatter mode for LRO */
1122 if (!eth_dev->data->scattered_rx)
1123 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1124 }
1125
1126 /* Start queues */
1127 if (qede_start_queues(eth_dev))
1128 goto err;
1129
1130 if (IS_PF(edev))
1131 qede_reset_queue_stats(qdev, true);
1132
1133 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1134 * enabling RSS. Hence RSS configuration is deferred up to this point.
1135 * Also, we would like to retain similar behavior in PF case, so we
1136 * don't do PF/VF specific check here.
1137 */
1138 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1139 if (qede_config_rss(eth_dev))
1140 goto err;
1141
1142 /* Enable vport*/
1143 if (qede_activate_vport(eth_dev, true))
1144 goto err;
1145
1146 /* Bring-up the link */
1147 qede_dev_set_link_state(eth_dev, true);
1148
1149 /* Update link status */
1150 qede_link_update(eth_dev, 0);
1151
1152 /* Start/resume traffic */
1153 qede_fastpath_start(edev);
1154
1155 /* Assign I/O handlers */
1156 qede_assign_rxtx_handlers(eth_dev, false);
1157
1158 DP_INFO(edev, "Device started\n");
1159
1160 return 0;
1161 err:
1162 DP_ERR(edev, "Device start fails\n");
1163 return -1; /* common error code is < 0 */
1164 }
1165
qede_dev_stop(struct rte_eth_dev * eth_dev)1166 static int qede_dev_stop(struct rte_eth_dev *eth_dev)
1167 {
1168 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1169 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1170
1171 PMD_INIT_FUNC_TRACE(edev);
1172 eth_dev->data->dev_started = 0;
1173
1174 /* Bring the link down */
1175 qede_dev_set_link_state(eth_dev, false);
1176
1177 /* Update link status */
1178 qede_link_update(eth_dev, 0);
1179
1180 /* Replace I/O functions with dummy ones. It cannot
1181 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1182 */
1183 qede_assign_rxtx_handlers(eth_dev, true);
1184
1185 /* Disable vport */
1186 if (qede_activate_vport(eth_dev, false))
1187 return 0;
1188
1189 if (qdev->enable_lro)
1190 qede_enable_tpa(eth_dev, false);
1191
1192 /* Stop queues */
1193 qede_stop_queues(eth_dev);
1194
1195 /* Disable traffic */
1196 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1197
1198 DP_INFO(edev, "Device is stopped\n");
1199
1200 return 0;
1201 }
1202
1203 static const char * const valid_args[] = {
1204 QEDE_NPAR_TX_SWITCHING,
1205 QEDE_VF_TX_SWITCHING,
1206 NULL,
1207 };
1208
qede_args_check(const char * key,const char * val,void * opaque)1209 static int qede_args_check(const char *key, const char *val, void *opaque)
1210 {
1211 unsigned long tmp;
1212 int ret = 0;
1213 struct rte_eth_dev *eth_dev = opaque;
1214 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1215 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1216
1217 errno = 0;
1218 tmp = strtoul(val, NULL, 0);
1219 if (errno) {
1220 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1221 return errno;
1222 }
1223
1224 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1225 ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1226 qdev->enable_tx_switching = !!tmp;
1227 DP_INFO(edev, "Disabling %s tx-switching\n",
1228 strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1229 "VF" : "NPAR");
1230 }
1231
1232 return ret;
1233 }
1234
qede_args(struct rte_eth_dev * eth_dev)1235 static int qede_args(struct rte_eth_dev *eth_dev)
1236 {
1237 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1238 struct rte_kvargs *kvlist;
1239 struct rte_devargs *devargs;
1240 int ret;
1241 int i;
1242
1243 devargs = pci_dev->device.devargs;
1244 if (!devargs)
1245 return 0; /* return success */
1246
1247 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1248 if (kvlist == NULL)
1249 return -EINVAL;
1250
1251 /* Process parameters. */
1252 for (i = 0; (valid_args[i] != NULL); ++i) {
1253 if (rte_kvargs_count(kvlist, valid_args[i])) {
1254 ret = rte_kvargs_process(kvlist, valid_args[i],
1255 qede_args_check, eth_dev);
1256 if (ret != ECORE_SUCCESS) {
1257 rte_kvargs_free(kvlist);
1258 return ret;
1259 }
1260 }
1261 }
1262 rte_kvargs_free(kvlist);
1263
1264 return 0;
1265 }
1266
qede_dev_configure(struct rte_eth_dev * eth_dev)1267 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1268 {
1269 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1270 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1271 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1272 uint8_t num_rxqs;
1273 uint8_t num_txqs;
1274 int ret;
1275
1276 PMD_INIT_FUNC_TRACE(edev);
1277
1278 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1279 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1280
1281 /* We need to have min 1 RX queue.There is no min check in
1282 * rte_eth_dev_configure(), so we are checking it here.
1283 */
1284 if (eth_dev->data->nb_rx_queues == 0) {
1285 DP_ERR(edev, "Minimum one RX queue is required\n");
1286 return -EINVAL;
1287 }
1288
1289 /* Enable Tx switching by default */
1290 qdev->enable_tx_switching = 1;
1291
1292 /* Parse devargs and fix up rxmode */
1293 if (qede_args(eth_dev))
1294 DP_NOTICE(edev, false,
1295 "Invalid devargs supplied, requested change will not take effect\n");
1296
1297 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1298 rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1299 DP_ERR(edev, "Unsupported multi-queue mode\n");
1300 return -ENOTSUP;
1301 }
1302 /* Flow director mode check */
1303 if (qede_check_fdir_support(eth_dev))
1304 return -ENOTSUP;
1305
1306 /* Allocate/reallocate fastpath resources only for new queue config */
1307 num_txqs = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1308 num_rxqs = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1309 if (qdev->num_tx_queues != num_txqs ||
1310 qdev->num_rx_queues != num_rxqs) {
1311 qede_dealloc_fp_resc(eth_dev);
1312 qdev->num_tx_queues = num_txqs;
1313 qdev->num_rx_queues = num_rxqs;
1314 if (qede_alloc_fp_resc(qdev))
1315 return -ENOMEM;
1316 }
1317
1318 /* If jumbo enabled adjust MTU */
1319 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1320 eth_dev->data->mtu =
1321 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1322 RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1323
1324 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1325 eth_dev->data->scattered_rx = 1;
1326
1327 if (qede_start_vport(qdev, eth_dev->data->mtu))
1328 return -1;
1329
1330 qdev->mtu = eth_dev->data->mtu;
1331
1332 /* Enable VLAN offloads by default */
1333 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1334 ETH_VLAN_FILTER_MASK);
1335 if (ret)
1336 return ret;
1337
1338 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1339 QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1340
1341 if (ECORE_IS_CMT(edev))
1342 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1343 qdev->num_rx_queues, qdev->num_tx_queues);
1344
1345
1346 return 0;
1347 }
1348
1349 /* Info about HW descriptor ring limitations */
1350 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1351 .nb_max = 0x8000, /* 32K */
1352 .nb_min = 128,
1353 .nb_align = 128 /* lowest common multiple */
1354 };
1355
1356 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1357 .nb_max = 0x8000, /* 32K */
1358 .nb_min = 256,
1359 .nb_align = 256,
1360 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1361 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1362 };
1363
1364 static int
qede_dev_info_get(struct rte_eth_dev * eth_dev,struct rte_eth_dev_info * dev_info)1365 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1366 struct rte_eth_dev_info *dev_info)
1367 {
1368 struct qede_dev *qdev = eth_dev->data->dev_private;
1369 struct ecore_dev *edev = &qdev->edev;
1370 struct qed_link_output link;
1371 uint32_t speed_cap = 0;
1372
1373 PMD_INIT_FUNC_TRACE(edev);
1374
1375 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1376 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1377 dev_info->rx_desc_lim = qede_rx_desc_lim;
1378 dev_info->tx_desc_lim = qede_tx_desc_lim;
1379
1380 if (IS_PF(edev))
1381 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1382 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1383 else
1384 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1385 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1386 /* Since CMT mode internally doubles the number of queues */
1387 if (ECORE_IS_CMT(edev))
1388 dev_info->max_rx_queues = dev_info->max_rx_queues / 2;
1389
1390 dev_info->max_tx_queues = dev_info->max_rx_queues;
1391
1392 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1393 dev_info->max_vfs = 0;
1394 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1395 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1396 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1397 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1398 DEV_RX_OFFLOAD_UDP_CKSUM |
1399 DEV_RX_OFFLOAD_TCP_CKSUM |
1400 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1401 DEV_RX_OFFLOAD_TCP_LRO |
1402 DEV_RX_OFFLOAD_KEEP_CRC |
1403 DEV_RX_OFFLOAD_SCATTER |
1404 DEV_RX_OFFLOAD_JUMBO_FRAME |
1405 DEV_RX_OFFLOAD_VLAN_FILTER |
1406 DEV_RX_OFFLOAD_VLAN_STRIP |
1407 DEV_RX_OFFLOAD_RSS_HASH);
1408 dev_info->rx_queue_offload_capa = 0;
1409
1410 /* TX offloads are on a per-packet basis, so it is applicable
1411 * to both at port and queue levels.
1412 */
1413 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1414 DEV_TX_OFFLOAD_IPV4_CKSUM |
1415 DEV_TX_OFFLOAD_UDP_CKSUM |
1416 DEV_TX_OFFLOAD_TCP_CKSUM |
1417 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1418 DEV_TX_OFFLOAD_MULTI_SEGS |
1419 DEV_TX_OFFLOAD_TCP_TSO |
1420 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1421 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1422 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1423
1424 dev_info->default_txconf = (struct rte_eth_txconf) {
1425 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1426 };
1427
1428 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1429 /* Packets are always dropped if no descriptors are available */
1430 .rx_drop_en = 1,
1431 .offloads = 0,
1432 };
1433
1434 memset(&link, 0, sizeof(struct qed_link_output));
1435 qdev->ops->common->get_link(edev, &link);
1436 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1437 speed_cap |= ETH_LINK_SPEED_1G;
1438 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1439 speed_cap |= ETH_LINK_SPEED_10G;
1440 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1441 speed_cap |= ETH_LINK_SPEED_25G;
1442 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1443 speed_cap |= ETH_LINK_SPEED_40G;
1444 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1445 speed_cap |= ETH_LINK_SPEED_50G;
1446 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1447 speed_cap |= ETH_LINK_SPEED_100G;
1448 dev_info->speed_capa = speed_cap;
1449
1450 return 0;
1451 }
1452
1453 /* return 0 means link status changed, -1 means not changed */
1454 int
qede_link_update(struct rte_eth_dev * eth_dev,__rte_unused int wait_to_complete)1455 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1456 {
1457 struct qede_dev *qdev = eth_dev->data->dev_private;
1458 struct ecore_dev *edev = &qdev->edev;
1459 struct qed_link_output q_link;
1460 struct rte_eth_link link;
1461 uint16_t link_duplex;
1462
1463 memset(&q_link, 0, sizeof(q_link));
1464 memset(&link, 0, sizeof(link));
1465
1466 qdev->ops->common->get_link(edev, &q_link);
1467
1468 /* Link Speed */
1469 link.link_speed = q_link.speed;
1470
1471 /* Link Mode */
1472 switch (q_link.duplex) {
1473 case QEDE_DUPLEX_HALF:
1474 link_duplex = ETH_LINK_HALF_DUPLEX;
1475 break;
1476 case QEDE_DUPLEX_FULL:
1477 link_duplex = ETH_LINK_FULL_DUPLEX;
1478 break;
1479 case QEDE_DUPLEX_UNKNOWN:
1480 default:
1481 link_duplex = -1;
1482 }
1483 link.link_duplex = link_duplex;
1484
1485 /* Link Status */
1486 link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1487
1488 /* AN */
1489 link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1490 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1491
1492 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1493 link.link_speed, link.link_duplex,
1494 link.link_autoneg, link.link_status);
1495
1496 return rte_eth_linkstatus_set(eth_dev, &link);
1497 }
1498
qede_promiscuous_enable(struct rte_eth_dev * eth_dev)1499 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1500 {
1501 enum _ecore_status_t ecore_status;
1502 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1503 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1504 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1505
1506 PMD_INIT_FUNC_TRACE(edev);
1507
1508 ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1509
1510 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1511 }
1512
qede_promiscuous_disable(struct rte_eth_dev * eth_dev)1513 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1514 {
1515 struct qede_dev *qdev = eth_dev->data->dev_private;
1516 struct ecore_dev *edev = &qdev->edev;
1517 enum _ecore_status_t ecore_status;
1518
1519 PMD_INIT_FUNC_TRACE(edev);
1520
1521 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1522 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1523 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1524 else
1525 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1526 QED_FILTER_RX_MODE_TYPE_REGULAR);
1527
1528 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1529 }
1530
qede_poll_sp_sb_cb(void * param)1531 static void qede_poll_sp_sb_cb(void *param)
1532 {
1533 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1534 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1535 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1536 int rc;
1537
1538 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1539 qede_interrupt_action(&edev->hwfns[1]);
1540
1541 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1542 qede_poll_sp_sb_cb,
1543 (void *)eth_dev);
1544 if (rc != 0) {
1545 DP_ERR(edev, "Unable to start periodic"
1546 " timer rc %d\n", rc);
1547 }
1548 }
1549
qede_dev_close(struct rte_eth_dev * eth_dev)1550 static int qede_dev_close(struct rte_eth_dev *eth_dev)
1551 {
1552 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1553 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1554 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1555 int ret = 0;
1556
1557 PMD_INIT_FUNC_TRACE(edev);
1558
1559 /* only close in case of the primary process */
1560 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1561 return 0;
1562
1563 /* dev_stop() shall cleanup fp resources in hw but without releasing
1564 * dma memories and sw structures so that dev_start() can be called
1565 * by the app without reconfiguration. However, in dev_close() we
1566 * can release all the resources and device can be brought up newly
1567 */
1568 if (eth_dev->data->dev_started)
1569 ret = qede_dev_stop(eth_dev);
1570
1571 if (qdev->vport_started)
1572 qede_stop_vport(edev);
1573 qdev->vport_started = false;
1574 qede_fdir_dealloc_resc(eth_dev);
1575 qede_dealloc_fp_resc(eth_dev);
1576
1577 eth_dev->data->nb_rx_queues = 0;
1578 eth_dev->data->nb_tx_queues = 0;
1579
1580 qdev->ops->common->slowpath_stop(edev);
1581 qdev->ops->common->remove(edev);
1582 rte_intr_disable(&pci_dev->intr_handle);
1583
1584 switch (pci_dev->intr_handle.type) {
1585 case RTE_INTR_HANDLE_UIO_INTX:
1586 case RTE_INTR_HANDLE_VFIO_LEGACY:
1587 rte_intr_callback_unregister(&pci_dev->intr_handle,
1588 qede_interrupt_handler_intx,
1589 (void *)eth_dev);
1590 break;
1591 default:
1592 rte_intr_callback_unregister(&pci_dev->intr_handle,
1593 qede_interrupt_handler,
1594 (void *)eth_dev);
1595 }
1596
1597 if (ECORE_IS_CMT(edev))
1598 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1599
1600 return ret;
1601 }
1602
1603 static int
qede_get_stats(struct rte_eth_dev * eth_dev,struct rte_eth_stats * eth_stats)1604 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1605 {
1606 struct qede_dev *qdev = eth_dev->data->dev_private;
1607 struct ecore_dev *edev = &qdev->edev;
1608 struct ecore_eth_stats stats;
1609 unsigned int i = 0, j = 0, qid, idx, hw_fn;
1610 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1611 struct qede_tx_queue *txq;
1612
1613 ecore_get_vport_stats(edev, &stats);
1614
1615 /* RX Stats */
1616 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1617 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1618
1619 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1620 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1621
1622 eth_stats->ierrors = stats.common.rx_crc_errors +
1623 stats.common.rx_align_errors +
1624 stats.common.rx_carrier_errors +
1625 stats.common.rx_oversize_packets +
1626 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1627
1628 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1629
1630 eth_stats->imissed = stats.common.mftag_filter_discards +
1631 stats.common.mac_filter_discards +
1632 stats.common.no_buff_discards +
1633 stats.common.brb_truncates + stats.common.brb_discards;
1634
1635 /* TX stats */
1636 eth_stats->opackets = stats.common.tx_ucast_pkts +
1637 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1638
1639 eth_stats->obytes = stats.common.tx_ucast_bytes +
1640 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1641
1642 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1643
1644 /* Queue stats */
1645 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1646 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1647 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1648 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1649 if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1650 txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1651 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1652 "Not all the queue stats will be displayed. Set"
1653 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1654 " appropriately and retry.\n");
1655
1656 for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1657 eth_stats->q_ipackets[i] = 0;
1658 eth_stats->q_errors[i] = 0;
1659
1660 for_each_hwfn(edev, hw_fn) {
1661 idx = qid * edev->num_hwfns + hw_fn;
1662
1663 eth_stats->q_ipackets[i] +=
1664 *(uint64_t *)
1665 (((char *)(qdev->fp_array[idx].rxq)) +
1666 offsetof(struct qede_rx_queue,
1667 rcv_pkts));
1668 eth_stats->q_errors[i] +=
1669 *(uint64_t *)
1670 (((char *)(qdev->fp_array[idx].rxq)) +
1671 offsetof(struct qede_rx_queue,
1672 rx_hw_errors)) +
1673 *(uint64_t *)
1674 (((char *)(qdev->fp_array[idx].rxq)) +
1675 offsetof(struct qede_rx_queue,
1676 rx_alloc_errors));
1677 }
1678
1679 i++;
1680 if (i == rxq_stat_cntrs)
1681 break;
1682 }
1683
1684 for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1685 eth_stats->q_opackets[j] = 0;
1686
1687 for_each_hwfn(edev, hw_fn) {
1688 idx = qid * edev->num_hwfns + hw_fn;
1689
1690 txq = qdev->fp_array[idx].txq;
1691 eth_stats->q_opackets[j] +=
1692 *((uint64_t *)(uintptr_t)
1693 (((uint64_t)(uintptr_t)(txq)) +
1694 offsetof(struct qede_tx_queue,
1695 xmit_pkts)));
1696 }
1697
1698 j++;
1699 if (j == txq_stat_cntrs)
1700 break;
1701 }
1702
1703 return 0;
1704 }
1705
1706 static unsigned
qede_get_xstats_count(struct qede_dev * qdev)1707 qede_get_xstats_count(struct qede_dev *qdev) {
1708 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1709
1710 if (ECORE_IS_BB(&qdev->edev))
1711 return RTE_DIM(qede_xstats_strings) +
1712 RTE_DIM(qede_bb_xstats_strings) +
1713 (RTE_DIM(qede_rxq_xstats_strings) *
1714 QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1715 else
1716 return RTE_DIM(qede_xstats_strings) +
1717 RTE_DIM(qede_ah_xstats_strings) +
1718 (RTE_DIM(qede_rxq_xstats_strings) *
1719 QEDE_RSS_COUNT(dev));
1720 }
1721
1722 static int
qede_get_xstats_names(struct rte_eth_dev * dev,struct rte_eth_xstat_name * xstats_names,__rte_unused unsigned int limit)1723 qede_get_xstats_names(struct rte_eth_dev *dev,
1724 struct rte_eth_xstat_name *xstats_names,
1725 __rte_unused unsigned int limit)
1726 {
1727 struct qede_dev *qdev = dev->data->dev_private;
1728 struct ecore_dev *edev = &qdev->edev;
1729 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1730 unsigned int i, qid, hw_fn, stat_idx = 0;
1731
1732 if (xstats_names == NULL)
1733 return stat_cnt;
1734
1735 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1736 strlcpy(xstats_names[stat_idx].name,
1737 qede_xstats_strings[i].name,
1738 sizeof(xstats_names[stat_idx].name));
1739 stat_idx++;
1740 }
1741
1742 if (ECORE_IS_BB(edev)) {
1743 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1744 strlcpy(xstats_names[stat_idx].name,
1745 qede_bb_xstats_strings[i].name,
1746 sizeof(xstats_names[stat_idx].name));
1747 stat_idx++;
1748 }
1749 } else {
1750 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1751 strlcpy(xstats_names[stat_idx].name,
1752 qede_ah_xstats_strings[i].name,
1753 sizeof(xstats_names[stat_idx].name));
1754 stat_idx++;
1755 }
1756 }
1757
1758 for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1759 for_each_hwfn(edev, hw_fn) {
1760 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1761 snprintf(xstats_names[stat_idx].name,
1762 RTE_ETH_XSTATS_NAME_SIZE,
1763 "%.4s%d.%d%s",
1764 qede_rxq_xstats_strings[i].name,
1765 hw_fn, qid,
1766 qede_rxq_xstats_strings[i].name + 4);
1767 stat_idx++;
1768 }
1769 }
1770 }
1771
1772 return stat_cnt;
1773 }
1774
1775 static int
qede_get_xstats(struct rte_eth_dev * dev,struct rte_eth_xstat * xstats,unsigned int n)1776 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1777 unsigned int n)
1778 {
1779 struct qede_dev *qdev = dev->data->dev_private;
1780 struct ecore_dev *edev = &qdev->edev;
1781 struct ecore_eth_stats stats;
1782 const unsigned int num = qede_get_xstats_count(qdev);
1783 unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1784
1785 if (n < num)
1786 return num;
1787
1788 ecore_get_vport_stats(edev, &stats);
1789
1790 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1791 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1792 qede_xstats_strings[i].offset);
1793 xstats[stat_idx].id = stat_idx;
1794 stat_idx++;
1795 }
1796
1797 if (ECORE_IS_BB(edev)) {
1798 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1799 xstats[stat_idx].value =
1800 *(uint64_t *)(((char *)&stats) +
1801 qede_bb_xstats_strings[i].offset);
1802 xstats[stat_idx].id = stat_idx;
1803 stat_idx++;
1804 }
1805 } else {
1806 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1807 xstats[stat_idx].value =
1808 *(uint64_t *)(((char *)&stats) +
1809 qede_ah_xstats_strings[i].offset);
1810 xstats[stat_idx].id = stat_idx;
1811 stat_idx++;
1812 }
1813 }
1814
1815 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1816 for_each_hwfn(edev, hw_fn) {
1817 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1818 fpidx = qid * edev->num_hwfns + hw_fn;
1819 xstats[stat_idx].value = *(uint64_t *)
1820 (((char *)(qdev->fp_array[fpidx].rxq)) +
1821 qede_rxq_xstats_strings[i].offset);
1822 xstats[stat_idx].id = stat_idx;
1823 stat_idx++;
1824 }
1825
1826 }
1827 }
1828
1829 return stat_idx;
1830 }
1831
1832 static int
qede_reset_xstats(struct rte_eth_dev * dev)1833 qede_reset_xstats(struct rte_eth_dev *dev)
1834 {
1835 struct qede_dev *qdev = dev->data->dev_private;
1836 struct ecore_dev *edev = &qdev->edev;
1837
1838 ecore_reset_vport_stats(edev);
1839 qede_reset_queue_stats(qdev, true);
1840
1841 return 0;
1842 }
1843
qede_dev_set_link_state(struct rte_eth_dev * eth_dev,bool link_up)1844 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1845 {
1846 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1847 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1848 struct qed_link_params link_params;
1849 int rc;
1850
1851 DP_INFO(edev, "setting link state %d\n", link_up);
1852 memset(&link_params, 0, sizeof(link_params));
1853 link_params.link_up = link_up;
1854 rc = qdev->ops->common->set_link(edev, &link_params);
1855 if (rc != ECORE_SUCCESS)
1856 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1857
1858 return rc;
1859 }
1860
qede_dev_set_link_up(struct rte_eth_dev * eth_dev)1861 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1862 {
1863 return qede_dev_set_link_state(eth_dev, true);
1864 }
1865
qede_dev_set_link_down(struct rte_eth_dev * eth_dev)1866 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1867 {
1868 return qede_dev_set_link_state(eth_dev, false);
1869 }
1870
qede_reset_stats(struct rte_eth_dev * eth_dev)1871 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1872 {
1873 struct qede_dev *qdev = eth_dev->data->dev_private;
1874 struct ecore_dev *edev = &qdev->edev;
1875
1876 ecore_reset_vport_stats(edev);
1877 qede_reset_queue_stats(qdev, false);
1878
1879 return 0;
1880 }
1881
qede_allmulticast_enable(struct rte_eth_dev * eth_dev)1882 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1883 {
1884 enum qed_filter_rx_mode_type type =
1885 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1886 enum _ecore_status_t ecore_status;
1887
1888 ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1889
1890 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1891 }
1892
qede_allmulticast_disable(struct rte_eth_dev * eth_dev)1893 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1894 {
1895 enum _ecore_status_t ecore_status;
1896
1897 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1898 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1899 QED_FILTER_RX_MODE_TYPE_PROMISC);
1900 else
1901 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1902 QED_FILTER_RX_MODE_TYPE_REGULAR);
1903
1904 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1905 }
1906
1907 static int
qede_set_mc_addr_list(struct rte_eth_dev * eth_dev,struct rte_ether_addr * mc_addrs,uint32_t mc_addrs_num)1908 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1909 struct rte_ether_addr *mc_addrs,
1910 uint32_t mc_addrs_num)
1911 {
1912 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1913 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1914 uint8_t i;
1915
1916 if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1917 DP_ERR(edev, "Reached max multicast filters limit,"
1918 "Please enable multicast promisc mode\n");
1919 return -ENOSPC;
1920 }
1921
1922 for (i = 0; i < mc_addrs_num; i++) {
1923 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1924 DP_ERR(edev, "Not a valid multicast MAC\n");
1925 return -EINVAL;
1926 }
1927 }
1928
1929 /* Flush all existing entries */
1930 if (qede_del_mcast_filters(eth_dev))
1931 return -1;
1932
1933 /* Set new mcast list */
1934 return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1935 }
1936
1937 /* Update MTU via vport-update without doing port restart.
1938 * The vport must be deactivated before calling this API.
1939 */
qede_update_mtu(struct rte_eth_dev * eth_dev,uint16_t mtu)1940 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1941 {
1942 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1943 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1944 struct ecore_hwfn *p_hwfn;
1945 int rc;
1946 int i;
1947
1948 if (IS_PF(edev)) {
1949 struct ecore_sp_vport_update_params params;
1950
1951 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1952 params.vport_id = 0;
1953 params.mtu = mtu;
1954 params.vport_id = 0;
1955 for_each_hwfn(edev, i) {
1956 p_hwfn = &edev->hwfns[i];
1957 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1958 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1959 ECORE_SPQ_MODE_EBLOCK, NULL);
1960 if (rc != ECORE_SUCCESS)
1961 goto err;
1962 }
1963 } else {
1964 for_each_hwfn(edev, i) {
1965 p_hwfn = &edev->hwfns[i];
1966 rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1967 if (rc == ECORE_INVAL) {
1968 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1969 /* Recreate vport */
1970 rc = qede_start_vport(qdev, mtu);
1971 if (rc != ECORE_SUCCESS)
1972 goto err;
1973
1974 /* Restore config lost due to vport stop */
1975 if (eth_dev->data->promiscuous)
1976 qede_promiscuous_enable(eth_dev);
1977 else
1978 qede_promiscuous_disable(eth_dev);
1979
1980 if (eth_dev->data->all_multicast)
1981 qede_allmulticast_enable(eth_dev);
1982 else
1983 qede_allmulticast_disable(eth_dev);
1984
1985 qede_vlan_offload_set(eth_dev,
1986 qdev->vlan_offload_mask);
1987 } else if (rc != ECORE_SUCCESS) {
1988 goto err;
1989 }
1990 }
1991 }
1992 DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1993
1994 return 0;
1995
1996 err:
1997 DP_ERR(edev, "Failed to update MTU\n");
1998 return -1;
1999 }
2000
qede_flow_ctrl_set(struct rte_eth_dev * eth_dev,struct rte_eth_fc_conf * fc_conf)2001 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2002 struct rte_eth_fc_conf *fc_conf)
2003 {
2004 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2005 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2006 struct qed_link_output current_link;
2007 struct qed_link_params params;
2008
2009 memset(¤t_link, 0, sizeof(current_link));
2010 qdev->ops->common->get_link(edev, ¤t_link);
2011
2012 memset(¶ms, 0, sizeof(params));
2013 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2014 if (fc_conf->autoneg) {
2015 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2016 DP_ERR(edev, "Autoneg not supported\n");
2017 return -EINVAL;
2018 }
2019 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2020 }
2021
2022 /* Pause is assumed to be supported (SUPPORTED_Pause) */
2023 if (fc_conf->mode == RTE_FC_FULL)
2024 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2025 QED_LINK_PAUSE_RX_ENABLE);
2026 if (fc_conf->mode == RTE_FC_TX_PAUSE)
2027 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2028 if (fc_conf->mode == RTE_FC_RX_PAUSE)
2029 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2030
2031 params.link_up = true;
2032 (void)qdev->ops->common->set_link(edev, ¶ms);
2033
2034 return 0;
2035 }
2036
qede_flow_ctrl_get(struct rte_eth_dev * eth_dev,struct rte_eth_fc_conf * fc_conf)2037 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2038 struct rte_eth_fc_conf *fc_conf)
2039 {
2040 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2041 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2042 struct qed_link_output current_link;
2043
2044 memset(¤t_link, 0, sizeof(current_link));
2045 qdev->ops->common->get_link(edev, ¤t_link);
2046
2047 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2048 fc_conf->autoneg = true;
2049
2050 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2051 QED_LINK_PAUSE_TX_ENABLE))
2052 fc_conf->mode = RTE_FC_FULL;
2053 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2054 fc_conf->mode = RTE_FC_RX_PAUSE;
2055 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2056 fc_conf->mode = RTE_FC_TX_PAUSE;
2057 else
2058 fc_conf->mode = RTE_FC_NONE;
2059
2060 return 0;
2061 }
2062
2063 static const uint32_t *
qede_dev_supported_ptypes_get(struct rte_eth_dev * eth_dev)2064 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2065 {
2066 static const uint32_t ptypes[] = {
2067 RTE_PTYPE_L2_ETHER,
2068 RTE_PTYPE_L2_ETHER_VLAN,
2069 RTE_PTYPE_L3_IPV4,
2070 RTE_PTYPE_L3_IPV6,
2071 RTE_PTYPE_L4_TCP,
2072 RTE_PTYPE_L4_UDP,
2073 RTE_PTYPE_TUNNEL_VXLAN,
2074 RTE_PTYPE_L4_FRAG,
2075 RTE_PTYPE_TUNNEL_GENEVE,
2076 RTE_PTYPE_TUNNEL_GRE,
2077 /* Inner */
2078 RTE_PTYPE_INNER_L2_ETHER,
2079 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2080 RTE_PTYPE_INNER_L3_IPV4,
2081 RTE_PTYPE_INNER_L3_IPV6,
2082 RTE_PTYPE_INNER_L4_TCP,
2083 RTE_PTYPE_INNER_L4_UDP,
2084 RTE_PTYPE_INNER_L4_FRAG,
2085 RTE_PTYPE_UNKNOWN
2086 };
2087
2088 if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2089 eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2090 eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2091 return ptypes;
2092
2093 return NULL;
2094 }
2095
qede_init_rss_caps(uint8_t * rss_caps,uint64_t hf)2096 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2097 {
2098 *rss_caps = 0;
2099 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2100 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2101 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2102 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2103 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2104 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2105 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2106 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2107 }
2108
qede_rss_hash_update(struct rte_eth_dev * eth_dev,struct rte_eth_rss_conf * rss_conf)2109 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2110 struct rte_eth_rss_conf *rss_conf)
2111 {
2112 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2113 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2114 struct ecore_sp_vport_update_params vport_update_params;
2115 struct ecore_rss_params rss_params;
2116 struct ecore_hwfn *p_hwfn;
2117 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2118 uint64_t hf = rss_conf->rss_hf;
2119 uint8_t len = rss_conf->rss_key_len;
2120 uint8_t idx, i, j, fpidx;
2121 int rc;
2122
2123 memset(&vport_update_params, 0, sizeof(vport_update_params));
2124 memset(&rss_params, 0, sizeof(rss_params));
2125
2126 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2127 (unsigned long)hf, len, key);
2128
2129 if (hf != 0) {
2130 /* Enabling RSS */
2131 DP_INFO(edev, "Enabling rss\n");
2132
2133 /* RSS caps */
2134 qede_init_rss_caps(&rss_params.rss_caps, hf);
2135 rss_params.update_rss_capabilities = 1;
2136
2137 /* RSS hash key */
2138 if (key) {
2139 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2140 DP_ERR(edev, "RSS key length exceeds limit\n");
2141 return -EINVAL;
2142 }
2143 DP_INFO(edev, "Applying user supplied hash key\n");
2144 rss_params.update_rss_key = 1;
2145 memcpy(&rss_params.rss_key, key, len);
2146 }
2147 rss_params.rss_enable = 1;
2148 }
2149
2150 rss_params.update_rss_config = 1;
2151 /* tbl_size has to be set with capabilities */
2152 rss_params.rss_table_size_log = 7;
2153 vport_update_params.vport_id = 0;
2154
2155 for_each_hwfn(edev, i) {
2156 /* pass the L2 handles instead of qids */
2157 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2158 idx = j % QEDE_RSS_COUNT(eth_dev);
2159 fpidx = idx * edev->num_hwfns + i;
2160 rss_params.rss_ind_table[j] =
2161 qdev->fp_array[fpidx].rxq->handle;
2162 }
2163
2164 vport_update_params.rss_params = &rss_params;
2165
2166 p_hwfn = &edev->hwfns[i];
2167 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2168 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2169 ECORE_SPQ_MODE_EBLOCK, NULL);
2170 if (rc) {
2171 DP_ERR(edev, "vport-update for RSS failed\n");
2172 return rc;
2173 }
2174 }
2175 qdev->rss_enable = rss_params.rss_enable;
2176
2177 /* Update local structure for hash query */
2178 qdev->rss_conf.rss_hf = hf;
2179 qdev->rss_conf.rss_key_len = len;
2180 if (qdev->rss_enable) {
2181 if (qdev->rss_conf.rss_key == NULL) {
2182 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2183 if (qdev->rss_conf.rss_key == NULL) {
2184 DP_ERR(edev, "No memory to store RSS key\n");
2185 return -ENOMEM;
2186 }
2187 }
2188 if (key && len) {
2189 DP_INFO(edev, "Storing RSS key\n");
2190 memcpy(qdev->rss_conf.rss_key, key, len);
2191 }
2192 } else if (!qdev->rss_enable && len == 0) {
2193 if (qdev->rss_conf.rss_key) {
2194 free(qdev->rss_conf.rss_key);
2195 qdev->rss_conf.rss_key = NULL;
2196 DP_INFO(edev, "Free RSS key\n");
2197 }
2198 }
2199
2200 return 0;
2201 }
2202
qede_rss_hash_conf_get(struct rte_eth_dev * eth_dev,struct rte_eth_rss_conf * rss_conf)2203 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2204 struct rte_eth_rss_conf *rss_conf)
2205 {
2206 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2207
2208 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2209 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2210
2211 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2212 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2213 rss_conf->rss_key_len);
2214 return 0;
2215 }
2216
qede_rss_reta_update(struct rte_eth_dev * eth_dev,struct rte_eth_rss_reta_entry64 * reta_conf,uint16_t reta_size)2217 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2218 struct rte_eth_rss_reta_entry64 *reta_conf,
2219 uint16_t reta_size)
2220 {
2221 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2222 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2223 struct ecore_sp_vport_update_params vport_update_params;
2224 struct ecore_rss_params *params;
2225 uint16_t i, j, idx, fid, shift;
2226 struct ecore_hwfn *p_hwfn;
2227 uint8_t entry;
2228 int rc = 0;
2229
2230 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2231 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2232 reta_size);
2233 return -EINVAL;
2234 }
2235
2236 memset(&vport_update_params, 0, sizeof(vport_update_params));
2237 params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2238 if (params == NULL) {
2239 DP_ERR(edev, "failed to allocate memory\n");
2240 return -ENOMEM;
2241 }
2242
2243 params->update_rss_ind_table = 1;
2244 params->rss_table_size_log = 7;
2245 params->update_rss_config = 1;
2246
2247 vport_update_params.vport_id = 0;
2248 /* Use the current value of rss_enable */
2249 params->rss_enable = qdev->rss_enable;
2250 vport_update_params.rss_params = params;
2251
2252 for_each_hwfn(edev, i) {
2253 for (j = 0; j < reta_size; j++) {
2254 idx = j / RTE_RETA_GROUP_SIZE;
2255 shift = j % RTE_RETA_GROUP_SIZE;
2256 if (reta_conf[idx].mask & (1ULL << shift)) {
2257 entry = reta_conf[idx].reta[shift];
2258 fid = entry * edev->num_hwfns + i;
2259 /* Pass rxq handles to ecore */
2260 params->rss_ind_table[j] =
2261 qdev->fp_array[fid].rxq->handle;
2262 /* Update the local copy for RETA query cmd */
2263 qdev->rss_ind_table[j] = entry;
2264 }
2265 }
2266
2267 p_hwfn = &edev->hwfns[i];
2268 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2269 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2270 ECORE_SPQ_MODE_EBLOCK, NULL);
2271 if (rc) {
2272 DP_ERR(edev, "vport-update for RSS failed\n");
2273 goto out;
2274 }
2275 }
2276
2277 out:
2278 rte_free(params);
2279 return rc;
2280 }
2281
qede_rss_reta_query(struct rte_eth_dev * eth_dev,struct rte_eth_rss_reta_entry64 * reta_conf,uint16_t reta_size)2282 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2283 struct rte_eth_rss_reta_entry64 *reta_conf,
2284 uint16_t reta_size)
2285 {
2286 struct qede_dev *qdev = eth_dev->data->dev_private;
2287 struct ecore_dev *edev = &qdev->edev;
2288 uint16_t i, idx, shift;
2289 uint8_t entry;
2290
2291 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2292 DP_ERR(edev, "reta_size %d is not supported\n",
2293 reta_size);
2294 return -EINVAL;
2295 }
2296
2297 for (i = 0; i < reta_size; i++) {
2298 idx = i / RTE_RETA_GROUP_SIZE;
2299 shift = i % RTE_RETA_GROUP_SIZE;
2300 if (reta_conf[idx].mask & (1ULL << shift)) {
2301 entry = qdev->rss_ind_table[i];
2302 reta_conf[idx].reta[shift] = entry;
2303 }
2304 }
2305
2306 return 0;
2307 }
2308
2309
2310
qede_set_mtu(struct rte_eth_dev * dev,uint16_t mtu)2311 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2312 {
2313 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2314 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2315 struct rte_eth_dev_info dev_info = {0};
2316 struct qede_fastpath *fp;
2317 uint32_t max_rx_pkt_len;
2318 uint32_t frame_size;
2319 uint16_t bufsz;
2320 bool restart = false;
2321 int i, rc;
2322
2323 PMD_INIT_FUNC_TRACE(edev);
2324 rc = qede_dev_info_get(dev, &dev_info);
2325 if (rc != 0) {
2326 DP_ERR(edev, "Error during getting ethernet device info\n");
2327 return rc;
2328 }
2329 max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2330 frame_size = max_rx_pkt_len;
2331 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2332 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2333 mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2334 QEDE_ETH_OVERHEAD);
2335 return -EINVAL;
2336 }
2337 if (!dev->data->scattered_rx &&
2338 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2339 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2340 dev->data->min_rx_buf_size);
2341 return -EINVAL;
2342 }
2343 if (dev->data->dev_started) {
2344 dev->data->dev_started = 0;
2345 rc = qede_dev_stop(dev);
2346 if (rc != 0)
2347 return rc;
2348 restart = true;
2349 }
2350 rte_delay_ms(1000);
2351 qdev->new_mtu = mtu;
2352
2353 /* Fix up RX buf size for all queues of the port */
2354 for (i = 0; i < qdev->num_rx_queues; i++) {
2355 fp = &qdev->fp_array[i];
2356 if (fp->rxq != NULL) {
2357 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2358 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2359 /* cache align the mbuf size to simplfy rx_buf_size
2360 * calculation
2361 */
2362 bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2363 rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2364 if (rc < 0)
2365 return rc;
2366
2367 fp->rxq->rx_buf_size = rc;
2368 }
2369 }
2370 if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2371 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2372 else
2373 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2374
2375 if (!dev->data->dev_started && restart) {
2376 qede_dev_start(dev);
2377 dev->data->dev_started = 1;
2378 }
2379
2380 /* update max frame size */
2381 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2382
2383 return 0;
2384 }
2385
2386 static int
qede_dev_reset(struct rte_eth_dev * dev)2387 qede_dev_reset(struct rte_eth_dev *dev)
2388 {
2389 int ret;
2390
2391 ret = qede_eth_dev_uninit(dev);
2392 if (ret)
2393 return ret;
2394
2395 return qede_eth_dev_init(dev);
2396 }
2397
2398 static const struct eth_dev_ops qede_eth_dev_ops = {
2399 .dev_configure = qede_dev_configure,
2400 .dev_infos_get = qede_dev_info_get,
2401 .rx_queue_setup = qede_rx_queue_setup,
2402 .rx_queue_release = qede_rx_queue_release,
2403 .tx_queue_setup = qede_tx_queue_setup,
2404 .tx_queue_release = qede_tx_queue_release,
2405 .dev_start = qede_dev_start,
2406 .dev_reset = qede_dev_reset,
2407 .dev_set_link_up = qede_dev_set_link_up,
2408 .dev_set_link_down = qede_dev_set_link_down,
2409 .link_update = qede_link_update,
2410 .promiscuous_enable = qede_promiscuous_enable,
2411 .promiscuous_disable = qede_promiscuous_disable,
2412 .allmulticast_enable = qede_allmulticast_enable,
2413 .allmulticast_disable = qede_allmulticast_disable,
2414 .set_mc_addr_list = qede_set_mc_addr_list,
2415 .dev_stop = qede_dev_stop,
2416 .dev_close = qede_dev_close,
2417 .stats_get = qede_get_stats,
2418 .stats_reset = qede_reset_stats,
2419 .xstats_get = qede_get_xstats,
2420 .xstats_reset = qede_reset_xstats,
2421 .xstats_get_names = qede_get_xstats_names,
2422 .mac_addr_add = qede_mac_addr_add,
2423 .mac_addr_remove = qede_mac_addr_remove,
2424 .mac_addr_set = qede_mac_addr_set,
2425 .vlan_offload_set = qede_vlan_offload_set,
2426 .vlan_filter_set = qede_vlan_filter_set,
2427 .flow_ctrl_set = qede_flow_ctrl_set,
2428 .flow_ctrl_get = qede_flow_ctrl_get,
2429 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2430 .rss_hash_update = qede_rss_hash_update,
2431 .rss_hash_conf_get = qede_rss_hash_conf_get,
2432 .reta_update = qede_rss_reta_update,
2433 .reta_query = qede_rss_reta_query,
2434 .mtu_set = qede_set_mtu,
2435 .filter_ctrl = qede_dev_filter_ctrl,
2436 .udp_tunnel_port_add = qede_udp_dst_port_add,
2437 .udp_tunnel_port_del = qede_udp_dst_port_del,
2438 .fw_version_get = qede_fw_version_get,
2439 .get_reg = qede_get_regs,
2440 };
2441
2442 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2443 .dev_configure = qede_dev_configure,
2444 .dev_infos_get = qede_dev_info_get,
2445 .rx_queue_setup = qede_rx_queue_setup,
2446 .rx_queue_release = qede_rx_queue_release,
2447 .tx_queue_setup = qede_tx_queue_setup,
2448 .tx_queue_release = qede_tx_queue_release,
2449 .dev_start = qede_dev_start,
2450 .dev_reset = qede_dev_reset,
2451 .dev_set_link_up = qede_dev_set_link_up,
2452 .dev_set_link_down = qede_dev_set_link_down,
2453 .link_update = qede_link_update,
2454 .promiscuous_enable = qede_promiscuous_enable,
2455 .promiscuous_disable = qede_promiscuous_disable,
2456 .allmulticast_enable = qede_allmulticast_enable,
2457 .allmulticast_disable = qede_allmulticast_disable,
2458 .set_mc_addr_list = qede_set_mc_addr_list,
2459 .dev_stop = qede_dev_stop,
2460 .dev_close = qede_dev_close,
2461 .stats_get = qede_get_stats,
2462 .stats_reset = qede_reset_stats,
2463 .xstats_get = qede_get_xstats,
2464 .xstats_reset = qede_reset_xstats,
2465 .xstats_get_names = qede_get_xstats_names,
2466 .vlan_offload_set = qede_vlan_offload_set,
2467 .vlan_filter_set = qede_vlan_filter_set,
2468 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2469 .rss_hash_update = qede_rss_hash_update,
2470 .rss_hash_conf_get = qede_rss_hash_conf_get,
2471 .reta_update = qede_rss_reta_update,
2472 .reta_query = qede_rss_reta_query,
2473 .mtu_set = qede_set_mtu,
2474 .udp_tunnel_port_add = qede_udp_dst_port_add,
2475 .udp_tunnel_port_del = qede_udp_dst_port_del,
2476 .mac_addr_add = qede_mac_addr_add,
2477 .mac_addr_remove = qede_mac_addr_remove,
2478 .mac_addr_set = qede_mac_addr_set,
2479 .fw_version_get = qede_fw_version_get,
2480 };
2481
qede_update_pf_params(struct ecore_dev * edev)2482 static void qede_update_pf_params(struct ecore_dev *edev)
2483 {
2484 struct ecore_pf_params pf_params;
2485
2486 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2487 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2488 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2489 qed_ops->common->update_pf_params(edev, &pf_params);
2490 }
2491
qede_generate_random_mac_addr(struct rte_ether_addr * mac_addr)2492 static void qede_generate_random_mac_addr(struct rte_ether_addr *mac_addr)
2493 {
2494 uint64_t random;
2495
2496 /* Set Organizationally Unique Identifier (OUI) prefix. */
2497 mac_addr->addr_bytes[0] = 0x00;
2498 mac_addr->addr_bytes[1] = 0x09;
2499 mac_addr->addr_bytes[2] = 0xC0;
2500
2501 /* Force indication of locally assigned MAC address. */
2502 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
2503
2504 /* Generate the last 3 bytes of the MAC address with a random number. */
2505 random = rte_rand();
2506
2507 memcpy(&mac_addr->addr_bytes[3], &random, 3);
2508 }
2509
qede_common_dev_init(struct rte_eth_dev * eth_dev,bool is_vf)2510 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2511 {
2512 struct rte_pci_device *pci_dev;
2513 struct rte_pci_addr pci_addr;
2514 struct qede_dev *adapter;
2515 struct ecore_dev *edev;
2516 struct qed_dev_eth_info dev_info;
2517 struct qed_slowpath_params params;
2518 static bool do_once = true;
2519 uint8_t bulletin_change;
2520 uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2521 uint8_t is_mac_forced;
2522 bool is_mac_exist = false;
2523 /* Fix up ecore debug level */
2524 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2525 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2526 uint32_t int_mode;
2527 int rc;
2528
2529 /* Extract key data structures */
2530 adapter = eth_dev->data->dev_private;
2531 adapter->ethdev = eth_dev;
2532 edev = &adapter->edev;
2533 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2534 pci_addr = pci_dev->addr;
2535
2536 PMD_INIT_FUNC_TRACE(edev);
2537
2538 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2539 pci_addr.bus, pci_addr.devid, pci_addr.function,
2540 eth_dev->data->port_id);
2541
2542 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2543 DP_ERR(edev, "Skipping device init from secondary process\n");
2544 return 0;
2545 }
2546
2547 rte_eth_copy_pci_info(eth_dev, pci_dev);
2548 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2549
2550 /* @DPDK */
2551 edev->vendor_id = pci_dev->id.vendor_id;
2552 edev->device_id = pci_dev->id.device_id;
2553
2554 qed_ops = qed_get_eth_ops();
2555 if (!qed_ops) {
2556 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2557 rc = -EINVAL;
2558 goto err;
2559 }
2560
2561 DP_INFO(edev, "Starting qede probe\n");
2562 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2563 dp_level, is_vf);
2564 if (rc != 0) {
2565 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2566 rc = -ENODEV;
2567 goto err;
2568 }
2569 qede_update_pf_params(edev);
2570
2571 switch (pci_dev->intr_handle.type) {
2572 case RTE_INTR_HANDLE_UIO_INTX:
2573 case RTE_INTR_HANDLE_VFIO_LEGACY:
2574 int_mode = ECORE_INT_MODE_INTA;
2575 rte_intr_callback_register(&pci_dev->intr_handle,
2576 qede_interrupt_handler_intx,
2577 (void *)eth_dev);
2578 break;
2579 default:
2580 int_mode = ECORE_INT_MODE_MSIX;
2581 rte_intr_callback_register(&pci_dev->intr_handle,
2582 qede_interrupt_handler,
2583 (void *)eth_dev);
2584 }
2585
2586 if (rte_intr_enable(&pci_dev->intr_handle)) {
2587 DP_ERR(edev, "rte_intr_enable() failed\n");
2588 rc = -ENODEV;
2589 goto err;
2590 }
2591
2592 /* Start the Slowpath-process */
2593 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2594
2595 params.int_mode = int_mode;
2596 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2597 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2598 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2599 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2600 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2601 QEDE_PMD_DRV_VER_STR_SIZE);
2602
2603 qede_assign_rxtx_handlers(eth_dev, true);
2604 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2605
2606 /* For CMT mode device do periodic polling for slowpath events.
2607 * This is required since uio device uses only one MSI-x
2608 * interrupt vector but we need one for each engine.
2609 */
2610 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2611 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2612 qede_poll_sp_sb_cb,
2613 (void *)eth_dev);
2614 if (rc != 0) {
2615 DP_ERR(edev, "Unable to start periodic"
2616 " timer rc %d\n", rc);
2617 rc = -EINVAL;
2618 goto err;
2619 }
2620 }
2621
2622 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2623 if (rc) {
2624 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2625 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2626 (void *)eth_dev);
2627 rc = -ENODEV;
2628 goto err;
2629 }
2630
2631 rc = qed_ops->fill_dev_info(edev, &dev_info);
2632 if (rc) {
2633 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2634 qed_ops->common->slowpath_stop(edev);
2635 qed_ops->common->remove(edev);
2636 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2637 (void *)eth_dev);
2638 rc = -ENODEV;
2639 goto err;
2640 }
2641
2642 qede_alloc_etherdev(adapter, &dev_info);
2643
2644 if (do_once) {
2645 qede_print_adapter_info(eth_dev);
2646 do_once = false;
2647 }
2648
2649 adapter->ops->common->set_name(edev, edev->name);
2650
2651 if (!is_vf)
2652 adapter->dev_info.num_mac_filters =
2653 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2654 ECORE_MAC);
2655 else
2656 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2657 (uint32_t *)&adapter->dev_info.num_mac_filters);
2658
2659 /* Allocate memory for storing MAC addr */
2660 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2661 (RTE_ETHER_ADDR_LEN *
2662 adapter->dev_info.num_mac_filters),
2663 RTE_CACHE_LINE_SIZE);
2664
2665 if (eth_dev->data->mac_addrs == NULL) {
2666 DP_ERR(edev, "Failed to allocate MAC address\n");
2667 qed_ops->common->slowpath_stop(edev);
2668 qed_ops->common->remove(edev);
2669 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2670 (void *)eth_dev);
2671 return -ENOMEM;
2672 }
2673
2674 if (!is_vf) {
2675 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2676 hw_info.hw_mac_addr,
2677 ð_dev->data->mac_addrs[0]);
2678 rte_ether_addr_copy(ð_dev->data->mac_addrs[0],
2679 &adapter->primary_mac);
2680 } else {
2681 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2682 &bulletin_change);
2683 if (bulletin_change) {
2684 is_mac_exist =
2685 ecore_vf_bulletin_get_forced_mac(
2686 ECORE_LEADING_HWFN(edev),
2687 vf_mac,
2688 &is_mac_forced);
2689 if (is_mac_exist) {
2690 DP_INFO(edev, "VF macaddr received from PF\n");
2691 rte_ether_addr_copy(
2692 (struct rte_ether_addr *)&vf_mac,
2693 ð_dev->data->mac_addrs[0]);
2694 rte_ether_addr_copy(
2695 ð_dev->data->mac_addrs[0],
2696 &adapter->primary_mac);
2697 } else {
2698 DP_ERR(edev, "No VF macaddr assigned\n");
2699 }
2700 }
2701
2702 /* If MAC doesn't exist from PF, generate random one */
2703 if (!is_mac_exist) {
2704 struct rte_ether_addr *mac_addr;
2705
2706 mac_addr = (struct rte_ether_addr *)&vf_mac;
2707 qede_generate_random_mac_addr(mac_addr);
2708
2709 rte_ether_addr_copy(mac_addr,
2710 ð_dev->data->mac_addrs[0]);
2711
2712 rte_ether_addr_copy(ð_dev->data->mac_addrs[0],
2713 &adapter->primary_mac);
2714 }
2715 }
2716
2717 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2718 eth_dev->rx_descriptor_status = qede_rx_descriptor_status;
2719
2720 adapter->num_tx_queues = 0;
2721 adapter->num_rx_queues = 0;
2722 SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2723 SLIST_INIT(&adapter->vlan_list_head);
2724 SLIST_INIT(&adapter->uc_list_head);
2725 SLIST_INIT(&adapter->mc_list_head);
2726 adapter->mtu = RTE_ETHER_MTU;
2727 adapter->vport_started = false;
2728
2729 /* VF tunnel offloads is enabled by default in PF driver */
2730 adapter->vxlan.num_filters = 0;
2731 adapter->geneve.num_filters = 0;
2732 adapter->ipgre.num_filters = 0;
2733 if (is_vf) {
2734 adapter->vxlan.enable = true;
2735 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2736 ETH_TUNNEL_FILTER_IVLAN;
2737 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2738 adapter->geneve.enable = true;
2739 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2740 ETH_TUNNEL_FILTER_IVLAN;
2741 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2742 adapter->ipgre.enable = true;
2743 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2744 ETH_TUNNEL_FILTER_IVLAN;
2745 } else {
2746 adapter->vxlan.enable = false;
2747 adapter->geneve.enable = false;
2748 adapter->ipgre.enable = false;
2749 qed_ops->sriov_configure(edev, pci_dev->max_vfs);
2750 }
2751
2752 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2753 adapter->primary_mac.addr_bytes[0],
2754 adapter->primary_mac.addr_bytes[1],
2755 adapter->primary_mac.addr_bytes[2],
2756 adapter->primary_mac.addr_bytes[3],
2757 adapter->primary_mac.addr_bytes[4],
2758 adapter->primary_mac.addr_bytes[5]);
2759
2760 DP_INFO(edev, "Device initialized\n");
2761
2762 return 0;
2763
2764 err:
2765 if (do_once) {
2766 qede_print_adapter_info(eth_dev);
2767 do_once = false;
2768 }
2769 return rc;
2770 }
2771
qedevf_eth_dev_init(struct rte_eth_dev * eth_dev)2772 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2773 {
2774 return qede_common_dev_init(eth_dev, 1);
2775 }
2776
qede_eth_dev_init(struct rte_eth_dev * eth_dev)2777 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2778 {
2779 return qede_common_dev_init(eth_dev, 0);
2780 }
2781
qede_dev_common_uninit(struct rte_eth_dev * eth_dev)2782 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2783 {
2784 struct qede_dev *qdev = eth_dev->data->dev_private;
2785 struct ecore_dev *edev = &qdev->edev;
2786 PMD_INIT_FUNC_TRACE(edev);
2787 qede_dev_close(eth_dev);
2788 return 0;
2789 }
2790
qede_eth_dev_uninit(struct rte_eth_dev * eth_dev)2791 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2792 {
2793 return qede_dev_common_uninit(eth_dev);
2794 }
2795
qedevf_eth_dev_uninit(struct rte_eth_dev * eth_dev)2796 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2797 {
2798 return qede_dev_common_uninit(eth_dev);
2799 }
2800
2801 static const struct rte_pci_id pci_id_qedevf_map[] = {
2802 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2803 {
2804 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2805 },
2806 {
2807 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2808 },
2809 {
2810 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2811 },
2812 {.vendor_id = 0,}
2813 };
2814
2815 static const struct rte_pci_id pci_id_qede_map[] = {
2816 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2817 {
2818 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2819 },
2820 {
2821 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2822 },
2823 {
2824 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2825 },
2826 {
2827 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2828 },
2829 {
2830 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2831 },
2832 {
2833 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2834 },
2835 {
2836 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2837 },
2838 {
2839 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2840 },
2841 {
2842 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2843 },
2844 {
2845 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2846 },
2847 {.vendor_id = 0,}
2848 };
2849
qedevf_eth_dev_pci_probe(struct rte_pci_driver * pci_drv __rte_unused,struct rte_pci_device * pci_dev)2850 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2851 struct rte_pci_device *pci_dev)
2852 {
2853 return rte_eth_dev_pci_generic_probe(pci_dev,
2854 sizeof(struct qede_dev), qedevf_eth_dev_init);
2855 }
2856
qedevf_eth_dev_pci_remove(struct rte_pci_device * pci_dev)2857 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2858 {
2859 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2860 }
2861
2862 static struct rte_pci_driver rte_qedevf_pmd = {
2863 .id_table = pci_id_qedevf_map,
2864 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2865 .probe = qedevf_eth_dev_pci_probe,
2866 .remove = qedevf_eth_dev_pci_remove,
2867 };
2868
qede_eth_dev_pci_probe(struct rte_pci_driver * pci_drv __rte_unused,struct rte_pci_device * pci_dev)2869 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2870 struct rte_pci_device *pci_dev)
2871 {
2872 return rte_eth_dev_pci_generic_probe(pci_dev,
2873 sizeof(struct qede_dev), qede_eth_dev_init);
2874 }
2875
qede_eth_dev_pci_remove(struct rte_pci_device * pci_dev)2876 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2877 {
2878 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2879 }
2880
2881 static struct rte_pci_driver rte_qede_pmd = {
2882 .id_table = pci_id_qede_map,
2883 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2884 .probe = qede_eth_dev_pci_probe,
2885 .remove = qede_eth_dev_pci_remove,
2886 };
2887
2888 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2889 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2890 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2891 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2892 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2893 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2894 RTE_LOG_REGISTER(qede_logtype_init, pmd.net.qede.init, NOTICE);
2895 RTE_LOG_REGISTER(qede_logtype_driver, pmd.net.qede.driver, NOTICE);
2896