1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2019-2020 Broadcom
3  * All rights reserved.
4  */
5 
6 #ifndef _TF_DEVICE_P45_H_
7 #define _TF_DEVICE_P45_H_
8 
9 #include <cfa_resource_types.h>
10 
11 #include "tf_core.h"
12 #include "tf_rm.h"
13 #include "tf_if_tbl.h"
14 #include "tf_global_cfg.h"
15 
16 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
17 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH },
18 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW },
19 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC },
20 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID },
21 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID },
22 	/* CFA_RESOURCE_TYPE_P45_L2_FUNC */
23 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
24 };
25 
26 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
27 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH },
28 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW },
29 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM },
30 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM },
31 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM },
32 	/* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */
33 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
34 	/* CFA_RESOURCE_TYPE_P45_VEB_TCAM */
35 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
36 };
37 
38 struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
39 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION },
40 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG },
41 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B },
42 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B },
43 	/* CFA_RESOURCE_TYPE_P45_ENCAP_32B */
44 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
45 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B },
46 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC },
47 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 },
48 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 },
49 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B },
50 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
51 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
52 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 },
53 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF },
54 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER },
55 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR },
56 	/* CFA_RESOURCE_TYPE_P45_UPAR */
57 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
58 	/* CFA_RESOURCE_TYPE_P45_EPOC */
59 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
60 	/* CFA_RESOURCE_TYPE_P45_METADATA */
61 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
62 	/* CFA_RESOURCE_TYPE_P45_CT_STATE */
63 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
64 	/* CFA_RESOURCE_TYPE_P45_RANGE_PROF */
65 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
66 	/* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */
67 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
68 	/* CFA_RESOURCE_TYPE_P45_LAG */
69 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
70 	/* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */
71 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
72 	/* CFA_RESOURCE_TYPE_P45_EM_FBK */
73 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
74 	/* CFA_RESOURCE_TYPE_P45_WC_FKB */
75 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
76 	/* CFA_RESOURCE_TYPE_P45_EXT */
77 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
78 };
79 
80 struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
81 	/* CFA_RESOURCE_TYPE_P45_EM_REC */
82 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
83 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
84 };
85 
86 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
87 	{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC },
88 	/* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */
89 	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
90 };
91 
92 struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
93 	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },
94 	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },
95 	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },
96 	{ TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },
97 	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },
98 	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }
99 };
100 
101 struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
102 	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },
103 	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },
104 };
105 #endif /* _TF_DEVICE_P45_H_ */
106