1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 5 * Copyright 2016 NXP. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DPAA2_HW_DPBP_H_ 35 #define _DPAA2_HW_DPBP_H_ 36 37 #define DPAA2_MAX_BUF_POOLS 8 38 39 struct buf_pool_cfg { 40 void *addr; 41 /**< The address from where DPAA2 will carve out the buffers */ 42 rte_iova_t phys_addr; 43 /**< Physical address of the memory provided in addr */ 44 uint32_t num; 45 /**< Number of buffers */ 46 uint32_t size; 47 /**< Size including headroom for each buffer */ 48 uint16_t align; 49 /**< Buffer alignment (in bytes) */ 50 uint16_t bpid; 51 /**< Autogenerated buffer pool ID for internal use */ 52 }; 53 54 struct buf_pool { 55 uint32_t size; /**< Size of the Pool */ 56 uint32_t num_bufs; /**< Number of buffers in Pool */ 57 uint16_t bpid; /**< Pool ID, from pool configuration */ 58 uint8_t *h_bpool_mem; /**< Internal context data */ 59 struct dpaa2_dpbp_dev *dpbp_node; /**< Hardware context */ 60 }; 61 62 /*! 63 * Buffer pool list configuration structure. User need to give DPAA2 the 64 * valid number of 'num_buf_pools'. 65 */ 66 struct dpaa2_bp_list_cfg { 67 struct buf_pool_cfg buf_pool; /* Configuration of each buffer pool*/ 68 }; 69 70 struct dpaa2_bp_list { 71 struct dpaa2_bp_list *next; 72 struct rte_mempool *mp; /**< DPDK RTE EAL pool reference */ 73 int32_t dpaa2_ops_index; /**< Index into DPDK Mempool ops table */ 74 struct buf_pool buf_pool; 75 }; 76 77 struct dpaa2_bp_info { 78 uint32_t meta_data_size; 79 uint32_t bpid; 80 struct dpaa2_bp_list *bp_list; 81 }; 82 83 #define mempool_to_bpinfo(mp) ((struct dpaa2_bp_info *)(mp)->pool_data) 84 #define mempool_to_bpid(mp) ((mempool_to_bpinfo(mp))->bpid) 85 86 extern struct dpaa2_bp_info rte_dpaa2_bpid_info[MAX_BPID]; 87 88 int rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, 89 void **obj_table, unsigned int count); 90 91 #endif /* _DPAA2_HW_DPBP_H_ */ 92