1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2019 NXP 5 * 6 */ 7 8 #ifndef _DPAA2_HW_DPBP_H_ 9 #define _DPAA2_HW_DPBP_H_ 10 11 #define DPAA2_MAX_BUF_POOLS 8 12 13 struct buf_pool_cfg { 14 void *addr; 15 /**< The address from where DPAA2 will carve out the buffers */ 16 rte_iova_t phys_addr; 17 /**< Physical address of the memory provided in addr */ 18 uint32_t num; 19 /**< Number of buffers */ 20 uint32_t size; 21 /**< Size including headroom for each buffer */ 22 uint16_t align; 23 /**< Buffer alignment (in bytes) */ 24 uint16_t bpid; 25 /**< Autogenerated buffer pool ID for internal use */ 26 }; 27 28 struct buf_pool { 29 uint32_t size; /**< Size of the Pool */ 30 uint32_t num_bufs; /**< Number of buffers in Pool */ 31 uint16_t bpid; /**< Pool ID, from pool configuration */ 32 uint8_t *h_bpool_mem; /**< Internal context data */ 33 struct dpaa2_dpbp_dev *dpbp_node; /**< Hardware context */ 34 }; 35 36 /*! 37 * Buffer pool list configuration structure. User need to give DPAA2 the 38 * valid number of 'num_buf_pools'. 39 */ 40 struct dpaa2_bp_list_cfg { 41 struct buf_pool_cfg buf_pool; /* Configuration of each buffer pool*/ 42 }; 43 44 struct dpaa2_bp_list { 45 struct dpaa2_bp_list *next; 46 struct rte_mempool *mp; /**< DPDK RTE EAL pool reference */ 47 int32_t dpaa2_ops_index; /**< Index into DPDK Mempool ops table */ 48 struct buf_pool buf_pool; 49 }; 50 51 struct dpaa2_bp_info { 52 uint32_t meta_data_size; 53 uint32_t bpid; 54 struct dpaa2_bp_list *bp_list; 55 }; 56 57 #define mempool_to_bpinfo(mp) ((struct dpaa2_bp_info *)(mp)->pool_data) 58 #define mempool_to_bpid(mp) ((mempool_to_bpinfo(mp))->bpid) 59 60 extern struct dpaa2_bp_info *rte_dpaa2_bpid_info; 61 62 __rte_internal 63 int rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, 64 void **obj_table, unsigned int count); 65 66 #endif /* _DPAA2_HW_DPBP_H_ */ 67