1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright (C) 2020 Marvell International Ltd.
3  */
4 
5 #include <rte_cryptodev.h>
6 #include <rte_eventdev.h>
7 
8 #include "otx2_cryptodev_hw_access.h"
9 #include "otx2_cryptodev_qp.h"
10 #include "otx2_cryptodev_mbox.h"
11 #include "otx2_evdev.h"
12 
13 int
otx2_ca_caps_get(const struct rte_eventdev * dev,const struct rte_cryptodev * cdev,uint32_t * caps)14 otx2_ca_caps_get(const struct rte_eventdev *dev,
15 		const struct rte_cryptodev *cdev, uint32_t *caps)
16 {
17 	RTE_SET_USED(dev);
18 	RTE_SET_USED(cdev);
19 
20 	*caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND |
21 		RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW;
22 
23 	return 0;
24 }
25 
26 int
otx2_ca_qp_add(const struct rte_eventdev * dev,const struct rte_cryptodev * cdev,int32_t queue_pair_id,const struct rte_event * event)27 otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,
28 		int32_t queue_pair_id, const struct rte_event *event)
29 {
30 	struct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev);
31 	union otx2_cpt_af_lf_ctl2 af_lf_ctl2;
32 	struct otx2_cpt_qp *qp;
33 	int ret;
34 
35 	qp = cdev->data->queue_pairs[queue_pair_id];
36 
37 	qp->ca_enable = 1;
38 	rte_memcpy(&qp->ev, event, sizeof(struct rte_event));
39 
40 	ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
41 			&af_lf_ctl2.u);
42 	if (ret)
43 		return ret;
44 
45 	af_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get();
46 	ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
47 			af_lf_ctl2.u);
48 	if (ret)
49 		return ret;
50 
51 	sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F;
52 	sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);
53 
54 	return 0;
55 }
56 
57 int
otx2_ca_qp_del(const struct rte_eventdev * dev,const struct rte_cryptodev * cdev,int32_t queue_pair_id)58 otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,
59 		int32_t queue_pair_id)
60 {
61 	union otx2_cpt_af_lf_ctl2 af_lf_ctl2;
62 	struct otx2_cpt_qp *qp;
63 	int ret;
64 
65 	RTE_SET_USED(dev);
66 
67 	qp = cdev->data->queue_pairs[queue_pair_id];
68 	qp->ca_enable = 0;
69 	memset(&qp->ev, 0, sizeof(struct rte_event));
70 
71 	ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
72 			&af_lf_ctl2.u);
73 	if (ret)
74 		return ret;
75 
76 	af_lf_ctl2.s.sso_pf_func = 0;
77 	ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
78 			af_lf_ctl2.u);
79 
80 	return ret;
81 }
82