1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
5 */
6
7 #include "efx.h"
8 #include "efx_impl.h"
9
10 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
11
12 static void
mcdi_phy_decode_cap(__in uint32_t mcdi_cap,__out uint32_t * maskp)13 mcdi_phy_decode_cap(
14 __in uint32_t mcdi_cap,
15 __out uint32_t *maskp)
16 {
17 uint32_t mask;
18
19 #define CHECK_CAP(_cap) \
20 EFX_STATIC_ASSERT(EFX_PHY_CAP_##_cap == MC_CMD_PHY_CAP_##_cap##_LBN)
21
22 CHECK_CAP(10HDX);
23 CHECK_CAP(10FDX);
24 CHECK_CAP(100HDX);
25 CHECK_CAP(100FDX);
26 CHECK_CAP(1000HDX);
27 CHECK_CAP(1000FDX);
28 CHECK_CAP(10000FDX);
29 CHECK_CAP(25000FDX);
30 CHECK_CAP(40000FDX);
31 CHECK_CAP(50000FDX);
32 CHECK_CAP(100000FDX);
33 CHECK_CAP(PAUSE);
34 CHECK_CAP(ASYM);
35 CHECK_CAP(AN);
36 CHECK_CAP(DDM);
37 CHECK_CAP(BASER_FEC);
38 CHECK_CAP(BASER_FEC_REQUESTED);
39 CHECK_CAP(RS_FEC);
40 CHECK_CAP(RS_FEC_REQUESTED);
41 CHECK_CAP(25G_BASER_FEC);
42 CHECK_CAP(25G_BASER_FEC_REQUESTED);
43 #undef CHECK_CAP
44
45 mask = 0;
46 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN))
47 mask |= (1 << EFX_PHY_CAP_10HDX);
48 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN))
49 mask |= (1 << EFX_PHY_CAP_10FDX);
50 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN))
51 mask |= (1 << EFX_PHY_CAP_100HDX);
52 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN))
53 mask |= (1 << EFX_PHY_CAP_100FDX);
54 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN))
55 mask |= (1 << EFX_PHY_CAP_1000HDX);
56 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN))
57 mask |= (1 << EFX_PHY_CAP_1000FDX);
58 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN))
59 mask |= (1 << EFX_PHY_CAP_10000FDX);
60 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25000FDX_LBN))
61 mask |= (1 << EFX_PHY_CAP_25000FDX);
62 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
63 mask |= (1 << EFX_PHY_CAP_40000FDX);
64 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_50000FDX_LBN))
65 mask |= (1 << EFX_PHY_CAP_50000FDX);
66 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100000FDX_LBN))
67 mask |= (1 << EFX_PHY_CAP_100000FDX);
68
69 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN))
70 mask |= (1 << EFX_PHY_CAP_PAUSE);
71 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN))
72 mask |= (1 << EFX_PHY_CAP_ASYM);
73 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
74 mask |= (1 << EFX_PHY_CAP_AN);
75
76 /* FEC caps (supported on Medford2 and later) */
77 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN))
78 mask |= (1 << EFX_PHY_CAP_BASER_FEC);
79 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN))
80 mask |= (1 << EFX_PHY_CAP_BASER_FEC_REQUESTED);
81
82 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN))
83 mask |= (1 << EFX_PHY_CAP_RS_FEC);
84 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN))
85 mask |= (1 << EFX_PHY_CAP_RS_FEC_REQUESTED);
86
87 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN))
88 mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC);
89 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN))
90 mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
91
92 *maskp = mask;
93 }
94
95 static void
mcdi_phy_decode_link_mode(__in efx_nic_t * enp,__in uint32_t link_flags,__in unsigned int speed,__in unsigned int fcntl,__in uint32_t fec,__out efx_link_mode_t * link_modep,__out unsigned int * fcntlp,__out efx_phy_fec_type_t * fecp)96 mcdi_phy_decode_link_mode(
97 __in efx_nic_t *enp,
98 __in uint32_t link_flags,
99 __in unsigned int speed,
100 __in unsigned int fcntl,
101 __in uint32_t fec,
102 __out efx_link_mode_t *link_modep,
103 __out unsigned int *fcntlp,
104 __out efx_phy_fec_type_t *fecp)
105 {
106 boolean_t fd = !!(link_flags &
107 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
108 boolean_t up = !!(link_flags &
109 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
110
111 _NOTE(ARGUNUSED(enp))
112
113 if (!up)
114 *link_modep = EFX_LINK_DOWN;
115 else if (speed == 100000 && fd)
116 *link_modep = EFX_LINK_100000FDX;
117 else if (speed == 50000 && fd)
118 *link_modep = EFX_LINK_50000FDX;
119 else if (speed == 40000 && fd)
120 *link_modep = EFX_LINK_40000FDX;
121 else if (speed == 25000 && fd)
122 *link_modep = EFX_LINK_25000FDX;
123 else if (speed == 10000 && fd)
124 *link_modep = EFX_LINK_10000FDX;
125 else if (speed == 1000)
126 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX;
127 else if (speed == 100)
128 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX;
129 else if (speed == 10)
130 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX;
131 else
132 *link_modep = EFX_LINK_UNKNOWN;
133
134 if (fcntl == MC_CMD_FCNTL_OFF)
135 *fcntlp = 0;
136 else if (fcntl == MC_CMD_FCNTL_RESPOND)
137 *fcntlp = EFX_FCNTL_RESPOND;
138 else if (fcntl == MC_CMD_FCNTL_GENERATE)
139 *fcntlp = EFX_FCNTL_GENERATE;
140 else if (fcntl == MC_CMD_FCNTL_BIDIR)
141 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
142 else {
143 EFSYS_PROBE1(mc_pcol_error, int, fcntl);
144 *fcntlp = 0;
145 }
146
147 switch (fec) {
148 case MC_CMD_FEC_NONE:
149 *fecp = EFX_PHY_FEC_NONE;
150 break;
151 case MC_CMD_FEC_BASER:
152 *fecp = EFX_PHY_FEC_BASER;
153 break;
154 case MC_CMD_FEC_RS:
155 *fecp = EFX_PHY_FEC_RS;
156 break;
157 default:
158 EFSYS_PROBE1(mc_pcol_error, int, fec);
159 *fecp = EFX_PHY_FEC_NONE;
160 break;
161 }
162 }
163
164
165 void
ef10_phy_link_ev(__in efx_nic_t * enp,__in efx_qword_t * eqp,__out efx_link_mode_t * link_modep)166 ef10_phy_link_ev(
167 __in efx_nic_t *enp,
168 __in efx_qword_t *eqp,
169 __out efx_link_mode_t *link_modep)
170 {
171 efx_port_t *epp = &(enp->en_port);
172 unsigned int link_flags;
173 unsigned int speed;
174 unsigned int fcntl;
175 efx_phy_fec_type_t fec = MC_CMD_FEC_NONE;
176 efx_link_mode_t link_mode;
177 uint32_t lp_cap_mask;
178
179 /*
180 * Convert the LINKCHANGE speed enumeration into mbit/s, in the
181 * same way as GET_LINK encodes the speed
182 */
183 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) {
184 case MCDI_EVENT_LINKCHANGE_SPEED_100M:
185 speed = 100;
186 break;
187 case MCDI_EVENT_LINKCHANGE_SPEED_1G:
188 speed = 1000;
189 break;
190 case MCDI_EVENT_LINKCHANGE_SPEED_10G:
191 speed = 10000;
192 break;
193 case MCDI_EVENT_LINKCHANGE_SPEED_25G:
194 speed = 25000;
195 break;
196 case MCDI_EVENT_LINKCHANGE_SPEED_40G:
197 speed = 40000;
198 break;
199 case MCDI_EVENT_LINKCHANGE_SPEED_50G:
200 speed = 50000;
201 break;
202 case MCDI_EVENT_LINKCHANGE_SPEED_100G:
203 speed = 100000;
204 break;
205 default:
206 speed = 0;
207 break;
208 }
209
210 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);
211 mcdi_phy_decode_link_mode(enp, link_flags, speed,
212 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),
213 MC_CMD_FEC_NONE, &link_mode,
214 &fcntl, &fec);
215 mcdi_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),
216 &lp_cap_mask);
217
218 /*
219 * It's safe to update ep_lp_cap_mask without the driver's port lock
220 * because presumably any concurrently running efx_port_poll() is
221 * only going to arrive at the same value.
222 *
223 * ep_fcntl has two meanings. It's either the link common fcntl
224 * (if the PHY supports AN), or it's the forced link state. If
225 * the former, it's safe to update the value for the same reason as
226 * for ep_lp_cap_mask. If the latter, then just ignore the value,
227 * because we can race with efx_mac_fcntl_set().
228 */
229 epp->ep_lp_cap_mask = lp_cap_mask;
230 epp->ep_fcntl = fcntl;
231
232 *link_modep = link_mode;
233 }
234
235 __checkReturn efx_rc_t
ef10_phy_power(__in efx_nic_t * enp,__in boolean_t power)236 ef10_phy_power(
237 __in efx_nic_t *enp,
238 __in boolean_t power)
239 {
240 efx_rc_t rc;
241
242 if (!power)
243 return (0);
244
245 /* Check if the PHY is a zombie */
246 if ((rc = ef10_phy_verify(enp)) != 0)
247 goto fail1;
248
249 enp->en_reset_flags |= EFX_RESET_PHY;
250
251 return (0);
252
253 fail1:
254 EFSYS_PROBE1(fail1, efx_rc_t, rc);
255
256 return (rc);
257 }
258
259 __checkReturn efx_rc_t
ef10_phy_get_link(__in efx_nic_t * enp,__out ef10_link_state_t * elsp)260 ef10_phy_get_link(
261 __in efx_nic_t *enp,
262 __out ef10_link_state_t *elsp)
263 {
264 efx_mcdi_req_t req;
265 uint32_t fec;
266 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN,
267 MC_CMD_GET_LINK_OUT_V2_LEN);
268 efx_rc_t rc;
269
270 req.emr_cmd = MC_CMD_GET_LINK;
271 req.emr_in_buf = payload;
272 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN;
273 req.emr_out_buf = payload;
274 req.emr_out_length = MC_CMD_GET_LINK_OUT_V2_LEN;
275
276 efx_mcdi_execute(enp, &req);
277
278 if (req.emr_rc != 0) {
279 rc = req.emr_rc;
280 goto fail1;
281 }
282
283 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) {
284 rc = EMSGSIZE;
285 goto fail2;
286 }
287
288 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP),
289 &elsp->epls.epls_adv_cap_mask);
290 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),
291 &elsp->epls.epls_lp_cap_mask);
292
293 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN)
294 fec = MC_CMD_FEC_NONE;
295 else
296 fec = MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_FEC_TYPE);
297
298 mcdi_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
299 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
300 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
301 fec, &elsp->epls.epls_link_mode,
302 &elsp->epls.epls_fcntl, &elsp->epls.epls_fec);
303
304 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN) {
305 elsp->epls.epls_ld_cap_mask = 0;
306 } else {
307 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_LD_CAP),
308 &elsp->epls.epls_ld_cap_mask);
309 }
310
311
312 #if EFSYS_OPT_LOOPBACK
313 /*
314 * MC_CMD_LOOPBACK and EFX_LOOPBACK names are equivalent, so use the
315 * MCDI value directly. Agreement is checked in efx_loopback_mask().
316 */
317 elsp->els_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE);
318 #endif /* EFSYS_OPT_LOOPBACK */
319
320 elsp->els_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;
321
322 return (0);
323
324 fail2:
325 EFSYS_PROBE(fail2);
326 fail1:
327 EFSYS_PROBE1(fail1, efx_rc_t, rc);
328
329 return (rc);
330 }
331
332 static __checkReturn efx_rc_t
efx_mcdi_phy_set_link(__in efx_nic_t * enp,__in uint32_t cap_mask,__in efx_loopback_type_t loopback_type,__in efx_link_mode_t loopback_link_mode,__in uint32_t phy_flags)333 efx_mcdi_phy_set_link(
334 __in efx_nic_t *enp,
335 __in uint32_t cap_mask,
336 __in efx_loopback_type_t loopback_type,
337 __in efx_link_mode_t loopback_link_mode,
338 __in uint32_t phy_flags)
339 {
340 efx_mcdi_req_t req;
341 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_LINK_IN_LEN,
342 MC_CMD_SET_LINK_OUT_LEN);
343 unsigned int speed;
344 efx_rc_t rc;
345
346 req.emr_cmd = MC_CMD_SET_LINK;
347 req.emr_in_buf = payload;
348 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN;
349 req.emr_out_buf = payload;
350 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN;
351
352 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP,
353 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1,
354 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1,
355 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1,
356 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1,
357 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1,
358 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1,
359 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1,
360 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1,
361 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,
362 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);
363 /* Too many fields for for POPULATE macros, so insert this afterwards */
364 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
365 PHY_CAP_25000FDX, (cap_mask >> EFX_PHY_CAP_25000FDX) & 0x1);
366 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
367 PHY_CAP_40000FDX, (cap_mask >> EFX_PHY_CAP_40000FDX) & 0x1);
368 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
369 PHY_CAP_50000FDX, (cap_mask >> EFX_PHY_CAP_50000FDX) & 0x1);
370 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
371 PHY_CAP_100000FDX, (cap_mask >> EFX_PHY_CAP_100000FDX) & 0x1);
372
373 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
374 PHY_CAP_BASER_FEC, (cap_mask >> EFX_PHY_CAP_BASER_FEC) & 0x1);
375 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
376 PHY_CAP_BASER_FEC_REQUESTED,
377 (cap_mask >> EFX_PHY_CAP_BASER_FEC_REQUESTED) & 0x1);
378
379 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
380 PHY_CAP_RS_FEC, (cap_mask >> EFX_PHY_CAP_RS_FEC) & 0x1);
381 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
382 PHY_CAP_RS_FEC_REQUESTED,
383 (cap_mask >> EFX_PHY_CAP_RS_FEC_REQUESTED) & 0x1);
384
385 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
386 PHY_CAP_25G_BASER_FEC,
387 (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC) & 0x1);
388 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
389 PHY_CAP_25G_BASER_FEC_REQUESTED,
390 (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC_REQUESTED) & 0x1);
391
392 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, loopback_type);
393
394 switch (loopback_link_mode) {
395 case EFX_LINK_100FDX:
396 speed = 100;
397 break;
398 case EFX_LINK_1000FDX:
399 speed = 1000;
400 break;
401 case EFX_LINK_10000FDX:
402 speed = 10000;
403 break;
404 case EFX_LINK_25000FDX:
405 speed = 25000;
406 break;
407 case EFX_LINK_40000FDX:
408 speed = 40000;
409 break;
410 case EFX_LINK_50000FDX:
411 speed = 50000;
412 break;
413 case EFX_LINK_100000FDX:
414 speed = 100000;
415 break;
416 default:
417 speed = 0;
418 break;
419 }
420 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed);
421
422 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, phy_flags);
423
424 efx_mcdi_execute(enp, &req);
425
426 if (req.emr_rc != 0) {
427 rc = req.emr_rc;
428 goto fail1;
429 }
430
431 return (0);
432
433 fail1:
434 EFSYS_PROBE1(fail1, efx_rc_t, rc);
435
436 return (rc);
437 }
438
439 static __checkReturn efx_rc_t
efx_mcdi_phy_set_led(__in efx_nic_t * enp,__in efx_phy_led_mode_t phy_led_mode)440 efx_mcdi_phy_set_led(
441 __in efx_nic_t *enp,
442 __in efx_phy_led_mode_t phy_led_mode)
443 {
444 efx_mcdi_req_t req;
445 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_ID_LED_IN_LEN,
446 MC_CMD_SET_ID_LED_OUT_LEN);
447 unsigned int led_mode;
448 efx_rc_t rc;
449
450 req.emr_cmd = MC_CMD_SET_ID_LED;
451 req.emr_in_buf = payload;
452 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN;
453 req.emr_out_buf = payload;
454 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;
455
456 switch (phy_led_mode) {
457 case EFX_PHY_LED_DEFAULT:
458 led_mode = MC_CMD_LED_DEFAULT;
459 break;
460 case EFX_PHY_LED_OFF:
461 led_mode = MC_CMD_LED_OFF;
462 break;
463 case EFX_PHY_LED_ON:
464 led_mode = MC_CMD_LED_ON;
465 break;
466 default:
467 EFSYS_ASSERT(0);
468 led_mode = MC_CMD_LED_DEFAULT;
469 break;
470 }
471
472 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);
473
474 efx_mcdi_execute(enp, &req);
475
476 if (req.emr_rc != 0) {
477 rc = req.emr_rc;
478 goto fail1;
479 }
480
481 return (0);
482
483 fail1:
484 EFSYS_PROBE1(fail1, efx_rc_t, rc);
485
486 return (rc);
487 }
488
489 __checkReturn efx_rc_t
ef10_phy_reconfigure(__in efx_nic_t * enp)490 ef10_phy_reconfigure(
491 __in efx_nic_t *enp)
492 {
493 efx_port_t *epp = &(enp->en_port);
494 efx_loopback_type_t loopback_type;
495 efx_link_mode_t loopback_link_mode;
496 uint32_t phy_flags;
497 efx_phy_led_mode_t phy_led_mode;
498 boolean_t supported;
499 efx_rc_t rc;
500
501 if ((rc = efx_mcdi_link_control_supported(enp, &supported)) != 0)
502 goto fail1;
503 if (supported == B_FALSE)
504 goto out;
505
506 #if EFSYS_OPT_LOOPBACK
507 loopback_type = epp->ep_loopback_type;
508 loopback_link_mode = epp->ep_loopback_link_mode;
509 #else
510 loopback_type = EFX_LOOPBACK_OFF;
511 loopback_link_mode = EFX_LINK_UNKNOWN;
512 #endif
513 #if EFSYS_OPT_PHY_FLAGS
514 phy_flags = epp->ep_phy_flags;
515 #else
516 phy_flags = 0;
517 #endif
518
519 rc = efx_mcdi_phy_set_link(enp, epp->ep_adv_cap_mask,
520 loopback_type, loopback_link_mode, phy_flags);
521 if (rc != 0)
522 goto fail2;
523
524 /* And set the blink mode */
525
526 #if EFSYS_OPT_PHY_LED_CONTROL
527 phy_led_mode = epp->ep_phy_led_mode;
528 #else
529 phy_led_mode = EFX_PHY_LED_DEFAULT;
530 #endif
531
532 rc = efx_mcdi_phy_set_led(enp, phy_led_mode);
533 if (rc != 0) {
534 /*
535 * If LED control is not supported by firmware, we can
536 * silently ignore default mode set failure
537 * (see FWRIVERHD-198).
538 */
539 if (rc == EOPNOTSUPP && phy_led_mode == EFX_PHY_LED_DEFAULT)
540 goto out;
541 goto fail3;
542 }
543
544 out:
545 return (0);
546
547 fail3:
548 EFSYS_PROBE(fail3);
549 fail2:
550 EFSYS_PROBE(fail2);
551 fail1:
552 EFSYS_PROBE1(fail1, efx_rc_t, rc);
553
554 return (rc);
555 }
556
557 __checkReturn efx_rc_t
ef10_phy_verify(__in efx_nic_t * enp)558 ef10_phy_verify(
559 __in efx_nic_t *enp)
560 {
561 efx_mcdi_req_t req;
562 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_STATE_IN_LEN,
563 MC_CMD_GET_PHY_STATE_OUT_LEN);
564 uint32_t state;
565 efx_rc_t rc;
566
567 req.emr_cmd = MC_CMD_GET_PHY_STATE;
568 req.emr_in_buf = payload;
569 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN;
570 req.emr_out_buf = payload;
571 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN;
572
573 efx_mcdi_execute(enp, &req);
574
575 if (req.emr_rc != 0) {
576 rc = req.emr_rc;
577 goto fail1;
578 }
579
580 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) {
581 rc = EMSGSIZE;
582 goto fail2;
583 }
584
585 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE);
586 if (state != MC_CMD_PHY_STATE_OK) {
587 if (state != MC_CMD_PHY_STATE_ZOMBIE)
588 EFSYS_PROBE1(mc_pcol_error, int, state);
589 rc = ENOTACTIVE;
590 goto fail3;
591 }
592
593 return (0);
594
595 fail3:
596 EFSYS_PROBE(fail3);
597 fail2:
598 EFSYS_PROBE(fail2);
599 fail1:
600 EFSYS_PROBE1(fail1, efx_rc_t, rc);
601
602 return (rc);
603 }
604
605 __checkReturn efx_rc_t
ef10_phy_oui_get(__in efx_nic_t * enp,__out uint32_t * ouip)606 ef10_phy_oui_get(
607 __in efx_nic_t *enp,
608 __out uint32_t *ouip)
609 {
610 _NOTE(ARGUNUSED(enp, ouip))
611
612 return (ENOTSUP);
613 }
614
615 __checkReturn efx_rc_t
ef10_phy_link_state_get(__in efx_nic_t * enp,__out efx_phy_link_state_t * eplsp)616 ef10_phy_link_state_get(
617 __in efx_nic_t *enp,
618 __out efx_phy_link_state_t *eplsp)
619 {
620 efx_rc_t rc;
621 ef10_link_state_t els;
622
623 /* Obtain the active link state */
624 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
625 goto fail1;
626
627 *eplsp = els.epls;
628
629 return (0);
630
631 fail1:
632 EFSYS_PROBE1(fail1, efx_rc_t, rc);
633
634 return (rc);
635 }
636
637
638 #if EFSYS_OPT_PHY_STATS
639
640 __checkReturn efx_rc_t
ef10_phy_stats_update(__in efx_nic_t * enp,__in efsys_mem_t * esmp,__inout_ecount (EFX_PHY_NSTATS)uint32_t * stat)641 ef10_phy_stats_update(
642 __in efx_nic_t *enp,
643 __in efsys_mem_t *esmp,
644 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
645 {
646 /* TBD: no stats support in firmware yet */
647 _NOTE(ARGUNUSED(enp, esmp))
648 memset(stat, 0, EFX_PHY_NSTATS * sizeof (*stat));
649
650 return (0);
651 }
652
653 #endif /* EFSYS_OPT_PHY_STATS */
654
655 #if EFSYS_OPT_BIST
656
657 __checkReturn efx_rc_t
ef10_bist_enable_offline(__in efx_nic_t * enp)658 ef10_bist_enable_offline(
659 __in efx_nic_t *enp)
660 {
661 efx_rc_t rc;
662
663 if ((rc = efx_mcdi_bist_enable_offline(enp)) != 0)
664 goto fail1;
665
666 return (0);
667
668 fail1:
669 EFSYS_PROBE1(fail1, efx_rc_t, rc);
670
671 return (rc);
672 }
673
674 __checkReturn efx_rc_t
ef10_bist_start(__in efx_nic_t * enp,__in efx_bist_type_t type)675 ef10_bist_start(
676 __in efx_nic_t *enp,
677 __in efx_bist_type_t type)
678 {
679 efx_rc_t rc;
680
681 if ((rc = efx_mcdi_bist_start(enp, type)) != 0)
682 goto fail1;
683
684 return (0);
685
686 fail1:
687 EFSYS_PROBE1(fail1, efx_rc_t, rc);
688
689 return (rc);
690 }
691
692 __checkReturn efx_rc_t
693 ef10_bist_poll(
694 __in efx_nic_t *enp,
695 __in efx_bist_type_t type,
696 __out efx_bist_result_t *resultp,
697 __out_opt __drv_when(count > 0, __notnull)
698 uint32_t *value_maskp,
699 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
700 unsigned long *valuesp,
701 __in size_t count)
702 {
703 /*
704 * MCDI_CTL_SDU_LEN_MAX_V1 is large enough cover all BIST results,
705 * whilst not wasting stack.
706 */
707 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_POLL_BIST_IN_LEN,
708 MCDI_CTL_SDU_LEN_MAX_V1);
709 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
710 efx_mcdi_req_t req;
711 uint32_t value_mask = 0;
712 uint32_t result;
713 efx_rc_t rc;
714
715 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_LEN <=
716 MCDI_CTL_SDU_LEN_MAX_V1);
717 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_SFT9001_LEN <=
718 MCDI_CTL_SDU_LEN_MAX_V1);
719 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MRSFP_LEN <=
720 MCDI_CTL_SDU_LEN_MAX_V1);
721 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MEM_LEN <=
722 MCDI_CTL_SDU_LEN_MAX_V1);
723
724 _NOTE(ARGUNUSED(type))
725
726 req.emr_cmd = MC_CMD_POLL_BIST;
727 req.emr_in_buf = payload;
728 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN;
729 req.emr_out_buf = payload;
730 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX_V1;
731
732 efx_mcdi_execute(enp, &req);
733
734 if (req.emr_rc != 0) {
735 rc = req.emr_rc;
736 goto fail1;
737 }
738
739 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) {
740 rc = EMSGSIZE;
741 goto fail2;
742 }
743
744 if (count > 0)
745 (void) memset(valuesp, '\0', count * sizeof (unsigned long));
746
747 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT);
748
749 if (result == MC_CMD_POLL_BIST_FAILED &&
750 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MEM_LEN &&
751 count > EFX_BIST_MEM_ECC_FATAL) {
752 if (valuesp != NULL) {
753 valuesp[EFX_BIST_MEM_TEST] =
754 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_TEST);
755 valuesp[EFX_BIST_MEM_ADDR] =
756 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ADDR);
757 valuesp[EFX_BIST_MEM_BUS] =
758 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_BUS);
759 valuesp[EFX_BIST_MEM_EXPECT] =
760 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_EXPECT);
761 valuesp[EFX_BIST_MEM_ACTUAL] =
762 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ACTUAL);
763 valuesp[EFX_BIST_MEM_ECC] =
764 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC);
765 valuesp[EFX_BIST_MEM_ECC_PARITY] =
766 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC_PARITY);
767 valuesp[EFX_BIST_MEM_ECC_FATAL] =
768 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC_FATAL);
769 }
770 value_mask |= (1 << EFX_BIST_MEM_TEST) |
771 (1 << EFX_BIST_MEM_ADDR) |
772 (1 << EFX_BIST_MEM_BUS) |
773 (1 << EFX_BIST_MEM_EXPECT) |
774 (1 << EFX_BIST_MEM_ACTUAL) |
775 (1 << EFX_BIST_MEM_ECC) |
776 (1 << EFX_BIST_MEM_ECC_PARITY) |
777 (1 << EFX_BIST_MEM_ECC_FATAL);
778 } else if (result == MC_CMD_POLL_BIST_FAILED &&
779 encp->enc_phy_type == EFX_PHY_XFI_FARMI &&
780 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN &&
781 count > EFX_BIST_FAULT_CODE) {
782 if (valuesp != NULL)
783 valuesp[EFX_BIST_FAULT_CODE] =
784 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST);
785 value_mask |= 1 << EFX_BIST_FAULT_CODE;
786 }
787
788 if (value_maskp != NULL)
789 *value_maskp = value_mask;
790
791 EFSYS_ASSERT(resultp != NULL);
792 if (result == MC_CMD_POLL_BIST_RUNNING)
793 *resultp = EFX_BIST_RESULT_RUNNING;
794 else if (result == MC_CMD_POLL_BIST_PASSED)
795 *resultp = EFX_BIST_RESULT_PASSED;
796 else
797 *resultp = EFX_BIST_RESULT_FAILED;
798
799 return (0);
800
801 fail2:
802 EFSYS_PROBE(fail2);
803 fail1:
804 EFSYS_PROBE1(fail1, efx_rc_t, rc);
805
806 return (rc);
807 }
808
809 void
ef10_bist_stop(__in efx_nic_t * enp,__in efx_bist_type_t type)810 ef10_bist_stop(
811 __in efx_nic_t *enp,
812 __in efx_bist_type_t type)
813 {
814 /* There is no way to stop BIST on EF10. */
815 _NOTE(ARGUNUSED(enp, type))
816 }
817
818 #endif /* EFSYS_OPT_BIST */
819
820 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
821