1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Intel Corporation 3 */ 4 5 /** 6 * @file Header file containing DPDK compilation parameters 7 * 8 * Header file containing DPDK compilation parameters. Also include the 9 * meson-generated header file containing the detected parameters that 10 * are variable across builds or build environments. 11 */ 12 #ifndef _RTE_CONFIG_H_ 13 #define _RTE_CONFIG_H_ 14 15 #include <rte_build_config.h> 16 #include "rte_compatibility_defines.h" 17 18 /* legacy defines */ 19 #ifdef RTE_EXEC_ENV_LINUX 20 #define RTE_EXEC_ENV_LINUXAPP 1 21 #endif 22 #ifdef RTE_EXEC_ENV_FREEBSD 23 #define RTE_EXEC_ENV_BSDAPP 1 24 #endif 25 26 /* String that appears before the version number */ 27 #define RTE_VER_PREFIX "DPDK" 28 29 /****** library defines ********/ 30 31 /* EAL defines */ 32 #define RTE_MAX_HEAPS 32 33 #define RTE_MAX_MEMSEG_LISTS 128 34 #define RTE_MAX_MEMSEG_PER_LIST 8192 35 #define RTE_MAX_MEM_MB_PER_LIST 32768 36 #define RTE_MAX_MEMSEG_PER_TYPE 32768 37 #define RTE_MAX_MEM_MB_PER_TYPE 65536 38 #define RTE_MAX_MEMZONE 2560 39 #define RTE_MAX_TAILQ 32 40 #define RTE_LOG_DP_LEVEL RTE_LOG_INFO 41 #define RTE_BACKTRACE 1 42 #define RTE_MAX_VFIO_CONTAINERS 64 43 44 /* bsd module defines */ 45 #define RTE_CONTIGMEM_MAX_NUM_BUFS 64 46 #define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1 47 #define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024) 48 49 /* mempool defines */ 50 #define RTE_MEMPOOL_CACHE_MAX_SIZE 512 51 52 /* mbuf defines */ 53 #define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc" 54 #define RTE_MBUF_REFCNT_ATOMIC 1 55 #define RTE_PKTMBUF_HEADROOM 128 56 57 /* ether defines */ 58 #define RTE_MAX_QUEUES_PER_PORT 1024 59 #define RTE_ETHDEV_QUEUE_STAT_CNTRS 16 /* max 256 */ 60 #define RTE_ETHDEV_RXTX_CALLBACKS 1 61 62 /* cryptodev defines */ 63 #define RTE_CRYPTO_MAX_DEVS 64 64 #define RTE_CRYPTODEV_NAME_LEN 64 65 66 /* compressdev defines */ 67 #define RTE_COMPRESS_MAX_DEVS 64 68 69 /* regexdev defines */ 70 #define RTE_MAX_REGEXDEV_DEVS 32 71 72 /* eventdev defines */ 73 #define RTE_EVENT_MAX_DEVS 16 74 #define RTE_EVENT_MAX_QUEUES_PER_DEV 255 75 #define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32 76 #define RTE_EVENT_ETH_INTR_RING_SIZE 1024 77 #define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32 78 #define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32 79 80 /* rawdev defines */ 81 #define RTE_RAWDEV_MAX_DEVS 64 82 83 /* ip_fragmentation defines */ 84 #define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4 85 #undef RTE_LIBRTE_IP_FRAG_TBL_STAT 86 87 /* rte_power defines */ 88 #define RTE_MAX_LCORE_FREQS 64 89 90 /* rte_sched defines */ 91 #undef RTE_SCHED_RED 92 #undef RTE_SCHED_COLLECT_STATS 93 #undef RTE_SCHED_SUBPORT_TC_OV 94 #define RTE_SCHED_PORT_N_GRINDERS 8 95 #undef RTE_SCHED_VECTOR 96 97 /* KNI defines */ 98 #define RTE_KNI_PREEMPT_DEFAULT 1 99 100 /* rte_graph defines */ 101 #define RTE_GRAPH_BURST_SIZE 256 102 #define RTE_LIBRTE_GRAPH_STATS 1 103 104 /****** driver defines ********/ 105 106 /* Packet prefetching in PMDs */ 107 #define RTE_PMD_PACKET_PREFETCH 1 108 109 /* QuickAssist device */ 110 /* Max. number of QuickAssist devices which can be attached */ 111 #define RTE_PMD_QAT_MAX_PCI_DEVICES 48 112 #define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16 113 #define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536 114 115 /* virtio crypto defines */ 116 #define RTE_MAX_VIRTIO_CRYPTO 32 117 118 /* DPAA SEC max cryptodev devices*/ 119 #define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4 120 121 /* fm10k defines */ 122 #define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1 123 124 /* hns3 defines */ 125 #define RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 256 126 127 /* i40e defines */ 128 #define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1 129 #undef RTE_LIBRTE_I40E_16BYTE_RX_DESC 130 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64 131 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 132 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4 133 134 /* Ring net PMD settings */ 135 #define RTE_PMD_RING_MAX_RX_RINGS 16 136 #define RTE_PMD_RING_MAX_TX_RINGS 16 137 138 /* QEDE PMD defines */ 139 #define RTE_LIBRTE_QEDE_FW "" 140 141 /* DLB PMD defines */ 142 #define RTE_LIBRTE_PMD_DLB_POLL_INTERVAL 1000 143 #define RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE 0 144 #undef RTE_LIBRTE_PMD_DLB_QUELL_STATS 145 #define RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA 32 146 147 /* DLB2 defines */ 148 #define RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL 1000 149 #define RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE 0 150 #undef RTE_LIBRTE_PMD_DLB2_QUELL_STATS 151 #define RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA 32 152 #define RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH 256 153 154 #endif /* _RTE_CONFIG_H_ */ 155