xref: /f-stack/dpdk/config/arm/meson.build (revision 2d9fd380) 
1# SPDX-License-Identifier: BSD-3-Clause
2# Copyright(c) 2017 Intel Corporation.
3# Copyright(c) 2017 Cavium, Inc
4
5# for checking defines we need to use the correct compiler flags
6march_opt = '-march=@0@'.format(machine)
7
8arm_force_native_march = false
9arm_force_default_march = (machine == 'default')
10
11flags_common_default = [
12	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
13	# to determine the best threshold in code. Refer to notes in source file
14	# (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
15	['RTE_ARCH_ARM64_MEMCPY', false],
16	#	['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
17	#	['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
18	# Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
19	# strong reasons.
20	#	['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
21	#	['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
22	#	['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
23
24	['RTE_NET_FM10K', false],
25	['RTE_NET_AVP', false],
26
27	['RTE_SCHED_VECTOR', false],
28	['RTE_ARM_USE_WFE', false],
29]
30
31flags_generic = [
32	['RTE_MACHINE', '"armv8a"'],
33	['RTE_MAX_LCORE', 256],
34	['RTE_USE_C11_MEM_MODEL', true],
35	['RTE_CACHE_LINE_SIZE', 128]]
36flags_arm = [
37	['RTE_MACHINE', '"armv8a"'],
38	['RTE_MAX_LCORE', 16],
39	['RTE_USE_C11_MEM_MODEL', true],
40	['RTE_CACHE_LINE_SIZE', 64]]
41flags_cavium = [
42	['RTE_CACHE_LINE_SIZE', 128],
43	['RTE_MAX_NUMA_NODES', 2],
44	['RTE_MAX_LCORE', 96],
45	['RTE_MAX_VFIO_GROUPS', 128]]
46flags_dpaa = [
47	['RTE_MACHINE', '"dpaa"'],
48	['RTE_USE_C11_MEM_MODEL', true],
49	['RTE_CACHE_LINE_SIZE', 64],
50	['RTE_MAX_NUMA_NODES', 1],
51	['RTE_MAX_LCORE', 16],
52	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
53flags_emag = [
54	['RTE_MACHINE', '"emag"'],
55	['RTE_CACHE_LINE_SIZE', 64],
56	['RTE_MAX_NUMA_NODES', 1],
57	['RTE_MAX_LCORE', 32]]
58flags_armada = [
59	['RTE_MACHINE', '"armv8a"'],
60	['RTE_CACHE_LINE_SIZE', 64],
61	['RTE_MAX_NUMA_NODES', 1],
62	['RTE_MAX_LCORE', 16]]
63
64flags_default_extra = []
65flags_thunderx_extra = [
66	['RTE_MACHINE', '"thunderx"'],
67	['RTE_USE_C11_MEM_MODEL', false]]
68flags_thunderx2_extra = [
69	['RTE_MACHINE', '"thunderx2"'],
70	['RTE_CACHE_LINE_SIZE', 64],
71	['RTE_MAX_NUMA_NODES', 2],
72	['RTE_MAX_LCORE', 256],
73	['RTE_ARM_FEATURE_ATOMICS', true],
74	['RTE_USE_C11_MEM_MODEL', true]]
75flags_octeontx2_extra = [
76	['RTE_MACHINE', '"octeontx2"'],
77	['RTE_MAX_NUMA_NODES', 1],
78	['RTE_MAX_LCORE', 36],
79	['RTE_ARM_FEATURE_ATOMICS', true],
80	['RTE_EAL_IGB_UIO', false],
81	['RTE_USE_C11_MEM_MODEL', true]]
82flags_n1generic_extra = [
83	['RTE_MACHINE', '"neoverse-n1"'],
84	['RTE_MAX_LCORE', 64],
85	['RTE_CACHE_LINE_SIZE', 64],
86	['RTE_ARM_FEATURE_ATOMICS', true],
87	['RTE_USE_C11_MEM_MODEL', true],
88	['RTE_MAX_MEM_MB', 1048576],
89	['RTE_MAX_NUMA_NODES', 1],
90	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
91	['RTE_LIBRTE_VHOST_NUMA', false]]
92
93machine_args_generic = [
94	['default', ['-march=armv8-a+crc', '-moutline-atomics']],
95	['native', ['-march=native']],
96	['0xd03', ['-mcpu=cortex-a53']],
97	['0xd04', ['-mcpu=cortex-a35']],
98	['0xd07', ['-mcpu=cortex-a57']],
99	['0xd08', ['-mcpu=cortex-a72']],
100	['0xd09', ['-mcpu=cortex-a73']],
101	['0xd0a', ['-mcpu=cortex-a75']],
102	['0xd0b', ['-mcpu=cortex-a76']],
103	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra]]
104
105machine_args_cavium = [
106	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
107	['native', ['-march=native']],
108	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
109	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
110	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
111	['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_thunderx2_extra],
112	['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_octeontx2_extra]]
113
114machine_args_emag = [
115	['default', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
116	['native', ['-march=native']]]
117
118## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
119impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
120impl_0x41 = ['Arm', flags_arm, machine_args_generic]
121impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
122impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
123impl_0x44 = ['DEC', flags_generic, machine_args_generic]
124impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
125impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
126impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
127impl_0x50 = ['Ampere Computing', flags_emag, machine_args_emag]
128impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
129impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
130impl_0x56 = ['Marvell ARMADA', flags_armada, machine_args_generic]
131impl_0x69 = ['Intel', flags_generic, machine_args_generic]
132impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
133
134dpdk_conf.set('RTE_ARCH_ARM', 1)
135dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
136
137if dpdk_conf.get('RTE_ARCH_32')
138	dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
139	dpdk_conf.set('RTE_ARCH_ARMv7', 1)
140	# the minimum architecture supported, armv7-a, needs the following,
141	# mk/machine/armv7a/rte.vars.mk sets it too
142	machine_args += '-mfpu=neon'
143else
144	dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
145	dpdk_conf.set('RTE_ARCH_ARM64', 1)
146
147	machine = []
148	cmd_generic = ['generic', '', '', 'default', '']
149	cmd_output = cmd_generic # Set generic by default
150	machine_args = [] # Clear previous machine args
151	if arm_force_default_march and not meson.is_cross_build()
152		machine = impl_generic
153		impl_pn = 'default'
154	elif not meson.is_cross_build()
155		# The script returns ['Implementer', 'Variant', 'Architecture',
156		# 'Primary Part number', 'Revision']
157		detect_vendor = find_program(join_paths(
158				meson.current_source_dir(), 'armv8_machine.py'))
159		cmd = run_command(detect_vendor.path())
160		if cmd.returncode() == 0
161			cmd_output = cmd.stdout().to_lower().strip().split(' ')
162		endif
163		# Set to generic if variable is not found
164		machine = get_variable('impl_' + cmd_output[0], ['generic'])
165		if machine[0] == 'generic'
166			machine = impl_generic
167			cmd_output = cmd_generic
168		endif
169		impl_pn = cmd_output[3]
170		if arm_force_native_march == true
171			impl_pn = 'native'
172		endif
173	else
174		impl_id = meson.get_cross_property('implementor_id', 'generic')
175		impl_pn = meson.get_cross_property('implementor_pn', 'default')
176		machine = get_variable('impl_' + impl_id)
177	endif
178
179	# Apply Common Defaults. These settings may be overwritten by machine
180	# settings later.
181	foreach flag: flags_common_default
182		if flag.length() > 0
183			dpdk_conf.set(flag[0], flag[1])
184		endif
185	endforeach
186
187	message('Implementer : ' + machine[0])
188	foreach flag: machine[1]
189		if flag.length() > 0
190			dpdk_conf.set(flag[0], flag[1])
191		endif
192	endforeach
193
194	foreach marg: machine[2]
195		if marg[0] == impl_pn
196			foreach flag: marg[1]
197				if cc.has_argument(flag)
198					machine_args += flag
199				endif
200			endforeach
201			# Apply any extra machine specific flags.
202			foreach flag: marg.get(2, flags_default_extra)
203				if flag.length() > 0
204					dpdk_conf.set(flag[0], flag[1])
205				endif
206			endforeach
207		endif
208	endforeach
209endif
210message(machine_args)
211
212if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
213    cc.get_define('__aarch64__', args: machine_args) != '')
214	compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
215endif
216
217if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
218	compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
219endif
220
221if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
222	compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
223	'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
224endif
225