1DPDK_22 { 2 global: 3 4 rte_approx; 5 rte_red_config_init; 6 rte_red_log2_1_minus_Wq; 7 rte_red_pow2_frac_inv; 8 rte_red_rand_seed; 9 rte_red_rand_val; 10 rte_red_rt_data_init; 11 rte_sched_pipe_config; 12 rte_sched_port_config; 13 rte_sched_port_dequeue; 14 rte_sched_port_enqueue; 15 rte_sched_port_free; 16 rte_sched_port_get_memory_footprint; 17 rte_sched_port_pkt_read_color; 18 rte_sched_port_pkt_read_tree_path; 19 rte_sched_port_pkt_write; 20 rte_sched_queue_read_stats; 21 rte_sched_subport_config; 22 rte_sched_subport_pipe_profile_add; 23 rte_sched_subport_read_stats; 24 25 local: *; 26}; 27 28EXPERIMENTAL { 29 global: 30 31 # added in 20.11 32 rte_sched_port_subport_profile_add; 33 34 # added in 21.11 35 rte_pie_rt_data_init; 36 rte_pie_config_init; 37}; 38