1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2021 Intel Corporation
3 */
4
5 #include <stdint.h>
6 #include <getopt.h>
7 #include <signal.h>
8 #include <stdbool.h>
9 #include <unistd.h>
10
11 #include <rte_malloc.h>
12 #include <rte_ethdev.h>
13 #include <rte_dmadev.h>
14
15 /* size of ring used for software copying between rx and tx. */
16 #define RTE_LOGTYPE_DMA RTE_LOGTYPE_USER1
17 #define MAX_PKT_BURST 32
18 #define MEMPOOL_CACHE_SIZE 512
19 #define MIN_POOL_SIZE 65536U
20 #define CMD_LINE_OPT_MAC_UPDATING "mac-updating"
21 #define CMD_LINE_OPT_NO_MAC_UPDATING "no-mac-updating"
22 #define CMD_LINE_OPT_PORTMASK "portmask"
23 #define CMD_LINE_OPT_NB_QUEUE "nb-queue"
24 #define CMD_LINE_OPT_COPY_TYPE "copy-type"
25 #define CMD_LINE_OPT_RING_SIZE "ring-size"
26 #define CMD_LINE_OPT_BATCH_SIZE "dma-batch-size"
27 #define CMD_LINE_OPT_FRAME_SIZE "max-frame-size"
28 #define CMD_LINE_OPT_STATS_INTERVAL "stats-interval"
29
30 /* configurable number of RX/TX ring descriptors */
31 #define RX_DEFAULT_RINGSIZE 1024
32 #define TX_DEFAULT_RINGSIZE 1024
33
34 /* max number of RX queues per port */
35 #define MAX_RX_QUEUES_COUNT 8
36
37 struct rxtx_port_config {
38 /* common config */
39 uint16_t rxtx_port;
40 uint16_t nb_queues;
41 /* for software copy mode */
42 struct rte_ring *rx_to_tx_ring;
43 /* for dmadev HW copy mode */
44 uint16_t dmadev_ids[MAX_RX_QUEUES_COUNT];
45 };
46
47 /* Configuring ports and number of assigned lcores in struct. 8< */
48 struct rxtx_transmission_config {
49 struct rxtx_port_config ports[RTE_MAX_ETHPORTS];
50 uint16_t nb_ports;
51 uint16_t nb_lcores;
52 };
53 /* >8 End of configuration of ports and number of assigned lcores. */
54
55 /* per-port statistics struct */
56 struct dma_port_statistics {
57 uint64_t rx[RTE_MAX_ETHPORTS];
58 uint64_t tx[RTE_MAX_ETHPORTS];
59 uint64_t tx_dropped[RTE_MAX_ETHPORTS];
60 uint64_t copy_dropped[RTE_MAX_ETHPORTS];
61 };
62 struct dma_port_statistics port_statistics;
63 struct total_statistics {
64 uint64_t total_packets_dropped;
65 uint64_t total_packets_tx;
66 uint64_t total_packets_rx;
67 uint64_t total_submitted;
68 uint64_t total_completed;
69 uint64_t total_failed;
70 };
71
72 typedef enum copy_mode_t {
73 #define COPY_MODE_SW "sw"
74 COPY_MODE_SW_NUM,
75 #define COPY_MODE_DMA "hw"
76 COPY_MODE_DMA_NUM,
77 COPY_MODE_INVALID_NUM,
78 COPY_MODE_SIZE_NUM = COPY_MODE_INVALID_NUM
79 } copy_mode_t;
80
81 /* mask of enabled ports */
82 static uint32_t dma_enabled_port_mask;
83
84 /* number of RX queues per port */
85 static uint16_t nb_queues = 1;
86
87 /* MAC updating enabled by default. */
88 static int mac_updating = 1;
89
90 /* hardware copy mode enabled by default. */
91 static copy_mode_t copy_mode = COPY_MODE_DMA_NUM;
92
93 /* size of descriptor ring for hardware copy mode or
94 * rte_ring for software copy mode
95 */
96 static unsigned short ring_size = 2048;
97
98 /* interval, in seconds, between stats prints */
99 static unsigned short stats_interval = 1;
100 /* global mbuf arrays for tracking DMA bufs */
101 #define MBUF_RING_SIZE 2048
102 #define MBUF_RING_MASK (MBUF_RING_SIZE - 1)
103 struct dma_bufs {
104 struct rte_mbuf *bufs[MBUF_RING_SIZE];
105 struct rte_mbuf *copies[MBUF_RING_SIZE];
106 uint16_t sent;
107 };
108 static struct dma_bufs dma_bufs[RTE_DMADEV_DEFAULT_MAX];
109
110 /* global transmission config */
111 struct rxtx_transmission_config cfg;
112
113 /* configurable number of RX/TX ring descriptors */
114 static uint16_t nb_rxd = RX_DEFAULT_RINGSIZE;
115 static uint16_t nb_txd = TX_DEFAULT_RINGSIZE;
116
117 static volatile bool force_quit;
118
119 static uint32_t dma_batch_sz = MAX_PKT_BURST;
120 static uint32_t max_frame_size = RTE_ETHER_MAX_LEN;
121
122 /* ethernet addresses of ports */
123 static struct rte_ether_addr dma_ports_eth_addr[RTE_MAX_ETHPORTS];
124
125 static struct rte_eth_dev_tx_buffer *tx_buffer[RTE_MAX_ETHPORTS];
126 struct rte_mempool *dma_pktmbuf_pool;
127
128 /* Print out statistics for one port. */
129 static void
print_port_stats(uint16_t port_id)130 print_port_stats(uint16_t port_id)
131 {
132 printf("\nStatistics for port %u ------------------------------"
133 "\nPackets sent: %34"PRIu64
134 "\nPackets received: %30"PRIu64
135 "\nPackets dropped on tx: %25"PRIu64
136 "\nPackets dropped on copy: %23"PRIu64,
137 port_id,
138 port_statistics.tx[port_id],
139 port_statistics.rx[port_id],
140 port_statistics.tx_dropped[port_id],
141 port_statistics.copy_dropped[port_id]);
142 }
143
144 /* Print out statistics for one dmadev device. */
145 static void
print_dmadev_stats(uint32_t dev_id,struct rte_dma_stats stats)146 print_dmadev_stats(uint32_t dev_id, struct rte_dma_stats stats)
147 {
148 printf("\nDMA channel %u", dev_id);
149 printf("\n\t Total submitted ops: %"PRIu64"", stats.submitted);
150 printf("\n\t Total completed ops: %"PRIu64"", stats.completed);
151 printf("\n\t Total failed ops: %"PRIu64"", stats.errors);
152 }
153
154 static void
print_total_stats(struct total_statistics * ts)155 print_total_stats(struct total_statistics *ts)
156 {
157 printf("\nAggregate statistics ==============================="
158 "\nTotal packets Tx: %22"PRIu64" [pkt/s]"
159 "\nTotal packets Rx: %22"PRIu64" [pkt/s]"
160 "\nTotal packets dropped: %17"PRIu64" [pkt/s]",
161 ts->total_packets_tx / stats_interval,
162 ts->total_packets_rx / stats_interval,
163 ts->total_packets_dropped / stats_interval);
164
165 if (copy_mode == COPY_MODE_DMA_NUM) {
166 printf("\nTotal submitted ops: %19"PRIu64" [ops/s]"
167 "\nTotal completed ops: %19"PRIu64" [ops/s]"
168 "\nTotal failed ops: %22"PRIu64" [ops/s]",
169 ts->total_submitted / stats_interval,
170 ts->total_completed / stats_interval,
171 ts->total_failed / stats_interval);
172 }
173
174 printf("\n====================================================\n");
175 }
176
177 /* Print out statistics on packets dropped. */
178 static void
print_stats(char * prgname)179 print_stats(char *prgname)
180 {
181 struct total_statistics ts, delta_ts;
182 struct rte_dma_stats stats = {0};
183 uint32_t i, port_id, dev_id;
184 char status_string[255]; /* to print at the top of the output */
185 int status_strlen;
186
187 const char clr[] = { 27, '[', '2', 'J', '\0' };
188 const char topLeft[] = { 27, '[', '1', ';', '1', 'H', '\0' };
189
190 status_strlen = snprintf(status_string, sizeof(status_string),
191 "%s, ", prgname);
192 status_strlen += snprintf(status_string + status_strlen,
193 sizeof(status_string) - status_strlen,
194 "Worker Threads = %d, ",
195 rte_lcore_count() > 2 ? 2 : 1);
196 status_strlen += snprintf(status_string + status_strlen,
197 sizeof(status_string) - status_strlen,
198 "Copy Mode = %s,\n", copy_mode == COPY_MODE_SW_NUM ?
199 COPY_MODE_SW : COPY_MODE_DMA);
200 status_strlen += snprintf(status_string + status_strlen,
201 sizeof(status_string) - status_strlen,
202 "Updating MAC = %s, ", mac_updating ?
203 "enabled" : "disabled");
204 status_strlen += snprintf(status_string + status_strlen,
205 sizeof(status_string) - status_strlen,
206 "Rx Queues = %d, ", nb_queues);
207 status_strlen += snprintf(status_string + status_strlen,
208 sizeof(status_string) - status_strlen,
209 "Ring Size = %d", ring_size);
210
211 memset(&ts, 0, sizeof(struct total_statistics));
212
213 while (!force_quit) {
214 /* Sleep for "stats_interval" seconds each round - init sleep allows reading
215 * messages from app startup.
216 */
217 sleep(stats_interval);
218
219 /* Clear screen and move to top left */
220 printf("%s%s", clr, topLeft);
221
222 memset(&delta_ts, 0, sizeof(struct total_statistics));
223
224 printf("%s\n", status_string);
225
226 for (i = 0; i < cfg.nb_ports; i++) {
227 port_id = cfg.ports[i].rxtx_port;
228 print_port_stats(port_id);
229
230 delta_ts.total_packets_dropped +=
231 port_statistics.tx_dropped[port_id]
232 + port_statistics.copy_dropped[port_id];
233 delta_ts.total_packets_tx +=
234 port_statistics.tx[port_id];
235 delta_ts.total_packets_rx +=
236 port_statistics.rx[port_id];
237
238 if (copy_mode == COPY_MODE_DMA_NUM) {
239 uint32_t j;
240
241 for (j = 0; j < cfg.ports[i].nb_queues; j++) {
242 dev_id = cfg.ports[i].dmadev_ids[j];
243 rte_dma_stats_get(dev_id, 0, &stats);
244 print_dmadev_stats(dev_id, stats);
245
246 delta_ts.total_submitted += stats.submitted;
247 delta_ts.total_completed += stats.completed;
248 delta_ts.total_failed += stats.errors;
249 }
250 }
251 }
252
253 delta_ts.total_packets_tx -= ts.total_packets_tx;
254 delta_ts.total_packets_rx -= ts.total_packets_rx;
255 delta_ts.total_packets_dropped -= ts.total_packets_dropped;
256 delta_ts.total_submitted -= ts.total_submitted;
257 delta_ts.total_completed -= ts.total_completed;
258 delta_ts.total_failed -= ts.total_failed;
259
260 printf("\n");
261 print_total_stats(&delta_ts);
262
263 fflush(stdout);
264
265 ts.total_packets_tx += delta_ts.total_packets_tx;
266 ts.total_packets_rx += delta_ts.total_packets_rx;
267 ts.total_packets_dropped += delta_ts.total_packets_dropped;
268 ts.total_submitted += delta_ts.total_submitted;
269 ts.total_completed += delta_ts.total_completed;
270 ts.total_failed += delta_ts.total_failed;
271 }
272 }
273
274 static void
update_mac_addrs(struct rte_mbuf * m,uint32_t dest_portid)275 update_mac_addrs(struct rte_mbuf *m, uint32_t dest_portid)
276 {
277 struct rte_ether_hdr *eth;
278 void *tmp;
279
280 eth = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
281
282 /* 02:00:00:00:00:xx - overwriting 2 bytes of source address but
283 * it's acceptable cause it gets overwritten by rte_ether_addr_copy
284 */
285 tmp = ð->dst_addr.addr_bytes[0];
286 *((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dest_portid << 40);
287
288 /* src addr */
289 rte_ether_addr_copy(&dma_ports_eth_addr[dest_portid], ð->src_addr);
290 }
291
292 /* Perform packet copy there is a user-defined function. 8< */
293 static inline void
pktmbuf_metadata_copy(const struct rte_mbuf * src,struct rte_mbuf * dst)294 pktmbuf_metadata_copy(const struct rte_mbuf *src, struct rte_mbuf *dst)
295 {
296 dst->data_off = src->data_off;
297 memcpy(&dst->rx_descriptor_fields1, &src->rx_descriptor_fields1,
298 offsetof(struct rte_mbuf, buf_len) -
299 offsetof(struct rte_mbuf, rx_descriptor_fields1));
300 }
301
302 /* Copy packet data */
303 static inline void
pktmbuf_sw_copy(struct rte_mbuf * src,struct rte_mbuf * dst)304 pktmbuf_sw_copy(struct rte_mbuf *src, struct rte_mbuf *dst)
305 {
306 rte_memcpy(rte_pktmbuf_mtod(dst, char *),
307 rte_pktmbuf_mtod(src, char *), src->data_len);
308 }
309 /* >8 End of perform packet copy there is a user-defined function. */
310
311 static uint32_t
dma_enqueue_packets(struct rte_mbuf * pkts[],struct rte_mbuf * pkts_copy[],uint32_t nb_rx,uint16_t dev_id)312 dma_enqueue_packets(struct rte_mbuf *pkts[], struct rte_mbuf *pkts_copy[],
313 uint32_t nb_rx, uint16_t dev_id)
314 {
315 struct dma_bufs *dma = &dma_bufs[dev_id];
316 int ret;
317 uint32_t i;
318
319 for (i = 0; i < nb_rx; i++) {
320 /* Perform data copy */
321 ret = rte_dma_copy(dev_id, 0,
322 rte_pktmbuf_iova(pkts[i]),
323 rte_pktmbuf_iova(pkts_copy[i]),
324 rte_pktmbuf_data_len(pkts[i]), 0);
325
326 if (ret < 0)
327 break;
328
329 dma->bufs[ret & MBUF_RING_MASK] = pkts[i];
330 dma->copies[ret & MBUF_RING_MASK] = pkts_copy[i];
331 }
332
333 ret = i;
334 return ret;
335 }
336
337 static inline uint32_t
dma_enqueue(struct rte_mbuf * pkts[],struct rte_mbuf * pkts_copy[],uint32_t num,uint32_t step,uint16_t dev_id)338 dma_enqueue(struct rte_mbuf *pkts[], struct rte_mbuf *pkts_copy[],
339 uint32_t num, uint32_t step, uint16_t dev_id)
340 {
341 uint32_t i, k, m, n;
342
343 k = 0;
344 for (i = 0; i < num; i += m) {
345
346 m = RTE_MIN(step, num - i);
347 n = dma_enqueue_packets(pkts + i, pkts_copy + i, m, dev_id);
348 k += n;
349 if (n > 0)
350 rte_dma_submit(dev_id, 0);
351
352 /* don't try to enqueue more if HW queue is full */
353 if (n != m)
354 break;
355 }
356
357 return k;
358 }
359
360 static inline uint32_t
dma_dequeue(struct rte_mbuf * src[],struct rte_mbuf * dst[],uint32_t num,uint16_t dev_id)361 dma_dequeue(struct rte_mbuf *src[], struct rte_mbuf *dst[], uint32_t num,
362 uint16_t dev_id)
363 {
364 struct dma_bufs *dma = &dma_bufs[dev_id];
365 uint16_t nb_dq, filled;
366 /* Dequeue the mbufs from DMA device. Since all memory
367 * is DPDK pinned memory and therefore all addresses should
368 * be valid, we don't check for copy errors
369 */
370 nb_dq = rte_dma_completed(dev_id, 0, num, NULL, NULL);
371
372 /* Return early if no work to do */
373 if (unlikely(nb_dq == 0))
374 return nb_dq;
375
376 /* Populate pkts_copy with the copies bufs from dma->copies for tx */
377 for (filled = 0; filled < nb_dq; filled++) {
378 src[filled] = dma->bufs[(dma->sent + filled) & MBUF_RING_MASK];
379 dst[filled] = dma->copies[(dma->sent + filled) & MBUF_RING_MASK];
380 }
381 dma->sent += nb_dq;
382
383 return filled;
384
385 }
386
387 /* Receive packets on one port and enqueue to dmadev or rte_ring. 8< */
388 static void
dma_rx_port(struct rxtx_port_config * rx_config)389 dma_rx_port(struct rxtx_port_config *rx_config)
390 {
391 int32_t ret;
392 uint32_t nb_rx, nb_enq, i, j;
393 struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
394 struct rte_mbuf *pkts_burst_copy[MAX_PKT_BURST];
395
396 for (i = 0; i < rx_config->nb_queues; i++) {
397
398 nb_rx = rte_eth_rx_burst(rx_config->rxtx_port, i,
399 pkts_burst, MAX_PKT_BURST);
400
401 if (nb_rx == 0)
402 continue;
403
404 port_statistics.rx[rx_config->rxtx_port] += nb_rx;
405
406 ret = rte_mempool_get_bulk(dma_pktmbuf_pool,
407 (void *)pkts_burst_copy, nb_rx);
408
409 if (unlikely(ret < 0))
410 rte_exit(EXIT_FAILURE,
411 "Unable to allocate memory.\n");
412
413 for (j = 0; j < nb_rx; j++)
414 pktmbuf_metadata_copy(pkts_burst[j],
415 pkts_burst_copy[j]);
416
417 if (copy_mode == COPY_MODE_DMA_NUM) {
418 /* enqueue packets for hardware copy */
419 nb_enq = dma_enqueue(pkts_burst, pkts_burst_copy,
420 nb_rx, dma_batch_sz, rx_config->dmadev_ids[i]);
421
422 /* free any not enqueued packets. */
423 rte_mempool_put_bulk(dma_pktmbuf_pool,
424 (void *)&pkts_burst[nb_enq],
425 nb_rx - nb_enq);
426 rte_mempool_put_bulk(dma_pktmbuf_pool,
427 (void *)&pkts_burst_copy[nb_enq],
428 nb_rx - nb_enq);
429
430 port_statistics.copy_dropped[rx_config->rxtx_port] +=
431 (nb_rx - nb_enq);
432
433 /* get completed copies */
434 nb_rx = dma_dequeue(pkts_burst, pkts_burst_copy,
435 MAX_PKT_BURST, rx_config->dmadev_ids[i]);
436 } else {
437 /* Perform packet software copy, free source packets */
438 for (j = 0; j < nb_rx; j++)
439 pktmbuf_sw_copy(pkts_burst[j],
440 pkts_burst_copy[j]);
441 }
442
443 rte_mempool_put_bulk(dma_pktmbuf_pool,
444 (void *)pkts_burst, nb_rx);
445
446 nb_enq = rte_ring_enqueue_burst(rx_config->rx_to_tx_ring,
447 (void *)pkts_burst_copy, nb_rx, NULL);
448
449 /* Free any not enqueued packets. */
450 rte_mempool_put_bulk(dma_pktmbuf_pool,
451 (void *)&pkts_burst_copy[nb_enq],
452 nb_rx - nb_enq);
453
454 port_statistics.copy_dropped[rx_config->rxtx_port] +=
455 (nb_rx - nb_enq);
456 }
457 }
458 /* >8 End of receive packets on one port and enqueue to dmadev or rte_ring. */
459
460 /* Transmit packets from dmadev/rte_ring for one port. 8< */
461 static void
dma_tx_port(struct rxtx_port_config * tx_config)462 dma_tx_port(struct rxtx_port_config *tx_config)
463 {
464 uint32_t i, j, nb_dq, nb_tx;
465 struct rte_mbuf *mbufs[MAX_PKT_BURST];
466
467 for (i = 0; i < tx_config->nb_queues; i++) {
468
469 /* Dequeue the mbufs from rx_to_tx_ring. */
470 nb_dq = rte_ring_dequeue_burst(tx_config->rx_to_tx_ring,
471 (void *)mbufs, MAX_PKT_BURST, NULL);
472 if (nb_dq == 0)
473 continue;
474
475 /* Update macs if enabled */
476 if (mac_updating) {
477 for (j = 0; j < nb_dq; j++)
478 update_mac_addrs(mbufs[j],
479 tx_config->rxtx_port);
480 }
481
482 nb_tx = rte_eth_tx_burst(tx_config->rxtx_port, 0,
483 (void *)mbufs, nb_dq);
484
485 port_statistics.tx[tx_config->rxtx_port] += nb_tx;
486
487 /* Free any unsent packets. */
488 if (unlikely(nb_tx < nb_dq))
489 rte_mempool_put_bulk(dma_pktmbuf_pool,
490 (void *)&mbufs[nb_tx], nb_dq - nb_tx);
491 }
492 }
493 /* >8 End of transmitting packets from dmadev. */
494
495 /* Main rx processing loop for dmadev. */
496 static void
rx_main_loop(void)497 rx_main_loop(void)
498 {
499 uint16_t i;
500 uint16_t nb_ports = cfg.nb_ports;
501
502 RTE_LOG(INFO, DMA, "Entering main rx loop for copy on lcore %u\n",
503 rte_lcore_id());
504
505 while (!force_quit)
506 for (i = 0; i < nb_ports; i++)
507 dma_rx_port(&cfg.ports[i]);
508 }
509
510 /* Main tx processing loop for hardware copy. */
511 static void
tx_main_loop(void)512 tx_main_loop(void)
513 {
514 uint16_t i;
515 uint16_t nb_ports = cfg.nb_ports;
516
517 RTE_LOG(INFO, DMA, "Entering main tx loop for copy on lcore %u\n",
518 rte_lcore_id());
519
520 while (!force_quit)
521 for (i = 0; i < nb_ports; i++)
522 dma_tx_port(&cfg.ports[i]);
523 }
524
525 /* Main rx and tx loop if only one worker lcore available */
526 static void
rxtx_main_loop(void)527 rxtx_main_loop(void)
528 {
529 uint16_t i;
530 uint16_t nb_ports = cfg.nb_ports;
531
532 RTE_LOG(INFO, DMA, "Entering main rx and tx loop for copy on"
533 " lcore %u\n", rte_lcore_id());
534
535 while (!force_quit)
536 for (i = 0; i < nb_ports; i++) {
537 dma_rx_port(&cfg.ports[i]);
538 dma_tx_port(&cfg.ports[i]);
539 }
540 }
541
542 /* Start processing for each lcore. 8< */
start_forwarding_cores(void)543 static void start_forwarding_cores(void)
544 {
545 uint32_t lcore_id = rte_lcore_id();
546
547 RTE_LOG(INFO, DMA, "Entering %s on lcore %u\n",
548 __func__, rte_lcore_id());
549
550 if (cfg.nb_lcores == 1) {
551 lcore_id = rte_get_next_lcore(lcore_id, true, true);
552 rte_eal_remote_launch((lcore_function_t *)rxtx_main_loop,
553 NULL, lcore_id);
554 } else if (cfg.nb_lcores > 1) {
555 lcore_id = rte_get_next_lcore(lcore_id, true, true);
556 rte_eal_remote_launch((lcore_function_t *)rx_main_loop,
557 NULL, lcore_id);
558
559 lcore_id = rte_get_next_lcore(lcore_id, true, true);
560 rte_eal_remote_launch((lcore_function_t *)tx_main_loop, NULL,
561 lcore_id);
562 }
563 }
564 /* >8 End of starting to process for each lcore. */
565
566 /* Display usage */
567 static void
dma_usage(const char * prgname)568 dma_usage(const char *prgname)
569 {
570 printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n"
571 " -b --dma-batch-size: number of requests per DMA batch\n"
572 " -f --max-frame-size: max frame size\n"
573 " -p --portmask: hexadecimal bitmask of ports to configure\n"
574 " -q NQ: number of RX queues per port (default is 1)\n"
575 " --[no-]mac-updating: Enable or disable MAC addresses updating (enabled by default)\n"
576 " When enabled:\n"
577 " - The source MAC address is replaced by the TX port MAC address\n"
578 " - The destination MAC address is replaced by 02:00:00:00:00:TX_PORT_ID\n"
579 " -c --copy-type CT: type of copy: sw|hw\n"
580 " -s --ring-size RS: size of dmadev descriptor ring for hardware copy mode or rte_ring for software copy mode\n"
581 " -i --stats-interval SI: interval, in seconds, between stats prints (default is 1)\n",
582 prgname);
583 }
584
585 static int
dma_parse_portmask(const char * portmask)586 dma_parse_portmask(const char *portmask)
587 {
588 char *end = NULL;
589 unsigned long pm;
590
591 /* Parse hexadecimal string */
592 pm = strtoul(portmask, &end, 16);
593 if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
594 return 0;
595
596 return pm;
597 }
598
599 static copy_mode_t
dma_parse_copy_mode(const char * copy_mode)600 dma_parse_copy_mode(const char *copy_mode)
601 {
602 if (strcmp(copy_mode, COPY_MODE_SW) == 0)
603 return COPY_MODE_SW_NUM;
604 else if (strcmp(copy_mode, COPY_MODE_DMA) == 0)
605 return COPY_MODE_DMA_NUM;
606
607 return COPY_MODE_INVALID_NUM;
608 }
609
610 /* Parse the argument given in the command line of the application */
611 static int
dma_parse_args(int argc,char ** argv,unsigned int nb_ports)612 dma_parse_args(int argc, char **argv, unsigned int nb_ports)
613 {
614 static const char short_options[] =
615 "b:" /* dma batch size */
616 "c:" /* copy type (sw|hw) */
617 "f:" /* max frame size */
618 "p:" /* portmask */
619 "q:" /* number of RX queues per port */
620 "s:" /* ring size */
621 "i:" /* interval, in seconds, between stats prints */
622 ;
623
624 static const struct option lgopts[] = {
625 {CMD_LINE_OPT_MAC_UPDATING, no_argument, &mac_updating, 1},
626 {CMD_LINE_OPT_NO_MAC_UPDATING, no_argument, &mac_updating, 0},
627 {CMD_LINE_OPT_PORTMASK, required_argument, NULL, 'p'},
628 {CMD_LINE_OPT_NB_QUEUE, required_argument, NULL, 'q'},
629 {CMD_LINE_OPT_COPY_TYPE, required_argument, NULL, 'c'},
630 {CMD_LINE_OPT_RING_SIZE, required_argument, NULL, 's'},
631 {CMD_LINE_OPT_BATCH_SIZE, required_argument, NULL, 'b'},
632 {CMD_LINE_OPT_FRAME_SIZE, required_argument, NULL, 'f'},
633 {CMD_LINE_OPT_STATS_INTERVAL, required_argument, NULL, 'i'},
634 {NULL, 0, 0, 0}
635 };
636
637 const unsigned int default_port_mask = (1 << nb_ports) - 1;
638 int opt, ret;
639 char **argvopt;
640 int option_index;
641 char *prgname = argv[0];
642
643 dma_enabled_port_mask = default_port_mask;
644 argvopt = argv;
645
646 while ((opt = getopt_long(argc, argvopt, short_options,
647 lgopts, &option_index)) != EOF) {
648
649 switch (opt) {
650 case 'b':
651 dma_batch_sz = atoi(optarg);
652 if (dma_batch_sz > MAX_PKT_BURST) {
653 printf("Invalid dma batch size, %s.\n", optarg);
654 dma_usage(prgname);
655 return -1;
656 }
657 break;
658 case 'f':
659 max_frame_size = atoi(optarg);
660 if (max_frame_size > RTE_ETHER_MAX_JUMBO_FRAME_LEN) {
661 printf("Invalid max frame size, %s.\n", optarg);
662 dma_usage(prgname);
663 return -1;
664 }
665 break;
666
667 /* portmask */
668 case 'p':
669 dma_enabled_port_mask = dma_parse_portmask(optarg);
670 if (dma_enabled_port_mask & ~default_port_mask ||
671 dma_enabled_port_mask <= 0) {
672 printf("Invalid portmask, %s, suggest 0x%x\n",
673 optarg, default_port_mask);
674 dma_usage(prgname);
675 return -1;
676 }
677 break;
678
679 case 'q':
680 nb_queues = atoi(optarg);
681 if (nb_queues == 0 || nb_queues > MAX_RX_QUEUES_COUNT) {
682 printf("Invalid RX queues number %s. Max %u\n",
683 optarg, MAX_RX_QUEUES_COUNT);
684 dma_usage(prgname);
685 return -1;
686 }
687 break;
688
689 case 'c':
690 copy_mode = dma_parse_copy_mode(optarg);
691 if (copy_mode == COPY_MODE_INVALID_NUM) {
692 printf("Invalid copy type. Use: sw, hw\n");
693 dma_usage(prgname);
694 return -1;
695 }
696 break;
697
698 case 's':
699 ring_size = atoi(optarg);
700 if (ring_size == 0) {
701 printf("Invalid ring size, %s.\n", optarg);
702 dma_usage(prgname);
703 return -1;
704 }
705 /* ring_size must be less-than or equal to MBUF_RING_SIZE
706 * to avoid overwriting bufs
707 */
708 if (ring_size > MBUF_RING_SIZE) {
709 printf("Max ring_size is %d, setting ring_size to max",
710 MBUF_RING_SIZE);
711 ring_size = MBUF_RING_SIZE;
712 }
713 break;
714
715 case 'i':
716 stats_interval = atoi(optarg);
717 if (stats_interval == 0) {
718 printf("Invalid stats interval, setting to 1\n");
719 stats_interval = 1; /* set to default */
720 }
721 break;
722
723 /* long options */
724 case 0:
725 break;
726
727 default:
728 dma_usage(prgname);
729 return -1;
730 }
731 }
732
733 printf("MAC updating %s\n", mac_updating ? "enabled" : "disabled");
734 if (optind >= 0)
735 argv[optind - 1] = prgname;
736
737 ret = optind - 1;
738 optind = 1; /* reset getopt lib */
739 return ret;
740 }
741
742 /* check link status, return true if at least one port is up */
743 static int
check_link_status(uint32_t port_mask)744 check_link_status(uint32_t port_mask)
745 {
746 uint16_t portid;
747 struct rte_eth_link link;
748 int ret, link_status = 0;
749 char link_status_text[RTE_ETH_LINK_MAX_STR_LEN];
750
751 printf("\nChecking link status\n");
752 RTE_ETH_FOREACH_DEV(portid) {
753 if ((port_mask & (1 << portid)) == 0)
754 continue;
755
756 memset(&link, 0, sizeof(link));
757 ret = rte_eth_link_get(portid, &link);
758 if (ret < 0) {
759 printf("Port %u link get failed: err=%d\n",
760 portid, ret);
761 continue;
762 }
763
764 /* Print link status */
765 rte_eth_link_to_str(link_status_text,
766 sizeof(link_status_text), &link);
767 printf("Port %d %s\n", portid, link_status_text);
768
769 if (link.link_status)
770 link_status = 1;
771 }
772 return link_status;
773 }
774
775 /* Configuration of device. 8< */
776 static void
configure_dmadev_queue(uint32_t dev_id)777 configure_dmadev_queue(uint32_t dev_id)
778 {
779 struct rte_dma_info info;
780 struct rte_dma_conf dev_config = { .nb_vchans = 1 };
781 struct rte_dma_vchan_conf qconf = {
782 .direction = RTE_DMA_DIR_MEM_TO_MEM,
783 .nb_desc = ring_size
784 };
785 uint16_t vchan = 0;
786
787 if (rte_dma_configure(dev_id, &dev_config) != 0)
788 rte_exit(EXIT_FAILURE, "Error with rte_dma_configure()\n");
789
790 if (rte_dma_vchan_setup(dev_id, vchan, &qconf) != 0) {
791 printf("Error with queue configuration\n");
792 rte_panic();
793 }
794 rte_dma_info_get(dev_id, &info);
795 if (info.nb_vchans != 1) {
796 printf("Error, no configured queues reported on device id %u\n", dev_id);
797 rte_panic();
798 }
799 if (rte_dma_start(dev_id) != 0)
800 rte_exit(EXIT_FAILURE, "Error with rte_dma_start()\n");
801 }
802 /* >8 End of configuration of device. */
803
804 /* Using dmadev API functions. 8< */
805 static void
assign_dmadevs(void)806 assign_dmadevs(void)
807 {
808 uint16_t nb_dmadev = 0;
809 int16_t dev_id = rte_dma_next_dev(0);
810 uint32_t i, j;
811
812 for (i = 0; i < cfg.nb_ports; i++) {
813 for (j = 0; j < cfg.ports[i].nb_queues; j++) {
814 if (dev_id == -1)
815 goto end;
816
817 cfg.ports[i].dmadev_ids[j] = dev_id;
818 configure_dmadev_queue(cfg.ports[i].dmadev_ids[j]);
819 dev_id = rte_dma_next_dev(dev_id + 1);
820 ++nb_dmadev;
821 }
822 }
823 end:
824 if (nb_dmadev < cfg.nb_ports * cfg.ports[0].nb_queues)
825 rte_exit(EXIT_FAILURE,
826 "Not enough dmadevs (%u) for all queues (%u).\n",
827 nb_dmadev, cfg.nb_ports * cfg.ports[0].nb_queues);
828 RTE_LOG(INFO, DMA, "Number of used dmadevs: %u.\n", nb_dmadev);
829 }
830 /* >8 End of using dmadev API functions. */
831
832 /* Assign ring structures for packet exchanging. 8< */
833 static void
assign_rings(void)834 assign_rings(void)
835 {
836 uint32_t i;
837
838 for (i = 0; i < cfg.nb_ports; i++) {
839 char ring_name[RTE_RING_NAMESIZE];
840
841 snprintf(ring_name, sizeof(ring_name), "rx_to_tx_ring_%u", i);
842 /* Create ring for inter core communication */
843 cfg.ports[i].rx_to_tx_ring = rte_ring_create(
844 ring_name, ring_size,
845 rte_socket_id(), RING_F_SP_ENQ | RING_F_SC_DEQ);
846
847 if (cfg.ports[i].rx_to_tx_ring == NULL)
848 rte_exit(EXIT_FAILURE, "Ring create failed: %s\n",
849 rte_strerror(rte_errno));
850 }
851 }
852 /* >8 End of assigning ring structures for packet exchanging. */
853
854 /*
855 * Initializes a given port using global settings and with the RX buffers
856 * coming from the mbuf_pool passed as a parameter.
857 */
858 static inline void
port_init(uint16_t portid,struct rte_mempool * mbuf_pool,uint16_t nb_queues)859 port_init(uint16_t portid, struct rte_mempool *mbuf_pool, uint16_t nb_queues)
860 {
861 /* Configuring port to use RSS for multiple RX queues. 8< */
862 static const struct rte_eth_conf port_conf = {
863 .rxmode = {
864 .mq_mode = RTE_ETH_MQ_RX_RSS,
865 },
866 .rx_adv_conf = {
867 .rss_conf = {
868 .rss_key = NULL,
869 .rss_hf = RTE_ETH_RSS_PROTO_MASK,
870 }
871 }
872 };
873 /* >8 End of configuring port to use RSS for multiple RX queues. */
874
875 struct rte_eth_rxconf rxq_conf;
876 struct rte_eth_txconf txq_conf;
877 struct rte_eth_conf local_port_conf = port_conf;
878 struct rte_eth_dev_info dev_info;
879 int ret, i;
880
881 if (max_frame_size > local_port_conf.rxmode.mtu)
882 local_port_conf.rxmode.mtu = max_frame_size;
883
884 /* Skip ports that are not enabled */
885 if ((dma_enabled_port_mask & (1 << portid)) == 0) {
886 printf("Skipping disabled port %u\n", portid);
887 return;
888 }
889
890 /* Init port */
891 printf("Initializing port %u... ", portid);
892 fflush(stdout);
893 ret = rte_eth_dev_info_get(portid, &dev_info);
894 if (ret < 0)
895 rte_exit(EXIT_FAILURE, "Cannot get device info: %s, port=%u\n",
896 rte_strerror(-ret), portid);
897
898 local_port_conf.rx_adv_conf.rss_conf.rss_hf &=
899 dev_info.flow_type_rss_offloads;
900 ret = rte_eth_dev_configure(portid, nb_queues, 1, &local_port_conf);
901 if (ret < 0)
902 rte_exit(EXIT_FAILURE, "Cannot configure device:"
903 " err=%d, port=%u\n", ret, portid);
904
905 ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &nb_rxd,
906 &nb_txd);
907 if (ret < 0)
908 rte_exit(EXIT_FAILURE,
909 "Cannot adjust number of descriptors: err=%d, port=%u\n",
910 ret, portid);
911
912 rte_eth_macaddr_get(portid, &dma_ports_eth_addr[portid]);
913
914 /* Init RX queues */
915 rxq_conf = dev_info.default_rxconf;
916 rxq_conf.offloads = local_port_conf.rxmode.offloads;
917 for (i = 0; i < nb_queues; i++) {
918 ret = rte_eth_rx_queue_setup(portid, i, nb_rxd,
919 rte_eth_dev_socket_id(portid), &rxq_conf,
920 mbuf_pool);
921 if (ret < 0)
922 rte_exit(EXIT_FAILURE,
923 "rte_eth_rx_queue_setup:err=%d,port=%u, queue_id=%u\n",
924 ret, portid, i);
925 }
926
927 /* Init one TX queue on each port */
928 txq_conf = dev_info.default_txconf;
929 txq_conf.offloads = local_port_conf.txmode.offloads;
930 ret = rte_eth_tx_queue_setup(portid, 0, nb_txd,
931 rte_eth_dev_socket_id(portid),
932 &txq_conf);
933 if (ret < 0)
934 rte_exit(EXIT_FAILURE,
935 "rte_eth_tx_queue_setup:err=%d,port=%u\n",
936 ret, portid);
937
938 /* Initialize TX buffers */
939 tx_buffer[portid] = rte_zmalloc_socket("tx_buffer",
940 RTE_ETH_TX_BUFFER_SIZE(MAX_PKT_BURST), 0,
941 rte_eth_dev_socket_id(portid));
942 if (tx_buffer[portid] == NULL)
943 rte_exit(EXIT_FAILURE,
944 "Cannot allocate buffer for tx on port %u\n",
945 portid);
946
947 rte_eth_tx_buffer_init(tx_buffer[portid], MAX_PKT_BURST);
948
949 ret = rte_eth_tx_buffer_set_err_callback(tx_buffer[portid],
950 rte_eth_tx_buffer_count_callback,
951 &port_statistics.tx_dropped[portid]);
952 if (ret < 0)
953 rte_exit(EXIT_FAILURE,
954 "Cannot set error callback for tx buffer on port %u\n",
955 portid);
956
957 /* Start device. 8< */
958 ret = rte_eth_dev_start(portid);
959 if (ret < 0)
960 rte_exit(EXIT_FAILURE,
961 "rte_eth_dev_start:err=%d, port=%u\n",
962 ret, portid);
963 /* >8 End of starting device. */
964
965 /* RX port is set in promiscuous mode. 8< */
966 rte_eth_promiscuous_enable(portid);
967 /* >8 End of RX port is set in promiscuous mode. */
968
969 printf("Port %u, MAC address: " RTE_ETHER_ADDR_PRT_FMT "\n\n",
970 portid,
971 RTE_ETHER_ADDR_BYTES(&dma_ports_eth_addr[portid]));
972
973 cfg.ports[cfg.nb_ports].rxtx_port = portid;
974 cfg.ports[cfg.nb_ports++].nb_queues = nb_queues;
975 }
976
977 /* Get a device dump for each device being used by the application */
978 static void
dmadev_dump(void)979 dmadev_dump(void)
980 {
981 uint32_t i, j;
982
983 if (copy_mode != COPY_MODE_DMA_NUM)
984 return;
985
986 for (i = 0; i < cfg.nb_ports; i++)
987 for (j = 0; j < cfg.ports[i].nb_queues; j++)
988 rte_dma_dump(cfg.ports[i].dmadev_ids[j], stdout);
989 }
990
991 static void
signal_handler(int signum)992 signal_handler(int signum)
993 {
994 if (signum == SIGINT || signum == SIGTERM) {
995 printf("\n\nSignal %d received, preparing to exit...\n",
996 signum);
997 force_quit = true;
998 } else if (signum == SIGUSR1) {
999 dmadev_dump();
1000 }
1001 }
1002
1003 int
main(int argc,char ** argv)1004 main(int argc, char **argv)
1005 {
1006 int ret;
1007 uint16_t nb_ports, portid;
1008 uint32_t i;
1009 unsigned int nb_mbufs;
1010 size_t sz;
1011
1012 /* Init EAL. 8< */
1013 ret = rte_eal_init(argc, argv);
1014 if (ret < 0)
1015 rte_exit(EXIT_FAILURE, "Invalid EAL arguments\n");
1016 /* >8 End of init EAL. */
1017 argc -= ret;
1018 argv += ret;
1019
1020 force_quit = false;
1021 signal(SIGINT, signal_handler);
1022 signal(SIGTERM, signal_handler);
1023 signal(SIGUSR1, signal_handler);
1024
1025 nb_ports = rte_eth_dev_count_avail();
1026 if (nb_ports == 0)
1027 rte_exit(EXIT_FAILURE, "No Ethernet ports - bye\n");
1028
1029 /* Parse application arguments (after the EAL ones) */
1030 ret = dma_parse_args(argc, argv, nb_ports);
1031 if (ret < 0)
1032 rte_exit(EXIT_FAILURE, "Invalid DMA arguments\n");
1033
1034 /* Allocates mempool to hold the mbufs. 8< */
1035 nb_mbufs = RTE_MAX(nb_ports * (nb_queues * (nb_rxd + nb_txd +
1036 4 * MAX_PKT_BURST + ring_size) + ring_size +
1037 rte_lcore_count() * MEMPOOL_CACHE_SIZE),
1038 MIN_POOL_SIZE);
1039
1040 /* Create the mbuf pool */
1041 sz = max_frame_size + RTE_PKTMBUF_HEADROOM;
1042 sz = RTE_MAX(sz, (size_t)RTE_MBUF_DEFAULT_BUF_SIZE);
1043 dma_pktmbuf_pool = rte_pktmbuf_pool_create("mbuf_pool", nb_mbufs,
1044 MEMPOOL_CACHE_SIZE, 0, sz, rte_socket_id());
1045 if (dma_pktmbuf_pool == NULL)
1046 rte_exit(EXIT_FAILURE, "Cannot init mbuf pool\n");
1047 /* >8 End of allocates mempool to hold the mbufs. */
1048
1049 /* Initialize each port. 8< */
1050 cfg.nb_ports = 0;
1051 RTE_ETH_FOREACH_DEV(portid)
1052 port_init(portid, dma_pktmbuf_pool, nb_queues);
1053 /* >8 End of initializing each port. */
1054
1055 /* Initialize port xstats */
1056 memset(&port_statistics, 0, sizeof(port_statistics));
1057
1058 /* Assigning each port resources. 8< */
1059 while (!check_link_status(dma_enabled_port_mask) && !force_quit)
1060 sleep(1);
1061
1062 /* Check if there is enough lcores for all ports. */
1063 cfg.nb_lcores = rte_lcore_count() - 1;
1064 if (cfg.nb_lcores < 1)
1065 rte_exit(EXIT_FAILURE,
1066 "There should be at least one worker lcore.\n");
1067
1068 if (copy_mode == COPY_MODE_DMA_NUM)
1069 assign_dmadevs();
1070
1071 assign_rings();
1072 /* >8 End of assigning each port resources. */
1073
1074 start_forwarding_cores();
1075 /* main core prints stats while other cores forward */
1076 print_stats(argv[0]);
1077
1078 /* force_quit is true when we get here */
1079 rte_eal_mp_wait_lcore();
1080
1081 uint32_t j;
1082 for (i = 0; i < cfg.nb_ports; i++) {
1083 printf("Closing port %d\n", cfg.ports[i].rxtx_port);
1084 ret = rte_eth_dev_stop(cfg.ports[i].rxtx_port);
1085 if (ret != 0)
1086 RTE_LOG(ERR, DMA, "rte_eth_dev_stop: err=%s, port=%u\n",
1087 rte_strerror(-ret), cfg.ports[i].rxtx_port);
1088
1089 rte_eth_dev_close(cfg.ports[i].rxtx_port);
1090 if (copy_mode == COPY_MODE_DMA_NUM) {
1091 for (j = 0; j < cfg.ports[i].nb_queues; j++) {
1092 printf("Stopping dmadev %d\n",
1093 cfg.ports[i].dmadev_ids[j]);
1094 rte_dma_stop(cfg.ports[i].dmadev_ids[j]);
1095 }
1096 } else /* copy_mode == COPY_MODE_SW_NUM */
1097 rte_ring_free(cfg.ports[i].rx_to_tx_ring);
1098 }
1099
1100 /* clean up the EAL */
1101 rte_eal_cleanup();
1102
1103 printf("Bye...\n");
1104 return 0;
1105 }
1106