1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #ifndef _TXGBE_ETHDEV_H_ 6 #define _TXGBE_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include "base/txgbe.h" 11 #include "txgbe_ptypes.h" 12 #ifdef RTE_LIB_SECURITY 13 #include "txgbe_ipsec.h" 14 #endif 15 #include <rte_flow.h> 16 #include <rte_flow_driver.h> 17 #include <rte_time.h> 18 #include <rte_ethdev.h> 19 #include <rte_ethdev_core.h> 20 #include <rte_hash.h> 21 #include <rte_hash_crc.h> 22 #include <rte_bus_pci.h> 23 #include <rte_tm_driver.h> 24 25 /* need update link, bit flag */ 26 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) 27 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1) 28 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2) 29 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3) 30 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4) 31 #define TXGBE_FLAG_NEED_AN_CONFIG (uint32_t)(1 << 5) 32 33 /* 34 * Defines that were not part of txgbe_type.h as they are not used by the 35 * FreeBSD driver. 36 */ 37 #define TXGBE_VFTA_SIZE 128 38 #define TXGBE_VLAN_TAG_SIZE 4 39 #define TXGBE_HKEY_MAX_INDEX 10 40 /*Default value of Max Rx Queue*/ 41 #define TXGBE_MAX_RX_QUEUE_NUM 128 42 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM 43 44 #ifndef NBBY 45 #define NBBY 8 /* number of bits in a byte */ 46 #endif 47 #define TXGBE_HWSTRIP_BITMAP_SIZE \ 48 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY)) 49 50 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */ 51 52 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8 53 54 #define TXGBE_5TUPLE_MAX_PRI 7 55 #define TXGBE_5TUPLE_MIN_PRI 1 56 57 #define TXGBE_RSS_OFFLOAD_ALL ( \ 58 ETH_RSS_IPV4 | \ 59 ETH_RSS_NONFRAG_IPV4_TCP | \ 60 ETH_RSS_NONFRAG_IPV4_UDP | \ 61 ETH_RSS_IPV6 | \ 62 ETH_RSS_NONFRAG_IPV6_TCP | \ 63 ETH_RSS_NONFRAG_IPV6_UDP | \ 64 ETH_RSS_IPV6_EX | \ 65 ETH_RSS_IPV6_TCP_EX | \ 66 ETH_RSS_IPV6_UDP_EX) 67 68 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 69 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 70 71 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32) 72 #define TXGBE_MAX_L2_TN_FILTER_NUM 128 73 74 /* 75 * Information about the fdir mode. 76 */ 77 struct txgbe_hw_fdir_mask { 78 uint16_t vlan_tci_mask; 79 uint32_t src_ipv4_mask; 80 uint32_t dst_ipv4_mask; 81 uint16_t src_ipv6_mask; 82 uint16_t dst_ipv6_mask; 83 uint16_t src_port_mask; 84 uint16_t dst_port_mask; 85 uint16_t flex_bytes_mask; 86 uint8_t mac_addr_byte_mask; 87 uint32_t tunnel_id_mask; 88 uint8_t tunnel_type_mask; 89 }; 90 91 struct txgbe_fdir_filter { 92 TAILQ_ENTRY(txgbe_fdir_filter) entries; 93 struct txgbe_atr_input input; /* key of fdir filter*/ 94 uint32_t fdirflags; /* drop or forward */ 95 uint32_t fdirhash; /* hash value for fdir */ 96 uint8_t queue; /* assigned rx queue */ 97 }; 98 99 /* list of fdir filters */ 100 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter); 101 102 struct txgbe_fdir_rule { 103 struct txgbe_hw_fdir_mask mask; 104 struct txgbe_atr_input input; /* key of fdir filter */ 105 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */ 106 bool b_mask; /* If TRUE, mask has meaning. */ 107 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */ 108 uint32_t fdirflags; /* drop or forward */ 109 uint32_t soft_id; /* an unique value for this rule */ 110 uint8_t queue; /* assigned rx queue */ 111 uint8_t flex_bytes_offset; 112 }; 113 114 struct txgbe_hw_fdir_info { 115 struct txgbe_hw_fdir_mask mask; 116 uint8_t flex_bytes_offset; 117 uint16_t collision; 118 uint16_t free; 119 uint16_t maxhash; 120 uint8_t maxlen; 121 uint64_t add; 122 uint64_t remove; 123 uint64_t f_add; 124 uint64_t f_remove; 125 struct txgbe_fdir_filter_list fdir_list; /* filter list*/ 126 /* store the pointers of the filters, index is the hash value. */ 127 struct txgbe_fdir_filter **hash_map; 128 struct rte_hash *hash_handle; /* cuckoo hash handler */ 129 bool mask_added; /* If already got mask from consistent filter */ 130 }; 131 132 struct txgbe_rte_flow_rss_conf { 133 struct rte_flow_action_rss conf; /**< RSS parameters. */ 134 uint8_t key[TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */ 135 uint16_t queue[TXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */ 136 }; 137 138 /* structure for interrupt relative data */ 139 struct txgbe_interrupt { 140 uint32_t flags; 141 uint32_t mask_misc; 142 uint32_t mask_misc_orig; /* save mask during delayed handler */ 143 uint64_t mask; 144 uint64_t mask_orig; /* save mask during delayed handler */ 145 }; 146 147 #define TXGBE_NB_STAT_MAPPING 32 148 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 149 #define NB_QMAP_FIELDS_PER_QSM_REG 4 150 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 151 struct txgbe_stat_mappings { 152 uint32_t tqsm[TXGBE_NB_STAT_MAPPING]; 153 uint32_t rqsm[TXGBE_NB_STAT_MAPPING]; 154 }; 155 156 struct txgbe_vfta { 157 uint32_t vfta[TXGBE_VFTA_SIZE]; 158 }; 159 160 struct txgbe_hwstrip { 161 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE]; 162 }; 163 164 /* 165 * VF data which used by PF host only 166 */ 167 #define TXGBE_MAX_VF_MC_ENTRIES 30 168 169 struct txgbe_uta_info { 170 uint8_t uc_filter_type; 171 uint16_t uta_in_use; 172 uint32_t uta_shadow[TXGBE_MAX_UTA]; 173 }; 174 175 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */ 176 177 struct txgbe_mirror_info { 178 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES]; 179 /* store PF mirror rules configuration */ 180 }; 181 182 struct txgbe_vf_info { 183 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN]; 184 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES]; 185 uint16_t num_vf_mc_hashes; 186 bool clear_to_send; 187 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF]; 188 uint16_t vlan_count; 189 uint8_t api_version; 190 uint16_t switch_domain_id; 191 uint16_t xcast_mode; 192 uint16_t mac_count; 193 }; 194 195 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter); 196 197 struct txgbe_5tuple_filter_info { 198 uint32_t dst_ip; 199 uint32_t src_ip; 200 uint16_t dst_port; 201 uint16_t src_port; 202 enum txgbe_5tuple_protocol proto; /* l4 protocol. */ 203 uint8_t priority; /* seven levels (001b-111b), 111b is highest, 204 * used when more than one filter matches. 205 */ 206 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ 207 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ 208 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ 209 src_port_mask:1, /* if mask is 1b, do not compare src port. */ 210 proto_mask:1; /* if mask is 1b, do not compare protocol. */ 211 }; 212 213 /* 5tuple filter structure */ 214 struct txgbe_5tuple_filter { 215 TAILQ_ENTRY(txgbe_5tuple_filter) entries; 216 uint16_t index; /* the index of 5tuple filter */ 217 struct txgbe_5tuple_filter_info filter_info; 218 uint16_t queue; /* rx queue assigned to */ 219 }; 220 221 #define TXGBE_5TUPLE_ARRAY_SIZE \ 222 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \ 223 (sizeof(uint32_t) * NBBY)) 224 225 struct txgbe_ethertype_filter { 226 uint16_t ethertype; 227 uint32_t etqf; 228 uint32_t etqs; 229 /** 230 * If this filter is added by configuration, 231 * it should not be removed. 232 */ 233 bool conf; 234 }; 235 236 /* 237 * Structure to store filters' info. 238 */ 239 struct txgbe_filter_info { 240 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */ 241 /* store used ethertype filters*/ 242 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX]; 243 /* Bit mask for every used 5tuple filter */ 244 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE]; 245 struct txgbe_5tuple_filter_list fivetuple_list; 246 /* store the SYN filter info */ 247 uint32_t syn_info; 248 /* store the rss filter info */ 249 struct txgbe_rte_flow_rss_conf rss_info; 250 }; 251 252 struct txgbe_l2_tn_key { 253 enum rte_eth_tunnel_type l2_tn_type; 254 uint32_t tn_id; 255 }; 256 257 struct txgbe_l2_tn_filter { 258 TAILQ_ENTRY(txgbe_l2_tn_filter) entries; 259 struct txgbe_l2_tn_key key; 260 uint32_t pool; 261 }; 262 263 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter); 264 265 struct txgbe_l2_tn_info { 266 struct txgbe_l2_tn_filter_list l2_tn_list; 267 struct txgbe_l2_tn_filter **hash_map; 268 struct rte_hash *hash_handle; 269 bool e_tag_en; /* e-tag enabled */ 270 bool e_tag_fwd_en; /* e-tag based forwarding enabled */ 271 uint16_t e_tag_ether_type; /* ether type for e-tag */ 272 }; 273 274 struct rte_flow { 275 enum rte_filter_type filter_type; 276 void *rule; 277 }; 278 279 /* The configuration of bandwidth */ 280 struct txgbe_bw_conf { 281 uint8_t tc_num; /* Number of TCs. */ 282 }; 283 284 /* Struct to store Traffic Manager shaper profile. */ 285 struct txgbe_tm_shaper_profile { 286 TAILQ_ENTRY(txgbe_tm_shaper_profile) node; 287 uint32_t shaper_profile_id; 288 uint32_t reference_count; 289 struct rte_tm_shaper_params profile; 290 }; 291 292 TAILQ_HEAD(txgbe_shaper_profile_list, txgbe_tm_shaper_profile); 293 294 /* node type of Traffic Manager */ 295 enum txgbe_tm_node_type { 296 TXGBE_TM_NODE_TYPE_PORT, 297 TXGBE_TM_NODE_TYPE_TC, 298 TXGBE_TM_NODE_TYPE_QUEUE, 299 TXGBE_TM_NODE_TYPE_MAX, 300 }; 301 302 /* Struct to store Traffic Manager node configuration. */ 303 struct txgbe_tm_node { 304 TAILQ_ENTRY(txgbe_tm_node) node; 305 uint32_t id; 306 uint32_t priority; 307 uint32_t weight; 308 uint32_t reference_count; 309 uint16_t no; 310 struct txgbe_tm_node *parent; 311 struct txgbe_tm_shaper_profile *shaper_profile; 312 struct rte_tm_node_params params; 313 }; 314 315 TAILQ_HEAD(txgbe_tm_node_list, txgbe_tm_node); 316 317 /* The configuration of Traffic Manager */ 318 struct txgbe_tm_conf { 319 struct txgbe_shaper_profile_list shaper_profile_list; 320 struct txgbe_tm_node *root; /* root node - port */ 321 struct txgbe_tm_node_list tc_list; /* node list for all the TCs */ 322 struct txgbe_tm_node_list queue_list; /* node list for all the queues */ 323 /** 324 * The number of added TC nodes. 325 * It should be no more than the TC number of this port. 326 */ 327 uint32_t nb_tc_node; 328 /** 329 * The number of added queue nodes. 330 * It should be no more than the queue number of this port. 331 */ 332 uint32_t nb_queue_node; 333 /** 334 * This flag is used to check if APP can change the TM node 335 * configuration. 336 * When it's true, means the configuration is applied to HW, 337 * APP should not change the configuration. 338 * As we don't support on-the-fly configuration, when starting 339 * the port, APP should call the hierarchy_commit API to set this 340 * flag to true. When stopping the port, this flag should be set 341 * to false. 342 */ 343 bool committed; 344 }; 345 346 /* 347 * Structure to store private data for each driver instance (for each port). 348 */ 349 struct txgbe_adapter { 350 struct txgbe_hw hw; 351 struct txgbe_hw_stats stats; 352 struct txgbe_hw_fdir_info fdir; 353 struct txgbe_interrupt intr; 354 struct txgbe_stat_mappings stat_mappings; 355 struct txgbe_vfta shadow_vfta; 356 struct txgbe_hwstrip hwstrip; 357 struct txgbe_dcb_config dcb_config; 358 struct txgbe_mirror_info mr_data; 359 struct txgbe_vf_info *vfdata; 360 struct txgbe_uta_info uta_info; 361 struct txgbe_filter_info filter; 362 struct txgbe_l2_tn_info l2_tn; 363 struct txgbe_bw_conf bw_conf; 364 #ifdef RTE_LIB_SECURITY 365 struct txgbe_ipsec ipsec; 366 #endif 367 bool rx_bulk_alloc_allowed; 368 struct rte_timecounter systime_tc; 369 struct rte_timecounter rx_tstamp_tc; 370 struct rte_timecounter tx_tstamp_tc; 371 struct txgbe_tm_conf tm_conf; 372 373 /* For RSS reta table update */ 374 uint8_t rss_reta_updated; 375 }; 376 377 #define TXGBE_DEV_ADAPTER(dev) \ 378 ((struct txgbe_adapter *)(dev)->data->dev_private) 379 380 #define TXGBE_DEV_HW(dev) \ 381 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw) 382 383 #define TXGBE_DEV_STATS(dev) \ 384 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats) 385 386 #define TXGBE_DEV_INTR(dev) \ 387 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr) 388 389 #define TXGBE_DEV_FDIR(dev) \ 390 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir) 391 392 #define TXGBE_DEV_STAT_MAPPINGS(dev) \ 393 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings) 394 395 #define TXGBE_DEV_VFTA(dev) \ 396 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta) 397 398 #define TXGBE_DEV_HWSTRIP(dev) \ 399 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip) 400 401 #define TXGBE_DEV_DCB_CONFIG(dev) \ 402 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config) 403 404 #define TXGBE_DEV_VFDATA(dev) \ 405 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata) 406 407 #define TXGBE_DEV_MR_INFO(dev) \ 408 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data) 409 410 #define TXGBE_DEV_UTA_INFO(dev) \ 411 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info) 412 413 #define TXGBE_DEV_FILTER(dev) \ 414 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter) 415 416 #define TXGBE_DEV_L2_TN(dev) \ 417 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn) 418 419 #define TXGBE_DEV_BW_CONF(dev) \ 420 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf) 421 422 #define TXGBE_DEV_TM_CONF(dev) \ 423 (&((struct txgbe_adapter *)(dev)->data->dev_private)->tm_conf) 424 425 #define TXGBE_DEV_IPSEC(dev) \ 426 (&((struct txgbe_adapter *)(dev)->data->dev_private)->ipsec) 427 428 /* 429 * RX/TX function prototypes 430 */ 431 void txgbe_dev_clear_queues(struct rte_eth_dev *dev); 432 433 void txgbe_dev_free_queues(struct rte_eth_dev *dev); 434 435 void txgbe_dev_rx_queue_release(void *rxq); 436 437 void txgbe_dev_tx_queue_release(void *txq); 438 439 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 440 uint16_t nb_rx_desc, unsigned int socket_id, 441 const struct rte_eth_rxconf *rx_conf, 442 struct rte_mempool *mb_pool); 443 444 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 445 uint16_t nb_tx_desc, unsigned int socket_id, 446 const struct rte_eth_txconf *tx_conf); 447 448 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev, 449 uint16_t rx_queue_id); 450 451 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); 452 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); 453 454 int txgbe_dev_rx_init(struct rte_eth_dev *dev); 455 456 void txgbe_dev_tx_init(struct rte_eth_dev *dev); 457 458 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev); 459 460 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id); 461 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id); 462 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id); 463 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id); 464 465 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 466 467 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 468 469 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 470 471 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 472 473 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 474 struct rte_eth_rxq_info *qinfo); 475 476 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 477 struct rte_eth_txq_info *qinfo); 478 479 int txgbevf_dev_rx_init(struct rte_eth_dev *dev); 480 481 void txgbevf_dev_tx_init(struct rte_eth_dev *dev); 482 483 void txgbevf_dev_rxtx_start(struct rte_eth_dev *dev); 484 485 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 486 uint16_t nb_pkts); 487 488 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts, 489 uint16_t nb_pkts); 490 491 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue, 492 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 493 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, 494 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 495 496 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 497 uint16_t nb_pkts); 498 499 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts, 500 uint16_t nb_pkts); 501 502 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 503 uint16_t nb_pkts); 504 505 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 506 struct rte_eth_rss_conf *rss_conf); 507 508 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 509 struct rte_eth_rss_conf *rss_conf); 510 511 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type); 512 513 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 514 struct rte_eth_ntuple_filter *filter, 515 bool add); 516 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 517 struct rte_eth_ethertype_filter *filter, 518 bool add); 519 int txgbe_syn_filter_set(struct rte_eth_dev *dev, 520 struct rte_eth_syn_filter *filter, 521 bool add); 522 523 /** 524 * l2 tunnel configuration. 525 */ 526 struct txgbe_l2_tunnel_conf { 527 enum rte_eth_tunnel_type l2_tunnel_type; 528 uint16_t ether_type; /* ether type in l2 header */ 529 uint32_t tunnel_id; /* port tag id for e-tag */ 530 uint16_t vf_id; /* VF id for tag insertion */ 531 uint32_t pool; /* destination pool for tag based forwarding */ 532 }; 533 534 int 535 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 536 struct txgbe_l2_tunnel_conf *l2_tunnel, 537 bool restore); 538 int 539 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 540 struct txgbe_l2_tunnel_conf *l2_tunnel); 541 void txgbe_filterlist_init(void); 542 void txgbe_filterlist_flush(void); 543 544 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction, 545 uint8_t queue, uint8_t msix_vector); 546 547 /* 548 * Flow director function prototypes 549 */ 550 int txgbe_fdir_configure(struct rte_eth_dev *dev); 551 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev); 552 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev, 553 uint16_t offset); 554 int txgbe_fdir_filter_program(struct rte_eth_dev *dev, 555 struct txgbe_fdir_rule *rule, 556 bool del, bool update); 557 558 void txgbe_configure_pb(struct rte_eth_dev *dev); 559 void txgbe_configure_port(struct rte_eth_dev *dev); 560 void txgbe_configure_dcb(struct rte_eth_dev *dev); 561 562 int 563 txgbe_dev_link_update_share(struct rte_eth_dev *dev, 564 int wait_to_complete); 565 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev); 566 567 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev); 568 569 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev); 570 571 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev); 572 573 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val); 574 575 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev); 576 int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev); 577 578 extern const struct rte_flow_ops txgbe_flow_ops; 579 580 void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev); 581 void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev); 582 void txgbe_clear_syn_filter(struct rte_eth_dev *dev); 583 int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev); 584 585 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 586 uint16_t tx_rate, uint64_t q_msk); 587 int txgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops); 588 void txgbe_tm_conf_init(struct rte_eth_dev *dev); 589 void txgbe_tm_conf_uninit(struct rte_eth_dev *dev); 590 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx, 591 uint16_t tx_rate); 592 int txgbe_rss_conf_init(struct txgbe_rte_flow_rss_conf *out, 593 const struct rte_flow_action_rss *in); 594 int txgbe_action_rss_same(const struct rte_flow_action_rss *comp, 595 const struct rte_flow_action_rss *with); 596 int txgbe_config_rss_filter(struct rte_eth_dev *dev, 597 struct txgbe_rte_flow_rss_conf *conf, bool add); 598 599 static inline int 600 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info, 601 uint16_t ethertype) 602 { 603 int i; 604 605 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 606 if (filter_info->ethertype_filters[i].ethertype == ethertype && 607 (filter_info->ethertype_mask & (1 << i))) 608 return i; 609 } 610 return -1; 611 } 612 613 static inline int 614 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info, 615 struct txgbe_ethertype_filter *ethertype_filter) 616 { 617 int i; 618 619 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 620 if (filter_info->ethertype_mask & (1 << i)) 621 continue; 622 623 filter_info->ethertype_mask |= 1 << i; 624 filter_info->ethertype_filters[i].ethertype = 625 ethertype_filter->ethertype; 626 filter_info->ethertype_filters[i].etqf = 627 ethertype_filter->etqf; 628 filter_info->ethertype_filters[i].etqs = 629 ethertype_filter->etqs; 630 filter_info->ethertype_filters[i].conf = 631 ethertype_filter->conf; 632 break; 633 } 634 return (i < TXGBE_ETF_ID_MAX ? i : -1); 635 } 636 637 static inline int 638 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info, 639 uint8_t idx) 640 { 641 if (idx >= TXGBE_ETF_ID_MAX) 642 return -1; 643 filter_info->ethertype_mask &= ~(1 << idx); 644 filter_info->ethertype_filters[idx].ethertype = 0; 645 filter_info->ethertype_filters[idx].etqf = 0; 646 filter_info->ethertype_filters[idx].etqs = 0; 647 filter_info->ethertype_filters[idx].etqs = FALSE; 648 return idx; 649 } 650 651 #ifdef RTE_LIB_SECURITY 652 int txgbe_ipsec_ctx_create(struct rte_eth_dev *dev); 653 #endif 654 655 /* High threshold controlling when to start sending XOFF frames. */ 656 #define TXGBE_FC_XOFF_HITH 128 /*KB*/ 657 /* Low threshold controlling when to start sending XON frames. */ 658 #define TXGBE_FC_XON_LOTH 64 /*KB*/ 659 660 /* Timer value included in XOFF frames. */ 661 #define TXGBE_FC_PAUSE_TIME 0x680 662 663 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 664 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 665 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 666 667 /* 668 * Default values for RX/TX configuration 669 */ 670 #define TXGBE_DEFAULT_RX_FREE_THRESH 32 671 #define TXGBE_DEFAULT_RX_PTHRESH 8 672 #define TXGBE_DEFAULT_RX_HTHRESH 8 673 #define TXGBE_DEFAULT_RX_WTHRESH 0 674 675 #define TXGBE_DEFAULT_TX_FREE_THRESH 32 676 #define TXGBE_DEFAULT_TX_PTHRESH 32 677 #define TXGBE_DEFAULT_TX_HTHRESH 0 678 #define TXGBE_DEFAULT_TX_WTHRESH 0 679 680 /* Additional timesync values. */ 681 #define NSEC_PER_SEC 1000000000L 682 #define TXGBE_INCVAL_10GB 0xCCCCCC 683 #define TXGBE_INCVAL_1GB 0x800000 684 #define TXGBE_INCVAL_100 0xA00000 685 #define TXGBE_INCVAL_10 0xC7F380 686 #define TXGBE_INCVAL_FPGA 0x800000 687 #define TXGBE_INCVAL_SHIFT_10GB 20 688 #define TXGBE_INCVAL_SHIFT_1GB 18 689 #define TXGBE_INCVAL_SHIFT_100 15 690 #define TXGBE_INCVAL_SHIFT_10 12 691 #define TXGBE_INCVAL_SHIFT_FPGA 17 692 693 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 694 695 /* store statistics names and its offset in stats structure */ 696 struct rte_txgbe_xstats_name_off { 697 char name[RTE_ETH_XSTATS_NAME_SIZE]; 698 unsigned int offset; 699 }; 700 701 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 702 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 703 struct rte_ether_addr *mc_addr_set, 704 uint32_t nb_mc_addr); 705 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 706 struct rte_eth_rss_reta_entry64 *reta_conf, 707 uint16_t reta_size); 708 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 709 struct rte_eth_rss_reta_entry64 *reta_conf, 710 uint16_t reta_size); 711 void txgbe_dev_setup_link_alarm_handler(void *param); 712 void txgbe_read_stats_registers(struct txgbe_hw *hw, 713 struct txgbe_hw_stats *hw_stats); 714 715 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev); 716 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev); 717 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev); 718 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 719 uint16_t queue, bool on); 720 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 721 int mask); 722 723 #endif /* _TXGBE_ETHDEV_H_ */ 724