1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #include "txgbe_hw.h" 6 #include "txgbe_eeprom.h" 7 #include "txgbe_mng.h" 8 #include "txgbe_phy.h" 9 10 static void txgbe_i2c_start(struct txgbe_hw *hw); 11 static void txgbe_i2c_stop(struct txgbe_hw *hw); 12 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw); 13 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability, 14 u32 link_partner, struct txgbe_hw *hw); 15 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability, 16 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw); 17 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw); 18 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw); 19 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode); 20 static s32 txgbe_check_kr_training(struct txgbe_hw *hw); 21 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw, 22 s32 post, s32 mode); 23 static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed); 24 25 /** 26 * txgbe_identify_extphy - Identify a single address for a PHY 27 * @hw: pointer to hardware structure 28 * @phy_addr: PHY address to probe 29 * 30 * Returns true if PHY found 31 */ 32 static bool txgbe_identify_extphy(struct txgbe_hw *hw) 33 { 34 u16 phy_addr = 0; 35 36 if (!txgbe_validate_phy_addr(hw, phy_addr)) { 37 DEBUGOUT("Unable to validate PHY address 0x%04X\n", 38 phy_addr); 39 return false; 40 } 41 42 if (txgbe_get_phy_id(hw)) 43 return false; 44 45 hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id); 46 if (hw->phy.type == txgbe_phy_unknown) { 47 u16 ext_ability = 0; 48 hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY, 49 TXGBE_MD_DEV_PMA_PMD, 50 &ext_ability); 51 52 if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY | 53 TXGBE_MD_PHY_1000BASET_ABILITY)) 54 hw->phy.type = txgbe_phy_cu_unknown; 55 else 56 hw->phy.type = txgbe_phy_generic; 57 } 58 59 return true; 60 } 61 62 /** 63 * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register 64 * @hw: pointer to hardware structure 65 * 66 * Read TXGBE_ETHPHYIF register and save field values, 67 * and check for valid field values. 68 **/ 69 static s32 txgbe_read_phy_if(struct txgbe_hw *hw) 70 { 71 hw->phy.media_type = hw->phy.get_media_type(hw); 72 73 /* Save NW management interface connected on board. This is used 74 * to determine internal PHY mode. 75 */ 76 hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF); 77 78 /* If MDIO is connected to external PHY, then set PHY address. */ 79 if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT) 80 hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel); 81 82 if (!hw->phy.phy_semaphore_mask) { 83 if (hw->bus.lan_id) 84 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY; 85 else 86 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY; 87 } 88 89 return 0; 90 } 91 92 /** 93 * txgbe_identify_phy - Get physical layer module 94 * @hw: pointer to hardware structure 95 * 96 * Determines the physical layer module found on the current adapter. 97 **/ 98 s32 txgbe_identify_phy(struct txgbe_hw *hw) 99 { 100 s32 err = TXGBE_ERR_PHY_ADDR_INVALID; 101 102 DEBUGFUNC("txgbe_identify_phy"); 103 104 txgbe_read_phy_if(hw); 105 106 if (hw->phy.type != txgbe_phy_unknown) 107 return 0; 108 109 /* Raptor 10GBASE-T requires an external PHY */ 110 if (hw->phy.media_type == txgbe_media_type_copper) { 111 err = txgbe_identify_extphy(hw); 112 } else if (hw->phy.media_type == txgbe_media_type_fiber) { 113 err = txgbe_identify_module(hw); 114 } else { 115 hw->phy.type = txgbe_phy_none; 116 return 0; 117 } 118 119 /* Return error if SFP module has been detected but is not supported */ 120 if (hw->phy.type == txgbe_phy_sfp_unsupported) 121 return TXGBE_ERR_SFP_NOT_SUPPORTED; 122 123 return err; 124 } 125 126 /** 127 * txgbe_check_reset_blocked - check status of MNG FW veto bit 128 * @hw: pointer to the hardware structure 129 * 130 * This function checks the STAT.MNGVETO bit to see if there are 131 * any constraints on link from manageability. For MAC's that don't 132 * have this bit just return faluse since the link can not be blocked 133 * via this method. 134 **/ 135 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw) 136 { 137 u32 mmngc; 138 139 DEBUGFUNC("txgbe_check_reset_blocked"); 140 141 mmngc = rd32(hw, TXGBE_STAT); 142 if (mmngc & TXGBE_STAT_MNGVETO) { 143 DEBUGOUT("MNG_VETO bit detected.\n"); 144 return true; 145 } 146 147 return false; 148 } 149 150 /** 151 * txgbe_validate_phy_addr - Determines phy address is valid 152 * @hw: pointer to hardware structure 153 * @phy_addr: PHY address 154 * 155 **/ 156 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr) 157 { 158 u16 phy_id = 0; 159 bool valid = false; 160 161 DEBUGFUNC("txgbe_validate_phy_addr"); 162 163 hw->phy.addr = phy_addr; 164 hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH, 165 TXGBE_MD_DEV_PMA_PMD, &phy_id); 166 167 if (phy_id != 0xFFFF && phy_id != 0x0) 168 valid = true; 169 170 DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id); 171 172 return valid; 173 } 174 175 /** 176 * txgbe_get_phy_id - Get the phy type 177 * @hw: pointer to hardware structure 178 * 179 **/ 180 s32 txgbe_get_phy_id(struct txgbe_hw *hw) 181 { 182 u32 err; 183 u16 phy_id_high = 0; 184 u16 phy_id_low = 0; 185 186 DEBUGFUNC("txgbe_get_phy_id"); 187 188 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH, 189 TXGBE_MD_DEV_PMA_PMD, 190 &phy_id_high); 191 192 if (err == 0) { 193 hw->phy.id = (u32)(phy_id_high << 16); 194 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW, 195 TXGBE_MD_DEV_PMA_PMD, 196 &phy_id_low); 197 hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK); 198 hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK); 199 } 200 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 201 phy_id_high, phy_id_low); 202 203 return err; 204 } 205 206 /** 207 * txgbe_get_phy_type_from_id - Get the phy type 208 * @phy_id: PHY ID information 209 * 210 **/ 211 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id) 212 { 213 enum txgbe_phy_type phy_type; 214 215 DEBUGFUNC("txgbe_get_phy_type_from_id"); 216 217 switch (phy_id) { 218 case TXGBE_PHYID_TN1010: 219 phy_type = txgbe_phy_tn; 220 break; 221 case TXGBE_PHYID_QT2022: 222 phy_type = txgbe_phy_qt; 223 break; 224 case TXGBE_PHYID_ATH: 225 phy_type = txgbe_phy_nl; 226 break; 227 case TXGBE_PHYID_MTD3310: 228 phy_type = txgbe_phy_cu_mtd; 229 break; 230 default: 231 phy_type = txgbe_phy_unknown; 232 break; 233 } 234 235 return phy_type; 236 } 237 238 static s32 239 txgbe_reset_extphy(struct txgbe_hw *hw) 240 { 241 u16 ctrl = 0; 242 int err, i; 243 244 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL, 245 TXGBE_MD_DEV_GENERAL, &ctrl); 246 if (err != 0) 247 return err; 248 ctrl |= TXGBE_MD_PORT_CTRL_RESET; 249 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL, 250 TXGBE_MD_DEV_GENERAL, ctrl); 251 if (err != 0) 252 return err; 253 254 /* 255 * Poll for reset bit to self-clear indicating reset is complete. 256 * Some PHYs could take up to 3 seconds to complete and need about 257 * 1.7 usec delay after the reset is complete. 258 */ 259 for (i = 0; i < 30; i++) { 260 msec_delay(100); 261 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL, 262 TXGBE_MD_DEV_GENERAL, &ctrl); 263 if (err != 0) 264 return err; 265 266 if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) { 267 usec_delay(2); 268 break; 269 } 270 } 271 272 if (ctrl & TXGBE_MD_PORT_CTRL_RESET) { 273 err = TXGBE_ERR_RESET_FAILED; 274 DEBUGOUT("PHY reset polling failed to complete.\n"); 275 } 276 277 return err; 278 } 279 280 /** 281 * txgbe_reset_phy - Performs a PHY reset 282 * @hw: pointer to hardware structure 283 **/ 284 s32 txgbe_reset_phy(struct txgbe_hw *hw) 285 { 286 s32 err = 0; 287 288 DEBUGFUNC("txgbe_reset_phy"); 289 290 if (hw->phy.type == txgbe_phy_unknown) 291 err = txgbe_identify_phy(hw); 292 293 if (err != 0 || hw->phy.type == txgbe_phy_none) 294 return err; 295 296 /* Don't reset PHY if it's shut down due to overtemp. */ 297 if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP) 298 return err; 299 300 /* Blocked by MNG FW so bail */ 301 if (txgbe_check_reset_blocked(hw)) 302 return err; 303 304 switch (hw->phy.type) { 305 case txgbe_phy_cu_mtd: 306 err = txgbe_reset_extphy(hw); 307 break; 308 default: 309 break; 310 } 311 312 return err; 313 } 314 315 /** 316 * txgbe_read_phy_mdi - Reads a value from a specified PHY register without 317 * the SWFW lock 318 * @hw: pointer to hardware structure 319 * @reg_addr: 32 bit address of PHY register to read 320 * @device_type: 5 bit device type 321 * @phy_data: Pointer to read data from PHY register 322 **/ 323 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type, 324 u16 *phy_data) 325 { 326 u32 command, data; 327 328 /* Setup and write the address cycle command */ 329 command = TXGBE_MDIOSCA_REG(reg_addr) | 330 TXGBE_MDIOSCA_DEV(device_type) | 331 TXGBE_MDIOSCA_PORT(hw->phy.addr); 332 wr32(hw, TXGBE_MDIOSCA, command); 333 334 command = TXGBE_MDIOSCD_CMD_READ | 335 TXGBE_MDIOSCD_BUSY; 336 wr32(hw, TXGBE_MDIOSCD, command); 337 338 /* 339 * Check every 10 usec to see if the address cycle completed. 340 * The MDI Command bit will clear when the operation is 341 * complete 342 */ 343 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY, 344 0, NULL, 100, 100)) { 345 DEBUGOUT("PHY address command did not complete\n"); 346 return TXGBE_ERR_PHY; 347 } 348 349 data = rd32(hw, TXGBE_MDIOSCD); 350 *phy_data = (u16)TXGBD_MDIOSCD_DAT(data); 351 352 return 0; 353 } 354 355 /** 356 * txgbe_read_phy_reg - Reads a value from a specified PHY register 357 * using the SWFW lock - this function is needed in most cases 358 * @hw: pointer to hardware structure 359 * @reg_addr: 32 bit address of PHY register to read 360 * @device_type: 5 bit device type 361 * @phy_data: Pointer to read data from PHY register 362 **/ 363 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr, 364 u32 device_type, u16 *phy_data) 365 { 366 s32 err; 367 u32 gssr = hw->phy.phy_semaphore_mask; 368 369 DEBUGFUNC("txgbe_read_phy_reg"); 370 371 if (hw->mac.acquire_swfw_sync(hw, gssr)) 372 return TXGBE_ERR_SWFW_SYNC; 373 374 err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data); 375 376 hw->mac.release_swfw_sync(hw, gssr); 377 378 return err; 379 } 380 381 /** 382 * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register 383 * without SWFW lock 384 * @hw: pointer to hardware structure 385 * @reg_addr: 32 bit PHY register to write 386 * @device_type: 5 bit device type 387 * @phy_data: Data to write to the PHY register 388 **/ 389 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, 390 u32 device_type, u16 phy_data) 391 { 392 u32 command; 393 394 /* write command */ 395 command = TXGBE_MDIOSCA_REG(reg_addr) | 396 TXGBE_MDIOSCA_DEV(device_type) | 397 TXGBE_MDIOSCA_PORT(hw->phy.addr); 398 wr32(hw, TXGBE_MDIOSCA, command); 399 400 command = TXGBE_MDIOSCD_CMD_WRITE | 401 TXGBE_MDIOSCD_DAT(phy_data) | 402 TXGBE_MDIOSCD_BUSY; 403 wr32(hw, TXGBE_MDIOSCD, command); 404 405 /* wait for completion */ 406 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY, 407 0, NULL, 100, 100)) { 408 TLOG_DEBUG("PHY write cmd didn't complete\n"); 409 return -TERR_PHY; 410 } 411 412 return 0; 413 } 414 415 /** 416 * txgbe_write_phy_reg - Writes a value to specified PHY register 417 * using SWFW lock- this function is needed in most cases 418 * @hw: pointer to hardware structure 419 * @reg_addr: 32 bit PHY register to write 420 * @device_type: 5 bit device type 421 * @phy_data: Data to write to the PHY register 422 **/ 423 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr, 424 u32 device_type, u16 phy_data) 425 { 426 s32 err; 427 u32 gssr = hw->phy.phy_semaphore_mask; 428 429 DEBUGFUNC("txgbe_write_phy_reg"); 430 431 if (hw->mac.acquire_swfw_sync(hw, gssr)) 432 err = TXGBE_ERR_SWFW_SYNC; 433 434 err = hw->phy.write_reg_mdi(hw, reg_addr, device_type, 435 phy_data); 436 hw->mac.release_swfw_sync(hw, gssr); 437 438 return err; 439 } 440 441 /** 442 * txgbe_setup_phy_link - Set and restart auto-neg 443 * @hw: pointer to hardware structure 444 * 445 * Restart auto-negotiation and PHY and waits for completion. 446 **/ 447 s32 txgbe_setup_phy_link(struct txgbe_hw *hw) 448 { 449 s32 err = 0; 450 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG; 451 bool autoneg = false; 452 u32 speed; 453 454 DEBUGFUNC("txgbe_setup_phy_link"); 455 456 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg); 457 458 /* Set or unset auto-negotiation 10G advertisement */ 459 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 460 TXGBE_MD_DEV_AUTO_NEG, 461 &autoneg_reg); 462 463 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE; 464 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) && 465 (speed & TXGBE_LINK_SPEED_10GB_FULL)) 466 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE; 467 468 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 469 TXGBE_MD_DEV_AUTO_NEG, 470 autoneg_reg); 471 472 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 473 TXGBE_MD_DEV_AUTO_NEG, 474 &autoneg_reg); 475 476 /* Set or unset auto-negotiation 5G advertisement */ 477 autoneg_reg &= ~TXGBE_MII_5GBASE_T_ADVERTISE; 478 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_5GB_FULL) && 479 (speed & TXGBE_LINK_SPEED_5GB_FULL)) 480 autoneg_reg |= TXGBE_MII_5GBASE_T_ADVERTISE; 481 482 /* Set or unset auto-negotiation 2.5G advertisement */ 483 autoneg_reg &= ~TXGBE_MII_2_5GBASE_T_ADVERTISE; 484 if ((hw->phy.autoneg_advertised & 485 TXGBE_LINK_SPEED_2_5GB_FULL) && 486 (speed & TXGBE_LINK_SPEED_2_5GB_FULL)) 487 autoneg_reg |= TXGBE_MII_2_5GBASE_T_ADVERTISE; 488 /* Set or unset auto-negotiation 1G advertisement */ 489 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE; 490 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) && 491 (speed & TXGBE_LINK_SPEED_1GB_FULL)) 492 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE; 493 494 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 495 TXGBE_MD_DEV_AUTO_NEG, 496 autoneg_reg); 497 498 /* Set or unset auto-negotiation 100M advertisement */ 499 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, 500 TXGBE_MD_DEV_AUTO_NEG, 501 &autoneg_reg); 502 503 autoneg_reg &= ~(TXGBE_MII_100BASE_T_ADVERTISE | 504 TXGBE_MII_100BASE_T_ADVERTISE_HALF); 505 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) && 506 (speed & TXGBE_LINK_SPEED_100M_FULL)) 507 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE; 508 509 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, 510 TXGBE_MD_DEV_AUTO_NEG, 511 autoneg_reg); 512 513 /* Blocked by MNG FW so don't reset PHY */ 514 if (txgbe_check_reset_blocked(hw)) 515 return err; 516 517 /* Restart PHY auto-negotiation. */ 518 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, 519 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg); 520 521 autoneg_reg |= TXGBE_MII_RESTART; 522 523 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, 524 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg); 525 526 return err; 527 } 528 529 /** 530 * txgbe_setup_phy_link_speed - Sets the auto advertised capabilities 531 * @hw: pointer to hardware structure 532 * @speed: new link speed 533 * @autoneg_wait_to_complete: unused 534 **/ 535 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw, 536 u32 speed, 537 bool autoneg_wait_to_complete) 538 { 539 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 540 541 DEBUGFUNC("txgbe_setup_phy_link_speed"); 542 543 /* 544 * Clear autoneg_advertised and set new values based on input link 545 * speed. 546 */ 547 hw->phy.autoneg_advertised = 0; 548 549 if (speed & TXGBE_LINK_SPEED_10GB_FULL) 550 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL; 551 552 if (speed & TXGBE_LINK_SPEED_5GB_FULL) 553 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_5GB_FULL; 554 555 if (speed & TXGBE_LINK_SPEED_2_5GB_FULL) 556 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_2_5GB_FULL; 557 558 if (speed & TXGBE_LINK_SPEED_1GB_FULL) 559 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL; 560 561 if (speed & TXGBE_LINK_SPEED_100M_FULL) 562 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL; 563 564 if (speed & TXGBE_LINK_SPEED_10M_FULL) 565 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10M_FULL; 566 567 /* Setup link based on the new speed settings */ 568 hw->phy.setup_link(hw); 569 570 return 0; 571 } 572 573 s32 txgbe_get_phy_fw_version(struct txgbe_hw *hw, u32 *fw_version) 574 { 575 u16 eeprom_verh, eeprom_verl; 576 577 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh); 578 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl); 579 580 *fw_version = (eeprom_verh << 16) | eeprom_verl; 581 582 return 0; 583 } 584 585 /** 586 * txgbe_get_copper_speeds_supported - Get copper link speeds from phy 587 * @hw: pointer to hardware structure 588 * 589 * Determines the supported link capabilities by reading the PHY auto 590 * negotiation register. 591 **/ 592 static s32 txgbe_get_copper_speeds_supported(struct txgbe_hw *hw) 593 { 594 s32 err; 595 u16 speed_ability; 596 597 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_SPEED_ABILITY, 598 TXGBE_MD_DEV_PMA_PMD, 599 &speed_ability); 600 if (err) 601 return err; 602 603 if (speed_ability & TXGBE_MD_PHY_SPEED_10G) 604 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_10GB_FULL; 605 if (speed_ability & TXGBE_MD_PHY_SPEED_1G) 606 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_1GB_FULL; 607 if (speed_ability & TXGBE_MD_PHY_SPEED_100M) 608 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_100M_FULL; 609 610 return err; 611 } 612 613 /** 614 * txgbe_get_copper_link_capabilities - Determines link capabilities 615 * @hw: pointer to hardware structure 616 * @speed: pointer to link speed 617 * @autoneg: boolean auto-negotiation value 618 **/ 619 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw, 620 u32 *speed, 621 bool *autoneg) 622 { 623 s32 err = 0; 624 625 DEBUGFUNC("txgbe_get_copper_link_capabilities"); 626 627 *autoneg = true; 628 if (!hw->phy.speeds_supported) 629 err = txgbe_get_copper_speeds_supported(hw); 630 631 *speed = hw->phy.speeds_supported; 632 return err; 633 } 634 635 /** 636 * txgbe_check_phy_link_tnx - Determine link and speed status 637 * @hw: pointer to hardware structure 638 * @speed: current link speed 639 * @link_up: true is link is up, false otherwise 640 * 641 * Reads the VS1 register to determine if link is up and the current speed for 642 * the PHY. 643 **/ 644 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw, u32 *speed, 645 bool *link_up) 646 { 647 s32 err = 0; 648 u32 time_out; 649 u32 max_time_out = 10; 650 u16 phy_link = 0; 651 u16 phy_speed = 0; 652 u16 phy_data = 0; 653 654 DEBUGFUNC("txgbe_check_phy_link_tnx"); 655 656 /* Initialize speed and link to default case */ 657 *link_up = false; 658 *speed = TXGBE_LINK_SPEED_10GB_FULL; 659 660 /* 661 * Check current speed and link status of the PHY register. 662 * This is a vendor specific register and may have to 663 * be changed for other copper PHYs. 664 */ 665 for (time_out = 0; time_out < max_time_out; time_out++) { 666 usec_delay(10); 667 err = hw->phy.read_reg(hw, 668 TXGBE_MD_VENDOR_SPECIFIC_1_STATUS, 669 TXGBE_MD_DEV_VENDOR_1, 670 &phy_data); 671 phy_link = phy_data & TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS; 672 phy_speed = phy_data & 673 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS; 674 if (phy_link == TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS) { 675 *link_up = true; 676 if (phy_speed == 677 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS) 678 *speed = TXGBE_LINK_SPEED_1GB_FULL; 679 break; 680 } 681 } 682 683 return err; 684 } 685 686 /** 687 * txgbe_setup_phy_link_tnx - Set and restart auto-neg 688 * @hw: pointer to hardware structure 689 * 690 * Restart auto-negotiation and PHY and waits for completion. 691 **/ 692 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw) 693 { 694 s32 err = 0; 695 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG; 696 bool autoneg = false; 697 u32 speed; 698 699 DEBUGFUNC("txgbe_setup_phy_link_tnx"); 700 701 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg); 702 703 if (speed & TXGBE_LINK_SPEED_10GB_FULL) { 704 /* Set or unset auto-negotiation 10G advertisement */ 705 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 706 TXGBE_MD_DEV_AUTO_NEG, 707 &autoneg_reg); 708 709 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE; 710 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) 711 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE; 712 713 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 714 TXGBE_MD_DEV_AUTO_NEG, 715 autoneg_reg); 716 } 717 718 if (speed & TXGBE_LINK_SPEED_1GB_FULL) { 719 /* Set or unset auto-negotiation 1G advertisement */ 720 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG, 721 TXGBE_MD_DEV_AUTO_NEG, 722 &autoneg_reg); 723 724 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 725 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) 726 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 727 728 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG, 729 TXGBE_MD_DEV_AUTO_NEG, 730 autoneg_reg); 731 } 732 733 if (speed & TXGBE_LINK_SPEED_100M_FULL) { 734 /* Set or unset auto-negotiation 100M advertisement */ 735 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, 736 TXGBE_MD_DEV_AUTO_NEG, 737 &autoneg_reg); 738 739 autoneg_reg &= ~TXGBE_MII_100BASE_T_ADVERTISE; 740 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) 741 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE; 742 743 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, 744 TXGBE_MD_DEV_AUTO_NEG, 745 autoneg_reg); 746 } 747 748 /* Blocked by MNG FW so don't reset PHY */ 749 if (txgbe_check_reset_blocked(hw)) 750 return err; 751 752 /* Restart PHY auto-negotiation. */ 753 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, 754 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg); 755 756 autoneg_reg |= TXGBE_MII_RESTART; 757 758 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, 759 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg); 760 761 return err; 762 } 763 764 /** 765 * txgbe_identify_module - Identifies module type 766 * @hw: pointer to hardware structure 767 * 768 * Determines HW type and calls appropriate function. 769 **/ 770 s32 txgbe_identify_module(struct txgbe_hw *hw) 771 { 772 s32 err = TXGBE_ERR_SFP_NOT_PRESENT; 773 774 DEBUGFUNC("txgbe_identify_module"); 775 776 switch (hw->phy.media_type) { 777 case txgbe_media_type_fiber: 778 err = txgbe_identify_sfp_module(hw); 779 break; 780 781 case txgbe_media_type_fiber_qsfp: 782 err = txgbe_identify_qsfp_module(hw); 783 break; 784 785 default: 786 hw->phy.sfp_type = txgbe_sfp_type_not_present; 787 err = TXGBE_ERR_SFP_NOT_PRESENT; 788 break; 789 } 790 791 return err; 792 } 793 794 /** 795 * txgbe_identify_sfp_module - Identifies SFP modules 796 * @hw: pointer to hardware structure 797 * 798 * Searches for and identifies the SFP module and assigns appropriate PHY type. 799 **/ 800 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) 801 { 802 s32 err = TXGBE_ERR_PHY_ADDR_INVALID; 803 u32 vendor_oui = 0; 804 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 805 u8 identifier = 0; 806 u8 comp_codes_1g = 0; 807 u8 comp_codes_10g = 0; 808 u8 oui_bytes[3] = {0, 0, 0}; 809 u8 cable_tech = 0; 810 u8 cable_spec = 0; 811 u16 enforce_sfp = 0; 812 813 DEBUGFUNC("txgbe_identify_sfp_module"); 814 815 if (hw->phy.media_type != txgbe_media_type_fiber) { 816 hw->phy.sfp_type = txgbe_sfp_type_not_present; 817 return TXGBE_ERR_SFP_NOT_PRESENT; 818 } 819 820 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER, 821 &identifier); 822 if (err != 0) { 823 ERR_I2C: 824 hw->phy.sfp_type = txgbe_sfp_type_not_present; 825 if (hw->phy.type != txgbe_phy_nl) { 826 hw->phy.id = 0; 827 hw->phy.type = txgbe_phy_unknown; 828 } 829 return TXGBE_ERR_SFP_NOT_PRESENT; 830 } 831 832 if (identifier != TXGBE_SFF_IDENTIFIER_SFP) { 833 hw->phy.type = txgbe_phy_sfp_unsupported; 834 return TXGBE_ERR_SFP_NOT_SUPPORTED; 835 } 836 837 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES, 838 &comp_codes_1g); 839 if (err != 0) 840 goto ERR_I2C; 841 842 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES, 843 &comp_codes_10g); 844 if (err != 0) 845 goto ERR_I2C; 846 847 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY, 848 &cable_tech); 849 if (err != 0) 850 goto ERR_I2C; 851 852 /* ID Module 853 * ========= 854 * 0 SFP_DA_CU 855 * 1 SFP_SR 856 * 2 SFP_LR 857 * 3 SFP_DA_CORE0 - chip-specific 858 * 4 SFP_DA_CORE1 - chip-specific 859 * 5 SFP_SR/LR_CORE0 - chip-specific 860 * 6 SFP_SR/LR_CORE1 - chip-specific 861 * 7 SFP_act_lmt_DA_CORE0 - chip-specific 862 * 8 SFP_act_lmt_DA_CORE1 - chip-specific 863 * 9 SFP_1g_cu_CORE0 - chip-specific 864 * 10 SFP_1g_cu_CORE1 - chip-specific 865 * 11 SFP_1g_sx_CORE0 - chip-specific 866 * 12 SFP_1g_sx_CORE1 - chip-specific 867 */ 868 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) { 869 if (hw->bus.lan_id == 0) 870 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0; 871 else 872 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1; 873 } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) { 874 err = hw->phy.read_i2c_eeprom(hw, 875 TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec); 876 if (err != 0) 877 goto ERR_I2C; 878 if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 879 hw->phy.sfp_type = (hw->bus.lan_id == 0 880 ? txgbe_sfp_type_da_act_lmt_core0 881 : txgbe_sfp_type_da_act_lmt_core1); 882 } else { 883 hw->phy.sfp_type = txgbe_sfp_type_unknown; 884 } 885 } else if (comp_codes_10g & 886 (TXGBE_SFF_10GBASESR_CAPABLE | 887 TXGBE_SFF_10GBASELR_CAPABLE)) { 888 hw->phy.sfp_type = (hw->bus.lan_id == 0 889 ? txgbe_sfp_type_srlr_core0 890 : txgbe_sfp_type_srlr_core1); 891 } else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) { 892 hw->phy.sfp_type = (hw->bus.lan_id == 0 893 ? txgbe_sfp_type_1g_cu_core0 894 : txgbe_sfp_type_1g_cu_core1); 895 } else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) { 896 hw->phy.sfp_type = (hw->bus.lan_id == 0 897 ? txgbe_sfp_type_1g_sx_core0 898 : txgbe_sfp_type_1g_sx_core1); 899 } else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) { 900 hw->phy.sfp_type = (hw->bus.lan_id == 0 901 ? txgbe_sfp_type_1g_lx_core0 902 : txgbe_sfp_type_1g_lx_core1); 903 } else { 904 hw->phy.sfp_type = txgbe_sfp_type_unknown; 905 } 906 907 if (hw->phy.sfp_type != stored_sfp_type) 908 hw->phy.sfp_setup_needed = true; 909 910 /* Determine if the SFP+ PHY is dual speed or not. */ 911 hw->phy.multispeed_fiber = false; 912 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) && 913 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) || 914 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) && 915 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE))) 916 hw->phy.multispeed_fiber = true; 917 918 /* Determine PHY vendor */ 919 if (hw->phy.type != txgbe_phy_nl) { 920 hw->phy.id = identifier; 921 err = hw->phy.read_i2c_eeprom(hw, 922 TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]); 923 if (err != 0) 924 goto ERR_I2C; 925 926 err = hw->phy.read_i2c_eeprom(hw, 927 TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]); 928 if (err != 0) 929 goto ERR_I2C; 930 931 err = hw->phy.read_i2c_eeprom(hw, 932 TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]); 933 if (err != 0) 934 goto ERR_I2C; 935 936 vendor_oui = ((u32)oui_bytes[0] << 24) | 937 ((u32)oui_bytes[1] << 16) | 938 ((u32)oui_bytes[2] << 8); 939 switch (vendor_oui) { 940 case TXGBE_SFF_VENDOR_OUI_TYCO: 941 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) 942 hw->phy.type = txgbe_phy_sfp_tyco_passive; 943 break; 944 case TXGBE_SFF_VENDOR_OUI_FTL: 945 if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) 946 hw->phy.type = txgbe_phy_sfp_ftl_active; 947 else 948 hw->phy.type = txgbe_phy_sfp_ftl; 949 break; 950 case TXGBE_SFF_VENDOR_OUI_AVAGO: 951 hw->phy.type = txgbe_phy_sfp_avago; 952 break; 953 case TXGBE_SFF_VENDOR_OUI_INTEL: 954 hw->phy.type = txgbe_phy_sfp_intel; 955 break; 956 default: 957 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) 958 hw->phy.type = txgbe_phy_sfp_unknown_passive; 959 else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) 960 hw->phy.type = txgbe_phy_sfp_unknown_active; 961 else 962 hw->phy.type = txgbe_phy_sfp_unknown; 963 break; 964 } 965 } 966 967 /* Allow any DA cable vendor */ 968 if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE | 969 TXGBE_SFF_CABLE_DA_ACTIVE)) { 970 return 0; 971 } 972 973 /* Verify supported 1G SFP modules */ 974 if (comp_codes_10g == 0 && 975 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 || 976 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 || 977 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 || 978 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 || 979 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 || 980 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) { 981 hw->phy.type = txgbe_phy_sfp_unsupported; 982 return TXGBE_ERR_SFP_NOT_SUPPORTED; 983 } 984 985 hw->mac.get_device_caps(hw, &enforce_sfp); 986 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 987 !hw->allow_unsupported_sfp && 988 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 || 989 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 || 990 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 || 991 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 || 992 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 || 993 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) { 994 DEBUGOUT("SFP+ module not supported\n"); 995 hw->phy.type = txgbe_phy_sfp_unsupported; 996 return TXGBE_ERR_SFP_NOT_SUPPORTED; 997 } 998 999 return err; 1000 } 1001 1002 /** 1003 * txgbe_identify_qsfp_module - Identifies QSFP modules 1004 * @hw: pointer to hardware structure 1005 * 1006 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1007 **/ 1008 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw) 1009 { 1010 s32 err = TXGBE_ERR_PHY_ADDR_INVALID; 1011 u32 vendor_oui = 0; 1012 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1013 u8 identifier = 0; 1014 u8 comp_codes_1g = 0; 1015 u8 comp_codes_10g = 0; 1016 u8 oui_bytes[3] = {0, 0, 0}; 1017 u16 enforce_sfp = 0; 1018 u8 connector = 0; 1019 u8 cable_length = 0; 1020 u8 device_tech = 0; 1021 bool active_cable = false; 1022 1023 DEBUGFUNC("txgbe_identify_qsfp_module"); 1024 1025 if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) { 1026 hw->phy.sfp_type = txgbe_sfp_type_not_present; 1027 err = TXGBE_ERR_SFP_NOT_PRESENT; 1028 goto out; 1029 } 1030 1031 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER, 1032 &identifier); 1033 ERR_I2C: 1034 if (err != 0) { 1035 hw->phy.sfp_type = txgbe_sfp_type_not_present; 1036 hw->phy.id = 0; 1037 hw->phy.type = txgbe_phy_unknown; 1038 return TXGBE_ERR_SFP_NOT_PRESENT; 1039 } 1040 if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1041 hw->phy.type = txgbe_phy_sfp_unsupported; 1042 err = TXGBE_ERR_SFP_NOT_SUPPORTED; 1043 goto out; 1044 } 1045 1046 hw->phy.id = identifier; 1047 1048 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP, 1049 &comp_codes_10g); 1050 1051 if (err != 0) 1052 goto ERR_I2C; 1053 1054 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP, 1055 &comp_codes_1g); 1056 1057 if (err != 0) 1058 goto ERR_I2C; 1059 1060 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1061 hw->phy.type = txgbe_phy_qsfp_unknown_passive; 1062 if (hw->bus.lan_id == 0) 1063 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0; 1064 else 1065 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1; 1066 } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE | 1067 TXGBE_SFF_10GBASELR_CAPABLE)) { 1068 if (hw->bus.lan_id == 0) 1069 hw->phy.sfp_type = txgbe_sfp_type_srlr_core0; 1070 else 1071 hw->phy.sfp_type = txgbe_sfp_type_srlr_core1; 1072 } else { 1073 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1074 active_cable = true; 1075 1076 if (!active_cable) { 1077 hw->phy.read_i2c_eeprom(hw, 1078 TXGBE_SFF_QSFP_CONNECTOR, 1079 &connector); 1080 1081 hw->phy.read_i2c_eeprom(hw, 1082 TXGBE_SFF_QSFP_CABLE_LENGTH, 1083 &cable_length); 1084 1085 hw->phy.read_i2c_eeprom(hw, 1086 TXGBE_SFF_QSFP_DEVICE_TECH, 1087 &device_tech); 1088 1089 if (connector == 1090 TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE && 1091 cable_length > 0 && 1092 ((device_tech >> 4) == 1093 TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL)) 1094 active_cable = true; 1095 } 1096 1097 if (active_cable) { 1098 hw->phy.type = txgbe_phy_qsfp_unknown_active; 1099 if (hw->bus.lan_id == 0) 1100 hw->phy.sfp_type = 1101 txgbe_sfp_type_da_act_lmt_core0; 1102 else 1103 hw->phy.sfp_type = 1104 txgbe_sfp_type_da_act_lmt_core1; 1105 } else { 1106 /* unsupported module type */ 1107 hw->phy.type = txgbe_phy_sfp_unsupported; 1108 err = TXGBE_ERR_SFP_NOT_SUPPORTED; 1109 goto out; 1110 } 1111 } 1112 1113 if (hw->phy.sfp_type != stored_sfp_type) 1114 hw->phy.sfp_setup_needed = true; 1115 1116 /* Determine if the QSFP+ PHY is dual speed or not. */ 1117 hw->phy.multispeed_fiber = false; 1118 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) && 1119 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) || 1120 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) && 1121 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE))) 1122 hw->phy.multispeed_fiber = true; 1123 1124 /* Determine PHY vendor for optical modules */ 1125 if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE | 1126 TXGBE_SFF_10GBASELR_CAPABLE)) { 1127 err = hw->phy.read_i2c_eeprom(hw, 1128 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1129 &oui_bytes[0]); 1130 1131 if (err != 0) 1132 goto ERR_I2C; 1133 1134 err = hw->phy.read_i2c_eeprom(hw, 1135 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1136 &oui_bytes[1]); 1137 1138 if (err != 0) 1139 goto ERR_I2C; 1140 1141 err = hw->phy.read_i2c_eeprom(hw, 1142 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1143 &oui_bytes[2]); 1144 1145 if (err != 0) 1146 goto ERR_I2C; 1147 1148 vendor_oui = 1149 ((oui_bytes[0] << 24) | 1150 (oui_bytes[1] << 16) | 1151 (oui_bytes[2] << 8)); 1152 1153 if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL) 1154 hw->phy.type = txgbe_phy_qsfp_intel; 1155 else 1156 hw->phy.type = txgbe_phy_qsfp_unknown; 1157 1158 hw->mac.get_device_caps(hw, &enforce_sfp); 1159 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1160 /* Make sure we're a supported PHY type */ 1161 if (hw->phy.type == txgbe_phy_qsfp_intel) { 1162 err = 0; 1163 } else { 1164 if (hw->allow_unsupported_sfp) { 1165 DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. " 1166 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1167 "Wangxun Corporation is not responsible for any harm caused by using untested modules.\n"); 1168 err = 0; 1169 } else { 1170 DEBUGOUT("QSFP module not supported\n"); 1171 hw->phy.type = 1172 txgbe_phy_sfp_unsupported; 1173 err = TXGBE_ERR_SFP_NOT_SUPPORTED; 1174 } 1175 } 1176 } else { 1177 err = 0; 1178 } 1179 } 1180 1181 out: 1182 return err; 1183 } 1184 1185 /** 1186 * txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1187 * @hw: pointer to hardware structure 1188 * @byte_offset: EEPROM byte offset to read 1189 * @eeprom_data: value read 1190 * 1191 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1192 **/ 1193 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, 1194 u8 *eeprom_data) 1195 { 1196 DEBUGFUNC("txgbe_read_i2c_eeprom"); 1197 1198 return hw->phy.read_i2c_byte(hw, byte_offset, 1199 TXGBE_I2C_EEPROM_DEV_ADDR, 1200 eeprom_data); 1201 } 1202 1203 /** 1204 * txgbe_read_i2c_sff8472 - Reads 8 bit word over I2C interface 1205 * @hw: pointer to hardware structure 1206 * @byte_offset: byte offset at address 0xA2 1207 * @sff8472_data: value read 1208 * 1209 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1210 **/ 1211 s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset, 1212 u8 *sff8472_data) 1213 { 1214 return hw->phy.read_i2c_byte(hw, byte_offset, 1215 TXGBE_I2C_EEPROM_DEV_ADDR2, 1216 sff8472_data); 1217 } 1218 1219 /** 1220 * txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1221 * @hw: pointer to hardware structure 1222 * @byte_offset: EEPROM byte offset to write 1223 * @eeprom_data: value to write 1224 * 1225 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1226 **/ 1227 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, 1228 u8 eeprom_data) 1229 { 1230 DEBUGFUNC("txgbe_write_i2c_eeprom"); 1231 1232 return hw->phy.write_i2c_byte(hw, byte_offset, 1233 TXGBE_I2C_EEPROM_DEV_ADDR, 1234 eeprom_data); 1235 } 1236 1237 /** 1238 * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C 1239 * @hw: pointer to hardware structure 1240 * @byte_offset: byte offset to read 1241 * @dev_addr: address to read from 1242 * @data: value read 1243 * 1244 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1245 * a specified device address. 1246 **/ 1247 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, 1248 u8 dev_addr, u8 *data) 1249 { 1250 UNREFERENCED_PARAMETER(dev_addr); 1251 1252 DEBUGFUNC("txgbe_read_i2c_byte"); 1253 1254 txgbe_i2c_start(hw); 1255 1256 /* wait tx empty */ 1257 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY, 1258 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) { 1259 return -TERR_TIMEOUT; 1260 } 1261 1262 /* read data */ 1263 wr32(hw, TXGBE_I2CDATA, 1264 byte_offset | TXGBE_I2CDATA_STOP); 1265 wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ); 1266 1267 /* wait for read complete */ 1268 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL, 1269 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) { 1270 return -TERR_TIMEOUT; 1271 } 1272 1273 txgbe_i2c_stop(hw); 1274 1275 *data = 0xFF & rd32(hw, TXGBE_I2CDATA); 1276 1277 return 0; 1278 } 1279 1280 /** 1281 * txgbe_read_i2c_byte - Reads 8 bit word over I2C 1282 * @hw: pointer to hardware structure 1283 * @byte_offset: byte offset to read 1284 * @dev_addr: address to read from 1285 * @data: value read 1286 * 1287 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1288 * a specified device address. 1289 **/ 1290 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, 1291 u8 dev_addr, u8 *data) 1292 { 1293 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1294 int err = 0; 1295 1296 if (hw->mac.acquire_swfw_sync(hw, swfw_mask)) 1297 return TXGBE_ERR_SWFW_SYNC; 1298 err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data); 1299 hw->mac.release_swfw_sync(hw, swfw_mask); 1300 return err; 1301 } 1302 1303 /** 1304 * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1305 * @hw: pointer to hardware structure 1306 * @byte_offset: byte offset to write 1307 * @dev_addr: address to write to 1308 * @data: value to write 1309 * 1310 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1311 * a specified device address. 1312 **/ 1313 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, 1314 u8 dev_addr, u8 data) 1315 { 1316 UNREFERENCED_PARAMETER(dev_addr); 1317 1318 DEBUGFUNC("txgbe_write_i2c_byte"); 1319 1320 txgbe_i2c_start(hw); 1321 1322 /* wait tx empty */ 1323 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY, 1324 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) { 1325 return -TERR_TIMEOUT; 1326 } 1327 1328 wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP); 1329 wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE); 1330 1331 /* wait for write complete */ 1332 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL, 1333 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) { 1334 return -TERR_TIMEOUT; 1335 } 1336 txgbe_i2c_stop(hw); 1337 1338 return 0; 1339 } 1340 1341 /** 1342 * txgbe_write_i2c_byte - Writes 8 bit word over I2C 1343 * @hw: pointer to hardware structure 1344 * @byte_offset: byte offset to write 1345 * @dev_addr: address to write to 1346 * @data: value to write 1347 * 1348 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1349 * a specified device address. 1350 **/ 1351 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, 1352 u8 dev_addr, u8 data) 1353 { 1354 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1355 int err = 0; 1356 1357 if (hw->mac.acquire_swfw_sync(hw, swfw_mask)) 1358 return TXGBE_ERR_SWFW_SYNC; 1359 err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data); 1360 hw->mac.release_swfw_sync(hw, swfw_mask); 1361 1362 return err; 1363 } 1364 1365 /** 1366 * txgbe_i2c_start - Sets I2C start condition 1367 * @hw: pointer to hardware structure 1368 * 1369 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1370 **/ 1371 static void txgbe_i2c_start(struct txgbe_hw *hw) 1372 { 1373 DEBUGFUNC("txgbe_i2c_start"); 1374 1375 wr32(hw, TXGBE_I2CENA, 0); 1376 1377 wr32(hw, TXGBE_I2CCON, 1378 (TXGBE_I2CCON_MENA | 1379 TXGBE_I2CCON_SPEED(1) | 1380 TXGBE_I2CCON_RESTART | 1381 TXGBE_I2CCON_SDIA)); 1382 wr32(hw, TXGBE_I2CTAR, TXGBE_I2C_SLAVEADDR); 1383 wr32(hw, TXGBE_I2CSSSCLHCNT, 600); 1384 wr32(hw, TXGBE_I2CSSSCLLCNT, 600); 1385 wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */ 1386 wr32(hw, TXGBE_I2CTXTL, 4); 1387 wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF); 1388 wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF); 1389 1390 wr32(hw, TXGBE_I2CICM, 0); 1391 wr32(hw, TXGBE_I2CENA, 1); 1392 } 1393 1394 /** 1395 * txgbe_i2c_stop - Sets I2C stop condition 1396 * @hw: pointer to hardware structure 1397 * 1398 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1399 **/ 1400 static void txgbe_i2c_stop(struct txgbe_hw *hw) 1401 { 1402 DEBUGFUNC("txgbe_i2c_stop"); 1403 1404 /* wait for completion */ 1405 if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST, 1406 0, NULL, 100, 100)) { 1407 DEBUGFUNC("i2c stop timeout."); 1408 } 1409 1410 wr32(hw, TXGBE_I2CENA, 0); 1411 } 1412 1413 static void 1414 txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw) 1415 { 1416 u32 value; 1417 1418 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002); 1419 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105); 1420 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200); 1421 value = rd32_epcs(hw, SR_MII_MMD_CTL); 1422 value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9); 1423 wr32_epcs(hw, SR_MII_MMD_CTL, value); 1424 } 1425 1426 static s32 1427 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg) 1428 { 1429 u32 i; 1430 u16 value; 1431 s32 err = 0; 1432 1433 /* 1. Wait xpcs power-up good */ 1434 for (i = 0; i < 100; i++) { 1435 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) & 1436 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) == 1437 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD) 1438 break; 1439 msec_delay(10); 1440 } 1441 if (i == 100) { 1442 err = TXGBE_ERR_XPCS_POWER_UP_FAILED; 1443 goto out; 1444 } 1445 BP_LOG("It is set to kr.\n"); 1446 1447 wr32_epcs(hw, VR_AN_INTR_MSK, 0x7); 1448 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC); 1449 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC); 1450 1451 if (!autoneg) { 1452 /* 2. Disable xpcs AN-73 */ 1453 wr32_epcs(hw, SR_AN_CTRL, 1454 SR_AN_CTRL_AN_EN | SR_AN_CTRL_EXT_NP); 1455 1456 wr32_epcs(hw, VR_AN_KR_MODE_CL, VR_AN_KR_MODE_CL_PDET); 1457 1458 if (!(hw->devarg.auto_neg == 1)) { 1459 wr32_epcs(hw, SR_AN_CTRL, 0); 1460 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0); 1461 } 1462 if (hw->devarg.present == 1) { 1463 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 1464 value |= TXGBE_PHY_TX_EQ_CTL1_DEF; 1465 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1466 } 1467 if (hw->devarg.poll == 1) { 1468 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL0, 1469 VR_PMA_KRTR_TIMER_MAX_WAIT); 1470 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL2, 0xA697); 1471 } 1472 1473 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register 1474 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16) 1475 */ 1476 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 1477 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR); 1478 1479 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register 1480 * Bit[12:8](RX_VREF_CTRL) = 5'hF (default: 5'h11) 1481 */ 1482 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 1483 1484 /* 5. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register 1485 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77 1486 * Bit[7:5](CTLE_POLE_0) = 3'h2 1487 * Bit[4:0](CTLE_BOOST_0) = 4'hA 1488 */ 1489 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774A); 1490 1491 /* 6. Set VR_MII_Gen5_12G_RX_GENCTRL3 Register 1492 * Bit[2:0](LOS_TRSHLD_0) = 3'h4 (default: 3) 1493 */ 1494 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, 0x0004); 1495 1496 /* 7. Initialize the mode by setting VR XS or PCS MMD Digital 1497 * Control1 Register Bit[15](VR_RST) 1498 */ 1499 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000); 1500 1501 /* Wait phy initialization done */ 1502 for (i = 0; i < 100; i++) { 1503 if ((rd32_epcs(hw, 1504 VR_XS_OR_PCS_MMD_DIGI_CTL1) & 1505 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0) 1506 break; 1507 msleep(100); 1508 } 1509 if (i == 100) { 1510 err = TXGBE_ERR_PHY_INIT_NOT_DONE; 1511 goto out; 1512 } 1513 } else { 1514 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1); 1515 } 1516 1517 if (hw->phy.ffe_set == TXGBE_BP_M_KR) { 1518 value = (0x1804 & ~0x3F3F); 1519 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 1520 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1521 1522 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; 1523 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1524 } 1525 out: 1526 return err; 1527 } 1528 1529 static s32 1530 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg) 1531 { 1532 u32 i; 1533 s32 err = 0; 1534 u32 value; 1535 1536 /* Check link status, if already set, skip setting it again */ 1537 if (hw->link_status == TXGBE_LINK_STATUS_KX4) 1538 goto out; 1539 1540 BP_LOG("It is set to kx4.\n"); 1541 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0); 1542 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0); 1543 1544 /* 1. Wait xpcs power-up good */ 1545 for (i = 0; i < 100; i++) { 1546 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) & 1547 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) == 1548 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD) 1549 break; 1550 msec_delay(10); 1551 } 1552 if (i == 100) { 1553 err = TXGBE_ERR_XPCS_POWER_UP_FAILED; 1554 goto out; 1555 } 1556 1557 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, 1558 ~TXGBE_MACTXCFG_TXE); 1559 1560 /* 2. Disable xpcs AN-73 */ 1561 if (!autoneg) 1562 wr32_epcs(hw, SR_AN_CTRL, 0x0); 1563 else 1564 wr32_epcs(hw, SR_AN_CTRL, 0x3000); 1565 1566 /* Disable PHY MPLLA for eth mode change(after ECO) */ 1567 wr32_ephy(hw, 0x4, 0x250A); 1568 txgbe_flush(hw); 1569 msec_delay(1); 1570 1571 /* Set the eth change_mode bit first in mis_rst register 1572 * for corresponding LAN port 1573 */ 1574 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id)); 1575 1576 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01 1577 * PCS_TYPE_SEL: non KR 1578 */ 1579 wr32_epcs(hw, SR_XS_PCS_CTRL2, 1580 SR_PCS_CTRL2_TYPE_SEL_X); 1581 1582 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b1 1583 * SS13: 10G speed 1584 */ 1585 wr32_epcs(hw, SR_PMA_CTRL1, 1586 SR_PMA_CTRL1_SS13_KX4); 1587 1588 value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0xF0; 1589 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value); 1590 1591 if ((hw->subsystem_device_id & 0xFF) == TXGBE_DEV_ID_MAC_XAUI) 1592 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 1593 else 1594 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00); 1595 1596 for (i = 0; i < 4; i++) { 1597 if (i == 0) 1598 value = (0x45 & ~0xFFFF) | (0x7 << 12) | 1599 (0x7 << 8) | 0x6; 1600 else 1601 value = (0xff06 & ~0xFFFF) | (0x7 << 12) | 1602 (0x7 << 8) | 0x6; 1603 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value); 1604 } 1605 1606 value = 0x0 & ~0x7777; 1607 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value); 1608 1609 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0); 1610 1611 value = (0x6db & ~0xFFF) | (0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1; 1612 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value); 1613 1614 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA 1615 * Control 0 Register Bit[7:0] = 8'd40 //MPLLA_MULTIPLIER 1616 */ 1617 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 1618 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER); 1619 1620 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA 1621 * Control 3 Register Bit[10:0] = 11'd86 //MPLLA_BANDWIDTH 1622 */ 1623 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 1624 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER); 1625 1626 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1627 * Calibration Load 0 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_0 1628 */ 1629 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 1630 TXGBE_PHY_VCO_CAL_LD0_OTHER); 1631 1632 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1633 * Calibration Load 1 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_1 1634 */ 1635 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 1636 TXGBE_PHY_VCO_CAL_LD0_OTHER); 1637 1638 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1639 * Calibration Load 2 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_2 1640 */ 1641 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 1642 TXGBE_PHY_VCO_CAL_LD0_OTHER); 1643 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1644 * Calibration Load 3 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_3 1645 */ 1646 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 1647 TXGBE_PHY_VCO_CAL_LD0_OTHER); 1648 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1649 * Calibration Reference 0 Register Bit[5:0] = 6'd34 //VCO_REF_LD_0/1 1650 */ 1651 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x2222); 1652 1653 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1654 * Calibration Reference 1 Register Bit[5:0] = 6'd34 //VCO_REF_LD_2/3 1655 */ 1656 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2222); 1657 1658 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE 1659 * Enable Register Bit[7:0] = 8'd0 //AFE_EN_0/3_1, DFE_EN_0/3_1 1660 */ 1661 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0); 1662 1663 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx 1664 * Equalization Control 4 Register Bit[3:0] = 4'd0 //CONT_ADAPT_0/3_1 1665 */ 1666 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x00F0); 1667 1668 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate 1669 * Control Register Bit[14:12], Bit[10:8], Bit[6:4], Bit[2:0], 1670 * all rates to 3'b010 //TX0/1/2/3_RATE 1671 */ 1672 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x2222); 1673 1674 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate 1675 * Control Register Bit[13:12], Bit[9:8], Bit[5:4], Bit[1:0], 1676 * all rates to 2'b10 //RX0/1/2/3_RATE 1677 */ 1678 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x2222); 1679 1680 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General 1681 * Control 2 Register Bit[15:8] = 2'b01 //TX0/1/2/3_WIDTH: 10bits 1682 */ 1683 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x5500); 1684 1685 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General 1686 * Control 2 Register Bit[15:8] = 2'b01 //RX0/1/2/3_WIDTH: 10bits 1687 */ 1688 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x5500); 1689 1690 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control 1691 * 2 Register Bit[10:8] = 3'b010 1692 * MPLLA_DIV16P5_CLK_EN=0, MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0 1693 */ 1694 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 1695 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10); 1696 1697 wr32_epcs(hw, 0x1f0000, 0x0); 1698 wr32_epcs(hw, 0x1f8001, 0x0); 1699 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0); 1700 1701 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1 1702 * Register Bit[15](VR_RST) 1703 */ 1704 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000); 1705 1706 /* Wait phy initialization done */ 1707 for (i = 0; i < 100; i++) { 1708 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) & 1709 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0) 1710 break; 1711 msleep(100); 1712 } 1713 1714 /* If success, set link status */ 1715 hw->link_status = TXGBE_LINK_STATUS_KX4; 1716 1717 if (i == 100) { 1718 err = TXGBE_ERR_PHY_INIT_NOT_DONE; 1719 goto out; 1720 } 1721 1722 if (hw->phy.ffe_set == TXGBE_BP_M_KX4) { 1723 value = (0x1804 & ~0x3F3F); 1724 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 1725 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1726 1727 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; 1728 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1729 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { 1730 value = (0x1804 & ~0x3F3F); 1731 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1732 1733 value = (0x50 & ~0x7F) | 40 | (1 << 6); 1734 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1735 } 1736 out: 1737 return err; 1738 } 1739 1740 static s32 1741 txgbe_set_link_to_kx(struct txgbe_hw *hw, 1742 u32 speed, 1743 bool autoneg) 1744 { 1745 u32 i; 1746 s32 err = 0; 1747 u32 wdata = 0; 1748 u32 value; 1749 1750 /* Check link status, if already set, skip setting it again */ 1751 if (hw->link_status == TXGBE_LINK_STATUS_KX) 1752 goto out; 1753 1754 BP_LOG("It is set to kx. speed =0x%x\n", speed); 1755 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC); 1756 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC); 1757 1758 /* 1. Wait xpcs power-up good */ 1759 for (i = 0; i < 100; i++) { 1760 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) & 1761 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) == 1762 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD) 1763 break; 1764 msec_delay(10); 1765 } 1766 if (i == 100) { 1767 err = TXGBE_ERR_XPCS_POWER_UP_FAILED; 1768 goto out; 1769 } 1770 1771 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, 1772 ~TXGBE_MACTXCFG_TXE); 1773 1774 /* 2. Disable xpcs AN-73 */ 1775 if (!autoneg) 1776 wr32_epcs(hw, SR_AN_CTRL, 0x0); 1777 else 1778 wr32_epcs(hw, SR_AN_CTRL, 0x3000); 1779 1780 /* Disable PHY MPLLA for eth mode change(after ECO) */ 1781 wr32_ephy(hw, 0x4, 0x240A); 1782 txgbe_flush(hw); 1783 msec_delay(1); 1784 1785 /* Set the eth change_mode bit first in mis_rst register 1786 * for corresponding LAN port 1787 */ 1788 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id)); 1789 1790 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01 1791 * PCS_TYPE_SEL: non KR 1792 */ 1793 wr32_epcs(hw, SR_XS_PCS_CTRL2, 1794 SR_PCS_CTRL2_TYPE_SEL_X); 1795 1796 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0 1797 * SS13: 1G speed 1798 */ 1799 wr32_epcs(hw, SR_PMA_CTRL1, 1800 SR_PMA_CTRL1_SS13_KX); 1801 1802 /* Set SR MII MMD Control Register to corresponding speed: {Bit[6], 1803 * Bit[13]}=[2'b00,2'b01,2'b10]->[10M,100M,1G] 1804 */ 1805 if (speed == TXGBE_LINK_SPEED_100M_FULL) 1806 wdata = 0x2100; 1807 else if (speed == TXGBE_LINK_SPEED_1GB_FULL) 1808 wdata = 0x0140; 1809 else if (speed == TXGBE_LINK_SPEED_10M_FULL) 1810 wdata = 0x0100; 1811 wr32_epcs(hw, SR_MII_MMD_CTL, 1812 wdata); 1813 1814 value = (0xf5f0 & ~0x710) | (0x5 << 8) | 0x10; 1815 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value); 1816 1817 if (hw->devarg.sgmii == 1) 1818 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00); 1819 else 1820 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 1821 1822 for (i = 0; i < 4; i++) { 1823 if (i) { 1824 value = 0xff06; 1825 } else { 1826 value = (0x45 & ~0xFFFF) | (0x7 << 12) | 1827 (0x7 << 8) | 0x6; 1828 } 1829 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value); 1830 } 1831 1832 value = 0x0 & ~0x7; 1833 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value); 1834 1835 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0); 1836 1837 value = (0x6db & ~0x7) | 0x4; 1838 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value); 1839 1840 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control 1841 * 0 Register Bit[7:0] = 8'd32 //MPLLA_MULTIPLIER 1842 */ 1843 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 1844 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX); 1845 1846 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA Control 1847 * 3 Register Bit[10:0] = 11'd70 //MPLLA_BANDWIDTH 1848 */ 1849 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 1850 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX); 1851 1852 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1853 * Calibration Load 0 Register Bit[12:0] = 13'd1344 //VCO_LD_VAL_0 1854 */ 1855 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 1856 TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX); 1857 1858 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 0x549); 1859 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 0x549); 1860 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 0x549); 1861 1862 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1863 * Calibration Reference 0 Register Bit[5:0] = 6'd42 //VCO_REF_LD_0 1864 */ 1865 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 1866 TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX); 1867 1868 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2929); 1869 1870 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE 1871 * Enable Register Bit[4], Bit[0] = 1'b0 //AFE_EN_0, DFE_EN_0 1872 */ 1873 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 1874 0x0); 1875 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx 1876 * Equalization Control 4 Register Bit[0] = 1'b0 //CONT_ADAPT_0 1877 */ 1878 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 1879 0x0010); 1880 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate 1881 * Control Register Bit[2:0] = 3'b011 //TX0_RATE 1882 */ 1883 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 1884 TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX); 1885 1886 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate 1887 * Control Register Bit[2:0] = 3'b011 //RX0_RATE 1888 */ 1889 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 1890 TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX); 1891 1892 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General 1893 * Control 2 Register Bit[9:8] = 2'b01 //TX0_WIDTH: 10bits 1894 */ 1895 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 1896 TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER); 1897 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General 1898 * Control 2 Register Bit[9:8] = 2'b01 //RX0_WIDTH: 10bits 1899 */ 1900 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 1901 TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER); 1902 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control 1903 * 2 Register Bit[10:8] = 3'b010 //MPLLA_DIV16P5_CLK_EN=0, 1904 * MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0 1905 */ 1906 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 1907 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10); 1908 1909 /* VR MII MMD AN Control Register Bit[8] = 1'b1 //MII_CTRL 1910 * Set to 8bit MII (required in 10M/100M SGMII) 1911 */ 1912 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 1913 0x0100); 1914 1915 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1 1916 * Register Bit[15](VR_RST) 1917 */ 1918 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000); 1919 1920 /* Wait phy initialization done */ 1921 for (i = 0; i < 100; i++) { 1922 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) & 1923 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0) 1924 break; 1925 msleep(100); 1926 } 1927 1928 /* If success, set link status */ 1929 hw->link_status = TXGBE_LINK_STATUS_KX; 1930 1931 if (i == 100) { 1932 err = TXGBE_ERR_PHY_INIT_NOT_DONE; 1933 goto out; 1934 } 1935 1936 if (hw->phy.ffe_set == TXGBE_BP_M_KX) { 1937 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F; 1938 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 1939 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1940 1941 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F; 1942 value |= hw->phy.ffe_post | (1 << 6); 1943 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1944 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { 1945 value = (0x1804 & ~0x3F3F) | (24 << 8) | 4; 1946 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1947 1948 value = (0x50 & ~0x7F) | 16 | (1 << 6); 1949 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1950 } 1951 out: 1952 return err; 1953 } 1954 1955 static s32 1956 txgbe_set_link_to_sfi(struct txgbe_hw *hw, 1957 u32 speed) 1958 { 1959 u32 i; 1960 s32 err = 0; 1961 u32 value = 0; 1962 1963 /* Set the module link speed */ 1964 hw->mac.set_rate_select_speed(hw, speed); 1965 /* 1. Wait xpcs power-up good */ 1966 for (i = 0; i < 100; i++) { 1967 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) & 1968 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) == 1969 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD) 1970 break; 1971 msec_delay(10); 1972 } 1973 if (i == 100) { 1974 err = TXGBE_ERR_XPCS_POWER_UP_FAILED; 1975 goto out; 1976 } 1977 1978 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, 1979 ~TXGBE_MACTXCFG_TXE); 1980 1981 /* 2. Disable xpcs AN-73 */ 1982 wr32_epcs(hw, SR_AN_CTRL, 0x0); 1983 1984 /* Disable PHY MPLLA for eth mode change(after ECO) */ 1985 wr32_ephy(hw, 0x4, 0x243A); 1986 txgbe_flush(hw); 1987 msec_delay(1); 1988 /* Set the eth change_mode bit first in mis_rst register 1989 * for corresponding LAN port 1990 */ 1991 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id)); 1992 1993 if (speed == TXGBE_LINK_SPEED_10GB_FULL) { 1994 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00 1995 * PCS_TYPE_SEL: KR 1996 */ 1997 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0); 1998 value = rd32_epcs(hw, SR_PMA_CTRL1); 1999 value = value | 0x2000; 2000 wr32_epcs(hw, SR_PMA_CTRL1, value); 2001 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL0 Register Bit[7:0] = 8'd33 2002 * MPLLA_MULTIPLIER 2003 */ 2004 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0021); 2005 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register 2006 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd0 2007 */ 2008 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0); 2009 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1); 2010 value = (value & ~0x700) | 0x500; 2011 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value); 2012 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register 2013 * Bit[12:8](RX_VREF_CTRL) = 5'hF 2014 */ 2015 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 2016 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_LD0 Register 2017 * Bit[12:0] = 13'd1353 //VCO_LD_VAL_0 2018 */ 2019 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0549); 2020 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_REF0 Register 2021 * Bit[5:0] = 6'd41 //VCO_REF_LD_0 2022 */ 2023 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x0029); 2024 /* Set VR_XS_PMA_Gen5_12G_TX_RATE_CTRL Register 2025 * Bit[2:0] = 3'b000 //TX0_RATE 2026 */ 2027 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0); 2028 /* Set VR_XS_PMA_Gen5_12G_RX_RATE_CTRL Register 2029 * Bit[2:0] = 3'b000 //RX0_RATE 2030 */ 2031 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0); 2032 /* Set VR_XS_PMA_Gen5_12G_TX_GENCTRL2 Register Bit[9:8] = 2'b11 2033 * TX0_WIDTH: 20bits 2034 */ 2035 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0300); 2036 /* Set VR_XS_PMA_Gen5_12G_RX_GENCTRL2 Register Bit[9:8] = 2'b11 2037 * RX0_WIDTH: 20bits 2038 */ 2039 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0300); 2040 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL2 Register 2041 * Bit[10:8] = 3'b110 2042 * MPLLA_DIV16P5_CLK_EN=1 2043 * MPLLA_DIV10_CLK_EN=1 2044 * MPLLA_DIV8_CLK_EN=0 2045 */ 2046 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600); 2047 2048 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 || 2049 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) { 2050 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register 2051 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77 2052 * Bit[7:5](CTLE_POLE_0) = 3'h2 2053 * Bit[4:0](CTLE_BOOST_0) = 4'hF 2054 */ 2055 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F); 2056 2057 } else { 2058 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register 2059 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00 2060 * Bit[7:5](CTLE_POLE_0) = 3'h2 2061 * Bit[4:0](CTLE_BOOST_0) = 4'hA 2062 */ 2063 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0); 2064 value = (value & ~0xFFFF) | (2 << 5) | 0x05; 2065 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value); 2066 } 2067 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0); 2068 value = (value & ~0x7) | 0x0; 2069 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value); 2070 2071 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 || 2072 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) { 2073 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register 2074 * Bit[7:0](DFE_TAP1_0) = 8'd20 2075 */ 2076 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0014); 2077 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE); 2078 value = (value & ~0x11) | 0x11; 2079 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value); 2080 } else { 2081 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register 2082 * Bit[7:0](DFE_TAP1_0) = 8'd20 2083 */ 2084 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0xBE); 2085 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register 2086 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0 2087 */ 2088 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE); 2089 value = (value & ~0x11) | 0x0; 2090 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value); 2091 } 2092 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL); 2093 value = value & ~0x1; 2094 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, value); 2095 } else { 2096 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00 2097 * PCS_TYPE_SEL: KR 2098 */ 2099 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0x1); 2100 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0 2101 * SS13: 1G speed 2102 */ 2103 wr32_epcs(hw, SR_PMA_CTRL1, 0x0000); 2104 /* Set SR MII MMD Control Register to corresponding speed */ 2105 wr32_epcs(hw, SR_MII_MMD_CTL, 0x0140); 2106 2107 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1); 2108 value = (value & ~0x710) | 0x500; 2109 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value); 2110 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register 2111 * Bit[12:8](RX_VREF_CTRL) = 5'hF 2112 */ 2113 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 2114 2115 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 || 2116 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) { 2117 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F); 2118 } else { 2119 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register 2120 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00 2121 * Bit[7:5](CTLE_POLE_0) = 3'h2 2122 * Bit[4:0](CTLE_BOOST_0) = 4'hA 2123 */ 2124 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0); 2125 value = (value & ~0xFFFF) | 0x7706; 2126 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value); 2127 } 2128 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0); 2129 value = (value & ~0x7) | 0x0; 2130 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value); 2131 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register 2132 * Bit[7:0](DFE_TAP1_0) = 8'd00 2133 */ 2134 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0); 2135 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register 2136 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0 2137 */ 2138 value = rd32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3); 2139 value = (value & ~0x7) | 0x4; 2140 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value); 2141 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0020); 2142 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0x0046); 2143 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0540); 2144 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x002A); 2145 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0); 2146 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x0010); 2147 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x0003); 2148 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x0003); 2149 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0100); 2150 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0100); 2151 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0200); 2152 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0100); 2153 } 2154 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1 2155 * Register Bit[15](VR_RST) 2156 */ 2157 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000); 2158 2159 /* Wait phy initialization done */ 2160 for (i = 0; i < 100; i++) { 2161 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) & 2162 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0) 2163 break; 2164 msleep(100); 2165 } 2166 if (i == 100) { 2167 err = TXGBE_ERR_PHY_INIT_NOT_DONE; 2168 goto out; 2169 } 2170 2171 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) { 2172 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F; 2173 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 2174 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2175 2176 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F; 2177 value |= hw->phy.ffe_post | (1 << 6); 2178 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2179 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { 2180 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); 2181 value = (value & ~0x3F3F) | (24 << 8) | 4; 2182 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2183 2184 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 2185 value = (value & ~0x7F) | 16 | (1 << 6); 2186 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2187 } 2188 out: 2189 return err; 2190 } 2191 2192 /** 2193 * txgbe_autoc_read - Hides MAC differences needed for AUTOC read 2194 * @hw: pointer to hardware structure 2195 */ 2196 u64 txgbe_autoc_read(struct txgbe_hw *hw) 2197 { 2198 u64 autoc; 2199 u32 sr_pcs_ctl; 2200 u32 sr_pma_ctl1; 2201 u32 sr_an_ctl; 2202 u32 sr_an_adv_reg2; 2203 u8 type = hw->subsystem_device_id & 0xFF; 2204 2205 autoc = hw->mac.autoc; 2206 2207 if (hw->phy.multispeed_fiber) { 2208 autoc |= TXGBE_AUTOC_LMS_10G; 2209 } else if (type == TXGBE_DEV_ID_SFP) { 2210 autoc |= TXGBE_AUTOC_LMS_10G; 2211 autoc |= TXGBE_AUTOC_10GS_SFI; 2212 } else if (type == TXGBE_DEV_ID_QSFP) { 2213 autoc = 0; /*TBD*/ 2214 } else if (type == TXGBE_DEV_ID_XAUI || type == TXGBE_DEV_ID_SFI_XAUI) { 2215 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN; 2216 autoc |= TXGBE_AUTOC_10G_XAUI; 2217 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T; 2218 } else if (type == TXGBE_DEV_ID_SGMII) { 2219 autoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M; 2220 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T | 2221 TXGBE_PHYSICAL_LAYER_100BASE_TX; 2222 } else if (type == TXGBE_DEV_ID_MAC_XAUI) { 2223 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN; 2224 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2225 } else if (type == TXGBE_DEV_ID_MAC_SGMII) { 2226 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN; 2227 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX; 2228 } 2229 2230 if (type != TXGBE_DEV_ID_KR_KX_KX4) 2231 return autoc; 2232 2233 sr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2); 2234 sr_pma_ctl1 = rd32_epcs(hw, SR_PMA_CTRL1); 2235 sr_an_ctl = rd32_epcs(hw, SR_AN_CTRL); 2236 sr_an_adv_reg2 = rd32_epcs(hw, SR_AN_MMD_ADV_REG2); 2237 2238 if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == SR_PCS_CTRL2_TYPE_SEL_X && 2239 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX && 2240 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) { 2241 /* 1G or KX - no backplane auto-negotiation */ 2242 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN | 2243 TXGBE_AUTOC_1G_KX; 2244 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX; 2245 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == 2246 SR_PCS_CTRL2_TYPE_SEL_X && 2247 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX4 && 2248 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) { 2249 autoc |= TXGBE_AUTOC_LMS_10G | 2250 TXGBE_AUTOC_10G_KX4; 2251 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2252 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == 2253 SR_PCS_CTRL2_TYPE_SEL_R && 2254 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) { 2255 /* 10 GbE serial link (KR -no backplane auto-negotiation) */ 2256 autoc |= TXGBE_AUTOC_LMS_10G | 2257 TXGBE_AUTOC_10GS_KR; 2258 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR; 2259 } else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) { 2260 /* KX/KX4/KR backplane auto-negotiation enable */ 2261 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR) 2262 autoc |= TXGBE_AUTOC_KR_SUPP; 2263 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4) 2264 autoc |= TXGBE_AUTOC_KX4_SUPP; 2265 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX) 2266 autoc |= TXGBE_AUTOC_KX_SUPP; 2267 autoc |= TXGBE_AUTOC_LMS_KX4_KX_KR; 2268 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR | 2269 TXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 2270 TXGBE_PHYSICAL_LAYER_1000BASE_KX; 2271 } 2272 2273 return autoc; 2274 } 2275 2276 /** 2277 * txgbe_autoc_write - Hides MAC differences needed for AUTOC write 2278 * @hw: pointer to hardware structure 2279 * @autoc: value to write to AUTOC 2280 */ 2281 void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc) 2282 { 2283 bool autoneg; 2284 u32 speed; 2285 u32 mactxcfg = 0; 2286 u8 device_type = hw->subsystem_device_id & 0xFF; 2287 2288 speed = TXGBD_AUTOC_SPEED(autoc); 2289 autoc &= ~TXGBE_AUTOC_SPEED_MASK; 2290 autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false); 2291 autoc &= ~TXGBE_AUTOC_AUTONEG; 2292 2293 if (device_type == TXGBE_DEV_ID_KR_KX_KX4) { 2294 if (!autoneg) { 2295 switch (hw->phy.link_mode) { 2296 case TXGBE_PHYSICAL_LAYER_10GBASE_KR: 2297 txgbe_set_link_to_kr(hw, autoneg); 2298 break; 2299 case TXGBE_PHYSICAL_LAYER_10GBASE_KX4: 2300 txgbe_set_link_to_kx4(hw, autoneg); 2301 break; 2302 case TXGBE_PHYSICAL_LAYER_1000BASE_KX: 2303 txgbe_set_link_to_kx(hw, speed, autoneg); 2304 break; 2305 default: 2306 return; 2307 } 2308 } else { 2309 txgbe_set_link_to_kr(hw, !autoneg); 2310 } 2311 } else if (device_type == TXGBE_DEV_ID_XAUI || 2312 device_type == TXGBE_DEV_ID_SGMII || 2313 device_type == TXGBE_DEV_ID_MAC_XAUI || 2314 device_type == TXGBE_DEV_ID_MAC_SGMII || 2315 (device_type == TXGBE_DEV_ID_SFI_XAUI && 2316 hw->phy.media_type == txgbe_media_type_copper)) { 2317 if (speed == TXGBE_LINK_SPEED_10GB_FULL) { 2318 txgbe_set_link_to_kx4(hw, 0); 2319 } else { 2320 txgbe_set_link_to_kx(hw, speed, 0); 2321 if (hw->devarg.auto_neg == 1) 2322 txgbe_set_sgmii_an37_ability(hw); 2323 } 2324 } else if (hw->phy.media_type == txgbe_media_type_fiber) { 2325 txgbe_set_link_to_sfi(hw, speed); 2326 } 2327 2328 if (speed == TXGBE_LINK_SPEED_10GB_FULL) 2329 mactxcfg = TXGBE_MACTXCFG_SPEED_10G; 2330 else if (speed == TXGBE_LINK_SPEED_1GB_FULL) 2331 mactxcfg = TXGBE_MACTXCFG_SPEED_1G; 2332 2333 /* enable mac transmitter */ 2334 wr32m(hw, TXGBE_MACTXCFG, 2335 TXGBE_MACTXCFG_SPEED_MASK | TXGBE_MACTXCFG_TXE, 2336 mactxcfg | TXGBE_MACTXCFG_TXE); 2337 } 2338 2339 void txgbe_bp_down_event(struct txgbe_hw *hw) 2340 { 2341 if (!(hw->devarg.auto_neg == 1)) 2342 return; 2343 2344 BP_LOG("restart phy power.\n"); 2345 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0); 2346 wr32_epcs(hw, SR_AN_CTRL, 0); 2347 wr32_epcs(hw, VR_AN_INTR_MSK, 0); 2348 2349 msleep(1050); 2350 txgbe_set_link_to_kr(hw, 0); 2351 } 2352 2353 void txgbe_bp_mode_set(struct txgbe_hw *hw) 2354 { 2355 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) 2356 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_SFP; 2357 else if (hw->phy.ffe_set == TXGBE_BP_M_KR) 2358 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_KR_KX_KX4; 2359 else if (hw->phy.ffe_set == TXGBE_BP_M_KX4) 2360 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_XAUI; 2361 else if (hw->phy.ffe_set == TXGBE_BP_M_KX) 2362 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_SGMII; 2363 } 2364 2365 void txgbe_set_phy_temp(struct txgbe_hw *hw) 2366 { 2367 u32 value; 2368 2369 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) { 2370 BP_LOG("Set SFI TX_EQ MAIN:%d PRE:%d POST:%d\n", 2371 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); 2372 2373 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); 2374 value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) | 2375 hw->phy.ffe_pre; 2376 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2377 2378 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 2379 value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6); 2380 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2381 } 2382 2383 if (hw->phy.ffe_set == TXGBE_BP_M_KR) { 2384 BP_LOG("Set KR TX_EQ MAIN:%d PRE:%d POST:%d\n", 2385 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); 2386 value = (0x1804 & ~0x3F3F); 2387 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 2388 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2389 2390 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; 2391 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2392 wr32_epcs(hw, 0x18035, 0x00FF); 2393 wr32_epcs(hw, 0x18055, 0x00FF); 2394 } 2395 2396 if (hw->phy.ffe_set == TXGBE_BP_M_KX) { 2397 BP_LOG("Set KX TX_EQ MAIN:%d PRE:%d POST:%d\n", 2398 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); 2399 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); 2400 value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) | 2401 hw->phy.ffe_pre; 2402 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2403 2404 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 2405 value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6); 2406 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2407 2408 wr32_epcs(hw, 0x18035, 0x00FF); 2409 wr32_epcs(hw, 0x18055, 0x00FF); 2410 } 2411 } 2412 2413 /** 2414 * txgbe_kr_handle - Handle the interrupt of auto-negotiation 2415 * @hw: pointer to hardware structure 2416 */ 2417 s32 txgbe_kr_handle(struct txgbe_hw *hw) 2418 { 2419 u32 value; 2420 s32 status = 0; 2421 2422 DEBUGFUNC("txgbe_kr_handle"); 2423 2424 value = rd32_epcs(hw, VR_AN_INTR); 2425 BP_LOG("AN INTERRUPT!! value: 0x%x\n", value); 2426 if (!(value & VR_AN_INTR_PG_RCV)) { 2427 wr32_epcs(hw, VR_AN_INTR, 0); 2428 return status; 2429 } 2430 2431 status = txgbe_handle_bp_flow(0, hw); 2432 2433 return status; 2434 } 2435 2436 /** 2437 * txgbe_handle_bp_flow - Handle backplane AN73 flow 2438 * @hw: pointer to hardware structure 2439 * @link_mode: local AN73 link mode 2440 */ 2441 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw) 2442 { 2443 u32 value, i, lp_reg, ld_reg; 2444 s32 status = 0; 2445 struct txgbe_backplane_ability local_ability, lp_ability; 2446 2447 DEBUGFUNC("txgbe_handle_bp_flow"); 2448 2449 local_ability.current_link_mode = link_mode; 2450 2451 /* 1. Get the local AN73 Base Page Ability */ 2452 BP_LOG("<1>. Get the local AN73 Base Page Ability ...\n"); 2453 txgbe_get_bp_ability(&local_ability, 0, hw); 2454 2455 /* 2. Check and clear the AN73 Interrupt Status */ 2456 BP_LOG("<2>. Check the AN73 Interrupt Status ...\n"); 2457 txgbe_clear_bp_intr(2, 0, hw); 2458 2459 /* 3.1. Get the link partner AN73 Base Page Ability */ 2460 BP_LOG("<3.1>. Get the link partner AN73 Base Page Ability ...\n"); 2461 txgbe_get_bp_ability(&lp_ability, 1, hw); 2462 2463 /* 3.2. Check the AN73 Link Ability with Link Partner */ 2464 BP_LOG("<3.2>. Check the AN73 Link Ability with Link Partner ...\n"); 2465 BP_LOG(" Local Link Ability: 0x%x\n", local_ability.link_ability); 2466 BP_LOG(" Link Partner Link Ability: 0x%x\n", lp_ability.link_ability); 2467 2468 status = txgbe_check_bp_ability(&local_ability, &lp_ability, hw); 2469 2470 wr32_epcs(hw, SR_AN_CTRL, 0); 2471 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0); 2472 2473 /* 3.3. Check the FEC and KR Training for KR mode */ 2474 BP_LOG("<3.3>. Check the FEC for KR mode ...\n"); 2475 if ((local_ability.fec_ability & lp_ability.fec_ability) == 0x03) { 2476 BP_LOG("Enable the Backplane KR FEC ...\n"); 2477 wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, SR_PMA_KR_FEC_CTRL_EN); 2478 } else { 2479 BP_LOG("Backplane KR FEC is disabled.\n"); 2480 } 2481 2482 printf("Enter training.\n"); 2483 /* CL72 KR training on */ 2484 for (i = 0; i < 2; i++) { 2485 /* 3.4. Check the CL72 KR Training for KR mode */ 2486 BP_LOG("<3.4>. Check the CL72 KR Training for KR mode ...\n"); 2487 BP_LOG("==================%d==================\n", i); 2488 status = txgbe_enable_kr_training(hw); 2489 BP_LOG("Check the Clause 72 KR Training status ...\n"); 2490 status |= txgbe_check_kr_training(hw); 2491 2492 lp_reg = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); 2493 lp_reg &= SR_PMA_KR_LP_CESTS_RR; 2494 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n", 2495 lp_reg); 2496 ld_reg = rd32_epcs(hw, SR_PMA_KR_LD_CESTS); 2497 ld_reg &= SR_PMA_KR_LD_CESTS_RR; 2498 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status Register: 0x%x\n", 2499 ld_reg); 2500 if (hw->devarg.poll == 0 && status != 0) 2501 lp_reg = SR_PMA_KR_LP_CESTS_RR; 2502 2503 if (lp_reg & ld_reg) { 2504 BP_LOG("==================out==================\n"); 2505 status = txgbe_disable_kr_training(hw, 0, 0); 2506 wr32_epcs(hw, SR_AN_CTRL, 0); 2507 txgbe_clear_bp_intr(2, 0, hw); 2508 txgbe_clear_bp_intr(1, 0, hw); 2509 txgbe_clear_bp_intr(0, 0, hw); 2510 for (i = 0; i < 10; i++) { 2511 value = rd32_epcs(hw, SR_XS_PCS_KR_STS1); 2512 if (value & SR_XS_PCS_KR_STS1_PLU) { 2513 BP_LOG("\nINT_AN_INT_CMPLT =1, AN73 Done Success.\n"); 2514 wr32_epcs(hw, SR_AN_CTRL, 0); 2515 return 0; 2516 } 2517 msec_delay(10); 2518 } 2519 msec_delay(1000); 2520 txgbe_set_link_to_kr(hw, 0); 2521 2522 return 0; 2523 } 2524 2525 status |= txgbe_disable_kr_training(hw, 0, 0); 2526 } 2527 2528 txgbe_clear_bp_intr(2, 0, hw); 2529 txgbe_clear_bp_intr(1, 0, hw); 2530 txgbe_clear_bp_intr(0, 0, hw); 2531 2532 return status; 2533 } 2534 2535 /** 2536 * txgbe_get_bp_ability 2537 * @hw: pointer to hardware structure 2538 * @ability: pointer to blackplane ability structure 2539 * @link_partner: 2540 * 1: Get Link Partner Base Page 2541 * 2: Get Link Partner Next Page 2542 * (only get NXP Ability Register 1 at the moment) 2543 * 0: Get Local Device Base Page 2544 */ 2545 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability, 2546 u32 link_partner, struct txgbe_hw *hw) 2547 { 2548 u32 value = 0; 2549 2550 DEBUGFUNC("txgbe_get_bp_ability"); 2551 2552 /* Link Partner Base Page */ 2553 if (link_partner == 1) { 2554 /* Read the link partner AN73 Base Page Ability Registers */ 2555 BP_LOG("Read the link partner AN73 Base Page Ability Registers...\n"); 2556 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL1); 2557 BP_LOG("SR AN MMD LP Base Page Ability Register 1: 0x%x\n", 2558 value); 2559 ability->next_page = SR_MMD_LP_ABL1_ADV_NP(value); 2560 BP_LOG(" Next Page (bit15): %d\n", ability->next_page); 2561 2562 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL2); 2563 BP_LOG("SR AN MMD LP Base Page Ability Register 2: 0x%x\n", 2564 value); 2565 ability->link_ability = 2566 value & SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX; 2567 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n", 2568 ability->link_ability); 2569 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n"); 2570 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n"); 2571 2572 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL3); 2573 BP_LOG("SR AN MMD LP Base Page Ability Register 3: 0x%x\n", 2574 value); 2575 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01)); 2576 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01)); 2577 ability->fec_ability = SR_AN_MMD_LP_ABL3_FCE(value); 2578 } else if (link_partner == 2) { 2579 /* Read the link partner AN73 Next Page Ability Registers */ 2580 BP_LOG("\nRead the link partner AN73 Next Page Ability Registers...\n"); 2581 value = rd32_epcs(hw, SR_AN_LP_XNP_ABL1); 2582 BP_LOG(" SR AN MMD LP XNP Ability Register 1: 0x%x\n", value); 2583 ability->next_page = SR_AN_LP_XNP_ABL1_NP(value); 2584 BP_LOG(" Next Page (bit15): %d\n", ability->next_page); 2585 } else { 2586 /* Read the local AN73 Base Page Ability Registers */ 2587 BP_LOG("Read the local AN73 Base Page Ability Registers...\n"); 2588 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1); 2589 BP_LOG("SR AN MMD Advertisement Register 1: 0x%x\n", value); 2590 ability->next_page = SR_AN_MMD_ADV_REG1_NP(value); 2591 BP_LOG(" Next Page (bit15): %d\n", ability->next_page); 2592 2593 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG2); 2594 BP_LOG("SR AN MMD Advertisement Register 2: 0x%x\n", value); 2595 ability->link_ability = 2596 value & SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX; 2597 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n", 2598 ability->link_ability); 2599 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n"); 2600 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n"); 2601 2602 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG3); 2603 BP_LOG("SR AN MMD Advertisement Register 3: 0x%x\n", value); 2604 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01)); 2605 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01)); 2606 ability->fec_ability = SR_AN_MMD_ADV_REG3_FCE(value); 2607 } 2608 2609 BP_LOG("done.\n"); 2610 } 2611 2612 /** 2613 * txgbe_check_bp_ability 2614 * @hw: pointer to hardware structure 2615 * @ability: pointer to blackplane ability structure 2616 */ 2617 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability, 2618 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw) 2619 { 2620 u32 com_link_abi; 2621 s32 ret = 0; 2622 2623 DEBUGFUNC("txgbe_check_bp_ability"); 2624 2625 com_link_abi = local_ability->link_ability & lp_ability->link_ability; 2626 BP_LOG("com_link_abi = 0x%x, local_ability = 0x%x, lp_ability = 0x%x\n", 2627 com_link_abi, local_ability->link_ability, 2628 lp_ability->link_ability); 2629 2630 if (!com_link_abi) { 2631 BP_LOG("The Link Partner does not support any compatible speed mode.\n"); 2632 ret = -1; 2633 } else if (com_link_abi & BP_TYPE_KR) { 2634 if (local_ability->current_link_mode) { 2635 BP_LOG("Link mode is not matched with Link Partner: [LINK_KR].\n"); 2636 BP_LOG("Set the local link mode to [LINK_KR] ...\n"); 2637 txgbe_set_link_to_kr(hw, 0); 2638 ret = 1; 2639 } else { 2640 BP_LOG("Link mode is matched with Link Partner: [LINK_KR].\n"); 2641 ret = 0; 2642 } 2643 } else if (com_link_abi & BP_TYPE_KX4) { 2644 if (local_ability->current_link_mode == 0x10) { 2645 BP_LOG("Link mode is matched with Link Partner: [LINK_KX4].\n"); 2646 ret = 0; 2647 } else { 2648 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX4].\n"); 2649 BP_LOG("Set the local link mode to [LINK_KX4] ...\n"); 2650 txgbe_set_link_to_kx4(hw, 1); 2651 ret = 1; 2652 } 2653 } else if (com_link_abi & BP_TYPE_KX) { 2654 if (local_ability->current_link_mode == 0x1) { 2655 BP_LOG("Link mode is matched with Link Partner: [LINK_KX].\n"); 2656 ret = 0; 2657 } else { 2658 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX].\n"); 2659 BP_LOG("Set the local link mode to [LINK_KX] ...\n"); 2660 txgbe_set_link_to_kx(hw, 1, 1); 2661 ret = 1; 2662 } 2663 } 2664 2665 return ret; 2666 } 2667 2668 /** 2669 * txgbe_clear_bp_intr 2670 * @hw: pointer to hardware structure 2671 * @index: the bit will be cleared 2672 * @index_high: 2673 * index_high = 0: Only the index bit will be cleared 2674 * index_high != 0: the [index_high, index] range will be cleared 2675 */ 2676 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw) 2677 { 2678 u32 rdata = 0, wdata, i; 2679 2680 DEBUGFUNC("txgbe_clear_bp_intr"); 2681 2682 rdata = rd32_epcs(hw, VR_AN_INTR); 2683 BP_LOG("[Before clear]Read VR AN MMD Interrupt Register: 0x%x\n", 2684 rdata); 2685 BP_LOG("Interrupt: 0- AN_INT_CMPLT, 1- AN_INC_LINK, 2- AN_PG_RCV\n\n"); 2686 2687 wdata = rdata; 2688 if (bit_high) { 2689 for (i = bit; i <= bit_high; i++) 2690 wdata &= ~(1 << i); 2691 } else { 2692 wdata &= ~(1 << bit); 2693 } 2694 2695 wr32_epcs(hw, VR_AN_INTR, wdata); 2696 2697 rdata = rd32_epcs(hw, VR_AN_INTR); 2698 BP_LOG("[After clear]Read VR AN MMD Interrupt Register: 0x%x\n", rdata); 2699 } 2700 2701 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw) 2702 { 2703 s32 status = 0; 2704 u32 value = 0; 2705 2706 DEBUGFUNC("txgbe_enable_kr_training"); 2707 2708 BP_LOG("Enable Clause 72 KR Training ...\n"); 2709 2710 if (CL72_KRTR_PRBS_MODE_EN != 0xFFFF) { 2711 /* Set PRBS Timer Duration Control to maximum 6.7ms in 2712 * VR_PMA_KRTR_PRBS_CTRL2 Register 2713 */ 2714 value = CL72_KRTR_PRBS_MODE_EN; 2715 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL2, value); 2716 /* Set PRBS Timer Duration Control to maximum 6.7ms in 2717 * VR_PMA_KRTR_PRBS_CTRL1 Register 2718 */ 2719 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL1, 2720 VR_PMA_KRTR_PRBS_TIME_LMT); 2721 /* Enable PRBS Mode to determine KR Training Status by setting 2722 * Bit 0 of VR_PMA_KRTR_PRBS_CTRL0 Register 2723 */ 2724 value = VR_PMA_KRTR_PRBS_MODE_EN; 2725 } 2726 #ifdef CL72_KRTR_PRBS31_EN 2727 /* Enable PRBS Mode to determine KR Training Status by setting 2728 * Bit 1 of VR_PMA_KRTR_PRBS_CTRL0 Register 2729 */ 2730 value = VR_PMA_KRTR_PRBS31_EN; 2731 #endif 2732 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL0, value); 2733 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */ 2734 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); 2735 2736 /* Enable the Clause 72 start-up protocol 2737 * by setting Bit 1 of SR_PMA_KR_PMD_CTRL Register. 2738 * Restart the Clause 72 start-up protocol 2739 * by setting Bit 0 of SR_PMA_KR_PMD_CTRL Register. 2740 */ 2741 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, 2742 SR_PMA_KR_PMD_CTRL_EN_TR | SR_PMA_KR_PMD_CTRL_RS_TR); 2743 2744 return status; 2745 } 2746 2747 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode) 2748 { 2749 s32 status = 0; 2750 2751 DEBUGFUNC("txgbe_disable_kr_training"); 2752 2753 BP_LOG("Disable Clause 72 KR Training ...\n"); 2754 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */ 2755 txgbe_read_phy_lane_tx_eq(0, hw, post, mode); 2756 2757 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, SR_PMA_KR_PMD_CTRL_RS_TR); 2758 2759 return status; 2760 } 2761 2762 static s32 txgbe_check_kr_training(struct txgbe_hw *hw) 2763 { 2764 s32 status = 0; 2765 u32 value, test; 2766 int i; 2767 int times = hw->devarg.poll ? 35 : 20; 2768 2769 DEBUGFUNC("txgbe_check_kr_training"); 2770 2771 for (i = 0; i < times; i++) { 2772 value = rd32_epcs(hw, SR_PMA_KR_LP_CEU); 2773 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Update Register: 0x%x\n", 2774 value); 2775 value = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); 2776 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n", 2777 value); 2778 value = rd32_epcs(hw, SR_PMA_KR_LD_CEU); 2779 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Update: 0x%x\n", 2780 value); 2781 value = rd32_epcs(hw, SR_PMA_KR_LD_CESTS); 2782 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status: 0x%x\n", 2783 value); 2784 value = rd32_epcs(hw, SR_PMA_KR_PMD_STS); 2785 BP_LOG("SR PMA MMD 10GBASE-KR Status Register: 0x%x\n", value); 2786 BP_LOG(" Training Failure (bit3): %d\n", 2787 ((value >> 3) & 0x01)); 2788 BP_LOG(" Start-Up Protocol Status (bit2): %d\n", 2789 ((value >> 2) & 0x01)); 2790 BP_LOG(" Frame Lock (bit1): %d\n", 2791 ((value >> 1) & 0x01)); 2792 BP_LOG(" Receiver Status (bit0): %d\n", 2793 ((value >> 0) & 0x01)); 2794 2795 test = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); 2796 if (test & SR_PMA_KR_LP_CESTS_RR) { 2797 BP_LOG("TEST Coefficient Status Register: 0x%x\n", 2798 test); 2799 status = 1; 2800 } 2801 2802 if (value & SR_PMA_KR_PMD_STS_TR_FAIL) { 2803 BP_LOG("Training is completed with failure.\n"); 2804 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); 2805 return 0; 2806 } 2807 2808 if (value & SR_PMA_KR_PMD_STS_RCV) { 2809 BP_LOG("Receiver trained and ready to receive data.\n"); 2810 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); 2811 return 0; 2812 } 2813 2814 msec_delay(20); 2815 } 2816 2817 BP_LOG("ERROR: Check Clause 72 KR Training Complete Timeout.\n"); 2818 return status; 2819 } 2820 2821 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw, 2822 s32 post, s32 mode) 2823 { 2824 u32 value = 0; 2825 u32 addr; 2826 u32 tx_main_cursor, tx_pre_cursor, tx_post_cursor, lmain; 2827 2828 DEBUGFUNC("txgbe_read_phy_lane_tx_eq"); 2829 2830 addr = TXGBE_PHY_LANE0_TX_EQ_CTL1 | (lane << 8); 2831 value = rd32_ephy(hw, addr); 2832 BP_LOG("PHY LANE TX EQ Read Value: %x\n", lane); 2833 tx_main_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(value); 2834 BP_LOG("TX_MAIN_CURSOR: %x\n", tx_main_cursor); 2835 UNREFERENCED_PARAMETER(tx_main_cursor); 2836 2837 addr = TXGBE_PHY_LANE0_TX_EQ_CTL2 | (lane << 8); 2838 value = rd32_ephy(hw, addr); 2839 tx_pre_cursor = value & TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE; 2840 tx_post_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(value); 2841 BP_LOG("TX_PRE_CURSOR: %x\n", tx_pre_cursor); 2842 BP_LOG("TX_POST_CURSOR: %x\n", tx_post_cursor); 2843 2844 if (mode == 1) { 2845 lmain = 160 - tx_pre_cursor - tx_post_cursor; 2846 if (lmain < 88) 2847 lmain = 88; 2848 2849 if (post) 2850 tx_post_cursor = post; 2851 2852 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL1, tx_post_cursor); 2853 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL0, 2854 tx_pre_cursor | (lmain << 8)); 2855 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 2856 value &= ~TXGBE_PHY_TX_EQ_CTL1_DEF; 2857 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2858 } 2859 } 2860