1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Marvell International Ltd. 3 * Copyright(c) 2017 Semihalf. 4 * All rights reserved. 5 */ 6 7 #ifndef _MRVL_ETHDEV_H_ 8 #define _MRVL_ETHDEV_H_ 9 10 #include <rte_spinlock.h> 11 #include <rte_flow_driver.h> 12 #include <rte_mtr_driver.h> 13 14 /* 15 * container_of is defined by both DPDK and MUSDK, 16 * we'll declare only one version. 17 * 18 * Note that it is not used in this PMD anyway. 19 */ 20 #ifdef container_of 21 #undef container_of 22 #endif 23 24 #include <env/mv_autogen_comp_flags.h> 25 #include <drivers/mv_pp2.h> 26 #include <drivers/mv_pp2_bpool.h> 27 #include <drivers/mv_pp2_cls.h> 28 #include <drivers/mv_pp2_hif.h> 29 #include <drivers/mv_pp2_ppio.h> 30 #include "env/mv_common.h" /* for BIT() */ 31 32 /** Maximum number of rx queues per port */ 33 #define MRVL_PP2_RXQ_MAX 32 34 35 /** Maximum number of tx queues per port */ 36 #define MRVL_PP2_TXQ_MAX 8 37 38 /** Minimum number of descriptors in tx queue */ 39 #define MRVL_PP2_TXD_MIN 16 40 41 /** Maximum number of descriptors in tx queue */ 42 #define MRVL_PP2_TXD_MAX 2048 43 44 /** Tx queue descriptors alignment */ 45 #define MRVL_PP2_TXD_ALIGN 16 46 47 /** Minimum number of descriptors in rx queue */ 48 #define MRVL_PP2_RXD_MIN 16 49 50 /** Maximum number of descriptors in rx queue */ 51 #define MRVL_PP2_RXD_MAX 2048 52 53 /** Rx queue descriptors alignment */ 54 #define MRVL_PP2_RXD_ALIGN 16 55 56 /** Maximum number of descriptors in tx aggregated queue */ 57 #define MRVL_PP2_AGGR_TXQD_MAX 2048 58 59 /** Maximum number of Traffic Classes. */ 60 #define MRVL_PP2_TC_MAX 8 61 62 /** Packet offset inside RX buffer. */ 63 #define MRVL_PKT_OFFS 64 64 65 /** Maximum number of descriptors in shadow queue. Must be power of 2 */ 66 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX 67 68 /** Shadow queue size mask (since shadow queue size is power of 2) */ 69 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1) 70 71 /** Minimum number of sent buffers to release from shadow queue to BM */ 72 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64 73 74 /** Maximum length of a match string */ 75 #define MRVL_MATCH_LEN 16 76 77 /** Parsed fields in processed rte_flow_item. */ 78 enum mrvl_parsed_fields { 79 /* eth flags */ 80 F_DMAC = BIT(0), 81 F_SMAC = BIT(1), 82 F_TYPE = BIT(2), 83 /* vlan flags */ 84 F_VLAN_PRI = BIT(3), 85 F_VLAN_ID = BIT(4), 86 F_VLAN_TCI = BIT(5), /* not supported by MUSDK yet */ 87 /* ip4 flags */ 88 F_IP4_TOS = BIT(6), 89 F_IP4_SIP = BIT(7), 90 F_IP4_DIP = BIT(8), 91 F_IP4_PROTO = BIT(9), 92 /* ip6 flags */ 93 F_IP6_TC = BIT(10), /* not supported by MUSDK yet */ 94 F_IP6_SIP = BIT(11), 95 F_IP6_DIP = BIT(12), 96 F_IP6_FLOW = BIT(13), 97 F_IP6_NEXT_HDR = BIT(14), 98 /* tcp flags */ 99 F_TCP_SPORT = BIT(15), 100 F_TCP_DPORT = BIT(16), 101 /* udp flags */ 102 F_UDP_SPORT = BIT(17), 103 F_UDP_DPORT = BIT(18), 104 }; 105 106 /** PMD-specific definition of a flow rule handle. */ 107 struct mrvl_mtr; 108 struct rte_flow { 109 LIST_ENTRY(rte_flow) next; 110 struct mrvl_mtr *mtr; 111 112 enum mrvl_parsed_fields pattern; 113 114 struct pp2_cls_tbl_rule rule; 115 struct pp2_cls_cos_desc cos; 116 struct pp2_cls_tbl_action action; 117 }; 118 119 struct mrvl_mtr_profile { 120 LIST_ENTRY(mrvl_mtr_profile) next; 121 uint32_t profile_id; 122 int refcnt; 123 struct rte_mtr_meter_profile profile; 124 }; 125 126 struct mrvl_mtr { 127 LIST_ENTRY(mrvl_mtr) next; 128 uint32_t mtr_id; 129 int refcnt; 130 int shared; 131 int enabled; 132 int plcr_bit; 133 struct mrvl_mtr_profile *profile; 134 struct pp2_cls_plcr *plcr; 135 }; 136 137 struct mrvl_priv { 138 /* Hot fields, used in fast path. */ 139 struct pp2_bpool *bpool; /**< BPool pointer */ 140 struct pp2_ppio *ppio; /**< Port handler pointer */ 141 rte_spinlock_t lock; /**< Spinlock for checking bpool status */ 142 uint16_t bpool_max_size; /**< BPool maximum size */ 143 uint16_t bpool_min_size; /**< BPool minimum size */ 144 uint16_t bpool_init_size; /**< Configured BPool size */ 145 146 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */ 147 struct { 148 uint8_t tc; /**< Traffic Class */ 149 uint8_t inq; /**< Relative in-queue number */ 150 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned; 151 152 /* Configuration data, used sporadically. */ 153 uint8_t pp_id; 154 uint8_t ppio_id; 155 uint8_t bpool_bit; 156 uint8_t rss_hf_tcp; 157 uint8_t uc_mc_flushed; 158 uint8_t vlan_flushed; 159 uint8_t isolated; 160 161 struct pp2_ppio_params ppio_params; 162 struct pp2_cls_qos_tbl_params qos_tbl_params; 163 struct pp2_cls_tbl *qos_tbl; 164 uint16_t nb_rx_queues; 165 166 struct pp2_cls_tbl_params cls_tbl_params; 167 struct pp2_cls_tbl *cls_tbl; 168 uint32_t cls_tbl_pattern; 169 LIST_HEAD(mrvl_flows, rte_flow) flows; 170 171 struct pp2_cls_plcr *policer; 172 173 LIST_HEAD(profiles, mrvl_mtr_profile) profiles; 174 LIST_HEAD(mtrs, mrvl_mtr) mtrs; 175 uint32_t used_plcrs; 176 }; 177 178 /** Flow operations forward declaration. */ 179 extern const struct rte_flow_ops mrvl_flow_ops; 180 181 /** Meter operations forward declaration. */ 182 extern const struct rte_mtr_ops mrvl_mtr_ops; 183 184 /** Current log type. */ 185 extern int mrvl_logtype; 186 187 #define MRVL_LOG(level, fmt, args...) \ 188 rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \ 189 __func__, ##args) 190 191 #endif /* _MRVL_ETHDEV_H_ */ 192