1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Marvell International Ltd. 3 * Copyright(c) 2017 Semihalf. 4 * All rights reserved. 5 */ 6 7 #ifndef _MRVL_ETHDEV_H_ 8 #define _MRVL_ETHDEV_H_ 9 10 #include <rte_spinlock.h> 11 #include <rte_flow_driver.h> 12 13 #include <env/mv_autogen_comp_flags.h> 14 #include <drivers/mv_pp2.h> 15 #include <drivers/mv_pp2_bpool.h> 16 #include <drivers/mv_pp2_cls.h> 17 #include <drivers/mv_pp2_hif.h> 18 #include <drivers/mv_pp2_ppio.h> 19 20 /** Maximum number of rx queues per port */ 21 #define MRVL_PP2_RXQ_MAX 32 22 23 /** Maximum number of tx queues per port */ 24 #define MRVL_PP2_TXQ_MAX 8 25 26 /** Minimum number of descriptors in tx queue */ 27 #define MRVL_PP2_TXD_MIN 16 28 29 /** Maximum number of descriptors in tx queue */ 30 #define MRVL_PP2_TXD_MAX 2048 31 32 /** Tx queue descriptors alignment */ 33 #define MRVL_PP2_TXD_ALIGN 16 34 35 /** Minimum number of descriptors in rx queue */ 36 #define MRVL_PP2_RXD_MIN 16 37 38 /** Maximum number of descriptors in rx queue */ 39 #define MRVL_PP2_RXD_MAX 2048 40 41 /** Rx queue descriptors alignment */ 42 #define MRVL_PP2_RXD_ALIGN 16 43 44 /** Maximum number of descriptors in tx aggregated queue */ 45 #define MRVL_PP2_AGGR_TXQD_MAX 2048 46 47 /** Maximum number of Traffic Classes. */ 48 #define MRVL_PP2_TC_MAX 8 49 50 /** Packet offset inside RX buffer. */ 51 #define MRVL_PKT_OFFS 64 52 53 /** Maximum number of descriptors in shadow queue. Must be power of 2 */ 54 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX 55 56 /** Shadow queue size mask (since shadow queue size is power of 2) */ 57 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1) 58 59 /** Minimum number of sent buffers to release from shadow queue to BM */ 60 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64 61 62 struct mrvl_priv { 63 /* Hot fields, used in fast path. */ 64 struct pp2_bpool *bpool; /**< BPool pointer */ 65 struct pp2_ppio *ppio; /**< Port handler pointer */ 66 rte_spinlock_t lock; /**< Spinlock for checking bpool status */ 67 uint16_t bpool_max_size; /**< BPool maximum size */ 68 uint16_t bpool_min_size; /**< BPool minimum size */ 69 uint16_t bpool_init_size; /**< Configured BPool size */ 70 71 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */ 72 struct { 73 uint8_t tc; /**< Traffic Class */ 74 uint8_t inq; /**< Relative in-queue number */ 75 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned; 76 77 /* Configuration data, used sporadically. */ 78 uint8_t pp_id; 79 uint8_t ppio_id; 80 uint8_t bpool_bit; 81 uint8_t rss_hf_tcp; 82 uint8_t uc_mc_flushed; 83 uint8_t vlan_flushed; 84 uint8_t isolated; 85 86 struct pp2_ppio_params ppio_params; 87 struct pp2_cls_qos_tbl_params qos_tbl_params; 88 struct pp2_cls_tbl *qos_tbl; 89 uint16_t nb_rx_queues; 90 91 struct pp2_cls_tbl_params cls_tbl_params; 92 struct pp2_cls_tbl *cls_tbl; 93 uint32_t cls_tbl_pattern; 94 LIST_HEAD(mrvl_flows, rte_flow) flows; 95 96 struct pp2_cls_plcr *policer; 97 }; 98 99 /** Flow operations forward declaration. */ 100 extern const struct rte_flow_ops mrvl_flow_ops; 101 #endif /* _MRVL_ETHDEV_H_ */ 102