1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Marvell International Ltd. 3 * Copyright(c) 2017 Semihalf. 4 * All rights reserved. 5 */ 6 7 #ifndef _MRVL_ETHDEV_H_ 8 #define _MRVL_ETHDEV_H_ 9 10 #include <rte_spinlock.h> 11 #include <rte_flow_driver.h> 12 #include <rte_mtr_driver.h> 13 #include <rte_tm_driver.h> 14 15 /* 16 * container_of is defined by both DPDK and MUSDK, 17 * we'll declare only one version. 18 * 19 * Note that it is not used in this PMD anyway. 20 */ 21 #ifdef container_of 22 #undef container_of 23 #endif 24 25 #include <env/mv_autogen_comp_flags.h> 26 #include <drivers/mv_pp2.h> 27 #include <drivers/mv_pp2_bpool.h> 28 #include <drivers/mv_pp2_cls.h> 29 #include <drivers/mv_pp2_hif.h> 30 #include <drivers/mv_pp2_ppio.h> 31 #include "env/mv_common.h" /* for BIT() */ 32 33 /** Maximum number of rx queues per port */ 34 #define MRVL_PP2_RXQ_MAX 32 35 36 /** Maximum number of tx queues per port */ 37 #define MRVL_PP2_TXQ_MAX 8 38 39 /** Minimum number of descriptors in tx queue */ 40 #define MRVL_PP2_TXD_MIN 16 41 42 /** Maximum number of descriptors in tx queue */ 43 #define MRVL_PP2_TXD_MAX 2048 44 45 /** Tx queue descriptors alignment */ 46 #define MRVL_PP2_TXD_ALIGN 16 47 48 /** Minimum number of descriptors in rx queue */ 49 #define MRVL_PP2_RXD_MIN 16 50 51 /** Maximum number of descriptors in rx queue */ 52 #define MRVL_PP2_RXD_MAX 2048 53 54 /** Rx queue descriptors alignment */ 55 #define MRVL_PP2_RXD_ALIGN 16 56 57 /** Maximum number of descriptors in tx aggregated queue */ 58 #define MRVL_PP2_AGGR_TXQD_MAX 2048 59 60 /** Maximum number of Traffic Classes. */ 61 #define MRVL_PP2_TC_MAX 8 62 63 /** Packet offset inside RX buffer. */ 64 #define MRVL_PKT_OFFS 64 65 66 /** Maximum number of descriptors in shadow queue. Must be power of 2 */ 67 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX 68 69 /** Shadow queue size mask (since shadow queue size is power of 2) */ 70 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1) 71 72 /** Minimum number of sent buffers to release from shadow queue to BM */ 73 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64 74 75 #define MRVL_PP2_VLAN_TAG_LEN 4 76 #define MRVL_PP2_ETH_HDRS_LEN (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \ 77 (2 * MRVL_PP2_VLAN_TAG_LEN)) 78 #define MRVL_PP2_HDRS_LEN (MV_MH_SIZE + MRVL_PP2_ETH_HDRS_LEN) 79 #define MRVL_PP2_MTU_TO_MRU(mtu) ((mtu) + MRVL_PP2_HDRS_LEN) 80 #define MRVL_PP2_MRU_TO_MTU(mru) ((mru) - MRVL_PP2_HDRS_LEN) 81 82 /** Maximum length of a match string */ 83 #define MRVL_MATCH_LEN 16 84 85 /** PMD-specific definition of a flow rule handle. */ 86 struct mrvl_mtr; 87 struct rte_flow { 88 LIST_ENTRY(rte_flow) next; 89 struct mrvl_mtr *mtr; 90 91 struct pp2_cls_tbl_key table_key; 92 struct pp2_cls_tbl_rule rule; 93 struct pp2_cls_cos_desc cos; 94 struct pp2_cls_tbl_action action; 95 }; 96 97 struct mrvl_mtr_profile { 98 LIST_ENTRY(mrvl_mtr_profile) next; 99 uint32_t profile_id; 100 int refcnt; 101 struct rte_mtr_meter_profile profile; 102 }; 103 104 struct mrvl_mtr { 105 LIST_ENTRY(mrvl_mtr) next; 106 uint32_t mtr_id; 107 int refcnt; 108 int shared; 109 int enabled; 110 int plcr_bit; 111 struct mrvl_mtr_profile *profile; 112 struct pp2_cls_plcr *plcr; 113 }; 114 115 struct mrvl_tm_shaper_profile { 116 LIST_ENTRY(mrvl_tm_shaper_profile) next; 117 uint32_t id; 118 int refcnt; 119 struct rte_tm_shaper_params params; 120 }; 121 122 enum { 123 MRVL_NODE_PORT, 124 MRVL_NODE_QUEUE, 125 }; 126 127 struct mrvl_tm_node { 128 LIST_ENTRY(mrvl_tm_node) next; 129 uint32_t id; 130 uint32_t type; 131 int refcnt; 132 struct mrvl_tm_node *parent; 133 struct mrvl_tm_shaper_profile *profile; 134 uint8_t weight; 135 uint64_t stats_mask; 136 }; 137 138 struct mrvl_priv { 139 /* Hot fields, used in fast path. */ 140 struct pp2_bpool *bpool; /**< BPool pointer */ 141 struct pp2_ppio *ppio; /**< Port handler pointer */ 142 rte_spinlock_t lock; /**< Spinlock for checking bpool status */ 143 uint16_t bpool_max_size; /**< BPool maximum size */ 144 uint16_t bpool_min_size; /**< BPool minimum size */ 145 uint16_t bpool_init_size; /**< Configured BPool size */ 146 147 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */ 148 struct { 149 uint8_t tc; /**< Traffic Class */ 150 uint8_t inq; /**< Relative in-queue number */ 151 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned; 152 153 /* Configuration data, used sporadically. */ 154 uint8_t pp_id; 155 uint8_t ppio_id; 156 uint8_t bpool_bit; 157 uint8_t rss_hf_tcp; 158 uint8_t uc_mc_flushed; 159 uint8_t isolated; 160 uint8_t multiseg; 161 162 struct pp2_ppio_params ppio_params; 163 struct pp2_cls_qos_tbl_params qos_tbl_params; 164 struct pp2_cls_tbl *qos_tbl; 165 uint16_t nb_rx_queues; 166 167 struct pp2_cls_tbl_params cls_tbl_params; 168 struct pp2_cls_tbl *cls_tbl; 169 LIST_HEAD(mrvl_flows, rte_flow) flows; 170 171 struct pp2_cls_plcr *default_policer; 172 173 LIST_HEAD(profiles, mrvl_mtr_profile) profiles; 174 LIST_HEAD(mtrs, mrvl_mtr) mtrs; 175 uint32_t used_plcrs; 176 177 LIST_HEAD(shaper_profiles, mrvl_tm_shaper_profile) shaper_profiles; 178 LIST_HEAD(nodes, mrvl_tm_node) nodes; 179 uint64_t rate_max; 180 }; 181 182 /** Flow operations forward declaration. */ 183 extern const struct rte_flow_ops mrvl_flow_ops; 184 185 /** Meter operations forward declaration. */ 186 extern const struct rte_mtr_ops mrvl_mtr_ops; 187 188 /** Traffic manager operations forward declaration. */ 189 extern const struct rte_tm_ops mrvl_tm_ops; 190 191 /** Current log type. */ 192 extern int mrvl_logtype; 193 194 #define MRVL_LOG(level, fmt, args...) \ 195 rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \ 196 __func__, ##args) 197 198 #endif /* _MRVL_ETHDEV_H_ */ 199