1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Marvell International Ltd. 3 * Copyright(c) 2017 Semihalf. 4 * All rights reserved. 5 */ 6 7 #ifndef _MRVL_ETHDEV_H_ 8 #define _MRVL_ETHDEV_H_ 9 10 #include <rte_spinlock.h> 11 #include <rte_flow_driver.h> 12 #include <rte_mtr_driver.h> 13 #include <rte_tm_driver.h> 14 15 /* 16 * container_of is defined by both DPDK and MUSDK, 17 * we'll declare only one version. 18 * 19 * Note that it is not used in this PMD anyway. 20 */ 21 #ifdef container_of 22 #undef container_of 23 #endif 24 25 #include <env/mv_autogen_comp_flags.h> 26 #include <drivers/mv_pp2.h> 27 #include <drivers/mv_pp2_bpool.h> 28 #include <drivers/mv_pp2_cls.h> 29 #include <drivers/mv_pp2_hif.h> 30 #include <drivers/mv_pp2_ppio.h> 31 #include "env/mv_common.h" /* for BIT() */ 32 33 /** Maximum number of rx queues per port */ 34 #define MRVL_PP2_RXQ_MAX 32 35 36 /** Maximum number of tx queues per port */ 37 #define MRVL_PP2_TXQ_MAX 8 38 39 /** Minimum number of descriptors in tx queue */ 40 #define MRVL_PP2_TXD_MIN 16 41 42 /** Maximum number of descriptors in tx queue */ 43 #define MRVL_PP2_TXD_MAX 2048 44 45 /** Tx queue descriptors alignment */ 46 #define MRVL_PP2_TXD_ALIGN 16 47 48 /** Minimum number of descriptors in rx queue */ 49 #define MRVL_PP2_RXD_MIN 16 50 51 /** Maximum number of descriptors in rx queue */ 52 #define MRVL_PP2_RXD_MAX 2048 53 54 /** Rx queue descriptors alignment */ 55 #define MRVL_PP2_RXD_ALIGN 16 56 57 /** Maximum number of descriptors in tx aggregated queue */ 58 #define MRVL_PP2_AGGR_TXQD_MAX 2048 59 60 /** Maximum number of Traffic Classes. */ 61 #define MRVL_PP2_TC_MAX 8 62 63 /** Packet offset inside RX buffer. */ 64 #define MRVL_PKT_OFFS 64 65 66 /** Maximum number of descriptors in shadow queue. Must be power of 2 */ 67 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX 68 69 /** Shadow queue size mask (since shadow queue size is power of 2) */ 70 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1) 71 72 /** Minimum number of sent buffers to release from shadow queue to BM */ 73 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64 74 75 /** Maximum length of a match string */ 76 #define MRVL_MATCH_LEN 16 77 78 /** Parsed fields in processed rte_flow_item. */ 79 enum mrvl_parsed_fields { 80 /* eth flags */ 81 F_DMAC = BIT(0), 82 F_SMAC = BIT(1), 83 F_TYPE = BIT(2), 84 /* vlan flags */ 85 F_VLAN_PRI = BIT(3), 86 F_VLAN_ID = BIT(4), 87 F_VLAN_TCI = BIT(5), /* not supported by MUSDK yet */ 88 /* ip4 flags */ 89 F_IP4_TOS = BIT(6), 90 F_IP4_SIP = BIT(7), 91 F_IP4_DIP = BIT(8), 92 F_IP4_PROTO = BIT(9), 93 /* ip6 flags */ 94 F_IP6_TC = BIT(10), /* not supported by MUSDK yet */ 95 F_IP6_SIP = BIT(11), 96 F_IP6_DIP = BIT(12), 97 F_IP6_FLOW = BIT(13), 98 F_IP6_NEXT_HDR = BIT(14), 99 /* tcp flags */ 100 F_TCP_SPORT = BIT(15), 101 F_TCP_DPORT = BIT(16), 102 /* udp flags */ 103 F_UDP_SPORT = BIT(17), 104 F_UDP_DPORT = BIT(18), 105 }; 106 107 /** PMD-specific definition of a flow rule handle. */ 108 struct mrvl_mtr; 109 struct rte_flow { 110 LIST_ENTRY(rte_flow) next; 111 struct mrvl_mtr *mtr; 112 113 enum mrvl_parsed_fields pattern; 114 115 struct pp2_cls_tbl_rule rule; 116 struct pp2_cls_cos_desc cos; 117 struct pp2_cls_tbl_action action; 118 }; 119 120 struct mrvl_mtr_profile { 121 LIST_ENTRY(mrvl_mtr_profile) next; 122 uint32_t profile_id; 123 int refcnt; 124 struct rte_mtr_meter_profile profile; 125 }; 126 127 struct mrvl_mtr { 128 LIST_ENTRY(mrvl_mtr) next; 129 uint32_t mtr_id; 130 int refcnt; 131 int shared; 132 int enabled; 133 int plcr_bit; 134 struct mrvl_mtr_profile *profile; 135 struct pp2_cls_plcr *plcr; 136 }; 137 138 struct mrvl_tm_shaper_profile { 139 LIST_ENTRY(mrvl_tm_shaper_profile) next; 140 uint32_t id; 141 int refcnt; 142 struct rte_tm_shaper_params params; 143 }; 144 145 enum { 146 MRVL_NODE_PORT, 147 MRVL_NODE_QUEUE, 148 }; 149 150 struct mrvl_tm_node { 151 LIST_ENTRY(mrvl_tm_node) next; 152 uint32_t id; 153 uint32_t type; 154 int refcnt; 155 struct mrvl_tm_node *parent; 156 struct mrvl_tm_shaper_profile *profile; 157 uint8_t weight; 158 uint64_t stats_mask; 159 }; 160 161 struct mrvl_priv { 162 /* Hot fields, used in fast path. */ 163 struct pp2_bpool *bpool; /**< BPool pointer */ 164 struct pp2_ppio *ppio; /**< Port handler pointer */ 165 rte_spinlock_t lock; /**< Spinlock for checking bpool status */ 166 uint16_t bpool_max_size; /**< BPool maximum size */ 167 uint16_t bpool_min_size; /**< BPool minimum size */ 168 uint16_t bpool_init_size; /**< Configured BPool size */ 169 170 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */ 171 struct { 172 uint8_t tc; /**< Traffic Class */ 173 uint8_t inq; /**< Relative in-queue number */ 174 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned; 175 176 /* Configuration data, used sporadically. */ 177 uint8_t pp_id; 178 uint8_t ppio_id; 179 uint8_t bpool_bit; 180 uint8_t rss_hf_tcp; 181 uint8_t uc_mc_flushed; 182 uint8_t vlan_flushed; 183 uint8_t isolated; 184 185 struct pp2_ppio_params ppio_params; 186 struct pp2_cls_qos_tbl_params qos_tbl_params; 187 struct pp2_cls_tbl *qos_tbl; 188 uint16_t nb_rx_queues; 189 190 struct pp2_cls_tbl_params cls_tbl_params; 191 struct pp2_cls_tbl *cls_tbl; 192 uint32_t cls_tbl_pattern; 193 LIST_HEAD(mrvl_flows, rte_flow) flows; 194 195 struct pp2_cls_plcr *default_policer; 196 197 LIST_HEAD(profiles, mrvl_mtr_profile) profiles; 198 LIST_HEAD(mtrs, mrvl_mtr) mtrs; 199 uint32_t used_plcrs; 200 201 LIST_HEAD(shaper_profiles, mrvl_tm_shaper_profile) shaper_profiles; 202 LIST_HEAD(nodes, mrvl_tm_node) nodes; 203 uint64_t rate_max; 204 }; 205 206 /** Flow operations forward declaration. */ 207 extern const struct rte_flow_ops mrvl_flow_ops; 208 209 /** Meter operations forward declaration. */ 210 extern const struct rte_mtr_ops mrvl_mtr_ops; 211 212 /** Traffic manager operations forward declaration. */ 213 extern const struct rte_tm_ops mrvl_tm_ops; 214 215 /** Current log type. */ 216 extern int mrvl_logtype; 217 218 #define MRVL_LOG(level, fmt, args...) \ 219 rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \ 220 __func__, ##args) 221 222 #endif /* _MRVL_ETHDEV_H_ */ 223