1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <rte_ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include "base/ice_sched.h" 14 #include "base/ice_flow.h" 15 #include "base/ice_dcb.h" 16 #include "base/ice_common.h" 17 18 #include "rte_pmd_ice.h" 19 #include "ice_ethdev.h" 20 #include "ice_rxtx.h" 21 #include "ice_generic_flow.h" 22 23 /* devargs */ 24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" 25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" 26 #define ICE_PROTO_XTR_ARG "proto_xtr" 27 28 static const char * const ice_valid_args[] = { 29 ICE_SAFE_MODE_SUPPORT_ARG, 30 ICE_PIPELINE_MODE_SUPPORT_ARG, 31 ICE_PROTO_XTR_ARG, 32 NULL 33 }; 34 35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = { 36 .name = "ice_dynfield_proto_xtr_metadata", 37 .size = sizeof(uint32_t), 38 .align = __alignof__(uint32_t), 39 .flags = 0, 40 }; 41 42 struct proto_xtr_ol_flag { 43 const struct rte_mbuf_dynflag param; 44 uint64_t *ol_flag; 45 bool required; 46 }; 47 48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX]; 49 50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = { 51 [PROTO_XTR_VLAN] = { 52 .param = { .name = "ice_dynflag_proto_xtr_vlan" }, 53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask }, 54 [PROTO_XTR_IPV4] = { 55 .param = { .name = "ice_dynflag_proto_xtr_ipv4" }, 56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask }, 57 [PROTO_XTR_IPV6] = { 58 .param = { .name = "ice_dynflag_proto_xtr_ipv6" }, 59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask }, 60 [PROTO_XTR_IPV6_FLOW] = { 61 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" }, 62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask }, 63 [PROTO_XTR_TCP] = { 64 .param = { .name = "ice_dynflag_proto_xtr_tcp" }, 65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask }, 66 [PROTO_XTR_IP_OFFSET] = { 67 .param = { .name = "ice_dynflag_proto_xtr_ip_offset" }, 68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask }, 69 }; 70 71 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 72 73 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package" 74 #define ICE_COMMS_PKG_NAME "ICE COMMS Package" 75 #define ICE_MAX_RES_DESC_NUM 1024 76 77 static int ice_dev_configure(struct rte_eth_dev *dev); 78 static int ice_dev_start(struct rte_eth_dev *dev); 79 static void ice_dev_stop(struct rte_eth_dev *dev); 80 static int ice_dev_close(struct rte_eth_dev *dev); 81 static int ice_dev_reset(struct rte_eth_dev *dev); 82 static int ice_dev_info_get(struct rte_eth_dev *dev, 83 struct rte_eth_dev_info *dev_info); 84 static int ice_link_update(struct rte_eth_dev *dev, 85 int wait_to_complete); 86 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 87 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 88 89 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 90 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 91 static int ice_rss_reta_update(struct rte_eth_dev *dev, 92 struct rte_eth_rss_reta_entry64 *reta_conf, 93 uint16_t reta_size); 94 static int ice_rss_reta_query(struct rte_eth_dev *dev, 95 struct rte_eth_rss_reta_entry64 *reta_conf, 96 uint16_t reta_size); 97 static int ice_rss_hash_update(struct rte_eth_dev *dev, 98 struct rte_eth_rss_conf *rss_conf); 99 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 100 struct rte_eth_rss_conf *rss_conf); 101 static int ice_promisc_enable(struct rte_eth_dev *dev); 102 static int ice_promisc_disable(struct rte_eth_dev *dev); 103 static int ice_allmulti_enable(struct rte_eth_dev *dev); 104 static int ice_allmulti_disable(struct rte_eth_dev *dev); 105 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 106 uint16_t vlan_id, 107 int on); 108 static int ice_macaddr_set(struct rte_eth_dev *dev, 109 struct rte_ether_addr *mac_addr); 110 static int ice_macaddr_add(struct rte_eth_dev *dev, 111 struct rte_ether_addr *mac_addr, 112 __rte_unused uint32_t index, 113 uint32_t pool); 114 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 115 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 116 uint16_t queue_id); 117 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 118 uint16_t queue_id); 119 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 120 size_t fw_size); 121 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 122 uint16_t pvid, int on); 123 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 124 static int ice_get_eeprom(struct rte_eth_dev *dev, 125 struct rte_dev_eeprom_info *eeprom); 126 static int ice_stats_get(struct rte_eth_dev *dev, 127 struct rte_eth_stats *stats); 128 static int ice_stats_reset(struct rte_eth_dev *dev); 129 static int ice_xstats_get(struct rte_eth_dev *dev, 130 struct rte_eth_xstat *xstats, unsigned int n); 131 static int ice_xstats_get_names(struct rte_eth_dev *dev, 132 struct rte_eth_xstat_name *xstats_names, 133 unsigned int limit); 134 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, 135 enum rte_filter_type filter_type, 136 enum rte_filter_op filter_op, 137 void *arg); 138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 139 struct rte_eth_udp_tunnel *udp_tunnel); 140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 141 struct rte_eth_udp_tunnel *udp_tunnel); 142 143 static const struct rte_pci_id pci_id_ice_map[] = { 144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) }, 145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) }, 146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) }, 147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) }, 148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) }, 149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) }, 153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) }, 154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) }, 155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) }, 156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) }, 157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) }, 158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) }, 159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) }, 160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) }, 161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) }, 162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) }, 163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) }, 164 { .vendor_id = 0, /* sentinel */ }, 165 }; 166 167 static const struct eth_dev_ops ice_eth_dev_ops = { 168 .dev_configure = ice_dev_configure, 169 .dev_start = ice_dev_start, 170 .dev_stop = ice_dev_stop, 171 .dev_close = ice_dev_close, 172 .dev_reset = ice_dev_reset, 173 .dev_set_link_up = ice_dev_set_link_up, 174 .dev_set_link_down = ice_dev_set_link_down, 175 .rx_queue_start = ice_rx_queue_start, 176 .rx_queue_stop = ice_rx_queue_stop, 177 .tx_queue_start = ice_tx_queue_start, 178 .tx_queue_stop = ice_tx_queue_stop, 179 .rx_queue_setup = ice_rx_queue_setup, 180 .rx_queue_release = ice_rx_queue_release, 181 .tx_queue_setup = ice_tx_queue_setup, 182 .tx_queue_release = ice_tx_queue_release, 183 .dev_infos_get = ice_dev_info_get, 184 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 185 .link_update = ice_link_update, 186 .mtu_set = ice_mtu_set, 187 .mac_addr_set = ice_macaddr_set, 188 .mac_addr_add = ice_macaddr_add, 189 .mac_addr_remove = ice_macaddr_remove, 190 .vlan_filter_set = ice_vlan_filter_set, 191 .vlan_offload_set = ice_vlan_offload_set, 192 .reta_update = ice_rss_reta_update, 193 .reta_query = ice_rss_reta_query, 194 .rss_hash_update = ice_rss_hash_update, 195 .rss_hash_conf_get = ice_rss_hash_conf_get, 196 .promiscuous_enable = ice_promisc_enable, 197 .promiscuous_disable = ice_promisc_disable, 198 .allmulticast_enable = ice_allmulti_enable, 199 .allmulticast_disable = ice_allmulti_disable, 200 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 201 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 202 .fw_version_get = ice_fw_version_get, 203 .vlan_pvid_set = ice_vlan_pvid_set, 204 .rxq_info_get = ice_rxq_info_get, 205 .txq_info_get = ice_txq_info_get, 206 .rx_burst_mode_get = ice_rx_burst_mode_get, 207 .tx_burst_mode_get = ice_tx_burst_mode_get, 208 .get_eeprom_length = ice_get_eeprom_length, 209 .get_eeprom = ice_get_eeprom, 210 .stats_get = ice_stats_get, 211 .stats_reset = ice_stats_reset, 212 .xstats_get = ice_xstats_get, 213 .xstats_get_names = ice_xstats_get_names, 214 .xstats_reset = ice_stats_reset, 215 .filter_ctrl = ice_dev_filter_ctrl, 216 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, 217 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, 218 .tx_done_cleanup = ice_tx_done_cleanup, 219 }; 220 221 /* store statistics names and its offset in stats structure */ 222 struct ice_xstats_name_off { 223 char name[RTE_ETH_XSTATS_NAME_SIZE]; 224 unsigned int offset; 225 }; 226 227 static const struct ice_xstats_name_off ice_stats_strings[] = { 228 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 229 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 230 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 231 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 232 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 233 rx_unknown_protocol)}, 234 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 235 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 236 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 237 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 238 }; 239 240 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 241 sizeof(ice_stats_strings[0])) 242 243 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 244 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 245 tx_dropped_link_down)}, 246 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 247 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 248 illegal_bytes)}, 249 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 250 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 251 mac_local_faults)}, 252 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 253 mac_remote_faults)}, 254 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 255 rx_len_errors)}, 256 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 257 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 258 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 259 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 260 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 261 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 262 rx_size_127)}, 263 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 264 rx_size_255)}, 265 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 266 rx_size_511)}, 267 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 268 rx_size_1023)}, 269 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 270 rx_size_1522)}, 271 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 272 rx_size_big)}, 273 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 274 rx_undersize)}, 275 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 276 rx_oversize)}, 277 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 278 mac_short_pkt_dropped)}, 279 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 280 rx_fragments)}, 281 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 282 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 283 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 284 tx_size_127)}, 285 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 286 tx_size_255)}, 287 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 288 tx_size_511)}, 289 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 290 tx_size_1023)}, 291 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 292 tx_size_1522)}, 293 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 294 tx_size_big)}, 295 }; 296 297 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 298 sizeof(ice_hw_port_strings[0])) 299 300 static void 301 ice_init_controlq_parameter(struct ice_hw *hw) 302 { 303 /* fields for adminq */ 304 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 305 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 306 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 307 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 308 309 /* fields for mailboxq, DPDK used as PF host */ 310 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 311 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 312 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 313 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 314 } 315 316 static int 317 lookup_proto_xtr_type(const char *xtr_name) 318 { 319 static struct { 320 const char *name; 321 enum proto_xtr_type type; 322 } xtr_type_map[] = { 323 { "vlan", PROTO_XTR_VLAN }, 324 { "ipv4", PROTO_XTR_IPV4 }, 325 { "ipv6", PROTO_XTR_IPV6 }, 326 { "ipv6_flow", PROTO_XTR_IPV6_FLOW }, 327 { "tcp", PROTO_XTR_TCP }, 328 { "ip_offset", PROTO_XTR_IP_OFFSET }, 329 }; 330 uint32_t i; 331 332 for (i = 0; i < RTE_DIM(xtr_type_map); i++) { 333 if (strcmp(xtr_name, xtr_type_map[i].name) == 0) 334 return xtr_type_map[i].type; 335 } 336 337 return -1; 338 } 339 340 /* 341 * Parse elem, the elem could be single number/range or '(' ')' group 342 * 1) A single number elem, it's just a simple digit. e.g. 9 343 * 2) A single range elem, two digits with a '-' between. e.g. 2-6 344 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6) 345 * Within group elem, '-' used for a range separator; 346 * ',' used for a single number. 347 */ 348 static int 349 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs) 350 { 351 const char *str = input; 352 char *end = NULL; 353 uint32_t min, max; 354 uint32_t idx; 355 356 while (isblank(*str)) 357 str++; 358 359 if (!isdigit(*str) && *str != '(') 360 return -1; 361 362 /* process single number or single range of number */ 363 if (*str != '(') { 364 errno = 0; 365 idx = strtoul(str, &end, 10); 366 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 367 return -1; 368 369 while (isblank(*end)) 370 end++; 371 372 min = idx; 373 max = idx; 374 375 /* process single <number>-<number> */ 376 if (*end == '-') { 377 end++; 378 while (isblank(*end)) 379 end++; 380 if (!isdigit(*end)) 381 return -1; 382 383 errno = 0; 384 idx = strtoul(end, &end, 10); 385 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 386 return -1; 387 388 max = idx; 389 while (isblank(*end)) 390 end++; 391 } 392 393 if (*end != ':') 394 return -1; 395 396 for (idx = RTE_MIN(min, max); 397 idx <= RTE_MAX(min, max); idx++) 398 devargs->proto_xtr[idx] = xtr_type; 399 400 return 0; 401 } 402 403 /* process set within bracket */ 404 str++; 405 while (isblank(*str)) 406 str++; 407 if (*str == '\0') 408 return -1; 409 410 min = ICE_MAX_QUEUE_NUM; 411 do { 412 /* go ahead to the first digit */ 413 while (isblank(*str)) 414 str++; 415 if (!isdigit(*str)) 416 return -1; 417 418 /* get the digit value */ 419 errno = 0; 420 idx = strtoul(str, &end, 10); 421 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 422 return -1; 423 424 /* go ahead to separator '-',',' and ')' */ 425 while (isblank(*end)) 426 end++; 427 if (*end == '-') { 428 if (min == ICE_MAX_QUEUE_NUM) 429 min = idx; 430 else /* avoid continuous '-' */ 431 return -1; 432 } else if (*end == ',' || *end == ')') { 433 max = idx; 434 if (min == ICE_MAX_QUEUE_NUM) 435 min = idx; 436 437 for (idx = RTE_MIN(min, max); 438 idx <= RTE_MAX(min, max); idx++) 439 devargs->proto_xtr[idx] = xtr_type; 440 441 min = ICE_MAX_QUEUE_NUM; 442 } else { 443 return -1; 444 } 445 446 str = end + 1; 447 } while (*end != ')' && *end != '\0'); 448 449 return 0; 450 } 451 452 static int 453 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs) 454 { 455 const char *queue_start; 456 uint32_t idx; 457 int xtr_type; 458 char xtr_name[32]; 459 460 while (isblank(*queues)) 461 queues++; 462 463 if (*queues != '[') { 464 xtr_type = lookup_proto_xtr_type(queues); 465 if (xtr_type < 0) 466 return -1; 467 468 devargs->proto_xtr_dflt = xtr_type; 469 470 return 0; 471 } 472 473 queues++; 474 do { 475 while (isblank(*queues)) 476 queues++; 477 if (*queues == '\0') 478 return -1; 479 480 queue_start = queues; 481 482 /* go across a complete bracket */ 483 if (*queue_start == '(') { 484 queues += strcspn(queues, ")"); 485 if (*queues != ')') 486 return -1; 487 } 488 489 /* scan the separator ':' */ 490 queues += strcspn(queues, ":"); 491 if (*queues++ != ':') 492 return -1; 493 while (isblank(*queues)) 494 queues++; 495 496 for (idx = 0; ; idx++) { 497 if (isblank(queues[idx]) || 498 queues[idx] == ',' || 499 queues[idx] == ']' || 500 queues[idx] == '\0') 501 break; 502 503 if (idx > sizeof(xtr_name) - 2) 504 return -1; 505 506 xtr_name[idx] = queues[idx]; 507 } 508 xtr_name[idx] = '\0'; 509 xtr_type = lookup_proto_xtr_type(xtr_name); 510 if (xtr_type < 0) 511 return -1; 512 513 queues += idx; 514 515 while (isblank(*queues) || *queues == ',' || *queues == ']') 516 queues++; 517 518 if (parse_queue_set(queue_start, xtr_type, devargs) < 0) 519 return -1; 520 } while (*queues != '\0'); 521 522 return 0; 523 } 524 525 static int 526 handle_proto_xtr_arg(__rte_unused const char *key, const char *value, 527 void *extra_args) 528 { 529 struct ice_devargs *devargs = extra_args; 530 531 if (value == NULL || extra_args == NULL) 532 return -EINVAL; 533 534 if (parse_queue_proto_xtr(value, devargs) < 0) { 535 PMD_DRV_LOG(ERR, 536 "The protocol extraction parameter is wrong : '%s'", 537 value); 538 return -1; 539 } 540 541 return 0; 542 } 543 544 static void 545 ice_check_proto_xtr_support(struct ice_hw *hw) 546 { 547 #define FLX_REG(val, fld, idx) \ 548 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ 549 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) 550 static struct { 551 uint32_t rxdid; 552 uint8_t opcode; 553 uint8_t protid_0; 554 uint8_t protid_1; 555 } xtr_sets[] = { 556 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN, 557 ICE_RX_OPC_EXTRACT, 558 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O}, 559 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4, 560 ICE_RX_OPC_EXTRACT, 561 ICE_PROT_IPV4_OF_OR_S, 562 ICE_PROT_IPV4_OF_OR_S }, 563 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6, 564 ICE_RX_OPC_EXTRACT, 565 ICE_PROT_IPV6_OF_OR_S, 566 ICE_PROT_IPV6_OF_OR_S }, 567 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW, 568 ICE_RX_OPC_EXTRACT, 569 ICE_PROT_IPV6_OF_OR_S, 570 ICE_PROT_IPV6_OF_OR_S }, 571 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP, 572 ICE_RX_OPC_EXTRACT, 573 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, 574 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET, 575 ICE_RX_OPC_PROTID, 576 ICE_PROT_IPV4_OF_OR_S, 577 ICE_PROT_IPV6_OF_OR_S }, 578 }; 579 uint32_t i; 580 581 for (i = 0; i < RTE_DIM(xtr_sets); i++) { 582 uint32_t rxdid = xtr_sets[i].rxdid; 583 uint32_t v; 584 585 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) { 586 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid)); 587 588 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 && 589 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode) 590 ice_proto_xtr_hw_support[i] = true; 591 } 592 593 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) { 594 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid)); 595 596 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 && 597 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode) 598 ice_proto_xtr_hw_support[i] = true; 599 } 600 } 601 } 602 603 static int 604 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 605 uint32_t num) 606 { 607 struct pool_entry *entry; 608 609 if (!pool || !num) 610 return -EINVAL; 611 612 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 613 if (!entry) { 614 PMD_INIT_LOG(ERR, 615 "Failed to allocate memory for resource pool"); 616 return -ENOMEM; 617 } 618 619 /* queue heap initialize */ 620 pool->num_free = num; 621 pool->num_alloc = 0; 622 pool->base = base; 623 LIST_INIT(&pool->alloc_list); 624 LIST_INIT(&pool->free_list); 625 626 /* Initialize element */ 627 entry->base = 0; 628 entry->len = num; 629 630 LIST_INSERT_HEAD(&pool->free_list, entry, next); 631 return 0; 632 } 633 634 static int 635 ice_res_pool_alloc(struct ice_res_pool_info *pool, 636 uint16_t num) 637 { 638 struct pool_entry *entry, *valid_entry; 639 640 if (!pool || !num) { 641 PMD_INIT_LOG(ERR, "Invalid parameter"); 642 return -EINVAL; 643 } 644 645 if (pool->num_free < num) { 646 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 647 num, pool->num_free); 648 return -ENOMEM; 649 } 650 651 valid_entry = NULL; 652 /* Lookup in free list and find most fit one */ 653 LIST_FOREACH(entry, &pool->free_list, next) { 654 if (entry->len >= num) { 655 /* Find best one */ 656 if (entry->len == num) { 657 valid_entry = entry; 658 break; 659 } 660 if (!valid_entry || 661 valid_entry->len > entry->len) 662 valid_entry = entry; 663 } 664 } 665 666 /* Not find one to satisfy the request, return */ 667 if (!valid_entry) { 668 PMD_INIT_LOG(ERR, "No valid entry found"); 669 return -ENOMEM; 670 } 671 /** 672 * The entry have equal queue number as requested, 673 * remove it from alloc_list. 674 */ 675 if (valid_entry->len == num) { 676 LIST_REMOVE(valid_entry, next); 677 } else { 678 /** 679 * The entry have more numbers than requested, 680 * create a new entry for alloc_list and minus its 681 * queue base and number in free_list. 682 */ 683 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 684 if (!entry) { 685 PMD_INIT_LOG(ERR, 686 "Failed to allocate memory for " 687 "resource pool"); 688 return -ENOMEM; 689 } 690 entry->base = valid_entry->base; 691 entry->len = num; 692 valid_entry->base += num; 693 valid_entry->len -= num; 694 valid_entry = entry; 695 } 696 697 /* Insert it into alloc list, not sorted */ 698 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 699 700 pool->num_free -= valid_entry->len; 701 pool->num_alloc += valid_entry->len; 702 703 return valid_entry->base + pool->base; 704 } 705 706 static void 707 ice_res_pool_destroy(struct ice_res_pool_info *pool) 708 { 709 struct pool_entry *entry, *next_entry; 710 711 if (!pool) 712 return; 713 714 for (entry = LIST_FIRST(&pool->alloc_list); 715 entry && (next_entry = LIST_NEXT(entry, next), 1); 716 entry = next_entry) { 717 LIST_REMOVE(entry, next); 718 rte_free(entry); 719 } 720 721 for (entry = LIST_FIRST(&pool->free_list); 722 entry && (next_entry = LIST_NEXT(entry, next), 1); 723 entry = next_entry) { 724 LIST_REMOVE(entry, next); 725 rte_free(entry); 726 } 727 728 pool->num_free = 0; 729 pool->num_alloc = 0; 730 pool->base = 0; 731 LIST_INIT(&pool->alloc_list); 732 LIST_INIT(&pool->free_list); 733 } 734 735 static void 736 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 737 { 738 /* Set VSI LUT selection */ 739 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 740 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 741 /* Set Hash scheme */ 742 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 743 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 744 /* enable TC */ 745 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 746 } 747 748 static enum ice_status 749 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 750 struct ice_aqc_vsi_props *info, 751 uint8_t enabled_tcmap) 752 { 753 uint16_t bsf, qp_idx; 754 755 /* default tc 0 now. Multi-TC supporting need to be done later. 756 * Configure TC and queue mapping parameters, for enabled TC, 757 * allocate qpnum_per_tc queues to this traffic. 758 */ 759 if (enabled_tcmap != 0x01) { 760 PMD_INIT_LOG(ERR, "only TC0 is supported"); 761 return -ENOTSUP; 762 } 763 764 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 765 bsf = rte_bsf32(vsi->nb_qps); 766 /* Adjust the queue number to actual queues that can be applied */ 767 vsi->nb_qps = 0x1 << bsf; 768 769 qp_idx = 0; 770 /* Set tc and queue mapping with VSI */ 771 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 772 ICE_AQ_VSI_TC_Q_OFFSET_S) | 773 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 774 775 /* Associate queue number with VSI */ 776 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 777 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 778 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 779 info->valid_sections |= 780 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 781 /* Set the info.ingress_table and info.egress_table 782 * for UP translate table. Now just set it to 1:1 map by default 783 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 784 */ 785 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 786 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 787 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 788 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 789 return 0; 790 } 791 792 static int 793 ice_init_mac_address(struct rte_eth_dev *dev) 794 { 795 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 796 797 if (!rte_is_unicast_ether_addr 798 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 799 PMD_INIT_LOG(ERR, "Invalid MAC address"); 800 return -EINVAL; 801 } 802 803 rte_ether_addr_copy( 804 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 805 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 806 807 dev->data->mac_addrs = 808 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0); 809 if (!dev->data->mac_addrs) { 810 PMD_INIT_LOG(ERR, 811 "Failed to allocate memory to store mac address"); 812 return -ENOMEM; 813 } 814 /* store it to dev data */ 815 rte_ether_addr_copy( 816 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 817 &dev->data->mac_addrs[0]); 818 return 0; 819 } 820 821 /* Find out specific MAC filter */ 822 static struct ice_mac_filter * 823 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 824 { 825 struct ice_mac_filter *f; 826 827 TAILQ_FOREACH(f, &vsi->mac_list, next) { 828 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 829 return f; 830 } 831 832 return NULL; 833 } 834 835 static int 836 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 837 { 838 struct ice_fltr_list_entry *m_list_itr = NULL; 839 struct ice_mac_filter *f; 840 struct LIST_HEAD_TYPE list_head; 841 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 842 int ret = 0; 843 844 /* If it's added and configured, return */ 845 f = ice_find_mac_filter(vsi, mac_addr); 846 if (f) { 847 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 848 return 0; 849 } 850 851 INIT_LIST_HEAD(&list_head); 852 853 m_list_itr = (struct ice_fltr_list_entry *) 854 ice_malloc(hw, sizeof(*m_list_itr)); 855 if (!m_list_itr) { 856 ret = -ENOMEM; 857 goto DONE; 858 } 859 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 860 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 861 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 862 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 863 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 864 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 865 m_list_itr->fltr_info.vsi_handle = vsi->idx; 866 867 LIST_ADD(&m_list_itr->list_entry, &list_head); 868 869 /* Add the mac */ 870 ret = ice_add_mac(hw, &list_head); 871 if (ret != ICE_SUCCESS) { 872 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 873 ret = -EINVAL; 874 goto DONE; 875 } 876 /* Add the mac addr into mac list */ 877 f = rte_zmalloc(NULL, sizeof(*f), 0); 878 if (!f) { 879 PMD_DRV_LOG(ERR, "failed to allocate memory"); 880 ret = -ENOMEM; 881 goto DONE; 882 } 883 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr); 884 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 885 vsi->mac_num++; 886 887 ret = 0; 888 889 DONE: 890 rte_free(m_list_itr); 891 return ret; 892 } 893 894 static int 895 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 896 { 897 struct ice_fltr_list_entry *m_list_itr = NULL; 898 struct ice_mac_filter *f; 899 struct LIST_HEAD_TYPE list_head; 900 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 901 int ret = 0; 902 903 /* Can't find it, return an error */ 904 f = ice_find_mac_filter(vsi, mac_addr); 905 if (!f) 906 return -EINVAL; 907 908 INIT_LIST_HEAD(&list_head); 909 910 m_list_itr = (struct ice_fltr_list_entry *) 911 ice_malloc(hw, sizeof(*m_list_itr)); 912 if (!m_list_itr) { 913 ret = -ENOMEM; 914 goto DONE; 915 } 916 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 917 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 918 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 919 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 920 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 921 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 922 m_list_itr->fltr_info.vsi_handle = vsi->idx; 923 924 LIST_ADD(&m_list_itr->list_entry, &list_head); 925 926 /* remove the mac filter */ 927 ret = ice_remove_mac(hw, &list_head); 928 if (ret != ICE_SUCCESS) { 929 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 930 ret = -EINVAL; 931 goto DONE; 932 } 933 934 /* Remove the mac addr from mac list */ 935 TAILQ_REMOVE(&vsi->mac_list, f, next); 936 rte_free(f); 937 vsi->mac_num--; 938 939 ret = 0; 940 DONE: 941 rte_free(m_list_itr); 942 return ret; 943 } 944 945 /* Find out specific VLAN filter */ 946 static struct ice_vlan_filter * 947 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 948 { 949 struct ice_vlan_filter *f; 950 951 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 952 if (vlan_id == f->vlan_info.vlan_id) 953 return f; 954 } 955 956 return NULL; 957 } 958 959 static int 960 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 961 { 962 struct ice_fltr_list_entry *v_list_itr = NULL; 963 struct ice_vlan_filter *f; 964 struct LIST_HEAD_TYPE list_head; 965 struct ice_hw *hw; 966 int ret = 0; 967 968 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID) 969 return -EINVAL; 970 971 hw = ICE_VSI_TO_HW(vsi); 972 973 /* If it's added and configured, return. */ 974 f = ice_find_vlan_filter(vsi, vlan_id); 975 if (f) { 976 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 977 return 0; 978 } 979 980 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 981 return 0; 982 983 INIT_LIST_HEAD(&list_head); 984 985 v_list_itr = (struct ice_fltr_list_entry *) 986 ice_malloc(hw, sizeof(*v_list_itr)); 987 if (!v_list_itr) { 988 ret = -ENOMEM; 989 goto DONE; 990 } 991 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 992 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 993 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 994 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 995 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 996 v_list_itr->fltr_info.vsi_handle = vsi->idx; 997 998 LIST_ADD(&v_list_itr->list_entry, &list_head); 999 1000 /* Add the vlan */ 1001 ret = ice_add_vlan(hw, &list_head); 1002 if (ret != ICE_SUCCESS) { 1003 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 1004 ret = -EINVAL; 1005 goto DONE; 1006 } 1007 1008 /* Add vlan into vlan list */ 1009 f = rte_zmalloc(NULL, sizeof(*f), 0); 1010 if (!f) { 1011 PMD_DRV_LOG(ERR, "failed to allocate memory"); 1012 ret = -ENOMEM; 1013 goto DONE; 1014 } 1015 f->vlan_info.vlan_id = vlan_id; 1016 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 1017 vsi->vlan_num++; 1018 1019 ret = 0; 1020 1021 DONE: 1022 rte_free(v_list_itr); 1023 return ret; 1024 } 1025 1026 static int 1027 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 1028 { 1029 struct ice_fltr_list_entry *v_list_itr = NULL; 1030 struct ice_vlan_filter *f; 1031 struct LIST_HEAD_TYPE list_head; 1032 struct ice_hw *hw; 1033 int ret = 0; 1034 1035 /** 1036 * Vlan 0 is the generic filter for untagged packets 1037 * and can't be removed. 1038 */ 1039 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID) 1040 return -EINVAL; 1041 1042 hw = ICE_VSI_TO_HW(vsi); 1043 1044 /* Can't find it, return an error */ 1045 f = ice_find_vlan_filter(vsi, vlan_id); 1046 if (!f) 1047 return -EINVAL; 1048 1049 INIT_LIST_HEAD(&list_head); 1050 1051 v_list_itr = (struct ice_fltr_list_entry *) 1052 ice_malloc(hw, sizeof(*v_list_itr)); 1053 if (!v_list_itr) { 1054 ret = -ENOMEM; 1055 goto DONE; 1056 } 1057 1058 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 1059 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1060 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1061 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1062 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1063 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1064 1065 LIST_ADD(&v_list_itr->list_entry, &list_head); 1066 1067 /* remove the vlan filter */ 1068 ret = ice_remove_vlan(hw, &list_head); 1069 if (ret != ICE_SUCCESS) { 1070 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 1071 ret = -EINVAL; 1072 goto DONE; 1073 } 1074 1075 /* Remove the vlan id from vlan list */ 1076 TAILQ_REMOVE(&vsi->vlan_list, f, next); 1077 rte_free(f); 1078 vsi->vlan_num--; 1079 1080 ret = 0; 1081 DONE: 1082 rte_free(v_list_itr); 1083 return ret; 1084 } 1085 1086 static int 1087 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 1088 { 1089 struct ice_mac_filter *m_f; 1090 struct ice_vlan_filter *v_f; 1091 int ret = 0; 1092 1093 if (!vsi || !vsi->mac_num) 1094 return -EINVAL; 1095 1096 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 1097 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 1098 if (ret != ICE_SUCCESS) { 1099 ret = -EINVAL; 1100 goto DONE; 1101 } 1102 } 1103 1104 if (vsi->vlan_num == 0) 1105 return 0; 1106 1107 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 1108 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 1109 if (ret != ICE_SUCCESS) { 1110 ret = -EINVAL; 1111 goto DONE; 1112 } 1113 } 1114 1115 DONE: 1116 return ret; 1117 } 1118 1119 static int 1120 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 1121 { 1122 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1123 struct ice_vsi_ctx ctxt; 1124 uint8_t qinq_flags; 1125 int ret = 0; 1126 1127 /* Check if it has been already on or off */ 1128 if (vsi->info.valid_sections & 1129 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1130 if (on) { 1131 if ((vsi->info.outer_tag_flags & 1132 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == 1133 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) 1134 return 0; /* already on */ 1135 } else { 1136 if (!(vsi->info.outer_tag_flags & 1137 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) 1138 return 0; /* already off */ 1139 } 1140 } 1141 1142 if (on) 1143 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; 1144 else 1145 qinq_flags = 0; 1146 /* clear global insertion and use per packet insertion */ 1147 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); 1148 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); 1149 vsi->info.outer_tag_flags |= qinq_flags; 1150 /* use default vlan type 0x8100 */ 1151 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1152 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1153 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1154 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1155 ctxt.info.valid_sections = 1156 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1157 ctxt.vsi_num = vsi->vsi_id; 1158 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1159 if (ret) { 1160 PMD_DRV_LOG(INFO, 1161 "Update VSI failed to %s qinq stripping", 1162 on ? "enable" : "disable"); 1163 return -EINVAL; 1164 } 1165 1166 vsi->info.valid_sections |= 1167 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1168 1169 return ret; 1170 } 1171 1172 static int 1173 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 1174 { 1175 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1176 struct ice_vsi_ctx ctxt; 1177 uint8_t qinq_flags; 1178 int ret = 0; 1179 1180 /* Check if it has been already on or off */ 1181 if (vsi->info.valid_sections & 1182 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1183 if (on) { 1184 if ((vsi->info.outer_tag_flags & 1185 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 1186 ICE_AQ_VSI_OUTER_TAG_COPY) 1187 return 0; /* already on */ 1188 } else { 1189 if ((vsi->info.outer_tag_flags & 1190 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 1191 ICE_AQ_VSI_OUTER_TAG_NOTHING) 1192 return 0; /* already off */ 1193 } 1194 } 1195 1196 if (on) 1197 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; 1198 else 1199 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; 1200 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); 1201 vsi->info.outer_tag_flags |= qinq_flags; 1202 /* use default vlan type 0x8100 */ 1203 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1204 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1205 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1206 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1207 ctxt.info.valid_sections = 1208 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1209 ctxt.vsi_num = vsi->vsi_id; 1210 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1211 if (ret) { 1212 PMD_DRV_LOG(INFO, 1213 "Update VSI failed to %s qinq stripping", 1214 on ? "enable" : "disable"); 1215 return -EINVAL; 1216 } 1217 1218 vsi->info.valid_sections |= 1219 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1220 1221 return ret; 1222 } 1223 1224 static int 1225 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 1226 { 1227 int ret; 1228 1229 ret = ice_vsi_config_qinq_stripping(vsi, on); 1230 if (ret) 1231 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 1232 1233 ret = ice_vsi_config_qinq_insertion(vsi, on); 1234 if (ret) 1235 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 1236 1237 return ret; 1238 } 1239 1240 /* Enable IRQ0 */ 1241 static void 1242 ice_pf_enable_irq0(struct ice_hw *hw) 1243 { 1244 /* reset the registers */ 1245 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 1246 ICE_READ_REG(hw, PFINT_OICR); 1247 1248 #ifdef ICE_LSE_SPT 1249 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 1250 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 1251 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 1252 1253 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 1254 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 1255 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 1256 PFINT_OICR_CTL_ITR_INDX_M) | 1257 PFINT_OICR_CTL_CAUSE_ENA_M); 1258 1259 ICE_WRITE_REG(hw, PFINT_FW_CTL, 1260 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 1261 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 1262 PFINT_FW_CTL_ITR_INDX_M) | 1263 PFINT_FW_CTL_CAUSE_ENA_M); 1264 #else 1265 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 1266 #endif 1267 1268 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1269 GLINT_DYN_CTL_INTENA_M | 1270 GLINT_DYN_CTL_CLEARPBA_M | 1271 GLINT_DYN_CTL_ITR_INDX_M); 1272 1273 ice_flush(hw); 1274 } 1275 1276 /* Disable IRQ0 */ 1277 static void 1278 ice_pf_disable_irq0(struct ice_hw *hw) 1279 { 1280 /* Disable all interrupt types */ 1281 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1282 ice_flush(hw); 1283 } 1284 1285 #ifdef ICE_LSE_SPT 1286 static void 1287 ice_handle_aq_msg(struct rte_eth_dev *dev) 1288 { 1289 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1290 struct ice_ctl_q_info *cq = &hw->adminq; 1291 struct ice_rq_event_info event; 1292 uint16_t pending, opcode; 1293 int ret; 1294 1295 event.buf_len = ICE_AQ_MAX_BUF_LEN; 1296 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 1297 if (!event.msg_buf) { 1298 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 1299 return; 1300 } 1301 1302 pending = 1; 1303 while (pending) { 1304 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 1305 1306 if (ret != ICE_SUCCESS) { 1307 PMD_DRV_LOG(INFO, 1308 "Failed to read msg from AdminQ, " 1309 "adminq_err: %u", 1310 hw->adminq.sq_last_status); 1311 break; 1312 } 1313 opcode = rte_le_to_cpu_16(event.desc.opcode); 1314 1315 switch (opcode) { 1316 case ice_aqc_opc_get_link_status: 1317 ret = ice_link_update(dev, 0); 1318 if (!ret) 1319 rte_eth_dev_callback_process 1320 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1321 break; 1322 default: 1323 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1324 opcode); 1325 break; 1326 } 1327 } 1328 rte_free(event.msg_buf); 1329 } 1330 #endif 1331 1332 /** 1333 * Interrupt handler triggered by NIC for handling 1334 * specific interrupt. 1335 * 1336 * @param handle 1337 * Pointer to interrupt handle. 1338 * @param param 1339 * The address of parameter (struct rte_eth_dev *) regsitered before. 1340 * 1341 * @return 1342 * void 1343 */ 1344 static void 1345 ice_interrupt_handler(void *param) 1346 { 1347 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1348 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1349 uint32_t oicr; 1350 uint32_t reg; 1351 uint8_t pf_num; 1352 uint8_t event; 1353 uint16_t queue; 1354 int ret; 1355 #ifdef ICE_LSE_SPT 1356 uint32_t int_fw_ctl; 1357 #endif 1358 1359 /* Disable interrupt */ 1360 ice_pf_disable_irq0(hw); 1361 1362 /* read out interrupt causes */ 1363 oicr = ICE_READ_REG(hw, PFINT_OICR); 1364 #ifdef ICE_LSE_SPT 1365 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1366 #endif 1367 1368 /* No interrupt event indicated */ 1369 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1370 PMD_DRV_LOG(INFO, "No interrupt event"); 1371 goto done; 1372 } 1373 1374 #ifdef ICE_LSE_SPT 1375 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1376 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1377 ice_handle_aq_msg(dev); 1378 } 1379 #else 1380 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1381 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1382 ret = ice_link_update(dev, 0); 1383 if (!ret) 1384 rte_eth_dev_callback_process 1385 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1386 } 1387 #endif 1388 1389 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1390 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1391 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1392 if (reg & GL_MDET_TX_PQM_VALID_M) { 1393 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1394 GL_MDET_TX_PQM_PF_NUM_S; 1395 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1396 GL_MDET_TX_PQM_MAL_TYPE_S; 1397 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1398 GL_MDET_TX_PQM_QNUM_S; 1399 1400 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1401 "%d by PQM on TX queue %d PF# %d", 1402 event, queue, pf_num); 1403 } 1404 1405 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1406 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1407 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1408 GL_MDET_TX_TCLAN_PF_NUM_S; 1409 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1410 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1411 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1412 GL_MDET_TX_TCLAN_QNUM_S; 1413 1414 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1415 "%d by TCLAN on TX queue %d PF# %d", 1416 event, queue, pf_num); 1417 } 1418 } 1419 done: 1420 /* Enable interrupt */ 1421 ice_pf_enable_irq0(hw); 1422 rte_intr_ack(dev->intr_handle); 1423 } 1424 1425 static void 1426 ice_init_proto_xtr(struct rte_eth_dev *dev) 1427 { 1428 struct ice_adapter *ad = 1429 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1430 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1431 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1432 const struct proto_xtr_ol_flag *ol_flag; 1433 bool proto_xtr_enable = false; 1434 int offset; 1435 uint16_t i; 1436 1437 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0); 1438 if (unlikely(pf->proto_xtr == NULL)) { 1439 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table"); 1440 return; 1441 } 1442 1443 for (i = 0; i < pf->lan_nb_qps; i++) { 1444 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ? 1445 ad->devargs.proto_xtr[i] : 1446 ad->devargs.proto_xtr_dflt; 1447 1448 if (pf->proto_xtr[i] != PROTO_XTR_NONE) { 1449 uint8_t type = pf->proto_xtr[i]; 1450 1451 ice_proto_xtr_ol_flag_params[type].required = true; 1452 proto_xtr_enable = true; 1453 } 1454 } 1455 1456 if (likely(!proto_xtr_enable)) 1457 return; 1458 1459 ice_check_proto_xtr_support(hw); 1460 1461 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param); 1462 if (unlikely(offset == -1)) { 1463 PMD_DRV_LOG(ERR, 1464 "Protocol extraction metadata is disabled in mbuf with error %d", 1465 -rte_errno); 1466 return; 1467 } 1468 1469 PMD_DRV_LOG(DEBUG, 1470 "Protocol extraction metadata offset in mbuf is : %d", 1471 offset); 1472 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset; 1473 1474 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) { 1475 ol_flag = &ice_proto_xtr_ol_flag_params[i]; 1476 1477 if (!ol_flag->required) 1478 continue; 1479 1480 if (!ice_proto_xtr_hw_support[i]) { 1481 PMD_DRV_LOG(ERR, 1482 "Protocol extraction type %u is not supported in hardware", 1483 i); 1484 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1485 break; 1486 } 1487 1488 offset = rte_mbuf_dynflag_register(&ol_flag->param); 1489 if (unlikely(offset == -1)) { 1490 PMD_DRV_LOG(ERR, 1491 "Protocol extraction offload '%s' failed to register with error %d", 1492 ol_flag->param.name, -rte_errno); 1493 1494 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1495 break; 1496 } 1497 1498 PMD_DRV_LOG(DEBUG, 1499 "Protocol extraction offload '%s' offset in mbuf is : %d", 1500 ol_flag->param.name, offset); 1501 *ol_flag->ol_flag = 1ULL << offset; 1502 } 1503 } 1504 1505 /* Initialize SW parameters of PF */ 1506 static int 1507 ice_pf_sw_init(struct rte_eth_dev *dev) 1508 { 1509 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1510 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1511 1512 pf->lan_nb_qp_max = 1513 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1514 hw->func_caps.common_cap.num_rxq); 1515 1516 pf->lan_nb_qps = pf->lan_nb_qp_max; 1517 1518 ice_init_proto_xtr(dev); 1519 1520 if (hw->func_caps.fd_fltr_guar > 0 || 1521 hw->func_caps.fd_fltr_best_effort > 0) { 1522 pf->flags |= ICE_FLAG_FDIR; 1523 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR; 1524 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps; 1525 } else { 1526 pf->fdir_nb_qps = 0; 1527 } 1528 pf->fdir_qp_offset = 0; 1529 1530 return 0; 1531 } 1532 1533 struct ice_vsi * 1534 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1535 { 1536 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1537 struct ice_vsi *vsi = NULL; 1538 struct ice_vsi_ctx vsi_ctx; 1539 int ret; 1540 struct rte_ether_addr broadcast = { 1541 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1542 struct rte_ether_addr mac_addr; 1543 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1544 uint8_t tc_bitmap = 0x1; 1545 uint16_t cfg; 1546 1547 /* hw->num_lports = 1 in NIC mode */ 1548 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1549 if (!vsi) 1550 return NULL; 1551 1552 vsi->idx = pf->next_vsi_idx; 1553 pf->next_vsi_idx++; 1554 vsi->type = type; 1555 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1556 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1557 vsi->vlan_anti_spoof_on = 0; 1558 vsi->vlan_filter_on = 1; 1559 TAILQ_INIT(&vsi->mac_list); 1560 TAILQ_INIT(&vsi->vlan_list); 1561 1562 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ 1563 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1564 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : 1565 hw->func_caps.common_cap.rss_table_size; 1566 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1567 1568 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1569 switch (type) { 1570 case ICE_VSI_PF: 1571 vsi->nb_qps = pf->lan_nb_qps; 1572 vsi->base_queue = 1; 1573 ice_vsi_config_default_rss(&vsi_ctx.info); 1574 vsi_ctx.alloc_from_pool = true; 1575 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1576 /* switch_id is queried by get_switch_config aq, which is done 1577 * by ice_init_hw 1578 */ 1579 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1580 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1581 /* Allow all untagged or tagged packets */ 1582 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; 1583 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; 1584 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1585 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1586 1587 /* FDIR */ 1588 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID | 1589 ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1590 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1591 cfg = ICE_AQ_VSI_FD_ENABLE; 1592 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1593 vsi_ctx.info.max_fd_fltr_dedicated = 1594 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar); 1595 vsi_ctx.info.max_fd_fltr_shared = 1596 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); 1597 1598 /* Enable VLAN/UP trip */ 1599 ret = ice_vsi_config_tc_queue_mapping(vsi, 1600 &vsi_ctx.info, 1601 ICE_DEFAULT_TCMAP); 1602 if (ret) { 1603 PMD_INIT_LOG(ERR, 1604 "tc queue mapping with vsi failed, " 1605 "err = %d", 1606 ret); 1607 goto fail_mem; 1608 } 1609 1610 break; 1611 case ICE_VSI_CTRL: 1612 vsi->nb_qps = pf->fdir_nb_qps; 1613 vsi->base_queue = ICE_FDIR_QUEUE_ID; 1614 vsi_ctx.alloc_from_pool = true; 1615 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1616 1617 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1618 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1619 cfg = ICE_AQ_VSI_FD_PROG_ENABLE; 1620 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1621 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1622 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1623 ret = ice_vsi_config_tc_queue_mapping(vsi, 1624 &vsi_ctx.info, 1625 ICE_DEFAULT_TCMAP); 1626 if (ret) { 1627 PMD_INIT_LOG(ERR, 1628 "tc queue mapping with vsi failed, " 1629 "err = %d", 1630 ret); 1631 goto fail_mem; 1632 } 1633 break; 1634 default: 1635 /* for other types of VSI */ 1636 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1637 goto fail_mem; 1638 } 1639 1640 /* VF has MSIX interrupt in VF range, don't allocate here */ 1641 if (type == ICE_VSI_PF) { 1642 ret = ice_res_pool_alloc(&pf->msix_pool, 1643 RTE_MIN(vsi->nb_qps, 1644 RTE_MAX_RXTX_INTR_VEC_ID)); 1645 if (ret < 0) { 1646 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1647 vsi->vsi_id, ret); 1648 } 1649 vsi->msix_intr = ret; 1650 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1651 } else if (type == ICE_VSI_CTRL) { 1652 ret = ice_res_pool_alloc(&pf->msix_pool, 1); 1653 if (ret < 0) { 1654 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", 1655 vsi->vsi_id, ret); 1656 } 1657 vsi->msix_intr = ret; 1658 vsi->nb_msix = 1; 1659 } else { 1660 vsi->msix_intr = 0; 1661 vsi->nb_msix = 0; 1662 } 1663 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1664 if (ret != ICE_SUCCESS) { 1665 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1666 goto fail_mem; 1667 } 1668 /* store vsi information is SW structure */ 1669 vsi->vsi_id = vsi_ctx.vsi_num; 1670 vsi->info = vsi_ctx.info; 1671 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1672 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1673 1674 if (type == ICE_VSI_PF) { 1675 /* MAC configuration */ 1676 rte_ether_addr_copy((struct rte_ether_addr *) 1677 hw->port_info->mac.perm_addr, 1678 &pf->dev_addr); 1679 1680 rte_ether_addr_copy(&pf->dev_addr, &mac_addr); 1681 ret = ice_add_mac_filter(vsi, &mac_addr); 1682 if (ret != ICE_SUCCESS) 1683 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1684 1685 rte_ether_addr_copy(&broadcast, &mac_addr); 1686 ret = ice_add_mac_filter(vsi, &mac_addr); 1687 if (ret != ICE_SUCCESS) 1688 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1689 } 1690 1691 /* At the beginning, only TC0. */ 1692 /* What we need here is the maximam number of the TX queues. 1693 * Currently vsi->nb_qps means it. 1694 * Correct it if any change. 1695 */ 1696 max_txqs[0] = vsi->nb_qps; 1697 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1698 tc_bitmap, max_txqs); 1699 if (ret != ICE_SUCCESS) 1700 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1701 1702 return vsi; 1703 fail_mem: 1704 rte_free(vsi); 1705 pf->next_vsi_idx--; 1706 return NULL; 1707 } 1708 1709 static int 1710 ice_send_driver_ver(struct ice_hw *hw) 1711 { 1712 struct ice_driver_ver dv; 1713 1714 /* we don't have driver version use 0 for dummy */ 1715 dv.major_ver = 0; 1716 dv.minor_ver = 0; 1717 dv.build_ver = 0; 1718 dv.subbuild_ver = 0; 1719 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1720 1721 return ice_aq_send_driver_ver(hw, &dv, NULL); 1722 } 1723 1724 static int 1725 ice_pf_setup(struct ice_pf *pf) 1726 { 1727 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1728 struct ice_vsi *vsi; 1729 uint16_t unused; 1730 1731 /* Clear all stats counters */ 1732 pf->offset_loaded = false; 1733 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1734 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1735 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1736 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1737 1738 /* force guaranteed filter pool for PF */ 1739 ice_alloc_fd_guar_item(hw, &unused, 1740 hw->func_caps.fd_fltr_guar); 1741 /* force shared filter pool for PF */ 1742 ice_alloc_fd_shrd_item(hw, &unused, 1743 hw->func_caps.fd_fltr_best_effort); 1744 1745 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1746 if (!vsi) { 1747 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1748 return -EINVAL; 1749 } 1750 1751 pf->main_vsi = vsi; 1752 1753 return 0; 1754 } 1755 1756 /* 1757 * Extract device serial number from PCIe Configuration Space and 1758 * determine the pkg file path according to the DSN. 1759 */ 1760 static int 1761 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file) 1762 { 1763 off_t pos; 1764 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; 1765 uint32_t dsn_low, dsn_high; 1766 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); 1767 1768 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN); 1769 1770 if (pos) { 1771 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4); 1772 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8); 1773 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, 1774 "ice-%08x%08x.pkg", dsn_high, dsn_low); 1775 } else { 1776 PMD_INIT_LOG(ERR, "Failed to read device serial number\n"); 1777 goto fail_dsn; 1778 } 1779 1780 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, 1781 ICE_MAX_PKG_FILENAME_SIZE); 1782 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1783 return 0; 1784 1785 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, 1786 ICE_MAX_PKG_FILENAME_SIZE); 1787 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1788 return 0; 1789 1790 fail_dsn: 1791 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); 1792 if (!access(pkg_file, 0)) 1793 return 0; 1794 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); 1795 return 0; 1796 } 1797 1798 enum ice_pkg_type 1799 ice_load_pkg_type(struct ice_hw *hw) 1800 { 1801 enum ice_pkg_type package_type; 1802 1803 /* store the activated package type (OS default or Comms) */ 1804 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME, 1805 ICE_PKG_NAME_SIZE)) 1806 package_type = ICE_PKG_TYPE_OS_DEFAULT; 1807 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, 1808 ICE_PKG_NAME_SIZE)) 1809 package_type = ICE_PKG_TYPE_COMMS; 1810 else 1811 package_type = ICE_PKG_TYPE_UNKNOWN; 1812 1813 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s", 1814 hw->active_pkg_ver.major, hw->active_pkg_ver.minor, 1815 hw->active_pkg_ver.update, hw->active_pkg_ver.draft, 1816 hw->active_pkg_name); 1817 1818 return package_type; 1819 } 1820 1821 static int ice_load_pkg(struct rte_eth_dev *dev) 1822 { 1823 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1824 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE]; 1825 int err; 1826 uint8_t *buf; 1827 int buf_len; 1828 FILE *file; 1829 struct stat fstat; 1830 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1831 struct ice_adapter *ad = 1832 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1833 1834 ice_pkg_file_search_path(pci_dev, pkg_file); 1835 1836 file = fopen(pkg_file, "rb"); 1837 if (!file) { 1838 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); 1839 return -1; 1840 } 1841 1842 err = stat(pkg_file, &fstat); 1843 if (err) { 1844 PMD_INIT_LOG(ERR, "failed to get file stats\n"); 1845 fclose(file); 1846 return err; 1847 } 1848 1849 buf_len = fstat.st_size; 1850 buf = rte_malloc(NULL, buf_len, 0); 1851 1852 if (!buf) { 1853 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", 1854 buf_len); 1855 fclose(file); 1856 return -1; 1857 } 1858 1859 err = fread(buf, buf_len, 1, file); 1860 if (err != 1) { 1861 PMD_INIT_LOG(ERR, "failed to read package data\n"); 1862 fclose(file); 1863 err = -1; 1864 goto fail_exit; 1865 } 1866 1867 fclose(file); 1868 1869 err = ice_copy_and_init_pkg(hw, buf, buf_len); 1870 if (err) { 1871 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1872 goto fail_exit; 1873 } 1874 1875 /* store the loaded pkg type info */ 1876 ad->active_pkg_type = ice_load_pkg_type(hw); 1877 1878 err = ice_init_hw_tbls(hw); 1879 if (err) { 1880 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); 1881 goto fail_init_tbls; 1882 } 1883 1884 return 0; 1885 1886 fail_init_tbls: 1887 rte_free(hw->pkg_copy); 1888 fail_exit: 1889 rte_free(buf); 1890 return err; 1891 } 1892 1893 static void 1894 ice_base_queue_get(struct ice_pf *pf) 1895 { 1896 uint32_t reg; 1897 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1898 1899 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); 1900 if (reg & PFLAN_RX_QALLOC_VALID_M) { 1901 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; 1902 } else { 1903 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" 1904 " index"); 1905 } 1906 } 1907 1908 static int 1909 parse_bool(const char *key, const char *value, void *args) 1910 { 1911 int *i = (int *)args; 1912 char *end; 1913 int num; 1914 1915 num = strtoul(value, &end, 10); 1916 1917 if (num != 0 && num != 1) { 1918 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 1919 "value must be 0 or 1", 1920 value, key); 1921 return -1; 1922 } 1923 1924 *i = num; 1925 return 0; 1926 } 1927 1928 static int ice_parse_devargs(struct rte_eth_dev *dev) 1929 { 1930 struct ice_adapter *ad = 1931 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1932 struct rte_devargs *devargs = dev->device->devargs; 1933 struct rte_kvargs *kvlist; 1934 int ret; 1935 1936 if (devargs == NULL) 1937 return 0; 1938 1939 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args); 1940 if (kvlist == NULL) { 1941 PMD_INIT_LOG(ERR, "Invalid kvargs key\n"); 1942 return -EINVAL; 1943 } 1944 1945 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE; 1946 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE, 1947 sizeof(ad->devargs.proto_xtr)); 1948 1949 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG, 1950 &handle_proto_xtr_arg, &ad->devargs); 1951 if (ret) 1952 goto bail; 1953 1954 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, 1955 &parse_bool, &ad->devargs.safe_mode_support); 1956 if (ret) 1957 goto bail; 1958 1959 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, 1960 &parse_bool, &ad->devargs.pipe_mode_support); 1961 if (ret) 1962 goto bail; 1963 1964 bail: 1965 rte_kvargs_free(kvlist); 1966 return ret; 1967 } 1968 1969 /* Forward LLDP packets to default VSI by set switch rules */ 1970 static int 1971 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on) 1972 { 1973 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1974 struct ice_fltr_list_entry *s_list_itr = NULL; 1975 struct LIST_HEAD_TYPE list_head; 1976 int ret = 0; 1977 1978 INIT_LIST_HEAD(&list_head); 1979 1980 s_list_itr = (struct ice_fltr_list_entry *) 1981 ice_malloc(hw, sizeof(*s_list_itr)); 1982 if (!s_list_itr) 1983 return -ENOMEM; 1984 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE; 1985 s_list_itr->fltr_info.vsi_handle = vsi->idx; 1986 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype = 1987 RTE_ETHER_TYPE_LLDP; 1988 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1989 s_list_itr->fltr_info.flag = ICE_FLTR_RX; 1990 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT; 1991 LIST_ADD(&s_list_itr->list_entry, &list_head); 1992 if (on) 1993 ret = ice_add_eth_mac(hw, &list_head); 1994 else 1995 ret = ice_remove_eth_mac(hw, &list_head); 1996 1997 rte_free(s_list_itr); 1998 return ret; 1999 } 2000 2001 static enum ice_status 2002 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, 2003 uint16_t num, uint16_t desc_id, 2004 uint16_t *prof_buf, uint16_t *num_prof) 2005 { 2006 struct ice_aqc_res_elem *resp_buf; 2007 int ret; 2008 uint16_t buf_len; 2009 bool res_shared = 1; 2010 struct ice_aq_desc aq_desc; 2011 struct ice_sq_cd *cd = NULL; 2012 struct ice_aqc_get_allocd_res_desc *cmd = 2013 &aq_desc.params.get_res_desc; 2014 2015 buf_len = sizeof(*resp_buf) * num; 2016 resp_buf = ice_malloc(hw, buf_len); 2017 if (!resp_buf) 2018 return -ENOMEM; 2019 2020 ice_fill_dflt_direct_cmd_desc(&aq_desc, 2021 ice_aqc_opc_get_allocd_res_desc); 2022 2023 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) & 2024 ICE_AQC_RES_TYPE_M) | (res_shared ? 2025 ICE_AQC_RES_TYPE_FLAG_SHARED : 0)); 2026 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id); 2027 2028 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd); 2029 if (!ret) 2030 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc); 2031 else 2032 goto exit; 2033 2034 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) * 2035 (*num_prof), ICE_NONDMA_TO_NONDMA); 2036 2037 exit: 2038 rte_free(resp_buf); 2039 return ret; 2040 } 2041 static int 2042 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type) 2043 { 2044 int ret; 2045 uint16_t prof_id; 2046 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM]; 2047 uint16_t first_desc = 1; 2048 uint16_t num_prof = 0; 2049 2050 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM, 2051 first_desc, prof_buf, &num_prof); 2052 if (ret) { 2053 PMD_INIT_LOG(ERR, "Failed to get fxp resource"); 2054 return ret; 2055 } 2056 2057 for (prof_id = 0; prof_id < num_prof; prof_id++) { 2058 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]); 2059 if (ret) { 2060 PMD_INIT_LOG(ERR, "Failed to free fxp resource"); 2061 return ret; 2062 } 2063 } 2064 return 0; 2065 } 2066 2067 static int 2068 ice_reset_fxp_resource(struct ice_hw *hw) 2069 { 2070 int ret; 2071 2072 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID); 2073 if (ret) { 2074 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource"); 2075 return ret; 2076 } 2077 2078 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID); 2079 if (ret) { 2080 PMD_INIT_LOG(ERR, "Failed to clearup rss resource"); 2081 return ret; 2082 } 2083 2084 return 0; 2085 } 2086 2087 static void 2088 ice_rss_ctx_init(struct ice_pf *pf) 2089 { 2090 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx)); 2091 } 2092 2093 static uint64_t 2094 ice_get_supported_rxdid(struct ice_hw *hw) 2095 { 2096 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */ 2097 uint32_t regval; 2098 int i; 2099 2100 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1); 2101 2102 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) { 2103 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0)); 2104 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) 2105 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) 2106 supported_rxdid |= BIT(i); 2107 } 2108 return supported_rxdid; 2109 } 2110 2111 static int 2112 ice_dev_init(struct rte_eth_dev *dev) 2113 { 2114 struct rte_pci_device *pci_dev; 2115 struct rte_intr_handle *intr_handle; 2116 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2117 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2118 struct ice_adapter *ad = 2119 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2120 struct ice_vsi *vsi; 2121 int ret; 2122 2123 dev->dev_ops = &ice_eth_dev_ops; 2124 dev->rx_queue_count = ice_rx_queue_count; 2125 dev->rx_descriptor_status = ice_rx_descriptor_status; 2126 dev->tx_descriptor_status = ice_tx_descriptor_status; 2127 dev->rx_pkt_burst = ice_recv_pkts; 2128 dev->tx_pkt_burst = ice_xmit_pkts; 2129 dev->tx_pkt_prepare = ice_prep_pkts; 2130 2131 /* for secondary processes, we don't initialise any further as primary 2132 * has already done this work. 2133 */ 2134 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2135 ice_set_rx_function(dev); 2136 ice_set_tx_function(dev); 2137 return 0; 2138 } 2139 2140 ice_set_default_ptype_table(dev); 2141 pci_dev = RTE_DEV_TO_PCI(dev->device); 2142 intr_handle = &pci_dev->intr_handle; 2143 2144 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2145 pf->adapter->eth_dev = dev; 2146 pf->dev_data = dev->data; 2147 hw->back = pf->adapter; 2148 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 2149 hw->vendor_id = pci_dev->id.vendor_id; 2150 hw->device_id = pci_dev->id.device_id; 2151 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2152 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 2153 hw->bus.device = pci_dev->addr.devid; 2154 hw->bus.func = pci_dev->addr.function; 2155 2156 ret = ice_parse_devargs(dev); 2157 if (ret) { 2158 PMD_INIT_LOG(ERR, "Failed to parse devargs"); 2159 return -EINVAL; 2160 } 2161 2162 ice_init_controlq_parameter(hw); 2163 2164 ret = ice_init_hw(hw); 2165 if (ret) { 2166 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 2167 return -EINVAL; 2168 } 2169 2170 ret = ice_load_pkg(dev); 2171 if (ret) { 2172 if (ad->devargs.safe_mode_support == 0) { 2173 PMD_INIT_LOG(ERR, "Failed to load the DDP package," 2174 "Use safe-mode-support=1 to enter Safe Mode"); 2175 return ret; 2176 } 2177 2178 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 2179 "Entering Safe Mode"); 2180 ad->is_safe_mode = 1; 2181 } 2182 2183 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 2184 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 2185 hw->api_maj_ver, hw->api_min_ver); 2186 2187 ice_pf_sw_init(dev); 2188 ret = ice_init_mac_address(dev); 2189 if (ret) { 2190 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 2191 goto err_init_mac; 2192 } 2193 2194 ret = ice_res_pool_init(&pf->msix_pool, 1, 2195 hw->func_caps.common_cap.num_msix_vectors - 1); 2196 if (ret) { 2197 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 2198 goto err_msix_pool_init; 2199 } 2200 2201 ret = ice_pf_setup(pf); 2202 if (ret) { 2203 PMD_INIT_LOG(ERR, "Failed to setup PF"); 2204 goto err_pf_setup; 2205 } 2206 2207 ret = ice_send_driver_ver(hw); 2208 if (ret) { 2209 PMD_INIT_LOG(ERR, "Failed to send driver version"); 2210 goto err_pf_setup; 2211 } 2212 2213 vsi = pf->main_vsi; 2214 2215 /* Disable double vlan by default */ 2216 ice_vsi_config_double_vlan(vsi, false); 2217 2218 ret = ice_aq_stop_lldp(hw, true, false, NULL); 2219 if (ret != ICE_SUCCESS) 2220 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 2221 ret = ice_init_dcb(hw, true); 2222 if (ret != ICE_SUCCESS) 2223 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n"); 2224 /* Forward LLDP packets to default VSI */ 2225 ret = ice_vsi_config_sw_lldp(vsi, true); 2226 if (ret != ICE_SUCCESS) 2227 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n"); 2228 /* register callback func to eal lib */ 2229 rte_intr_callback_register(intr_handle, 2230 ice_interrupt_handler, dev); 2231 2232 ice_pf_enable_irq0(hw); 2233 2234 /* enable uio intr after callback register */ 2235 rte_intr_enable(intr_handle); 2236 2237 /* get base queue pairs index in the device */ 2238 ice_base_queue_get(pf); 2239 2240 /* Initialize RSS context for gtpu_eh */ 2241 ice_rss_ctx_init(pf); 2242 2243 if (!ad->is_safe_mode) { 2244 ret = ice_flow_init(ad); 2245 if (ret) { 2246 PMD_INIT_LOG(ERR, "Failed to initialize flow"); 2247 return ret; 2248 } 2249 } 2250 2251 ret = ice_reset_fxp_resource(hw); 2252 if (ret) { 2253 PMD_INIT_LOG(ERR, "Failed to reset fxp resource"); 2254 return ret; 2255 } 2256 2257 pf->supported_rxdid = ice_get_supported_rxdid(hw); 2258 2259 return 0; 2260 2261 err_pf_setup: 2262 ice_res_pool_destroy(&pf->msix_pool); 2263 err_msix_pool_init: 2264 rte_free(dev->data->mac_addrs); 2265 dev->data->mac_addrs = NULL; 2266 err_init_mac: 2267 ice_sched_cleanup_all(hw); 2268 rte_free(hw->port_info); 2269 ice_shutdown_all_ctrlq(hw); 2270 rte_free(pf->proto_xtr); 2271 2272 return ret; 2273 } 2274 2275 int 2276 ice_release_vsi(struct ice_vsi *vsi) 2277 { 2278 struct ice_hw *hw; 2279 struct ice_vsi_ctx vsi_ctx; 2280 enum ice_status ret; 2281 int error = 0; 2282 2283 if (!vsi) 2284 return error; 2285 2286 hw = ICE_VSI_TO_HW(vsi); 2287 2288 ice_remove_all_mac_vlan_filters(vsi); 2289 2290 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 2291 2292 vsi_ctx.vsi_num = vsi->vsi_id; 2293 vsi_ctx.info = vsi->info; 2294 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 2295 if (ret != ICE_SUCCESS) { 2296 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 2297 error = -1; 2298 } 2299 2300 rte_free(vsi->rss_lut); 2301 rte_free(vsi->rss_key); 2302 rte_free(vsi); 2303 return error; 2304 } 2305 2306 void 2307 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 2308 { 2309 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2310 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2311 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2312 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2313 uint16_t msix_intr, i; 2314 2315 /* disable interrupt and also clear all the exist config */ 2316 for (i = 0; i < vsi->nb_qps; i++) { 2317 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2318 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2319 rte_wmb(); 2320 } 2321 2322 if (rte_intr_allow_others(intr_handle)) 2323 /* vfio-pci */ 2324 for (i = 0; i < vsi->nb_msix; i++) { 2325 msix_intr = vsi->msix_intr + i; 2326 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2327 GLINT_DYN_CTL_WB_ON_ITR_M); 2328 } 2329 else 2330 /* igb_uio */ 2331 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 2332 } 2333 2334 static void 2335 ice_dev_stop(struct rte_eth_dev *dev) 2336 { 2337 struct rte_eth_dev_data *data = dev->data; 2338 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2339 struct ice_vsi *main_vsi = pf->main_vsi; 2340 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2341 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2342 uint16_t i; 2343 2344 /* avoid stopping again */ 2345 if (pf->adapter_stopped) 2346 return; 2347 2348 /* stop and clear all Rx queues */ 2349 for (i = 0; i < data->nb_rx_queues; i++) 2350 ice_rx_queue_stop(dev, i); 2351 2352 /* stop and clear all Tx queues */ 2353 for (i = 0; i < data->nb_tx_queues; i++) 2354 ice_tx_queue_stop(dev, i); 2355 2356 /* disable all queue interrupts */ 2357 ice_vsi_disable_queues_intr(main_vsi); 2358 2359 if (pf->init_link_up) 2360 ice_dev_set_link_up(dev); 2361 else 2362 ice_dev_set_link_down(dev); 2363 2364 /* Clean datapath event and queue/vec mapping */ 2365 rte_intr_efd_disable(intr_handle); 2366 if (intr_handle->intr_vec) { 2367 rte_free(intr_handle->intr_vec); 2368 intr_handle->intr_vec = NULL; 2369 } 2370 2371 pf->adapter_stopped = true; 2372 } 2373 2374 static int 2375 ice_dev_close(struct rte_eth_dev *dev) 2376 { 2377 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2378 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2379 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2380 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2381 struct ice_adapter *ad = 2382 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2383 2384 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2385 return 0; 2386 2387 /* Since stop will make link down, then the link event will be 2388 * triggered, disable the irq firstly to avoid the port_infoe etc 2389 * resources deallocation causing the interrupt service thread 2390 * crash. 2391 */ 2392 ice_pf_disable_irq0(hw); 2393 2394 ice_dev_stop(dev); 2395 2396 if (!ad->is_safe_mode) 2397 ice_flow_uninit(ad); 2398 2399 /* release all queue resource */ 2400 ice_free_queues(dev); 2401 2402 ice_res_pool_destroy(&pf->msix_pool); 2403 ice_release_vsi(pf->main_vsi); 2404 ice_sched_cleanup_all(hw); 2405 ice_free_hw_tbls(hw); 2406 rte_free(hw->port_info); 2407 hw->port_info = NULL; 2408 ice_shutdown_all_ctrlq(hw); 2409 rte_free(pf->proto_xtr); 2410 pf->proto_xtr = NULL; 2411 2412 dev->dev_ops = NULL; 2413 dev->rx_pkt_burst = NULL; 2414 dev->tx_pkt_burst = NULL; 2415 2416 /* disable uio intr before callback unregister */ 2417 rte_intr_disable(intr_handle); 2418 2419 /* unregister callback func from eal lib */ 2420 rte_intr_callback_unregister(intr_handle, 2421 ice_interrupt_handler, dev); 2422 2423 return 0; 2424 } 2425 2426 static int 2427 ice_dev_uninit(struct rte_eth_dev *dev) 2428 { 2429 ice_dev_close(dev); 2430 2431 return 0; 2432 } 2433 2434 static bool 2435 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg) 2436 { 2437 return ((cfg->hash_func >= ICE_RSS_HASH_TOEPLITZ && 2438 cfg->hash_func <= ICE_RSS_HASH_JHASH) && 2439 (cfg->hash_flds != 0 && cfg->addl_hdrs != 0)) ? 2440 true : false; 2441 } 2442 2443 static void 2444 hash_cfg_reset(struct ice_rss_hash_cfg *cfg) 2445 { 2446 cfg->hash_flds = 0; 2447 cfg->addl_hdrs = 0; 2448 cfg->hash_func = 0; 2449 } 2450 2451 static int 2452 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2453 { 2454 enum ice_status status = ICE_SUCCESS; 2455 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2456 struct ice_vsi *vsi = pf->main_vsi; 2457 2458 if (!is_hash_cfg_valid(cfg)) 2459 return -ENOENT; 2460 2461 status = ice_rem_rss_cfg(hw, vsi->idx, cfg->hash_flds, 2462 cfg->addl_hdrs); 2463 if (status && status != ICE_ERR_DOES_NOT_EXIST) { 2464 PMD_DRV_LOG(ERR, 2465 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n", 2466 vsi->idx, status); 2467 return -EBUSY; 2468 } 2469 2470 return 0; 2471 } 2472 2473 static int 2474 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2475 { 2476 enum ice_status status = ICE_SUCCESS; 2477 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2478 struct ice_vsi *vsi = pf->main_vsi; 2479 bool symm; 2480 2481 if (!is_hash_cfg_valid(cfg)) 2482 return -ENOENT; 2483 2484 symm = (cfg->hash_func == ICE_RSS_HASH_TOEPLITZ_SYMMETRIC) ? 2485 true : false; 2486 2487 status = ice_add_rss_cfg(hw, vsi->idx, cfg->hash_flds, 2488 cfg->addl_hdrs, symm); 2489 if (status) { 2490 PMD_DRV_LOG(ERR, 2491 "ice_add_rss_cfg failed for VSI:%d, error:%d\n", 2492 vsi->idx, status); 2493 return -EBUSY; 2494 } 2495 2496 return 0; 2497 } 2498 2499 static int 2500 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2501 { 2502 int ret; 2503 2504 ret = ice_hash_moveout(pf, cfg); 2505 if (ret && (ret != -ENOENT)) 2506 return ret; 2507 2508 hash_cfg_reset(cfg); 2509 2510 return 0; 2511 } 2512 2513 static int 2514 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2515 u8 ctx_idx) 2516 { 2517 int ret; 2518 2519 switch (ctx_idx) { 2520 case ICE_HASH_GTPU_CTX_EH_IP: 2521 ret = ice_hash_remove(pf, 2522 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2523 if (ret && (ret != -ENOENT)) 2524 return ret; 2525 2526 ret = ice_hash_remove(pf, 2527 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2528 if (ret && (ret != -ENOENT)) 2529 return ret; 2530 2531 ret = ice_hash_remove(pf, 2532 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2533 if (ret && (ret != -ENOENT)) 2534 return ret; 2535 2536 ret = ice_hash_remove(pf, 2537 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2538 if (ret && (ret != -ENOENT)) 2539 return ret; 2540 2541 ret = ice_hash_remove(pf, 2542 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2543 if (ret && (ret != -ENOENT)) 2544 return ret; 2545 2546 ret = ice_hash_remove(pf, 2547 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2548 if (ret && (ret != -ENOENT)) 2549 return ret; 2550 2551 ret = ice_hash_remove(pf, 2552 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2553 if (ret && (ret != -ENOENT)) 2554 return ret; 2555 2556 ret = ice_hash_remove(pf, 2557 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2558 if (ret && (ret != -ENOENT)) 2559 return ret; 2560 2561 break; 2562 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 2563 ret = ice_hash_remove(pf, 2564 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2565 if (ret && (ret != -ENOENT)) 2566 return ret; 2567 2568 ret = ice_hash_remove(pf, 2569 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2570 if (ret && (ret != -ENOENT)) 2571 return ret; 2572 2573 ret = ice_hash_moveout(pf, 2574 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2575 if (ret && (ret != -ENOENT)) 2576 return ret; 2577 2578 ret = ice_hash_moveout(pf, 2579 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2580 if (ret && (ret != -ENOENT)) 2581 return ret; 2582 2583 ret = ice_hash_moveout(pf, 2584 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2585 if (ret && (ret != -ENOENT)) 2586 return ret; 2587 2588 ret = ice_hash_moveout(pf, 2589 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2590 if (ret && (ret != -ENOENT)) 2591 return ret; 2592 2593 break; 2594 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 2595 ret = ice_hash_remove(pf, 2596 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2597 if (ret && (ret != -ENOENT)) 2598 return ret; 2599 2600 ret = ice_hash_remove(pf, 2601 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2602 if (ret && (ret != -ENOENT)) 2603 return ret; 2604 2605 ret = ice_hash_moveout(pf, 2606 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2607 if (ret && (ret != -ENOENT)) 2608 return ret; 2609 2610 ret = ice_hash_moveout(pf, 2611 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2612 if (ret && (ret != -ENOENT)) 2613 return ret; 2614 2615 ret = ice_hash_moveout(pf, 2616 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2617 if (ret && (ret != -ENOENT)) 2618 return ret; 2619 2620 ret = ice_hash_moveout(pf, 2621 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2622 if (ret && (ret != -ENOENT)) 2623 return ret; 2624 2625 break; 2626 case ICE_HASH_GTPU_CTX_UP_IP: 2627 ret = ice_hash_remove(pf, 2628 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2629 if (ret && (ret != -ENOENT)) 2630 return ret; 2631 2632 ret = ice_hash_remove(pf, 2633 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2634 if (ret && (ret != -ENOENT)) 2635 return ret; 2636 2637 ret = ice_hash_moveout(pf, 2638 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2639 if (ret && (ret != -ENOENT)) 2640 return ret; 2641 2642 ret = ice_hash_moveout(pf, 2643 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2644 if (ret && (ret != -ENOENT)) 2645 return ret; 2646 2647 ret = ice_hash_moveout(pf, 2648 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2649 if (ret && (ret != -ENOENT)) 2650 return ret; 2651 2652 break; 2653 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 2654 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 2655 ret = ice_hash_moveout(pf, 2656 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2657 if (ret && (ret != -ENOENT)) 2658 return ret; 2659 2660 ret = ice_hash_moveout(pf, 2661 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2662 if (ret && (ret != -ENOENT)) 2663 return ret; 2664 2665 ret = ice_hash_moveout(pf, 2666 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2667 if (ret && (ret != -ENOENT)) 2668 return ret; 2669 2670 break; 2671 case ICE_HASH_GTPU_CTX_DW_IP: 2672 ret = ice_hash_remove(pf, 2673 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2674 if (ret && (ret != -ENOENT)) 2675 return ret; 2676 2677 ret = ice_hash_remove(pf, 2678 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2679 if (ret && (ret != -ENOENT)) 2680 return ret; 2681 2682 ret = ice_hash_moveout(pf, 2683 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2684 if (ret && (ret != -ENOENT)) 2685 return ret; 2686 2687 ret = ice_hash_moveout(pf, 2688 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2689 if (ret && (ret != -ENOENT)) 2690 return ret; 2691 2692 ret = ice_hash_moveout(pf, 2693 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2694 if (ret && (ret != -ENOENT)) 2695 return ret; 2696 2697 break; 2698 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 2699 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 2700 ret = ice_hash_moveout(pf, 2701 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2702 if (ret && (ret != -ENOENT)) 2703 return ret; 2704 2705 ret = ice_hash_moveout(pf, 2706 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2707 if (ret && (ret != -ENOENT)) 2708 return ret; 2709 2710 ret = ice_hash_moveout(pf, 2711 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2712 if (ret && (ret != -ENOENT)) 2713 return ret; 2714 2715 break; 2716 default: 2717 break; 2718 } 2719 2720 return 0; 2721 } 2722 2723 static u8 calc_gtpu_ctx_idx(uint32_t hdr) 2724 { 2725 u8 eh_idx, ip_idx; 2726 2727 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) 2728 eh_idx = 0; 2729 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP) 2730 eh_idx = 1; 2731 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN) 2732 eh_idx = 2; 2733 else 2734 return ICE_HASH_GTPU_CTX_MAX; 2735 2736 ip_idx = 0; 2737 if (hdr & ICE_FLOW_SEG_HDR_UDP) 2738 ip_idx = 1; 2739 else if (hdr & ICE_FLOW_SEG_HDR_TCP) 2740 ip_idx = 2; 2741 2742 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)) 2743 return eh_idx * 3 + ip_idx; 2744 else 2745 return ICE_HASH_GTPU_CTX_MAX; 2746 } 2747 2748 static int 2749 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr) 2750 { 2751 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2752 2753 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2754 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4, 2755 gtpu_ctx_idx); 2756 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2757 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6, 2758 gtpu_ctx_idx); 2759 2760 return 0; 2761 } 2762 2763 static int 2764 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2765 u32 hdr, u64 fld, bool symm, u8 ctx_idx) 2766 { 2767 int ret; 2768 2769 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX) { 2770 ctx->ctx[ctx_idx].addl_hdrs = hdr; 2771 ctx->ctx[ctx_idx].hash_flds = fld; 2772 ctx->ctx[ctx_idx].hash_func = symm; 2773 } 2774 2775 switch (ctx_idx) { 2776 case ICE_HASH_GTPU_CTX_EH_IP: 2777 break; 2778 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 2779 ret = ice_hash_moveback(pf, 2780 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2781 if (ret && (ret != -ENOENT)) 2782 return ret; 2783 2784 ret = ice_hash_moveback(pf, 2785 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2786 if (ret && (ret != -ENOENT)) 2787 return ret; 2788 2789 ret = ice_hash_moveback(pf, 2790 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2791 if (ret && (ret != -ENOENT)) 2792 return ret; 2793 2794 ret = ice_hash_moveback(pf, 2795 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2796 if (ret && (ret != -ENOENT)) 2797 return ret; 2798 2799 break; 2800 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 2801 ret = ice_hash_moveback(pf, 2802 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2803 if (ret && (ret != -ENOENT)) 2804 return ret; 2805 2806 ret = ice_hash_moveback(pf, 2807 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2808 if (ret && (ret != -ENOENT)) 2809 return ret; 2810 2811 ret = ice_hash_moveback(pf, 2812 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2813 if (ret && (ret != -ENOENT)) 2814 return ret; 2815 2816 ret = ice_hash_moveback(pf, 2817 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2818 if (ret && (ret != -ENOENT)) 2819 return ret; 2820 2821 break; 2822 case ICE_HASH_GTPU_CTX_UP_IP: 2823 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 2824 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 2825 case ICE_HASH_GTPU_CTX_DW_IP: 2826 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 2827 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 2828 ret = ice_hash_moveback(pf, 2829 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2830 if (ret && (ret != -ENOENT)) 2831 return ret; 2832 2833 ret = ice_hash_moveback(pf, 2834 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2835 if (ret && (ret != -ENOENT)) 2836 return ret; 2837 2838 ret = ice_hash_moveback(pf, 2839 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2840 if (ret && (ret != -ENOENT)) 2841 return ret; 2842 2843 break; 2844 default: 2845 break; 2846 } 2847 2848 return 0; 2849 } 2850 2851 static int 2852 ice_add_rss_cfg_post(struct ice_pf *pf, uint32_t hdr, uint64_t fld, bool symm) 2853 { 2854 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2855 2856 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2857 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4, hdr, 2858 fld, symm, gtpu_ctx_idx); 2859 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2860 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6, hdr, 2861 fld, symm, gtpu_ctx_idx); 2862 2863 return 0; 2864 } 2865 2866 static void 2867 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr) 2868 { 2869 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2870 2871 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX) 2872 return; 2873 2874 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2875 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]); 2876 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2877 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]); 2878 } 2879 2880 int 2881 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 2882 uint64_t fld, uint32_t hdr) 2883 { 2884 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2885 int ret; 2886 2887 ret = ice_rem_rss_cfg(hw, vsi_id, fld, hdr); 2888 if (ret && ret != ICE_ERR_DOES_NOT_EXIST) 2889 PMD_DRV_LOG(ERR, "remove rss cfg failed\n"); 2890 2891 ice_rem_rss_cfg_post(pf, hdr); 2892 2893 return 0; 2894 } 2895 2896 int 2897 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 2898 uint64_t fld, uint32_t hdr, bool symm) 2899 { 2900 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2901 int ret; 2902 2903 ret = ice_add_rss_cfg_pre(pf, hdr); 2904 if (ret) 2905 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n"); 2906 2907 ret = ice_add_rss_cfg(hw, vsi_id, fld, hdr, symm); 2908 if (ret) 2909 PMD_DRV_LOG(ERR, "add rss cfg failed\n"); 2910 2911 ret = ice_add_rss_cfg_post(pf, hdr, fld, symm); 2912 if (ret) 2913 PMD_DRV_LOG(ERR, "add rss cfg post failed\n"); 2914 2915 return 0; 2916 } 2917 2918 static void 2919 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf) 2920 { 2921 struct ice_vsi *vsi = pf->main_vsi; 2922 int ret; 2923 2924 /* Configure RSS for IPv4 with src/dst addr as input set */ 2925 if (rss_hf & ETH_RSS_IPV4) { 2926 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 2927 ICE_FLOW_SEG_HDR_IPV4 | 2928 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2929 if (ret) 2930 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", 2931 __func__, ret); 2932 } 2933 2934 /* Configure RSS for IPv6 with src/dst addr as input set */ 2935 if (rss_hf & ETH_RSS_IPV6) { 2936 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 2937 ICE_FLOW_SEG_HDR_IPV6 | 2938 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2939 if (ret) 2940 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", 2941 __func__, ret); 2942 } 2943 2944 /* Configure RSS for udp4 with src/dst addr and port as input set */ 2945 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 2946 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4, 2947 ICE_FLOW_SEG_HDR_UDP | 2948 ICE_FLOW_SEG_HDR_IPV4 | 2949 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2950 if (ret) 2951 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", 2952 __func__, ret); 2953 } 2954 2955 /* Configure RSS for udp6 with src/dst addr and port as input set */ 2956 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 2957 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6, 2958 ICE_FLOW_SEG_HDR_UDP | 2959 ICE_FLOW_SEG_HDR_IPV6 | 2960 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2961 if (ret) 2962 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", 2963 __func__, ret); 2964 } 2965 2966 /* Configure RSS for tcp4 with src/dst addr and port as input set */ 2967 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 2968 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4, 2969 ICE_FLOW_SEG_HDR_TCP | 2970 ICE_FLOW_SEG_HDR_IPV4 | 2971 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2972 if (ret) 2973 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", 2974 __func__, ret); 2975 } 2976 2977 /* Configure RSS for tcp6 with src/dst addr and port as input set */ 2978 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 2979 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6, 2980 ICE_FLOW_SEG_HDR_TCP | 2981 ICE_FLOW_SEG_HDR_IPV6 | 2982 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2983 if (ret) 2984 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", 2985 __func__, ret); 2986 } 2987 2988 /* Configure RSS for sctp4 with src/dst addr and port as input set */ 2989 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) { 2990 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 2991 ICE_FLOW_SEG_HDR_SCTP | 2992 ICE_FLOW_SEG_HDR_IPV4 | 2993 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2994 if (ret) 2995 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 2996 __func__, ret); 2997 } 2998 2999 /* Configure RSS for sctp6 with src/dst addr and port as input set */ 3000 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) { 3001 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 3002 ICE_FLOW_SEG_HDR_SCTP | 3003 ICE_FLOW_SEG_HDR_IPV6 | 3004 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3005 if (ret) 3006 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 3007 __func__, ret); 3008 } 3009 3010 if (rss_hf & ETH_RSS_IPV4) { 3011 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 3012 ICE_FLOW_SEG_HDR_GTPU_IP | 3013 ICE_FLOW_SEG_HDR_IPV4 | 3014 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3015 if (ret) 3016 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d", 3017 __func__, ret); 3018 3019 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 3020 ICE_FLOW_SEG_HDR_GTPU_EH | 3021 ICE_FLOW_SEG_HDR_IPV4 | 3022 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3023 if (ret) 3024 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d", 3025 __func__, ret); 3026 3027 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 3028 ICE_FLOW_SEG_HDR_PPPOE | 3029 ICE_FLOW_SEG_HDR_IPV4 | 3030 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3031 if (ret) 3032 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d", 3033 __func__, ret); 3034 } 3035 3036 if (rss_hf & ETH_RSS_IPV6) { 3037 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 3038 ICE_FLOW_SEG_HDR_GTPU_IP | 3039 ICE_FLOW_SEG_HDR_IPV6 | 3040 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3041 if (ret) 3042 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d", 3043 __func__, ret); 3044 3045 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 3046 ICE_FLOW_SEG_HDR_GTPU_EH | 3047 ICE_FLOW_SEG_HDR_IPV6 | 3048 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3049 if (ret) 3050 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d", 3051 __func__, ret); 3052 3053 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 3054 ICE_FLOW_SEG_HDR_PPPOE | 3055 ICE_FLOW_SEG_HDR_IPV6 | 3056 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3057 if (ret) 3058 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d", 3059 __func__, ret); 3060 } 3061 3062 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 3063 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4, 3064 ICE_FLOW_SEG_HDR_GTPU_IP | 3065 ICE_FLOW_SEG_HDR_UDP | 3066 ICE_FLOW_SEG_HDR_IPV4 | 3067 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3068 if (ret) 3069 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d", 3070 __func__, ret); 3071 3072 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4, 3073 ICE_FLOW_SEG_HDR_GTPU_EH | 3074 ICE_FLOW_SEG_HDR_UDP | 3075 ICE_FLOW_SEG_HDR_IPV4 | 3076 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3077 if (ret) 3078 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d", 3079 __func__, ret); 3080 3081 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4, 3082 ICE_FLOW_SEG_HDR_PPPOE | 3083 ICE_FLOW_SEG_HDR_UDP | 3084 ICE_FLOW_SEG_HDR_IPV4 | 3085 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3086 if (ret) 3087 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d", 3088 __func__, ret); 3089 } 3090 3091 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 3092 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6, 3093 ICE_FLOW_SEG_HDR_GTPU_IP | 3094 ICE_FLOW_SEG_HDR_UDP | 3095 ICE_FLOW_SEG_HDR_IPV6 | 3096 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3097 if (ret) 3098 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d", 3099 __func__, ret); 3100 3101 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6, 3102 ICE_FLOW_SEG_HDR_GTPU_EH | 3103 ICE_FLOW_SEG_HDR_UDP | 3104 ICE_FLOW_SEG_HDR_IPV6 | 3105 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3106 if (ret) 3107 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d", 3108 __func__, ret); 3109 3110 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6, 3111 ICE_FLOW_SEG_HDR_PPPOE | 3112 ICE_FLOW_SEG_HDR_UDP | 3113 ICE_FLOW_SEG_HDR_IPV6 | 3114 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3115 if (ret) 3116 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d", 3117 __func__, ret); 3118 } 3119 3120 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 3121 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4, 3122 ICE_FLOW_SEG_HDR_GTPU_IP | 3123 ICE_FLOW_SEG_HDR_TCP | 3124 ICE_FLOW_SEG_HDR_IPV4 | 3125 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3126 if (ret) 3127 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d", 3128 __func__, ret); 3129 3130 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4, 3131 ICE_FLOW_SEG_HDR_GTPU_EH | 3132 ICE_FLOW_SEG_HDR_TCP | 3133 ICE_FLOW_SEG_HDR_IPV4 | 3134 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3135 if (ret) 3136 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d", 3137 __func__, ret); 3138 3139 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4, 3140 ICE_FLOW_SEG_HDR_PPPOE | 3141 ICE_FLOW_SEG_HDR_TCP | 3142 ICE_FLOW_SEG_HDR_IPV4 | 3143 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3144 if (ret) 3145 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d", 3146 __func__, ret); 3147 } 3148 3149 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 3150 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6, 3151 ICE_FLOW_SEG_HDR_GTPU_IP | 3152 ICE_FLOW_SEG_HDR_TCP | 3153 ICE_FLOW_SEG_HDR_IPV6 | 3154 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3155 if (ret) 3156 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d", 3157 __func__, ret); 3158 3159 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6, 3160 ICE_FLOW_SEG_HDR_GTPU_EH | 3161 ICE_FLOW_SEG_HDR_TCP | 3162 ICE_FLOW_SEG_HDR_IPV6 | 3163 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3164 if (ret) 3165 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d", 3166 __func__, ret); 3167 3168 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6, 3169 ICE_FLOW_SEG_HDR_PPPOE | 3170 ICE_FLOW_SEG_HDR_TCP | 3171 ICE_FLOW_SEG_HDR_IPV6 | 3172 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3173 if (ret) 3174 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d", 3175 __func__, ret); 3176 } 3177 3178 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) { 3179 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4, 3180 ICE_FLOW_SEG_HDR_GTPU_IP | 3181 ICE_FLOW_SEG_HDR_SCTP | 3182 ICE_FLOW_SEG_HDR_IPV4 | 3183 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3184 if (ret) 3185 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d", 3186 __func__, ret); 3187 3188 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4, 3189 ICE_FLOW_SEG_HDR_GTPU_EH | 3190 ICE_FLOW_SEG_HDR_SCTP | 3191 ICE_FLOW_SEG_HDR_IPV4 | 3192 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3193 if (ret) 3194 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d", 3195 __func__, ret); 3196 } 3197 3198 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) { 3199 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6, 3200 ICE_FLOW_SEG_HDR_GTPU_IP | 3201 ICE_FLOW_SEG_HDR_SCTP | 3202 ICE_FLOW_SEG_HDR_IPV6 | 3203 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3204 if (ret) 3205 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d", 3206 __func__, ret); 3207 3208 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6, 3209 ICE_FLOW_SEG_HDR_GTPU_EH | 3210 ICE_FLOW_SEG_HDR_SCTP | 3211 ICE_FLOW_SEG_HDR_IPV6 | 3212 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3213 if (ret) 3214 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d", 3215 __func__, ret); 3216 } 3217 } 3218 3219 static int ice_init_rss(struct ice_pf *pf) 3220 { 3221 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3222 struct ice_vsi *vsi = pf->main_vsi; 3223 struct rte_eth_dev *dev = pf->adapter->eth_dev; 3224 struct rte_eth_rss_conf *rss_conf; 3225 struct ice_aqc_get_set_rss_keys key; 3226 uint16_t i, nb_q; 3227 int ret = 0; 3228 bool is_safe_mode = pf->adapter->is_safe_mode; 3229 uint32_t reg; 3230 3231 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 3232 nb_q = dev->data->nb_rx_queues; 3233 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 3234 vsi->rss_lut_size = pf->hash_lut_size; 3235 3236 if (is_safe_mode) { 3237 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 3238 return 0; 3239 } 3240 3241 if (!vsi->rss_key) { 3242 vsi->rss_key = rte_zmalloc(NULL, 3243 vsi->rss_key_size, 0); 3244 if (vsi->rss_key == NULL) { 3245 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3246 return -ENOMEM; 3247 } 3248 } 3249 if (!vsi->rss_lut) { 3250 vsi->rss_lut = rte_zmalloc(NULL, 3251 vsi->rss_lut_size, 0); 3252 if (vsi->rss_lut == NULL) { 3253 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3254 rte_free(vsi->rss_key); 3255 vsi->rss_key = NULL; 3256 return -ENOMEM; 3257 } 3258 } 3259 /* configure RSS key */ 3260 if (!rss_conf->rss_key) { 3261 /* Calculate the default hash key */ 3262 for (i = 0; i <= vsi->rss_key_size; i++) 3263 vsi->rss_key[i] = (uint8_t)rte_rand(); 3264 } else { 3265 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 3266 RTE_MIN(rss_conf->rss_key_len, 3267 vsi->rss_key_size)); 3268 } 3269 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 3270 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 3271 if (ret) 3272 goto out; 3273 3274 /* init RSS LUT table */ 3275 for (i = 0; i < vsi->rss_lut_size; i++) 3276 vsi->rss_lut[i] = i % nb_q; 3277 3278 ret = ice_aq_set_rss_lut(hw, vsi->idx, 3279 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, 3280 vsi->rss_lut, vsi->rss_lut_size); 3281 if (ret) 3282 goto out; 3283 3284 /* Enable registers for symmetric_toeplitz function. */ 3285 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id)); 3286 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) | 3287 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S); 3288 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg); 3289 3290 /* RSS hash configuration */ 3291 ice_rss_hash_set(pf, rss_conf->rss_hf); 3292 3293 return 0; 3294 out: 3295 rte_free(vsi->rss_key); 3296 vsi->rss_key = NULL; 3297 rte_free(vsi->rss_lut); 3298 vsi->rss_lut = NULL; 3299 return -EINVAL; 3300 } 3301 3302 static int 3303 ice_dev_configure(struct rte_eth_dev *dev) 3304 { 3305 struct ice_adapter *ad = 3306 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 3307 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3308 int ret; 3309 3310 /* Initialize to TRUE. If any of Rx queues doesn't meet the 3311 * bulk allocation or vector Rx preconditions we will reset it. 3312 */ 3313 ad->rx_bulk_alloc_allowed = true; 3314 ad->tx_simple_allowed = true; 3315 3316 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 3317 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 3318 3319 ret = ice_init_rss(pf); 3320 if (ret) { 3321 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 3322 return ret; 3323 } 3324 3325 return 0; 3326 } 3327 3328 static void 3329 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 3330 int base_queue, int nb_queue) 3331 { 3332 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3333 uint32_t val, val_tx; 3334 int i; 3335 3336 for (i = 0; i < nb_queue; i++) { 3337 /*do actual bind*/ 3338 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 3339 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 3340 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 3341 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 3342 3343 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 3344 base_queue + i, msix_vect); 3345 /* set ITR0 value */ 3346 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); 3347 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 3348 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 3349 } 3350 } 3351 3352 void 3353 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 3354 { 3355 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 3356 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3357 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3358 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3359 uint16_t msix_vect = vsi->msix_intr; 3360 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 3361 uint16_t queue_idx = 0; 3362 int record = 0; 3363 int i; 3364 3365 /* clear Rx/Tx queue interrupt */ 3366 for (i = 0; i < vsi->nb_used_qps; i++) { 3367 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 3368 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 3369 } 3370 3371 /* PF bind interrupt */ 3372 if (rte_intr_dp_is_en(intr_handle)) { 3373 queue_idx = 0; 3374 record = 1; 3375 } 3376 3377 for (i = 0; i < vsi->nb_used_qps; i++) { 3378 if (nb_msix <= 1) { 3379 if (!rte_intr_allow_others(intr_handle)) 3380 msix_vect = ICE_MISC_VEC_ID; 3381 3382 /* uio mapping all queue to one msix_vect */ 3383 __vsi_queues_bind_intr(vsi, msix_vect, 3384 vsi->base_queue + i, 3385 vsi->nb_used_qps - i); 3386 3387 for (; !!record && i < vsi->nb_used_qps; i++) 3388 intr_handle->intr_vec[queue_idx + i] = 3389 msix_vect; 3390 break; 3391 } 3392 3393 /* vfio 1:1 queue/msix_vect mapping */ 3394 __vsi_queues_bind_intr(vsi, msix_vect, 3395 vsi->base_queue + i, 1); 3396 3397 if (!!record) 3398 intr_handle->intr_vec[queue_idx + i] = msix_vect; 3399 3400 msix_vect++; 3401 nb_msix--; 3402 } 3403 } 3404 3405 void 3406 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 3407 { 3408 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 3409 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3410 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3411 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3412 uint16_t msix_intr, i; 3413 3414 if (rte_intr_allow_others(intr_handle)) 3415 for (i = 0; i < vsi->nb_used_qps; i++) { 3416 msix_intr = vsi->msix_intr + i; 3417 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 3418 GLINT_DYN_CTL_INTENA_M | 3419 GLINT_DYN_CTL_CLEARPBA_M | 3420 GLINT_DYN_CTL_ITR_INDX_M | 3421 GLINT_DYN_CTL_WB_ON_ITR_M); 3422 } 3423 else 3424 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 3425 GLINT_DYN_CTL_INTENA_M | 3426 GLINT_DYN_CTL_CLEARPBA_M | 3427 GLINT_DYN_CTL_ITR_INDX_M | 3428 GLINT_DYN_CTL_WB_ON_ITR_M); 3429 } 3430 3431 static int 3432 ice_rxq_intr_setup(struct rte_eth_dev *dev) 3433 { 3434 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3435 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3436 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3437 struct ice_vsi *vsi = pf->main_vsi; 3438 uint32_t intr_vector = 0; 3439 3440 rte_intr_disable(intr_handle); 3441 3442 /* check and configure queue intr-vector mapping */ 3443 if ((rte_intr_cap_multiple(intr_handle) || 3444 !RTE_ETH_DEV_SRIOV(dev).active) && 3445 dev->data->dev_conf.intr_conf.rxq != 0) { 3446 intr_vector = dev->data->nb_rx_queues; 3447 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 3448 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 3449 ICE_MAX_INTR_QUEUE_NUM); 3450 return -ENOTSUP; 3451 } 3452 if (rte_intr_efd_enable(intr_handle, intr_vector)) 3453 return -1; 3454 } 3455 3456 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 3457 intr_handle->intr_vec = 3458 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 3459 0); 3460 if (!intr_handle->intr_vec) { 3461 PMD_DRV_LOG(ERR, 3462 "Failed to allocate %d rx_queues intr_vec", 3463 dev->data->nb_rx_queues); 3464 return -ENOMEM; 3465 } 3466 } 3467 3468 /* Map queues with MSIX interrupt */ 3469 vsi->nb_used_qps = dev->data->nb_rx_queues; 3470 ice_vsi_queues_bind_intr(vsi); 3471 3472 /* Enable interrupts for all the queues */ 3473 ice_vsi_enable_queues_intr(vsi); 3474 3475 rte_intr_enable(intr_handle); 3476 3477 return 0; 3478 } 3479 3480 static void 3481 ice_get_init_link_status(struct rte_eth_dev *dev) 3482 { 3483 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3484 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3485 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3486 struct ice_link_status link_status; 3487 int ret; 3488 3489 ret = ice_aq_get_link_info(hw->port_info, enable_lse, 3490 &link_status, NULL); 3491 if (ret != ICE_SUCCESS) { 3492 PMD_DRV_LOG(ERR, "Failed to get link info"); 3493 pf->init_link_up = false; 3494 return; 3495 } 3496 3497 if (link_status.link_info & ICE_AQ_LINK_UP) 3498 pf->init_link_up = true; 3499 } 3500 3501 static int 3502 ice_dev_start(struct rte_eth_dev *dev) 3503 { 3504 struct rte_eth_dev_data *data = dev->data; 3505 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3506 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3507 struct ice_vsi *vsi = pf->main_vsi; 3508 uint16_t nb_rxq = 0; 3509 uint16_t nb_txq, i; 3510 uint16_t max_frame_size; 3511 int mask, ret; 3512 3513 /* program Tx queues' context in hardware */ 3514 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 3515 ret = ice_tx_queue_start(dev, nb_txq); 3516 if (ret) { 3517 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 3518 goto tx_err; 3519 } 3520 } 3521 3522 /* program Rx queues' context in hardware*/ 3523 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 3524 ret = ice_rx_queue_start(dev, nb_rxq); 3525 if (ret) { 3526 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 3527 goto rx_err; 3528 } 3529 } 3530 3531 ice_set_rx_function(dev); 3532 ice_set_tx_function(dev); 3533 3534 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 3535 ETH_VLAN_EXTEND_MASK; 3536 ret = ice_vlan_offload_set(dev, mask); 3537 if (ret) { 3538 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 3539 goto rx_err; 3540 } 3541 3542 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 3543 if (ice_rxq_intr_setup(dev)) 3544 return -EIO; 3545 3546 /* Enable receiving broadcast packets and transmitting packets */ 3547 ret = ice_set_vsi_promisc(hw, vsi->idx, 3548 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 3549 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 3550 0); 3551 if (ret != ICE_SUCCESS) 3552 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 3553 3554 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 3555 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 3556 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 3557 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 3558 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 3559 ICE_AQ_LINK_EVENT_AN_COMPLETED | 3560 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 3561 NULL); 3562 if (ret != ICE_SUCCESS) 3563 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 3564 3565 ice_get_init_link_status(dev); 3566 3567 ice_dev_set_link_up(dev); 3568 3569 /* Call get_link_info aq commond to enable/disable LSE */ 3570 ice_link_update(dev, 0); 3571 3572 pf->adapter_stopped = false; 3573 3574 /* Set the max frame size to default value*/ 3575 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ? 3576 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len : 3577 ICE_FRAME_SIZE_MAX; 3578 3579 /* Set the max frame size to HW*/ 3580 ice_aq_set_mac_cfg(hw, max_frame_size, NULL); 3581 3582 return 0; 3583 3584 /* stop the started queues if failed to start all queues */ 3585 rx_err: 3586 for (i = 0; i < nb_rxq; i++) 3587 ice_rx_queue_stop(dev, i); 3588 tx_err: 3589 for (i = 0; i < nb_txq; i++) 3590 ice_tx_queue_stop(dev, i); 3591 3592 return -EIO; 3593 } 3594 3595 static int 3596 ice_dev_reset(struct rte_eth_dev *dev) 3597 { 3598 int ret; 3599 3600 if (dev->data->sriov.active) 3601 return -ENOTSUP; 3602 3603 ret = ice_dev_uninit(dev); 3604 if (ret) { 3605 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 3606 return -ENXIO; 3607 } 3608 3609 ret = ice_dev_init(dev); 3610 if (ret) { 3611 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 3612 return -ENXIO; 3613 } 3614 3615 return 0; 3616 } 3617 3618 static int 3619 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3620 { 3621 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3622 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3623 struct ice_vsi *vsi = pf->main_vsi; 3624 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 3625 bool is_safe_mode = pf->adapter->is_safe_mode; 3626 u64 phy_type_low; 3627 u64 phy_type_high; 3628 3629 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 3630 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 3631 dev_info->max_rx_queues = vsi->nb_qps; 3632 dev_info->max_tx_queues = vsi->nb_qps; 3633 dev_info->max_mac_addrs = vsi->max_macaddrs; 3634 dev_info->max_vfs = pci_dev->max_vfs; 3635 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 3636 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3637 3638 dev_info->rx_offload_capa = 3639 DEV_RX_OFFLOAD_VLAN_STRIP | 3640 DEV_RX_OFFLOAD_JUMBO_FRAME | 3641 DEV_RX_OFFLOAD_KEEP_CRC | 3642 DEV_RX_OFFLOAD_SCATTER | 3643 DEV_RX_OFFLOAD_VLAN_FILTER; 3644 dev_info->tx_offload_capa = 3645 DEV_TX_OFFLOAD_VLAN_INSERT | 3646 DEV_TX_OFFLOAD_TCP_TSO | 3647 DEV_TX_OFFLOAD_MULTI_SEGS | 3648 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3649 dev_info->flow_type_rss_offloads = 0; 3650 3651 if (!is_safe_mode) { 3652 dev_info->rx_offload_capa |= 3653 DEV_RX_OFFLOAD_IPV4_CKSUM | 3654 DEV_RX_OFFLOAD_UDP_CKSUM | 3655 DEV_RX_OFFLOAD_TCP_CKSUM | 3656 DEV_RX_OFFLOAD_QINQ_STRIP | 3657 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3658 DEV_RX_OFFLOAD_VLAN_EXTEND | 3659 DEV_RX_OFFLOAD_RSS_HASH; 3660 dev_info->tx_offload_capa |= 3661 DEV_TX_OFFLOAD_QINQ_INSERT | 3662 DEV_TX_OFFLOAD_IPV4_CKSUM | 3663 DEV_TX_OFFLOAD_UDP_CKSUM | 3664 DEV_TX_OFFLOAD_TCP_CKSUM | 3665 DEV_TX_OFFLOAD_SCTP_CKSUM | 3666 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3667 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 3668 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 3669 } 3670 3671 dev_info->rx_queue_offload_capa = 0; 3672 dev_info->tx_queue_offload_capa = 0; 3673 3674 dev_info->reta_size = pf->hash_lut_size; 3675 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 3676 3677 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3678 .rx_thresh = { 3679 .pthresh = ICE_DEFAULT_RX_PTHRESH, 3680 .hthresh = ICE_DEFAULT_RX_HTHRESH, 3681 .wthresh = ICE_DEFAULT_RX_WTHRESH, 3682 }, 3683 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 3684 .rx_drop_en = 0, 3685 .offloads = 0, 3686 }; 3687 3688 dev_info->default_txconf = (struct rte_eth_txconf) { 3689 .tx_thresh = { 3690 .pthresh = ICE_DEFAULT_TX_PTHRESH, 3691 .hthresh = ICE_DEFAULT_TX_HTHRESH, 3692 .wthresh = ICE_DEFAULT_TX_WTHRESH, 3693 }, 3694 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 3695 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 3696 .offloads = 0, 3697 }; 3698 3699 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3700 .nb_max = ICE_MAX_RING_DESC, 3701 .nb_min = ICE_MIN_RING_DESC, 3702 .nb_align = ICE_ALIGN_RING_DESC, 3703 }; 3704 3705 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3706 .nb_max = ICE_MAX_RING_DESC, 3707 .nb_min = ICE_MIN_RING_DESC, 3708 .nb_align = ICE_ALIGN_RING_DESC, 3709 }; 3710 3711 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3712 ETH_LINK_SPEED_100M | 3713 ETH_LINK_SPEED_1G | 3714 ETH_LINK_SPEED_2_5G | 3715 ETH_LINK_SPEED_5G | 3716 ETH_LINK_SPEED_10G | 3717 ETH_LINK_SPEED_20G | 3718 ETH_LINK_SPEED_25G; 3719 3720 phy_type_low = hw->port_info->phy.phy_type_low; 3721 phy_type_high = hw->port_info->phy.phy_type_high; 3722 3723 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 3724 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 3725 3726 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 3727 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 3728 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 3729 3730 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 3731 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 3732 3733 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 3734 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 3735 dev_info->default_rxportconf.nb_queues = 1; 3736 dev_info->default_txportconf.nb_queues = 1; 3737 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 3738 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 3739 3740 return 0; 3741 } 3742 3743 static inline int 3744 ice_atomic_read_link_status(struct rte_eth_dev *dev, 3745 struct rte_eth_link *link) 3746 { 3747 struct rte_eth_link *dst = link; 3748 struct rte_eth_link *src = &dev->data->dev_link; 3749 3750 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3751 *(uint64_t *)src) == 0) 3752 return -1; 3753 3754 return 0; 3755 } 3756 3757 static inline int 3758 ice_atomic_write_link_status(struct rte_eth_dev *dev, 3759 struct rte_eth_link *link) 3760 { 3761 struct rte_eth_link *dst = &dev->data->dev_link; 3762 struct rte_eth_link *src = link; 3763 3764 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3765 *(uint64_t *)src) == 0) 3766 return -1; 3767 3768 return 0; 3769 } 3770 3771 static int 3772 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 3773 { 3774 #define CHECK_INTERVAL 100 /* 100ms */ 3775 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 3776 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3777 struct ice_link_status link_status; 3778 struct rte_eth_link link, old; 3779 int status; 3780 unsigned int rep_cnt = MAX_REPEAT_TIME; 3781 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3782 3783 memset(&link, 0, sizeof(link)); 3784 memset(&old, 0, sizeof(old)); 3785 memset(&link_status, 0, sizeof(link_status)); 3786 ice_atomic_read_link_status(dev, &old); 3787 3788 do { 3789 /* Get link status information from hardware */ 3790 status = ice_aq_get_link_info(hw->port_info, enable_lse, 3791 &link_status, NULL); 3792 if (status != ICE_SUCCESS) { 3793 link.link_speed = ETH_SPEED_NUM_100M; 3794 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3795 PMD_DRV_LOG(ERR, "Failed to get link info"); 3796 goto out; 3797 } 3798 3799 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 3800 if (!wait_to_complete || link.link_status) 3801 break; 3802 3803 rte_delay_ms(CHECK_INTERVAL); 3804 } while (--rep_cnt); 3805 3806 if (!link.link_status) 3807 goto out; 3808 3809 /* Full-duplex operation at all supported speeds */ 3810 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3811 3812 /* Parse the link status */ 3813 switch (link_status.link_speed) { 3814 case ICE_AQ_LINK_SPEED_10MB: 3815 link.link_speed = ETH_SPEED_NUM_10M; 3816 break; 3817 case ICE_AQ_LINK_SPEED_100MB: 3818 link.link_speed = ETH_SPEED_NUM_100M; 3819 break; 3820 case ICE_AQ_LINK_SPEED_1000MB: 3821 link.link_speed = ETH_SPEED_NUM_1G; 3822 break; 3823 case ICE_AQ_LINK_SPEED_2500MB: 3824 link.link_speed = ETH_SPEED_NUM_2_5G; 3825 break; 3826 case ICE_AQ_LINK_SPEED_5GB: 3827 link.link_speed = ETH_SPEED_NUM_5G; 3828 break; 3829 case ICE_AQ_LINK_SPEED_10GB: 3830 link.link_speed = ETH_SPEED_NUM_10G; 3831 break; 3832 case ICE_AQ_LINK_SPEED_20GB: 3833 link.link_speed = ETH_SPEED_NUM_20G; 3834 break; 3835 case ICE_AQ_LINK_SPEED_25GB: 3836 link.link_speed = ETH_SPEED_NUM_25G; 3837 break; 3838 case ICE_AQ_LINK_SPEED_40GB: 3839 link.link_speed = ETH_SPEED_NUM_40G; 3840 break; 3841 case ICE_AQ_LINK_SPEED_50GB: 3842 link.link_speed = ETH_SPEED_NUM_50G; 3843 break; 3844 case ICE_AQ_LINK_SPEED_100GB: 3845 link.link_speed = ETH_SPEED_NUM_100G; 3846 break; 3847 case ICE_AQ_LINK_SPEED_UNKNOWN: 3848 PMD_DRV_LOG(ERR, "Unknown link speed"); 3849 link.link_speed = ETH_SPEED_NUM_UNKNOWN; 3850 break; 3851 default: 3852 PMD_DRV_LOG(ERR, "None link speed"); 3853 link.link_speed = ETH_SPEED_NUM_NONE; 3854 break; 3855 } 3856 3857 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 3858 ETH_LINK_SPEED_FIXED); 3859 3860 out: 3861 ice_atomic_write_link_status(dev, &link); 3862 if (link.link_status == old.link_status) 3863 return -1; 3864 3865 return 0; 3866 } 3867 3868 /* Force the physical link state by getting the current PHY capabilities from 3869 * hardware and setting the PHY config based on the determined capabilities. If 3870 * link changes, link event will be triggered because both the Enable Automatic 3871 * Link Update and LESM Enable bits are set when setting the PHY capabilities. 3872 */ 3873 static enum ice_status 3874 ice_force_phys_link_state(struct ice_hw *hw, bool link_up) 3875 { 3876 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3877 struct ice_aqc_get_phy_caps_data *pcaps; 3878 struct ice_port_info *pi; 3879 enum ice_status status; 3880 3881 if (!hw || !hw->port_info) 3882 return ICE_ERR_PARAM; 3883 3884 pi = hw->port_info; 3885 3886 pcaps = (struct ice_aqc_get_phy_caps_data *) 3887 ice_malloc(hw, sizeof(*pcaps)); 3888 if (!pcaps) 3889 return ICE_ERR_NO_MEMORY; 3890 3891 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 3892 NULL); 3893 if (status) 3894 goto out; 3895 3896 /* No change in link */ 3897 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) && 3898 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) 3899 goto out; 3900 3901 cfg.phy_type_low = pcaps->phy_type_low; 3902 cfg.phy_type_high = pcaps->phy_type_high; 3903 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3904 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an; 3905 cfg.eee_cap = pcaps->eee_cap; 3906 cfg.eeer_value = pcaps->eeer_value; 3907 cfg.link_fec_opt = pcaps->link_fec_options; 3908 if (link_up) 3909 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 3910 else 3911 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 3912 3913 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3914 3915 out: 3916 ice_free(hw, pcaps); 3917 return status; 3918 } 3919 3920 static int 3921 ice_dev_set_link_up(struct rte_eth_dev *dev) 3922 { 3923 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3924 3925 return ice_force_phys_link_state(hw, true); 3926 } 3927 3928 static int 3929 ice_dev_set_link_down(struct rte_eth_dev *dev) 3930 { 3931 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3932 3933 return ice_force_phys_link_state(hw, false); 3934 } 3935 3936 static int 3937 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3938 { 3939 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3940 struct rte_eth_dev_data *dev_data = pf->dev_data; 3941 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 3942 3943 /* check if mtu is within the allowed range */ 3944 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 3945 return -EINVAL; 3946 3947 /* mtu setting is forbidden if port is start */ 3948 if (dev_data->dev_started) { 3949 PMD_DRV_LOG(ERR, 3950 "port %d must be stopped before configuration", 3951 dev_data->port_id); 3952 return -EBUSY; 3953 } 3954 3955 if (frame_size > RTE_ETHER_MAX_LEN) 3956 dev_data->dev_conf.rxmode.offloads |= 3957 DEV_RX_OFFLOAD_JUMBO_FRAME; 3958 else 3959 dev_data->dev_conf.rxmode.offloads &= 3960 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 3961 3962 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3963 3964 return 0; 3965 } 3966 3967 static int ice_macaddr_set(struct rte_eth_dev *dev, 3968 struct rte_ether_addr *mac_addr) 3969 { 3970 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3971 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3972 struct ice_vsi *vsi = pf->main_vsi; 3973 struct ice_mac_filter *f; 3974 uint8_t flags = 0; 3975 int ret; 3976 3977 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 3978 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 3979 return -EINVAL; 3980 } 3981 3982 TAILQ_FOREACH(f, &vsi->mac_list, next) { 3983 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 3984 break; 3985 } 3986 3987 if (!f) { 3988 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 3989 return -EIO; 3990 } 3991 3992 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 3993 if (ret != ICE_SUCCESS) { 3994 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 3995 return -EIO; 3996 } 3997 ret = ice_add_mac_filter(vsi, mac_addr); 3998 if (ret != ICE_SUCCESS) { 3999 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 4000 return -EIO; 4001 } 4002 rte_ether_addr_copy(mac_addr, &pf->dev_addr); 4003 4004 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 4005 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 4006 if (ret != ICE_SUCCESS) 4007 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 4008 4009 return 0; 4010 } 4011 4012 /* Add a MAC address, and update filters */ 4013 static int 4014 ice_macaddr_add(struct rte_eth_dev *dev, 4015 struct rte_ether_addr *mac_addr, 4016 __rte_unused uint32_t index, 4017 __rte_unused uint32_t pool) 4018 { 4019 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4020 struct ice_vsi *vsi = pf->main_vsi; 4021 int ret; 4022 4023 ret = ice_add_mac_filter(vsi, mac_addr); 4024 if (ret != ICE_SUCCESS) { 4025 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 4026 return -EINVAL; 4027 } 4028 4029 return ICE_SUCCESS; 4030 } 4031 4032 /* Remove a MAC address, and update filters */ 4033 static void 4034 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 4035 { 4036 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4037 struct ice_vsi *vsi = pf->main_vsi; 4038 struct rte_eth_dev_data *data = dev->data; 4039 struct rte_ether_addr *macaddr; 4040 int ret; 4041 4042 macaddr = &data->mac_addrs[index]; 4043 ret = ice_remove_mac_filter(vsi, macaddr); 4044 if (ret) { 4045 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 4046 return; 4047 } 4048 } 4049 4050 static int 4051 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 4052 { 4053 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4054 struct ice_vsi *vsi = pf->main_vsi; 4055 int ret; 4056 4057 PMD_INIT_FUNC_TRACE(); 4058 4059 if (on) { 4060 ret = ice_add_vlan_filter(vsi, vlan_id); 4061 if (ret < 0) { 4062 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 4063 return -EINVAL; 4064 } 4065 } else { 4066 ret = ice_remove_vlan_filter(vsi, vlan_id); 4067 if (ret < 0) { 4068 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 4069 return -EINVAL; 4070 } 4071 } 4072 4073 return 0; 4074 } 4075 4076 /* Configure vlan filter on or off */ 4077 static int 4078 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 4079 { 4080 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4081 struct ice_vsi_ctx ctxt; 4082 uint8_t sec_flags, sw_flags2; 4083 int ret = 0; 4084 4085 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 4086 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 4087 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 4088 4089 if (on) { 4090 vsi->info.sec_flags |= sec_flags; 4091 vsi->info.sw_flags2 |= sw_flags2; 4092 } else { 4093 vsi->info.sec_flags &= ~sec_flags; 4094 vsi->info.sw_flags2 &= ~sw_flags2; 4095 } 4096 vsi->info.sw_id = hw->port_info->sw_id; 4097 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4098 ctxt.info.valid_sections = 4099 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 4100 ICE_AQ_VSI_PROP_SECURITY_VALID); 4101 ctxt.vsi_num = vsi->vsi_id; 4102 4103 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4104 if (ret) { 4105 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 4106 on ? "enable" : "disable"); 4107 return -EINVAL; 4108 } else { 4109 vsi->info.valid_sections |= 4110 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 4111 ICE_AQ_VSI_PROP_SECURITY_VALID); 4112 } 4113 4114 /* consist with other drivers, allow untagged packet when vlan filter on */ 4115 if (on) 4116 ret = ice_add_vlan_filter(vsi, 0); 4117 else 4118 ret = ice_remove_vlan_filter(vsi, 0); 4119 4120 return 0; 4121 } 4122 4123 static int 4124 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 4125 { 4126 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4127 struct ice_vsi_ctx ctxt; 4128 uint8_t vlan_flags; 4129 int ret = 0; 4130 4131 /* Check if it has been already on or off */ 4132 if (vsi->info.valid_sections & 4133 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 4134 if (on) { 4135 if ((vsi->info.vlan_flags & 4136 ICE_AQ_VSI_VLAN_EMOD_M) == 4137 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) 4138 return 0; /* already on */ 4139 } else { 4140 if ((vsi->info.vlan_flags & 4141 ICE_AQ_VSI_VLAN_EMOD_M) == 4142 ICE_AQ_VSI_VLAN_EMOD_NOTHING) 4143 return 0; /* already off */ 4144 } 4145 } 4146 4147 if (on) 4148 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; 4149 else 4150 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; 4151 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); 4152 vsi->info.vlan_flags |= vlan_flags; 4153 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4154 ctxt.info.valid_sections = 4155 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4156 ctxt.vsi_num = vsi->vsi_id; 4157 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4158 if (ret) { 4159 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 4160 on ? "enable" : "disable"); 4161 return -EINVAL; 4162 } 4163 4164 vsi->info.valid_sections |= 4165 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4166 4167 return ret; 4168 } 4169 4170 static int 4171 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 4172 { 4173 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4174 struct ice_vsi *vsi = pf->main_vsi; 4175 struct rte_eth_rxmode *rxmode; 4176 4177 rxmode = &dev->data->dev_conf.rxmode; 4178 if (mask & ETH_VLAN_FILTER_MASK) { 4179 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 4180 ice_vsi_config_vlan_filter(vsi, true); 4181 else 4182 ice_vsi_config_vlan_filter(vsi, false); 4183 } 4184 4185 if (mask & ETH_VLAN_STRIP_MASK) { 4186 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 4187 ice_vsi_config_vlan_stripping(vsi, true); 4188 else 4189 ice_vsi_config_vlan_stripping(vsi, false); 4190 } 4191 4192 if (mask & ETH_VLAN_EXTEND_MASK) { 4193 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 4194 ice_vsi_config_double_vlan(vsi, true); 4195 else 4196 ice_vsi_config_double_vlan(vsi, false); 4197 } 4198 4199 return 0; 4200 } 4201 4202 static int 4203 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4204 { 4205 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 4206 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4207 int ret; 4208 4209 if (!lut) 4210 return -EINVAL; 4211 4212 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 4213 ret = ice_aq_get_rss_lut(hw, vsi->idx, 4214 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); 4215 if (ret) { 4216 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 4217 return -EINVAL; 4218 } 4219 } else { 4220 uint64_t *lut_dw = (uint64_t *)lut; 4221 uint16_t i, lut_size_dw = lut_size / 4; 4222 4223 for (i = 0; i < lut_size_dw; i++) 4224 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 4225 } 4226 4227 return 0; 4228 } 4229 4230 static int 4231 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4232 { 4233 struct ice_pf *pf; 4234 struct ice_hw *hw; 4235 int ret; 4236 4237 if (!vsi || !lut) 4238 return -EINVAL; 4239 4240 pf = ICE_VSI_TO_PF(vsi); 4241 hw = ICE_VSI_TO_HW(vsi); 4242 4243 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 4244 ret = ice_aq_set_rss_lut(hw, vsi->idx, 4245 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); 4246 if (ret) { 4247 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 4248 return -EINVAL; 4249 } 4250 } else { 4251 uint64_t *lut_dw = (uint64_t *)lut; 4252 uint16_t i, lut_size_dw = lut_size / 4; 4253 4254 for (i = 0; i < lut_size_dw; i++) 4255 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 4256 4257 ice_flush(hw); 4258 } 4259 4260 return 0; 4261 } 4262 4263 static int 4264 ice_rss_reta_update(struct rte_eth_dev *dev, 4265 struct rte_eth_rss_reta_entry64 *reta_conf, 4266 uint16_t reta_size) 4267 { 4268 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4269 uint16_t i, lut_size = pf->hash_lut_size; 4270 uint16_t idx, shift; 4271 uint8_t *lut; 4272 int ret; 4273 4274 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 4275 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 4276 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 4277 PMD_DRV_LOG(ERR, 4278 "The size of hash lookup table configured (%d)" 4279 "doesn't match the number hardware can " 4280 "supported (128, 512, 2048)", 4281 reta_size); 4282 return -EINVAL; 4283 } 4284 4285 /* It MUST use the current LUT size to get the RSS lookup table, 4286 * otherwise if will fail with -100 error code. 4287 */ 4288 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 4289 if (!lut) { 4290 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4291 return -ENOMEM; 4292 } 4293 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 4294 if (ret) 4295 goto out; 4296 4297 for (i = 0; i < reta_size; i++) { 4298 idx = i / RTE_RETA_GROUP_SIZE; 4299 shift = i % RTE_RETA_GROUP_SIZE; 4300 if (reta_conf[idx].mask & (1ULL << shift)) 4301 lut[i] = reta_conf[idx].reta[shift]; 4302 } 4303 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 4304 if (ret == 0 && lut_size != reta_size) { 4305 PMD_DRV_LOG(INFO, 4306 "The size of hash lookup table is changed from (%d) to (%d)", 4307 lut_size, reta_size); 4308 pf->hash_lut_size = reta_size; 4309 } 4310 4311 out: 4312 rte_free(lut); 4313 4314 return ret; 4315 } 4316 4317 static int 4318 ice_rss_reta_query(struct rte_eth_dev *dev, 4319 struct rte_eth_rss_reta_entry64 *reta_conf, 4320 uint16_t reta_size) 4321 { 4322 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4323 uint16_t i, lut_size = pf->hash_lut_size; 4324 uint16_t idx, shift; 4325 uint8_t *lut; 4326 int ret; 4327 4328 if (reta_size != lut_size) { 4329 PMD_DRV_LOG(ERR, 4330 "The size of hash lookup table configured (%d)" 4331 "doesn't match the number hardware can " 4332 "supported (%d)", 4333 reta_size, lut_size); 4334 return -EINVAL; 4335 } 4336 4337 lut = rte_zmalloc(NULL, reta_size, 0); 4338 if (!lut) { 4339 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4340 return -ENOMEM; 4341 } 4342 4343 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 4344 if (ret) 4345 goto out; 4346 4347 for (i = 0; i < reta_size; i++) { 4348 idx = i / RTE_RETA_GROUP_SIZE; 4349 shift = i % RTE_RETA_GROUP_SIZE; 4350 if (reta_conf[idx].mask & (1ULL << shift)) 4351 reta_conf[idx].reta[shift] = lut[i]; 4352 } 4353 4354 out: 4355 rte_free(lut); 4356 4357 return ret; 4358 } 4359 4360 static int 4361 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 4362 { 4363 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4364 int ret = 0; 4365 4366 if (!key || key_len == 0) { 4367 PMD_DRV_LOG(DEBUG, "No key to be configured"); 4368 return 0; 4369 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 4370 sizeof(uint32_t)) { 4371 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 4372 return -EINVAL; 4373 } 4374 4375 struct ice_aqc_get_set_rss_keys *key_dw = 4376 (struct ice_aqc_get_set_rss_keys *)key; 4377 4378 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 4379 if (ret) { 4380 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 4381 ret = -EINVAL; 4382 } 4383 4384 return ret; 4385 } 4386 4387 static int 4388 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 4389 { 4390 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4391 int ret; 4392 4393 if (!key || !key_len) 4394 return -EINVAL; 4395 4396 ret = ice_aq_get_rss_key 4397 (hw, vsi->idx, 4398 (struct ice_aqc_get_set_rss_keys *)key); 4399 if (ret) { 4400 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 4401 return -EINVAL; 4402 } 4403 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 4404 4405 return 0; 4406 } 4407 4408 static int 4409 ice_rss_hash_update(struct rte_eth_dev *dev, 4410 struct rte_eth_rss_conf *rss_conf) 4411 { 4412 enum ice_status status = ICE_SUCCESS; 4413 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4414 struct ice_vsi *vsi = pf->main_vsi; 4415 4416 /* set hash key */ 4417 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 4418 if (status) 4419 return status; 4420 4421 if (rss_conf->rss_hf == 0) 4422 return 0; 4423 4424 /* RSS hash configuration */ 4425 ice_rss_hash_set(pf, rss_conf->rss_hf); 4426 4427 return 0; 4428 } 4429 4430 static int 4431 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 4432 struct rte_eth_rss_conf *rss_conf) 4433 { 4434 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4435 struct ice_vsi *vsi = pf->main_vsi; 4436 4437 ice_get_rss_key(vsi, rss_conf->rss_key, 4438 &rss_conf->rss_key_len); 4439 4440 /* TODO: default set to 0 as hf config is not supported now */ 4441 rss_conf->rss_hf = 0; 4442 return 0; 4443 } 4444 4445 static int 4446 ice_promisc_enable(struct rte_eth_dev *dev) 4447 { 4448 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4449 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4450 struct ice_vsi *vsi = pf->main_vsi; 4451 enum ice_status status; 4452 uint8_t pmask; 4453 int ret = 0; 4454 4455 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 4456 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4457 4458 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4459 switch (status) { 4460 case ICE_ERR_ALREADY_EXISTS: 4461 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 4462 case ICE_SUCCESS: 4463 break; 4464 default: 4465 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 4466 ret = -EAGAIN; 4467 } 4468 4469 return ret; 4470 } 4471 4472 static int 4473 ice_promisc_disable(struct rte_eth_dev *dev) 4474 { 4475 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4476 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4477 struct ice_vsi *vsi = pf->main_vsi; 4478 enum ice_status status; 4479 uint8_t pmask; 4480 int ret = 0; 4481 4482 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 4483 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4484 4485 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 4486 if (status != ICE_SUCCESS) { 4487 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 4488 ret = -EAGAIN; 4489 } 4490 4491 return ret; 4492 } 4493 4494 static int 4495 ice_allmulti_enable(struct rte_eth_dev *dev) 4496 { 4497 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4498 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4499 struct ice_vsi *vsi = pf->main_vsi; 4500 enum ice_status status; 4501 uint8_t pmask; 4502 int ret = 0; 4503 4504 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4505 4506 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4507 4508 switch (status) { 4509 case ICE_ERR_ALREADY_EXISTS: 4510 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled"); 4511 case ICE_SUCCESS: 4512 break; 4513 default: 4514 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 4515 ret = -EAGAIN; 4516 } 4517 4518 return ret; 4519 } 4520 4521 static int 4522 ice_allmulti_disable(struct rte_eth_dev *dev) 4523 { 4524 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4525 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4526 struct ice_vsi *vsi = pf->main_vsi; 4527 enum ice_status status; 4528 uint8_t pmask; 4529 int ret = 0; 4530 4531 if (dev->data->promiscuous == 1) 4532 return 0; /* must remain in all_multicast mode */ 4533 4534 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4535 4536 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 4537 if (status != ICE_SUCCESS) { 4538 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 4539 ret = -EAGAIN; 4540 } 4541 4542 return ret; 4543 } 4544 4545 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 4546 uint16_t queue_id) 4547 { 4548 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 4549 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4550 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4551 uint32_t val; 4552 uint16_t msix_intr; 4553 4554 msix_intr = intr_handle->intr_vec[queue_id]; 4555 4556 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 4557 GLINT_DYN_CTL_ITR_INDX_M; 4558 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 4559 4560 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 4561 rte_intr_ack(&pci_dev->intr_handle); 4562 4563 return 0; 4564 } 4565 4566 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 4567 uint16_t queue_id) 4568 { 4569 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 4570 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4571 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4572 uint16_t msix_intr; 4573 4574 msix_intr = intr_handle->intr_vec[queue_id]; 4575 4576 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 4577 4578 return 0; 4579 } 4580 4581 static int 4582 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 4583 { 4584 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4585 u8 ver, patch; 4586 u16 build; 4587 int ret; 4588 4589 ver = hw->flash.orom.major; 4590 patch = hw->flash.orom.patch; 4591 build = hw->flash.orom.build; 4592 4593 ret = snprintf(fw_version, fw_size, 4594 "%x.%02x 0x%08x %d.%d.%d", 4595 hw->flash.nvm.major, 4596 hw->flash.nvm.minor, 4597 hw->flash.nvm.eetrack, 4598 ver, build, patch); 4599 4600 /* add the size of '\0' */ 4601 ret += 1; 4602 if (fw_size < (u32)ret) 4603 return ret; 4604 else 4605 return 0; 4606 } 4607 4608 static int 4609 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 4610 { 4611 struct ice_hw *hw; 4612 struct ice_vsi_ctx ctxt; 4613 uint8_t vlan_flags = 0; 4614 int ret; 4615 4616 if (!vsi || !info) { 4617 PMD_DRV_LOG(ERR, "invalid parameters"); 4618 return -EINVAL; 4619 } 4620 4621 if (info->on) { 4622 vsi->info.pvid = info->config.pvid; 4623 /** 4624 * If insert pvid is enabled, only tagged pkts are 4625 * allowed to be sent out. 4626 */ 4627 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | 4628 ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 4629 } else { 4630 vsi->info.pvid = 0; 4631 if (info->config.reject.tagged == 0) 4632 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; 4633 4634 if (info->config.reject.untagged == 0) 4635 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 4636 } 4637 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | 4638 ICE_AQ_VSI_VLAN_MODE_M); 4639 vsi->info.vlan_flags |= vlan_flags; 4640 memset(&ctxt, 0, sizeof(ctxt)); 4641 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4642 ctxt.info.valid_sections = 4643 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4644 ctxt.vsi_num = vsi->vsi_id; 4645 4646 hw = ICE_VSI_TO_HW(vsi); 4647 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4648 if (ret != ICE_SUCCESS) { 4649 PMD_DRV_LOG(ERR, 4650 "update VSI for VLAN insert failed, err %d", 4651 ret); 4652 return -EINVAL; 4653 } 4654 4655 vsi->info.valid_sections |= 4656 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4657 4658 return ret; 4659 } 4660 4661 static int 4662 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 4663 { 4664 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4665 struct ice_vsi *vsi = pf->main_vsi; 4666 struct rte_eth_dev_data *data = pf->dev_data; 4667 struct ice_vsi_vlan_pvid_info info; 4668 int ret; 4669 4670 memset(&info, 0, sizeof(info)); 4671 info.on = on; 4672 if (info.on) { 4673 info.config.pvid = pvid; 4674 } else { 4675 info.config.reject.tagged = 4676 data->dev_conf.txmode.hw_vlan_reject_tagged; 4677 info.config.reject.untagged = 4678 data->dev_conf.txmode.hw_vlan_reject_untagged; 4679 } 4680 4681 ret = ice_vsi_vlan_pvid_set(vsi, &info); 4682 if (ret < 0) { 4683 PMD_DRV_LOG(ERR, "Failed to set pvid."); 4684 return -EINVAL; 4685 } 4686 4687 return 0; 4688 } 4689 4690 static int 4691 ice_get_eeprom_length(struct rte_eth_dev *dev) 4692 { 4693 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4694 4695 return hw->flash.flash_size; 4696 } 4697 4698 static int 4699 ice_get_eeprom(struct rte_eth_dev *dev, 4700 struct rte_dev_eeprom_info *eeprom) 4701 { 4702 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4703 enum ice_status status = ICE_SUCCESS; 4704 uint8_t *data = eeprom->data; 4705 4706 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4707 4708 status = ice_acquire_nvm(hw, ICE_RES_READ); 4709 if (status) { 4710 PMD_DRV_LOG(ERR, "acquire nvm failed."); 4711 return -EIO; 4712 } 4713 4714 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length, 4715 data, false); 4716 4717 ice_release_nvm(hw); 4718 4719 if (status) { 4720 PMD_DRV_LOG(ERR, "EEPROM read failed."); 4721 return -EIO; 4722 } 4723 4724 return 0; 4725 } 4726 4727 static void 4728 ice_stat_update_32(struct ice_hw *hw, 4729 uint32_t reg, 4730 bool offset_loaded, 4731 uint64_t *offset, 4732 uint64_t *stat) 4733 { 4734 uint64_t new_data; 4735 4736 new_data = (uint64_t)ICE_READ_REG(hw, reg); 4737 if (!offset_loaded) 4738 *offset = new_data; 4739 4740 if (new_data >= *offset) 4741 *stat = (uint64_t)(new_data - *offset); 4742 else 4743 *stat = (uint64_t)((new_data + 4744 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 4745 - *offset); 4746 } 4747 4748 static void 4749 ice_stat_update_40(struct ice_hw *hw, 4750 uint32_t hireg, 4751 uint32_t loreg, 4752 bool offset_loaded, 4753 uint64_t *offset, 4754 uint64_t *stat) 4755 { 4756 uint64_t new_data; 4757 4758 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 4759 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 4760 ICE_32_BIT_WIDTH; 4761 4762 if (!offset_loaded) 4763 *offset = new_data; 4764 4765 if (new_data >= *offset) 4766 *stat = new_data - *offset; 4767 else 4768 *stat = (uint64_t)((new_data + 4769 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 4770 *offset); 4771 4772 *stat &= ICE_40_BIT_MASK; 4773 } 4774 4775 /* Get all the statistics of a VSI */ 4776 static void 4777 ice_update_vsi_stats(struct ice_vsi *vsi) 4778 { 4779 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 4780 struct ice_eth_stats *nes = &vsi->eth_stats; 4781 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4782 int idx = rte_le_to_cpu_16(vsi->vsi_id); 4783 4784 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 4785 vsi->offset_loaded, &oes->rx_bytes, 4786 &nes->rx_bytes); 4787 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 4788 vsi->offset_loaded, &oes->rx_unicast, 4789 &nes->rx_unicast); 4790 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 4791 vsi->offset_loaded, &oes->rx_multicast, 4792 &nes->rx_multicast); 4793 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 4794 vsi->offset_loaded, &oes->rx_broadcast, 4795 &nes->rx_broadcast); 4796 /* enlarge the limitation when rx_bytes overflowed */ 4797 if (vsi->offset_loaded) { 4798 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes) 4799 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4800 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes); 4801 } 4802 vsi->old_rx_bytes = nes->rx_bytes; 4803 /* exclude CRC bytes */ 4804 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 4805 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 4806 4807 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 4808 &oes->rx_discards, &nes->rx_discards); 4809 /* GLV_REPC not supported */ 4810 /* GLV_RMPC not supported */ 4811 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 4812 &oes->rx_unknown_protocol, 4813 &nes->rx_unknown_protocol); 4814 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 4815 vsi->offset_loaded, &oes->tx_bytes, 4816 &nes->tx_bytes); 4817 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 4818 vsi->offset_loaded, &oes->tx_unicast, 4819 &nes->tx_unicast); 4820 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 4821 vsi->offset_loaded, &oes->tx_multicast, 4822 &nes->tx_multicast); 4823 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 4824 vsi->offset_loaded, &oes->tx_broadcast, 4825 &nes->tx_broadcast); 4826 /* GLV_TDPC not supported */ 4827 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 4828 &oes->tx_errors, &nes->tx_errors); 4829 /* enlarge the limitation when tx_bytes overflowed */ 4830 if (vsi->offset_loaded) { 4831 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes) 4832 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4833 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes); 4834 } 4835 vsi->old_tx_bytes = nes->tx_bytes; 4836 vsi->offset_loaded = true; 4837 4838 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 4839 vsi->vsi_id); 4840 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 4841 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 4842 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 4843 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 4844 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 4845 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 4846 nes->rx_unknown_protocol); 4847 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 4848 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 4849 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 4850 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 4851 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 4852 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 4853 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 4854 vsi->vsi_id); 4855 } 4856 4857 static void 4858 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 4859 { 4860 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 4861 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 4862 4863 /* Get statistics of struct ice_eth_stats */ 4864 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 4865 GLPRT_GORCL(hw->port_info->lport), 4866 pf->offset_loaded, &os->eth.rx_bytes, 4867 &ns->eth.rx_bytes); 4868 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 4869 GLPRT_UPRCL(hw->port_info->lport), 4870 pf->offset_loaded, &os->eth.rx_unicast, 4871 &ns->eth.rx_unicast); 4872 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 4873 GLPRT_MPRCL(hw->port_info->lport), 4874 pf->offset_loaded, &os->eth.rx_multicast, 4875 &ns->eth.rx_multicast); 4876 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 4877 GLPRT_BPRCL(hw->port_info->lport), 4878 pf->offset_loaded, &os->eth.rx_broadcast, 4879 &ns->eth.rx_broadcast); 4880 ice_stat_update_32(hw, PRTRPB_RDPC, 4881 pf->offset_loaded, &os->eth.rx_discards, 4882 &ns->eth.rx_discards); 4883 /* enlarge the limitation when rx_bytes overflowed */ 4884 if (pf->offset_loaded) { 4885 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes) 4886 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4887 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes); 4888 } 4889 pf->old_rx_bytes = ns->eth.rx_bytes; 4890 4891 /* Workaround: CRC size should not be included in byte statistics, 4892 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 4893 * packet. 4894 */ 4895 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 4896 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 4897 4898 /* GLPRT_REPC not supported */ 4899 /* GLPRT_RMPC not supported */ 4900 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 4901 pf->offset_loaded, 4902 &os->eth.rx_unknown_protocol, 4903 &ns->eth.rx_unknown_protocol); 4904 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 4905 GLPRT_GOTCL(hw->port_info->lport), 4906 pf->offset_loaded, &os->eth.tx_bytes, 4907 &ns->eth.tx_bytes); 4908 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 4909 GLPRT_UPTCL(hw->port_info->lport), 4910 pf->offset_loaded, &os->eth.tx_unicast, 4911 &ns->eth.tx_unicast); 4912 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 4913 GLPRT_MPTCL(hw->port_info->lport), 4914 pf->offset_loaded, &os->eth.tx_multicast, 4915 &ns->eth.tx_multicast); 4916 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 4917 GLPRT_BPTCL(hw->port_info->lport), 4918 pf->offset_loaded, &os->eth.tx_broadcast, 4919 &ns->eth.tx_broadcast); 4920 /* enlarge the limitation when tx_bytes overflowed */ 4921 if (pf->offset_loaded) { 4922 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes) 4923 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4924 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes); 4925 } 4926 pf->old_tx_bytes = ns->eth.tx_bytes; 4927 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 4928 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 4929 4930 /* GLPRT_TEPC not supported */ 4931 4932 /* additional port specific stats */ 4933 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 4934 pf->offset_loaded, &os->tx_dropped_link_down, 4935 &ns->tx_dropped_link_down); 4936 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 4937 pf->offset_loaded, &os->crc_errors, 4938 &ns->crc_errors); 4939 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 4940 pf->offset_loaded, &os->illegal_bytes, 4941 &ns->illegal_bytes); 4942 /* GLPRT_ERRBC not supported */ 4943 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 4944 pf->offset_loaded, &os->mac_local_faults, 4945 &ns->mac_local_faults); 4946 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 4947 pf->offset_loaded, &os->mac_remote_faults, 4948 &ns->mac_remote_faults); 4949 4950 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 4951 pf->offset_loaded, &os->rx_len_errors, 4952 &ns->rx_len_errors); 4953 4954 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 4955 pf->offset_loaded, &os->link_xon_rx, 4956 &ns->link_xon_rx); 4957 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 4958 pf->offset_loaded, &os->link_xoff_rx, 4959 &ns->link_xoff_rx); 4960 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 4961 pf->offset_loaded, &os->link_xon_tx, 4962 &ns->link_xon_tx); 4963 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 4964 pf->offset_loaded, &os->link_xoff_tx, 4965 &ns->link_xoff_tx); 4966 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 4967 GLPRT_PRC64L(hw->port_info->lport), 4968 pf->offset_loaded, &os->rx_size_64, 4969 &ns->rx_size_64); 4970 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 4971 GLPRT_PRC127L(hw->port_info->lport), 4972 pf->offset_loaded, &os->rx_size_127, 4973 &ns->rx_size_127); 4974 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 4975 GLPRT_PRC255L(hw->port_info->lport), 4976 pf->offset_loaded, &os->rx_size_255, 4977 &ns->rx_size_255); 4978 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 4979 GLPRT_PRC511L(hw->port_info->lport), 4980 pf->offset_loaded, &os->rx_size_511, 4981 &ns->rx_size_511); 4982 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 4983 GLPRT_PRC1023L(hw->port_info->lport), 4984 pf->offset_loaded, &os->rx_size_1023, 4985 &ns->rx_size_1023); 4986 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 4987 GLPRT_PRC1522L(hw->port_info->lport), 4988 pf->offset_loaded, &os->rx_size_1522, 4989 &ns->rx_size_1522); 4990 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 4991 GLPRT_PRC9522L(hw->port_info->lport), 4992 pf->offset_loaded, &os->rx_size_big, 4993 &ns->rx_size_big); 4994 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 4995 pf->offset_loaded, &os->rx_undersize, 4996 &ns->rx_undersize); 4997 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 4998 pf->offset_loaded, &os->rx_fragments, 4999 &ns->rx_fragments); 5000 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 5001 pf->offset_loaded, &os->rx_oversize, 5002 &ns->rx_oversize); 5003 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 5004 pf->offset_loaded, &os->rx_jabber, 5005 &ns->rx_jabber); 5006 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 5007 GLPRT_PTC64L(hw->port_info->lport), 5008 pf->offset_loaded, &os->tx_size_64, 5009 &ns->tx_size_64); 5010 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 5011 GLPRT_PTC127L(hw->port_info->lport), 5012 pf->offset_loaded, &os->tx_size_127, 5013 &ns->tx_size_127); 5014 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 5015 GLPRT_PTC255L(hw->port_info->lport), 5016 pf->offset_loaded, &os->tx_size_255, 5017 &ns->tx_size_255); 5018 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 5019 GLPRT_PTC511L(hw->port_info->lport), 5020 pf->offset_loaded, &os->tx_size_511, 5021 &ns->tx_size_511); 5022 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 5023 GLPRT_PTC1023L(hw->port_info->lport), 5024 pf->offset_loaded, &os->tx_size_1023, 5025 &ns->tx_size_1023); 5026 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 5027 GLPRT_PTC1522L(hw->port_info->lport), 5028 pf->offset_loaded, &os->tx_size_1522, 5029 &ns->tx_size_1522); 5030 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 5031 GLPRT_PTC9522L(hw->port_info->lport), 5032 pf->offset_loaded, &os->tx_size_big, 5033 &ns->tx_size_big); 5034 5035 /* GLPRT_MSPDC not supported */ 5036 /* GLPRT_XEC not supported */ 5037 5038 pf->offset_loaded = true; 5039 5040 if (pf->main_vsi) 5041 ice_update_vsi_stats(pf->main_vsi); 5042 } 5043 5044 /* Get all statistics of a port */ 5045 static int 5046 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 5047 { 5048 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5049 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5050 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 5051 5052 /* call read registers - updates values, now write them to struct */ 5053 ice_read_stats_registers(pf, hw); 5054 5055 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 5056 pf->main_vsi->eth_stats.rx_multicast + 5057 pf->main_vsi->eth_stats.rx_broadcast - 5058 pf->main_vsi->eth_stats.rx_discards; 5059 stats->opackets = ns->eth.tx_unicast + 5060 ns->eth.tx_multicast + 5061 ns->eth.tx_broadcast; 5062 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 5063 stats->obytes = ns->eth.tx_bytes; 5064 stats->oerrors = ns->eth.tx_errors + 5065 pf->main_vsi->eth_stats.tx_errors; 5066 5067 /* Rx Errors */ 5068 stats->imissed = ns->eth.rx_discards + 5069 pf->main_vsi->eth_stats.rx_discards; 5070 stats->ierrors = ns->crc_errors + 5071 ns->rx_undersize + 5072 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 5073 5074 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 5075 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 5076 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 5077 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 5078 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 5079 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 5080 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 5081 pf->main_vsi->eth_stats.rx_discards); 5082 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 5083 ns->eth.rx_unknown_protocol); 5084 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 5085 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 5086 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 5087 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 5088 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 5089 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 5090 pf->main_vsi->eth_stats.tx_discards); 5091 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 5092 5093 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 5094 ns->tx_dropped_link_down); 5095 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 5096 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 5097 ns->illegal_bytes); 5098 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 5099 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 5100 ns->mac_local_faults); 5101 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 5102 ns->mac_remote_faults); 5103 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 5104 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 5105 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 5106 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 5107 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 5108 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 5109 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 5110 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 5111 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 5112 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 5113 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 5114 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 5115 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 5116 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 5117 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 5118 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 5119 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 5120 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 5121 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 5122 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 5123 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 5124 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 5125 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 5126 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 5127 return 0; 5128 } 5129 5130 /* Reset the statistics */ 5131 static int 5132 ice_stats_reset(struct rte_eth_dev *dev) 5133 { 5134 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5135 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5136 5137 /* Mark PF and VSI stats to update the offset, aka "reset" */ 5138 pf->offset_loaded = false; 5139 if (pf->main_vsi) 5140 pf->main_vsi->offset_loaded = false; 5141 5142 /* read the stats, reading current register values into offset */ 5143 ice_read_stats_registers(pf, hw); 5144 5145 return 0; 5146 } 5147 5148 static uint32_t 5149 ice_xstats_calc_num(void) 5150 { 5151 uint32_t num; 5152 5153 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 5154 5155 return num; 5156 } 5157 5158 static int 5159 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 5160 unsigned int n) 5161 { 5162 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5163 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5164 unsigned int i; 5165 unsigned int count; 5166 struct ice_hw_port_stats *hw_stats = &pf->stats; 5167 5168 count = ice_xstats_calc_num(); 5169 if (n < count) 5170 return count; 5171 5172 ice_read_stats_registers(pf, hw); 5173 5174 if (!xstats) 5175 return 0; 5176 5177 count = 0; 5178 5179 /* Get stats from ice_eth_stats struct */ 5180 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 5181 xstats[count].value = 5182 *(uint64_t *)((char *)&hw_stats->eth + 5183 ice_stats_strings[i].offset); 5184 xstats[count].id = count; 5185 count++; 5186 } 5187 5188 /* Get individiual stats from ice_hw_port struct */ 5189 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 5190 xstats[count].value = 5191 *(uint64_t *)((char *)hw_stats + 5192 ice_hw_port_strings[i].offset); 5193 xstats[count].id = count; 5194 count++; 5195 } 5196 5197 return count; 5198 } 5199 5200 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 5201 struct rte_eth_xstat_name *xstats_names, 5202 __rte_unused unsigned int limit) 5203 { 5204 unsigned int count = 0; 5205 unsigned int i; 5206 5207 if (!xstats_names) 5208 return ice_xstats_calc_num(); 5209 5210 /* Note: limit checked in rte_eth_xstats_names() */ 5211 5212 /* Get stats from ice_eth_stats struct */ 5213 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 5214 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 5215 sizeof(xstats_names[count].name)); 5216 count++; 5217 } 5218 5219 /* Get individiual stats from ice_hw_port struct */ 5220 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 5221 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 5222 sizeof(xstats_names[count].name)); 5223 count++; 5224 } 5225 5226 return count; 5227 } 5228 5229 static int 5230 ice_dev_filter_ctrl(struct rte_eth_dev *dev, 5231 enum rte_filter_type filter_type, 5232 enum rte_filter_op filter_op, 5233 void *arg) 5234 { 5235 int ret = 0; 5236 5237 if (!dev) 5238 return -EINVAL; 5239 5240 switch (filter_type) { 5241 case RTE_ETH_FILTER_GENERIC: 5242 if (filter_op != RTE_ETH_FILTER_GET) 5243 return -EINVAL; 5244 *(const void **)arg = &ice_flow_ops; 5245 break; 5246 default: 5247 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 5248 filter_type); 5249 ret = -EINVAL; 5250 break; 5251 } 5252 5253 return ret; 5254 } 5255 5256 /* Add UDP tunneling port */ 5257 static int 5258 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 5259 struct rte_eth_udp_tunnel *udp_tunnel) 5260 { 5261 int ret = 0; 5262 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5263 5264 if (udp_tunnel == NULL) 5265 return -EINVAL; 5266 5267 switch (udp_tunnel->prot_type) { 5268 case RTE_TUNNEL_TYPE_VXLAN: 5269 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); 5270 break; 5271 default: 5272 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5273 ret = -EINVAL; 5274 break; 5275 } 5276 5277 return ret; 5278 } 5279 5280 /* Delete UDP tunneling port */ 5281 static int 5282 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 5283 struct rte_eth_udp_tunnel *udp_tunnel) 5284 { 5285 int ret = 0; 5286 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5287 5288 if (udp_tunnel == NULL) 5289 return -EINVAL; 5290 5291 switch (udp_tunnel->prot_type) { 5292 case RTE_TUNNEL_TYPE_VXLAN: 5293 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); 5294 break; 5295 default: 5296 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5297 ret = -EINVAL; 5298 break; 5299 } 5300 5301 return ret; 5302 } 5303 5304 static int 5305 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5306 struct rte_pci_device *pci_dev) 5307 { 5308 return rte_eth_dev_pci_generic_probe(pci_dev, 5309 sizeof(struct ice_adapter), 5310 ice_dev_init); 5311 } 5312 5313 static int 5314 ice_pci_remove(struct rte_pci_device *pci_dev) 5315 { 5316 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 5317 } 5318 5319 static struct rte_pci_driver rte_ice_pmd = { 5320 .id_table = pci_id_ice_map, 5321 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 5322 .probe = ice_pci_probe, 5323 .remove = ice_pci_remove, 5324 }; 5325 5326 /** 5327 * Driver initialization routine. 5328 * Invoked once at EAL init time. 5329 * Register itself as the [Poll Mode] Driver of PCI devices. 5330 */ 5331 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 5332 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 5333 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 5334 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 5335 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>" 5336 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" 5337 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"); 5338 5339 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE); 5340 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE); 5341 #ifdef RTE_LIBRTE_ICE_DEBUG_RX 5342 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG); 5343 #endif 5344 #ifdef RTE_LIBRTE_ICE_DEBUG_TX 5345 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG); 5346 #endif 5347 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE 5348 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG); 5349 #endif 5350