1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <rte_ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include "base/ice_sched.h" 14 #include "base/ice_flow.h" 15 #include "base/ice_dcb.h" 16 #include "base/ice_common.h" 17 18 #include "rte_pmd_ice.h" 19 #include "ice_ethdev.h" 20 #include "ice_rxtx.h" 21 #include "ice_generic_flow.h" 22 23 /* devargs */ 24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" 25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" 26 #define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support" 27 #define ICE_PROTO_XTR_ARG "proto_xtr" 28 29 static const char * const ice_valid_args[] = { 30 ICE_SAFE_MODE_SUPPORT_ARG, 31 ICE_PIPELINE_MODE_SUPPORT_ARG, 32 ICE_FLOW_MARK_SUPPORT_ARG, 33 ICE_PROTO_XTR_ARG, 34 NULL 35 }; 36 37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = { 38 .name = "ice_dynfield_proto_xtr_metadata", 39 .size = sizeof(uint32_t), 40 .align = __alignof__(uint32_t), 41 .flags = 0, 42 }; 43 44 struct proto_xtr_ol_flag { 45 const struct rte_mbuf_dynflag param; 46 uint64_t *ol_flag; 47 bool required; 48 }; 49 50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = { 51 [PROTO_XTR_VLAN] = { 52 .param = { .name = "ice_dynflag_proto_xtr_vlan" }, 53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask }, 54 [PROTO_XTR_IPV4] = { 55 .param = { .name = "ice_dynflag_proto_xtr_ipv4" }, 56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask }, 57 [PROTO_XTR_IPV6] = { 58 .param = { .name = "ice_dynflag_proto_xtr_ipv6" }, 59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask }, 60 [PROTO_XTR_IPV6_FLOW] = { 61 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" }, 62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask }, 63 [PROTO_XTR_TCP] = { 64 .param = { .name = "ice_dynflag_proto_xtr_tcp" }, 65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask }, 66 }; 67 68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 69 70 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package" 71 #define ICE_COMMS_PKG_NAME "ICE COMMS Package" 72 #define ICE_MAX_RES_DESC_NUM 1024 73 74 static int ice_dev_configure(struct rte_eth_dev *dev); 75 static int ice_dev_start(struct rte_eth_dev *dev); 76 static void ice_dev_stop(struct rte_eth_dev *dev); 77 static void ice_dev_close(struct rte_eth_dev *dev); 78 static int ice_dev_reset(struct rte_eth_dev *dev); 79 static int ice_dev_info_get(struct rte_eth_dev *dev, 80 struct rte_eth_dev_info *dev_info); 81 static int ice_link_update(struct rte_eth_dev *dev, 82 int wait_to_complete); 83 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 84 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 85 86 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 87 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 88 static int ice_rss_reta_update(struct rte_eth_dev *dev, 89 struct rte_eth_rss_reta_entry64 *reta_conf, 90 uint16_t reta_size); 91 static int ice_rss_reta_query(struct rte_eth_dev *dev, 92 struct rte_eth_rss_reta_entry64 *reta_conf, 93 uint16_t reta_size); 94 static int ice_rss_hash_update(struct rte_eth_dev *dev, 95 struct rte_eth_rss_conf *rss_conf); 96 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 97 struct rte_eth_rss_conf *rss_conf); 98 static int ice_promisc_enable(struct rte_eth_dev *dev); 99 static int ice_promisc_disable(struct rte_eth_dev *dev); 100 static int ice_allmulti_enable(struct rte_eth_dev *dev); 101 static int ice_allmulti_disable(struct rte_eth_dev *dev); 102 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 103 uint16_t vlan_id, 104 int on); 105 static int ice_macaddr_set(struct rte_eth_dev *dev, 106 struct rte_ether_addr *mac_addr); 107 static int ice_macaddr_add(struct rte_eth_dev *dev, 108 struct rte_ether_addr *mac_addr, 109 __rte_unused uint32_t index, 110 uint32_t pool); 111 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 112 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 113 uint16_t queue_id); 114 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 115 uint16_t queue_id); 116 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 117 size_t fw_size); 118 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 119 uint16_t pvid, int on); 120 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 121 static int ice_get_eeprom(struct rte_eth_dev *dev, 122 struct rte_dev_eeprom_info *eeprom); 123 static int ice_stats_get(struct rte_eth_dev *dev, 124 struct rte_eth_stats *stats); 125 static int ice_stats_reset(struct rte_eth_dev *dev); 126 static int ice_xstats_get(struct rte_eth_dev *dev, 127 struct rte_eth_xstat *xstats, unsigned int n); 128 static int ice_xstats_get_names(struct rte_eth_dev *dev, 129 struct rte_eth_xstat_name *xstats_names, 130 unsigned int limit); 131 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, 132 enum rte_filter_type filter_type, 133 enum rte_filter_op filter_op, 134 void *arg); 135 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 136 struct rte_eth_udp_tunnel *udp_tunnel); 137 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 138 struct rte_eth_udp_tunnel *udp_tunnel); 139 140 static const struct rte_pci_id pci_id_ice_map[] = { 141 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 142 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 143 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) }, 145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) }, 146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) }, 147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) }, 148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) }, 149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) }, 150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) }, 151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) }, 152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) }, 153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) }, 154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) }, 155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) }, 156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) }, 157 { .vendor_id = 0, /* sentinel */ }, 158 }; 159 160 static const struct eth_dev_ops ice_eth_dev_ops = { 161 .dev_configure = ice_dev_configure, 162 .dev_start = ice_dev_start, 163 .dev_stop = ice_dev_stop, 164 .dev_close = ice_dev_close, 165 .dev_reset = ice_dev_reset, 166 .dev_set_link_up = ice_dev_set_link_up, 167 .dev_set_link_down = ice_dev_set_link_down, 168 .rx_queue_start = ice_rx_queue_start, 169 .rx_queue_stop = ice_rx_queue_stop, 170 .tx_queue_start = ice_tx_queue_start, 171 .tx_queue_stop = ice_tx_queue_stop, 172 .rx_queue_setup = ice_rx_queue_setup, 173 .rx_queue_release = ice_rx_queue_release, 174 .tx_queue_setup = ice_tx_queue_setup, 175 .tx_queue_release = ice_tx_queue_release, 176 .dev_infos_get = ice_dev_info_get, 177 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 178 .link_update = ice_link_update, 179 .mtu_set = ice_mtu_set, 180 .mac_addr_set = ice_macaddr_set, 181 .mac_addr_add = ice_macaddr_add, 182 .mac_addr_remove = ice_macaddr_remove, 183 .vlan_filter_set = ice_vlan_filter_set, 184 .vlan_offload_set = ice_vlan_offload_set, 185 .reta_update = ice_rss_reta_update, 186 .reta_query = ice_rss_reta_query, 187 .rss_hash_update = ice_rss_hash_update, 188 .rss_hash_conf_get = ice_rss_hash_conf_get, 189 .promiscuous_enable = ice_promisc_enable, 190 .promiscuous_disable = ice_promisc_disable, 191 .allmulticast_enable = ice_allmulti_enable, 192 .allmulticast_disable = ice_allmulti_disable, 193 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 194 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 195 .fw_version_get = ice_fw_version_get, 196 .vlan_pvid_set = ice_vlan_pvid_set, 197 .rxq_info_get = ice_rxq_info_get, 198 .txq_info_get = ice_txq_info_get, 199 .rx_burst_mode_get = ice_rx_burst_mode_get, 200 .tx_burst_mode_get = ice_tx_burst_mode_get, 201 .get_eeprom_length = ice_get_eeprom_length, 202 .get_eeprom = ice_get_eeprom, 203 .rx_queue_count = ice_rx_queue_count, 204 .rx_descriptor_status = ice_rx_descriptor_status, 205 .tx_descriptor_status = ice_tx_descriptor_status, 206 .stats_get = ice_stats_get, 207 .stats_reset = ice_stats_reset, 208 .xstats_get = ice_xstats_get, 209 .xstats_get_names = ice_xstats_get_names, 210 .xstats_reset = ice_stats_reset, 211 .filter_ctrl = ice_dev_filter_ctrl, 212 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, 213 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, 214 .tx_done_cleanup = ice_tx_done_cleanup, 215 }; 216 217 /* store statistics names and its offset in stats structure */ 218 struct ice_xstats_name_off { 219 char name[RTE_ETH_XSTATS_NAME_SIZE]; 220 unsigned int offset; 221 }; 222 223 static const struct ice_xstats_name_off ice_stats_strings[] = { 224 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 225 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 226 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 227 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 228 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 229 rx_unknown_protocol)}, 230 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 231 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 232 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 233 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 234 }; 235 236 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 237 sizeof(ice_stats_strings[0])) 238 239 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 240 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 241 tx_dropped_link_down)}, 242 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 243 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 244 illegal_bytes)}, 245 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 246 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 247 mac_local_faults)}, 248 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 249 mac_remote_faults)}, 250 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 251 rx_len_errors)}, 252 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 253 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 254 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 255 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 256 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 257 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 258 rx_size_127)}, 259 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 260 rx_size_255)}, 261 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 262 rx_size_511)}, 263 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 264 rx_size_1023)}, 265 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 266 rx_size_1522)}, 267 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 268 rx_size_big)}, 269 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 270 rx_undersize)}, 271 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 272 rx_oversize)}, 273 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 274 mac_short_pkt_dropped)}, 275 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 276 rx_fragments)}, 277 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 278 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 279 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 280 tx_size_127)}, 281 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 282 tx_size_255)}, 283 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 284 tx_size_511)}, 285 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 286 tx_size_1023)}, 287 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 288 tx_size_1522)}, 289 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 290 tx_size_big)}, 291 }; 292 293 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 294 sizeof(ice_hw_port_strings[0])) 295 296 static void 297 ice_init_controlq_parameter(struct ice_hw *hw) 298 { 299 /* fields for adminq */ 300 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 301 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 302 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 303 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 304 305 /* fields for mailboxq, DPDK used as PF host */ 306 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 307 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 308 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 309 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 310 } 311 312 static int 313 lookup_proto_xtr_type(const char *xtr_name) 314 { 315 static struct { 316 const char *name; 317 enum proto_xtr_type type; 318 } xtr_type_map[] = { 319 { "vlan", PROTO_XTR_VLAN }, 320 { "ipv4", PROTO_XTR_IPV4 }, 321 { "ipv6", PROTO_XTR_IPV6 }, 322 { "ipv6_flow", PROTO_XTR_IPV6_FLOW }, 323 { "tcp", PROTO_XTR_TCP }, 324 }; 325 uint32_t i; 326 327 for (i = 0; i < RTE_DIM(xtr_type_map); i++) { 328 if (strcmp(xtr_name, xtr_type_map[i].name) == 0) 329 return xtr_type_map[i].type; 330 } 331 332 return -1; 333 } 334 335 /* 336 * Parse elem, the elem could be single number/range or '(' ')' group 337 * 1) A single number elem, it's just a simple digit. e.g. 9 338 * 2) A single range elem, two digits with a '-' between. e.g. 2-6 339 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6) 340 * Within group elem, '-' used for a range separator; 341 * ',' used for a single number. 342 */ 343 static int 344 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs) 345 { 346 const char *str = input; 347 char *end = NULL; 348 uint32_t min, max; 349 uint32_t idx; 350 351 while (isblank(*str)) 352 str++; 353 354 if (!isdigit(*str) && *str != '(') 355 return -1; 356 357 /* process single number or single range of number */ 358 if (*str != '(') { 359 errno = 0; 360 idx = strtoul(str, &end, 10); 361 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 362 return -1; 363 364 while (isblank(*end)) 365 end++; 366 367 min = idx; 368 max = idx; 369 370 /* process single <number>-<number> */ 371 if (*end == '-') { 372 end++; 373 while (isblank(*end)) 374 end++; 375 if (!isdigit(*end)) 376 return -1; 377 378 errno = 0; 379 idx = strtoul(end, &end, 10); 380 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 381 return -1; 382 383 max = idx; 384 while (isblank(*end)) 385 end++; 386 } 387 388 if (*end != ':') 389 return -1; 390 391 for (idx = RTE_MIN(min, max); 392 idx <= RTE_MAX(min, max); idx++) 393 devargs->proto_xtr[idx] = xtr_type; 394 395 return 0; 396 } 397 398 /* process set within bracket */ 399 str++; 400 while (isblank(*str)) 401 str++; 402 if (*str == '\0') 403 return -1; 404 405 min = ICE_MAX_QUEUE_NUM; 406 do { 407 /* go ahead to the first digit */ 408 while (isblank(*str)) 409 str++; 410 if (!isdigit(*str)) 411 return -1; 412 413 /* get the digit value */ 414 errno = 0; 415 idx = strtoul(str, &end, 10); 416 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 417 return -1; 418 419 /* go ahead to separator '-',',' and ')' */ 420 while (isblank(*end)) 421 end++; 422 if (*end == '-') { 423 if (min == ICE_MAX_QUEUE_NUM) 424 min = idx; 425 else /* avoid continuous '-' */ 426 return -1; 427 } else if (*end == ',' || *end == ')') { 428 max = idx; 429 if (min == ICE_MAX_QUEUE_NUM) 430 min = idx; 431 432 for (idx = RTE_MIN(min, max); 433 idx <= RTE_MAX(min, max); idx++) 434 devargs->proto_xtr[idx] = xtr_type; 435 436 min = ICE_MAX_QUEUE_NUM; 437 } else { 438 return -1; 439 } 440 441 str = end + 1; 442 } while (*end != ')' && *end != '\0'); 443 444 return 0; 445 } 446 447 static int 448 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs) 449 { 450 const char *queue_start; 451 uint32_t idx; 452 int xtr_type; 453 char xtr_name[32]; 454 455 while (isblank(*queues)) 456 queues++; 457 458 if (*queues != '[') { 459 xtr_type = lookup_proto_xtr_type(queues); 460 if (xtr_type < 0) 461 return -1; 462 463 devargs->proto_xtr_dflt = xtr_type; 464 465 return 0; 466 } 467 468 queues++; 469 do { 470 while (isblank(*queues)) 471 queues++; 472 if (*queues == '\0') 473 return -1; 474 475 queue_start = queues; 476 477 /* go across a complete bracket */ 478 if (*queue_start == '(') { 479 queues += strcspn(queues, ")"); 480 if (*queues != ')') 481 return -1; 482 } 483 484 /* scan the separator ':' */ 485 queues += strcspn(queues, ":"); 486 if (*queues++ != ':') 487 return -1; 488 while (isblank(*queues)) 489 queues++; 490 491 for (idx = 0; ; idx++) { 492 if (isblank(queues[idx]) || 493 queues[idx] == ',' || 494 queues[idx] == ']' || 495 queues[idx] == '\0') 496 break; 497 498 if (idx > sizeof(xtr_name) - 2) 499 return -1; 500 501 xtr_name[idx] = queues[idx]; 502 } 503 xtr_name[idx] = '\0'; 504 xtr_type = lookup_proto_xtr_type(xtr_name); 505 if (xtr_type < 0) 506 return -1; 507 508 queues += idx; 509 510 while (isblank(*queues) || *queues == ',' || *queues == ']') 511 queues++; 512 513 if (parse_queue_set(queue_start, xtr_type, devargs) < 0) 514 return -1; 515 } while (*queues != '\0'); 516 517 return 0; 518 } 519 520 static int 521 handle_proto_xtr_arg(__rte_unused const char *key, const char *value, 522 void *extra_args) 523 { 524 struct ice_devargs *devargs = extra_args; 525 526 if (value == NULL || extra_args == NULL) 527 return -EINVAL; 528 529 if (parse_queue_proto_xtr(value, devargs) < 0) { 530 PMD_DRV_LOG(ERR, 531 "The protocol extraction parameter is wrong : '%s'", 532 value); 533 return -1; 534 } 535 536 return 0; 537 } 538 539 static bool 540 ice_proto_xtr_support(struct ice_hw *hw) 541 { 542 #define FLX_REG(val, fld, idx) \ 543 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ 544 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) 545 static struct { 546 uint32_t rxdid; 547 uint16_t protid_0; 548 uint16_t protid_1; 549 } xtr_sets[] = { 550 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O }, 551 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S, 552 ICE_PROT_IPV4_OF_OR_S }, 553 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S, 554 ICE_PROT_IPV6_OF_OR_S }, 555 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S, 556 ICE_PROT_IPV6_OF_OR_S }, 557 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, 558 }; 559 uint32_t i; 560 561 for (i = 0; i < RTE_DIM(xtr_sets); i++) { 562 uint32_t rxdid = xtr_sets[i].rxdid; 563 uint32_t v; 564 565 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) { 566 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid)); 567 568 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 || 569 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT) 570 return false; 571 } 572 573 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) { 574 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid)); 575 576 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 || 577 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT) 578 return false; 579 } 580 } 581 582 return true; 583 } 584 585 static int 586 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 587 uint32_t num) 588 { 589 struct pool_entry *entry; 590 591 if (!pool || !num) 592 return -EINVAL; 593 594 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 595 if (!entry) { 596 PMD_INIT_LOG(ERR, 597 "Failed to allocate memory for resource pool"); 598 return -ENOMEM; 599 } 600 601 /* queue heap initialize */ 602 pool->num_free = num; 603 pool->num_alloc = 0; 604 pool->base = base; 605 LIST_INIT(&pool->alloc_list); 606 LIST_INIT(&pool->free_list); 607 608 /* Initialize element */ 609 entry->base = 0; 610 entry->len = num; 611 612 LIST_INSERT_HEAD(&pool->free_list, entry, next); 613 return 0; 614 } 615 616 static int 617 ice_res_pool_alloc(struct ice_res_pool_info *pool, 618 uint16_t num) 619 { 620 struct pool_entry *entry, *valid_entry; 621 622 if (!pool || !num) { 623 PMD_INIT_LOG(ERR, "Invalid parameter"); 624 return -EINVAL; 625 } 626 627 if (pool->num_free < num) { 628 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 629 num, pool->num_free); 630 return -ENOMEM; 631 } 632 633 valid_entry = NULL; 634 /* Lookup in free list and find most fit one */ 635 LIST_FOREACH(entry, &pool->free_list, next) { 636 if (entry->len >= num) { 637 /* Find best one */ 638 if (entry->len == num) { 639 valid_entry = entry; 640 break; 641 } 642 if (!valid_entry || 643 valid_entry->len > entry->len) 644 valid_entry = entry; 645 } 646 } 647 648 /* Not find one to satisfy the request, return */ 649 if (!valid_entry) { 650 PMD_INIT_LOG(ERR, "No valid entry found"); 651 return -ENOMEM; 652 } 653 /** 654 * The entry have equal queue number as requested, 655 * remove it from alloc_list. 656 */ 657 if (valid_entry->len == num) { 658 LIST_REMOVE(valid_entry, next); 659 } else { 660 /** 661 * The entry have more numbers than requested, 662 * create a new entry for alloc_list and minus its 663 * queue base and number in free_list. 664 */ 665 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 666 if (!entry) { 667 PMD_INIT_LOG(ERR, 668 "Failed to allocate memory for " 669 "resource pool"); 670 return -ENOMEM; 671 } 672 entry->base = valid_entry->base; 673 entry->len = num; 674 valid_entry->base += num; 675 valid_entry->len -= num; 676 valid_entry = entry; 677 } 678 679 /* Insert it into alloc list, not sorted */ 680 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 681 682 pool->num_free -= valid_entry->len; 683 pool->num_alloc += valid_entry->len; 684 685 return valid_entry->base + pool->base; 686 } 687 688 static void 689 ice_res_pool_destroy(struct ice_res_pool_info *pool) 690 { 691 struct pool_entry *entry, *next_entry; 692 693 if (!pool) 694 return; 695 696 for (entry = LIST_FIRST(&pool->alloc_list); 697 entry && (next_entry = LIST_NEXT(entry, next), 1); 698 entry = next_entry) { 699 LIST_REMOVE(entry, next); 700 rte_free(entry); 701 } 702 703 for (entry = LIST_FIRST(&pool->free_list); 704 entry && (next_entry = LIST_NEXT(entry, next), 1); 705 entry = next_entry) { 706 LIST_REMOVE(entry, next); 707 rte_free(entry); 708 } 709 710 pool->num_free = 0; 711 pool->num_alloc = 0; 712 pool->base = 0; 713 LIST_INIT(&pool->alloc_list); 714 LIST_INIT(&pool->free_list); 715 } 716 717 static void 718 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 719 { 720 /* Set VSI LUT selection */ 721 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 722 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 723 /* Set Hash scheme */ 724 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 725 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 726 /* enable TC */ 727 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 728 } 729 730 static enum ice_status 731 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 732 struct ice_aqc_vsi_props *info, 733 uint8_t enabled_tcmap) 734 { 735 uint16_t bsf, qp_idx; 736 737 /* default tc 0 now. Multi-TC supporting need to be done later. 738 * Configure TC and queue mapping parameters, for enabled TC, 739 * allocate qpnum_per_tc queues to this traffic. 740 */ 741 if (enabled_tcmap != 0x01) { 742 PMD_INIT_LOG(ERR, "only TC0 is supported"); 743 return -ENOTSUP; 744 } 745 746 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 747 bsf = rte_bsf32(vsi->nb_qps); 748 /* Adjust the queue number to actual queues that can be applied */ 749 vsi->nb_qps = 0x1 << bsf; 750 751 qp_idx = 0; 752 /* Set tc and queue mapping with VSI */ 753 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 754 ICE_AQ_VSI_TC_Q_OFFSET_S) | 755 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 756 757 /* Associate queue number with VSI */ 758 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 759 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 760 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 761 info->valid_sections |= 762 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 763 /* Set the info.ingress_table and info.egress_table 764 * for UP translate table. Now just set it to 1:1 map by default 765 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 766 */ 767 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 768 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 769 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 770 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 771 return 0; 772 } 773 774 static int 775 ice_init_mac_address(struct rte_eth_dev *dev) 776 { 777 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 778 779 if (!rte_is_unicast_ether_addr 780 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 781 PMD_INIT_LOG(ERR, "Invalid MAC address"); 782 return -EINVAL; 783 } 784 785 rte_ether_addr_copy( 786 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 787 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 788 789 dev->data->mac_addrs = 790 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0); 791 if (!dev->data->mac_addrs) { 792 PMD_INIT_LOG(ERR, 793 "Failed to allocate memory to store mac address"); 794 return -ENOMEM; 795 } 796 /* store it to dev data */ 797 rte_ether_addr_copy( 798 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 799 &dev->data->mac_addrs[0]); 800 return 0; 801 } 802 803 /* Find out specific MAC filter */ 804 static struct ice_mac_filter * 805 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 806 { 807 struct ice_mac_filter *f; 808 809 TAILQ_FOREACH(f, &vsi->mac_list, next) { 810 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 811 return f; 812 } 813 814 return NULL; 815 } 816 817 static int 818 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 819 { 820 struct ice_fltr_list_entry *m_list_itr = NULL; 821 struct ice_mac_filter *f; 822 struct LIST_HEAD_TYPE list_head; 823 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 824 int ret = 0; 825 826 /* If it's added and configured, return */ 827 f = ice_find_mac_filter(vsi, mac_addr); 828 if (f) { 829 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 830 return 0; 831 } 832 833 INIT_LIST_HEAD(&list_head); 834 835 m_list_itr = (struct ice_fltr_list_entry *) 836 ice_malloc(hw, sizeof(*m_list_itr)); 837 if (!m_list_itr) { 838 ret = -ENOMEM; 839 goto DONE; 840 } 841 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 842 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 843 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 844 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 845 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 846 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 847 m_list_itr->fltr_info.vsi_handle = vsi->idx; 848 849 LIST_ADD(&m_list_itr->list_entry, &list_head); 850 851 /* Add the mac */ 852 ret = ice_add_mac(hw, &list_head); 853 if (ret != ICE_SUCCESS) { 854 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 855 ret = -EINVAL; 856 goto DONE; 857 } 858 /* Add the mac addr into mac list */ 859 f = rte_zmalloc(NULL, sizeof(*f), 0); 860 if (!f) { 861 PMD_DRV_LOG(ERR, "failed to allocate memory"); 862 ret = -ENOMEM; 863 goto DONE; 864 } 865 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr); 866 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 867 vsi->mac_num++; 868 869 ret = 0; 870 871 DONE: 872 rte_free(m_list_itr); 873 return ret; 874 } 875 876 static int 877 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 878 { 879 struct ice_fltr_list_entry *m_list_itr = NULL; 880 struct ice_mac_filter *f; 881 struct LIST_HEAD_TYPE list_head; 882 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 883 int ret = 0; 884 885 /* Can't find it, return an error */ 886 f = ice_find_mac_filter(vsi, mac_addr); 887 if (!f) 888 return -EINVAL; 889 890 INIT_LIST_HEAD(&list_head); 891 892 m_list_itr = (struct ice_fltr_list_entry *) 893 ice_malloc(hw, sizeof(*m_list_itr)); 894 if (!m_list_itr) { 895 ret = -ENOMEM; 896 goto DONE; 897 } 898 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 899 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 900 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 901 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 902 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 903 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 904 m_list_itr->fltr_info.vsi_handle = vsi->idx; 905 906 LIST_ADD(&m_list_itr->list_entry, &list_head); 907 908 /* remove the mac filter */ 909 ret = ice_remove_mac(hw, &list_head); 910 if (ret != ICE_SUCCESS) { 911 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 912 ret = -EINVAL; 913 goto DONE; 914 } 915 916 /* Remove the mac addr from mac list */ 917 TAILQ_REMOVE(&vsi->mac_list, f, next); 918 rte_free(f); 919 vsi->mac_num--; 920 921 ret = 0; 922 DONE: 923 rte_free(m_list_itr); 924 return ret; 925 } 926 927 /* Find out specific VLAN filter */ 928 static struct ice_vlan_filter * 929 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 930 { 931 struct ice_vlan_filter *f; 932 933 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 934 if (vlan_id == f->vlan_info.vlan_id) 935 return f; 936 } 937 938 return NULL; 939 } 940 941 static int 942 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 943 { 944 struct ice_fltr_list_entry *v_list_itr = NULL; 945 struct ice_vlan_filter *f; 946 struct LIST_HEAD_TYPE list_head; 947 struct ice_hw *hw; 948 int ret = 0; 949 950 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID) 951 return -EINVAL; 952 953 hw = ICE_VSI_TO_HW(vsi); 954 955 /* If it's added and configured, return. */ 956 f = ice_find_vlan_filter(vsi, vlan_id); 957 if (f) { 958 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 959 return 0; 960 } 961 962 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 963 return 0; 964 965 INIT_LIST_HEAD(&list_head); 966 967 v_list_itr = (struct ice_fltr_list_entry *) 968 ice_malloc(hw, sizeof(*v_list_itr)); 969 if (!v_list_itr) { 970 ret = -ENOMEM; 971 goto DONE; 972 } 973 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 974 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 975 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 976 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 977 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 978 v_list_itr->fltr_info.vsi_handle = vsi->idx; 979 980 LIST_ADD(&v_list_itr->list_entry, &list_head); 981 982 /* Add the vlan */ 983 ret = ice_add_vlan(hw, &list_head); 984 if (ret != ICE_SUCCESS) { 985 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 986 ret = -EINVAL; 987 goto DONE; 988 } 989 990 /* Add vlan into vlan list */ 991 f = rte_zmalloc(NULL, sizeof(*f), 0); 992 if (!f) { 993 PMD_DRV_LOG(ERR, "failed to allocate memory"); 994 ret = -ENOMEM; 995 goto DONE; 996 } 997 f->vlan_info.vlan_id = vlan_id; 998 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 999 vsi->vlan_num++; 1000 1001 ret = 0; 1002 1003 DONE: 1004 rte_free(v_list_itr); 1005 return ret; 1006 } 1007 1008 static int 1009 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 1010 { 1011 struct ice_fltr_list_entry *v_list_itr = NULL; 1012 struct ice_vlan_filter *f; 1013 struct LIST_HEAD_TYPE list_head; 1014 struct ice_hw *hw; 1015 int ret = 0; 1016 1017 /** 1018 * Vlan 0 is the generic filter for untagged packets 1019 * and can't be removed. 1020 */ 1021 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID) 1022 return -EINVAL; 1023 1024 hw = ICE_VSI_TO_HW(vsi); 1025 1026 /* Can't find it, return an error */ 1027 f = ice_find_vlan_filter(vsi, vlan_id); 1028 if (!f) 1029 return -EINVAL; 1030 1031 INIT_LIST_HEAD(&list_head); 1032 1033 v_list_itr = (struct ice_fltr_list_entry *) 1034 ice_malloc(hw, sizeof(*v_list_itr)); 1035 if (!v_list_itr) { 1036 ret = -ENOMEM; 1037 goto DONE; 1038 } 1039 1040 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 1041 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1042 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1043 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1044 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1045 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1046 1047 LIST_ADD(&v_list_itr->list_entry, &list_head); 1048 1049 /* remove the vlan filter */ 1050 ret = ice_remove_vlan(hw, &list_head); 1051 if (ret != ICE_SUCCESS) { 1052 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 1053 ret = -EINVAL; 1054 goto DONE; 1055 } 1056 1057 /* Remove the vlan id from vlan list */ 1058 TAILQ_REMOVE(&vsi->vlan_list, f, next); 1059 rte_free(f); 1060 vsi->vlan_num--; 1061 1062 ret = 0; 1063 DONE: 1064 rte_free(v_list_itr); 1065 return ret; 1066 } 1067 1068 static int 1069 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 1070 { 1071 struct ice_mac_filter *m_f; 1072 struct ice_vlan_filter *v_f; 1073 int ret = 0; 1074 1075 if (!vsi || !vsi->mac_num) 1076 return -EINVAL; 1077 1078 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 1079 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 1080 if (ret != ICE_SUCCESS) { 1081 ret = -EINVAL; 1082 goto DONE; 1083 } 1084 } 1085 1086 if (vsi->vlan_num == 0) 1087 return 0; 1088 1089 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 1090 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 1091 if (ret != ICE_SUCCESS) { 1092 ret = -EINVAL; 1093 goto DONE; 1094 } 1095 } 1096 1097 DONE: 1098 return ret; 1099 } 1100 1101 static int 1102 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 1103 { 1104 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1105 struct ice_vsi_ctx ctxt; 1106 uint8_t qinq_flags; 1107 int ret = 0; 1108 1109 /* Check if it has been already on or off */ 1110 if (vsi->info.valid_sections & 1111 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1112 if (on) { 1113 if ((vsi->info.outer_tag_flags & 1114 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == 1115 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) 1116 return 0; /* already on */ 1117 } else { 1118 if (!(vsi->info.outer_tag_flags & 1119 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) 1120 return 0; /* already off */ 1121 } 1122 } 1123 1124 if (on) 1125 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; 1126 else 1127 qinq_flags = 0; 1128 /* clear global insertion and use per packet insertion */ 1129 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); 1130 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); 1131 vsi->info.outer_tag_flags |= qinq_flags; 1132 /* use default vlan type 0x8100 */ 1133 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1134 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1135 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1136 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1137 ctxt.info.valid_sections = 1138 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1139 ctxt.vsi_num = vsi->vsi_id; 1140 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1141 if (ret) { 1142 PMD_DRV_LOG(INFO, 1143 "Update VSI failed to %s qinq stripping", 1144 on ? "enable" : "disable"); 1145 return -EINVAL; 1146 } 1147 1148 vsi->info.valid_sections |= 1149 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1150 1151 return ret; 1152 } 1153 1154 static int 1155 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 1156 { 1157 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1158 struct ice_vsi_ctx ctxt; 1159 uint8_t qinq_flags; 1160 int ret = 0; 1161 1162 /* Check if it has been already on or off */ 1163 if (vsi->info.valid_sections & 1164 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1165 if (on) { 1166 if ((vsi->info.outer_tag_flags & 1167 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 1168 ICE_AQ_VSI_OUTER_TAG_COPY) 1169 return 0; /* already on */ 1170 } else { 1171 if ((vsi->info.outer_tag_flags & 1172 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 1173 ICE_AQ_VSI_OUTER_TAG_NOTHING) 1174 return 0; /* already off */ 1175 } 1176 } 1177 1178 if (on) 1179 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; 1180 else 1181 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; 1182 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); 1183 vsi->info.outer_tag_flags |= qinq_flags; 1184 /* use default vlan type 0x8100 */ 1185 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1186 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1187 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1188 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1189 ctxt.info.valid_sections = 1190 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1191 ctxt.vsi_num = vsi->vsi_id; 1192 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1193 if (ret) { 1194 PMD_DRV_LOG(INFO, 1195 "Update VSI failed to %s qinq stripping", 1196 on ? "enable" : "disable"); 1197 return -EINVAL; 1198 } 1199 1200 vsi->info.valid_sections |= 1201 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1202 1203 return ret; 1204 } 1205 1206 static int 1207 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 1208 { 1209 int ret; 1210 1211 ret = ice_vsi_config_qinq_stripping(vsi, on); 1212 if (ret) 1213 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 1214 1215 ret = ice_vsi_config_qinq_insertion(vsi, on); 1216 if (ret) 1217 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 1218 1219 return ret; 1220 } 1221 1222 /* Enable IRQ0 */ 1223 static void 1224 ice_pf_enable_irq0(struct ice_hw *hw) 1225 { 1226 /* reset the registers */ 1227 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 1228 ICE_READ_REG(hw, PFINT_OICR); 1229 1230 #ifdef ICE_LSE_SPT 1231 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 1232 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 1233 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 1234 1235 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 1236 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 1237 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 1238 PFINT_OICR_CTL_ITR_INDX_M) | 1239 PFINT_OICR_CTL_CAUSE_ENA_M); 1240 1241 ICE_WRITE_REG(hw, PFINT_FW_CTL, 1242 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 1243 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 1244 PFINT_FW_CTL_ITR_INDX_M) | 1245 PFINT_FW_CTL_CAUSE_ENA_M); 1246 #else 1247 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 1248 #endif 1249 1250 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1251 GLINT_DYN_CTL_INTENA_M | 1252 GLINT_DYN_CTL_CLEARPBA_M | 1253 GLINT_DYN_CTL_ITR_INDX_M); 1254 1255 ice_flush(hw); 1256 } 1257 1258 /* Disable IRQ0 */ 1259 static void 1260 ice_pf_disable_irq0(struct ice_hw *hw) 1261 { 1262 /* Disable all interrupt types */ 1263 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1264 ice_flush(hw); 1265 } 1266 1267 #ifdef ICE_LSE_SPT 1268 static void 1269 ice_handle_aq_msg(struct rte_eth_dev *dev) 1270 { 1271 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1272 struct ice_ctl_q_info *cq = &hw->adminq; 1273 struct ice_rq_event_info event; 1274 uint16_t pending, opcode; 1275 int ret; 1276 1277 event.buf_len = ICE_AQ_MAX_BUF_LEN; 1278 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 1279 if (!event.msg_buf) { 1280 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 1281 return; 1282 } 1283 1284 pending = 1; 1285 while (pending) { 1286 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 1287 1288 if (ret != ICE_SUCCESS) { 1289 PMD_DRV_LOG(INFO, 1290 "Failed to read msg from AdminQ, " 1291 "adminq_err: %u", 1292 hw->adminq.sq_last_status); 1293 break; 1294 } 1295 opcode = rte_le_to_cpu_16(event.desc.opcode); 1296 1297 switch (opcode) { 1298 case ice_aqc_opc_get_link_status: 1299 ret = ice_link_update(dev, 0); 1300 if (!ret) 1301 _rte_eth_dev_callback_process 1302 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1303 break; 1304 default: 1305 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1306 opcode); 1307 break; 1308 } 1309 } 1310 rte_free(event.msg_buf); 1311 } 1312 #endif 1313 1314 /** 1315 * Interrupt handler triggered by NIC for handling 1316 * specific interrupt. 1317 * 1318 * @param handle 1319 * Pointer to interrupt handle. 1320 * @param param 1321 * The address of parameter (struct rte_eth_dev *) regsitered before. 1322 * 1323 * @return 1324 * void 1325 */ 1326 static void 1327 ice_interrupt_handler(void *param) 1328 { 1329 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1330 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1331 uint32_t oicr; 1332 uint32_t reg; 1333 uint8_t pf_num; 1334 uint8_t event; 1335 uint16_t queue; 1336 int ret; 1337 #ifdef ICE_LSE_SPT 1338 uint32_t int_fw_ctl; 1339 #endif 1340 1341 /* Disable interrupt */ 1342 ice_pf_disable_irq0(hw); 1343 1344 /* read out interrupt causes */ 1345 oicr = ICE_READ_REG(hw, PFINT_OICR); 1346 #ifdef ICE_LSE_SPT 1347 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1348 #endif 1349 1350 /* No interrupt event indicated */ 1351 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1352 PMD_DRV_LOG(INFO, "No interrupt event"); 1353 goto done; 1354 } 1355 1356 #ifdef ICE_LSE_SPT 1357 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1358 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1359 ice_handle_aq_msg(dev); 1360 } 1361 #else 1362 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1363 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1364 ret = ice_link_update(dev, 0); 1365 if (!ret) 1366 _rte_eth_dev_callback_process 1367 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1368 } 1369 #endif 1370 1371 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1372 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1373 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1374 if (reg & GL_MDET_TX_PQM_VALID_M) { 1375 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1376 GL_MDET_TX_PQM_PF_NUM_S; 1377 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1378 GL_MDET_TX_PQM_MAL_TYPE_S; 1379 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1380 GL_MDET_TX_PQM_QNUM_S; 1381 1382 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1383 "%d by PQM on TX queue %d PF# %d", 1384 event, queue, pf_num); 1385 } 1386 1387 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1388 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1389 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1390 GL_MDET_TX_TCLAN_PF_NUM_S; 1391 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1392 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1393 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1394 GL_MDET_TX_TCLAN_QNUM_S; 1395 1396 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1397 "%d by TCLAN on TX queue %d PF# %d", 1398 event, queue, pf_num); 1399 } 1400 } 1401 done: 1402 /* Enable interrupt */ 1403 ice_pf_enable_irq0(hw); 1404 rte_intr_ack(dev->intr_handle); 1405 } 1406 1407 static void 1408 ice_init_proto_xtr(struct rte_eth_dev *dev) 1409 { 1410 struct ice_adapter *ad = 1411 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1412 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1413 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1414 const struct proto_xtr_ol_flag *ol_flag; 1415 bool proto_xtr_enable = false; 1416 int offset; 1417 uint16_t i; 1418 1419 if (!ice_proto_xtr_support(hw)) { 1420 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported"); 1421 return; 1422 } 1423 1424 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0); 1425 if (unlikely(pf->proto_xtr == NULL)) { 1426 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table"); 1427 return; 1428 } 1429 1430 for (i = 0; i < pf->lan_nb_qps; i++) { 1431 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ? 1432 ad->devargs.proto_xtr[i] : 1433 ad->devargs.proto_xtr_dflt; 1434 1435 if (pf->proto_xtr[i] != PROTO_XTR_NONE) { 1436 uint8_t type = pf->proto_xtr[i]; 1437 1438 ice_proto_xtr_ol_flag_params[type].required = true; 1439 proto_xtr_enable = true; 1440 } 1441 } 1442 1443 if (likely(!proto_xtr_enable)) 1444 return; 1445 1446 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param); 1447 if (unlikely(offset == -1)) { 1448 PMD_DRV_LOG(ERR, 1449 "Protocol extraction metadata is disabled in mbuf with error %d", 1450 -rte_errno); 1451 return; 1452 } 1453 1454 PMD_DRV_LOG(DEBUG, 1455 "Protocol extraction metadata offset in mbuf is : %d", 1456 offset); 1457 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset; 1458 1459 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) { 1460 ol_flag = &ice_proto_xtr_ol_flag_params[i]; 1461 1462 if (!ol_flag->required) 1463 continue; 1464 1465 offset = rte_mbuf_dynflag_register(&ol_flag->param); 1466 if (unlikely(offset == -1)) { 1467 PMD_DRV_LOG(ERR, 1468 "Protocol extraction offload '%s' failed to register with error %d", 1469 ol_flag->param.name, -rte_errno); 1470 1471 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1472 break; 1473 } 1474 1475 PMD_DRV_LOG(DEBUG, 1476 "Protocol extraction offload '%s' offset in mbuf is : %d", 1477 ol_flag->param.name, offset); 1478 *ol_flag->ol_flag = 1ULL << offset; 1479 } 1480 } 1481 1482 /* Initialize SW parameters of PF */ 1483 static int 1484 ice_pf_sw_init(struct rte_eth_dev *dev) 1485 { 1486 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1487 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1488 1489 pf->lan_nb_qp_max = 1490 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1491 hw->func_caps.common_cap.num_rxq); 1492 1493 pf->lan_nb_qps = pf->lan_nb_qp_max; 1494 1495 ice_init_proto_xtr(dev); 1496 1497 if (hw->func_caps.fd_fltr_guar > 0 || 1498 hw->func_caps.fd_fltr_best_effort > 0) { 1499 pf->flags |= ICE_FLAG_FDIR; 1500 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR; 1501 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps; 1502 } else { 1503 pf->fdir_nb_qps = 0; 1504 } 1505 pf->fdir_qp_offset = 0; 1506 1507 return 0; 1508 } 1509 1510 struct ice_vsi * 1511 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1512 { 1513 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1514 struct ice_vsi *vsi = NULL; 1515 struct ice_vsi_ctx vsi_ctx; 1516 int ret; 1517 struct rte_ether_addr broadcast = { 1518 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1519 struct rte_ether_addr mac_addr; 1520 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1521 uint8_t tc_bitmap = 0x1; 1522 uint16_t cfg; 1523 1524 /* hw->num_lports = 1 in NIC mode */ 1525 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1526 if (!vsi) 1527 return NULL; 1528 1529 vsi->idx = pf->next_vsi_idx; 1530 pf->next_vsi_idx++; 1531 vsi->type = type; 1532 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1533 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1534 vsi->vlan_anti_spoof_on = 0; 1535 vsi->vlan_filter_on = 1; 1536 TAILQ_INIT(&vsi->mac_list); 1537 TAILQ_INIT(&vsi->vlan_list); 1538 1539 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ 1540 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1541 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : 1542 hw->func_caps.common_cap.rss_table_size; 1543 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1544 1545 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1546 switch (type) { 1547 case ICE_VSI_PF: 1548 vsi->nb_qps = pf->lan_nb_qps; 1549 vsi->base_queue = 1; 1550 ice_vsi_config_default_rss(&vsi_ctx.info); 1551 vsi_ctx.alloc_from_pool = true; 1552 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1553 /* switch_id is queried by get_switch_config aq, which is done 1554 * by ice_init_hw 1555 */ 1556 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1557 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1558 /* Allow all untagged or tagged packets */ 1559 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; 1560 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; 1561 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1562 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1563 1564 /* FDIR */ 1565 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID | 1566 ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1567 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1568 cfg = ICE_AQ_VSI_FD_ENABLE; 1569 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1570 vsi_ctx.info.max_fd_fltr_dedicated = 1571 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar); 1572 vsi_ctx.info.max_fd_fltr_shared = 1573 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); 1574 1575 /* Enable VLAN/UP trip */ 1576 ret = ice_vsi_config_tc_queue_mapping(vsi, 1577 &vsi_ctx.info, 1578 ICE_DEFAULT_TCMAP); 1579 if (ret) { 1580 PMD_INIT_LOG(ERR, 1581 "tc queue mapping with vsi failed, " 1582 "err = %d", 1583 ret); 1584 goto fail_mem; 1585 } 1586 1587 break; 1588 case ICE_VSI_CTRL: 1589 vsi->nb_qps = pf->fdir_nb_qps; 1590 vsi->base_queue = ICE_FDIR_QUEUE_ID; 1591 vsi_ctx.alloc_from_pool = true; 1592 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1593 1594 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1595 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1596 cfg = ICE_AQ_VSI_FD_PROG_ENABLE; 1597 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1598 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1599 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1600 ret = ice_vsi_config_tc_queue_mapping(vsi, 1601 &vsi_ctx.info, 1602 ICE_DEFAULT_TCMAP); 1603 if (ret) { 1604 PMD_INIT_LOG(ERR, 1605 "tc queue mapping with vsi failed, " 1606 "err = %d", 1607 ret); 1608 goto fail_mem; 1609 } 1610 break; 1611 default: 1612 /* for other types of VSI */ 1613 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1614 goto fail_mem; 1615 } 1616 1617 /* VF has MSIX interrupt in VF range, don't allocate here */ 1618 if (type == ICE_VSI_PF) { 1619 ret = ice_res_pool_alloc(&pf->msix_pool, 1620 RTE_MIN(vsi->nb_qps, 1621 RTE_MAX_RXTX_INTR_VEC_ID)); 1622 if (ret < 0) { 1623 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1624 vsi->vsi_id, ret); 1625 } 1626 vsi->msix_intr = ret; 1627 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1628 } else if (type == ICE_VSI_CTRL) { 1629 ret = ice_res_pool_alloc(&pf->msix_pool, 1); 1630 if (ret < 0) { 1631 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", 1632 vsi->vsi_id, ret); 1633 } 1634 vsi->msix_intr = ret; 1635 vsi->nb_msix = 1; 1636 } else { 1637 vsi->msix_intr = 0; 1638 vsi->nb_msix = 0; 1639 } 1640 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1641 if (ret != ICE_SUCCESS) { 1642 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1643 goto fail_mem; 1644 } 1645 /* store vsi information is SW structure */ 1646 vsi->vsi_id = vsi_ctx.vsi_num; 1647 vsi->info = vsi_ctx.info; 1648 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1649 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1650 1651 if (type == ICE_VSI_PF) { 1652 /* MAC configuration */ 1653 rte_ether_addr_copy((struct rte_ether_addr *) 1654 hw->port_info->mac.perm_addr, 1655 &pf->dev_addr); 1656 1657 rte_ether_addr_copy(&pf->dev_addr, &mac_addr); 1658 ret = ice_add_mac_filter(vsi, &mac_addr); 1659 if (ret != ICE_SUCCESS) 1660 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1661 1662 rte_ether_addr_copy(&broadcast, &mac_addr); 1663 ret = ice_add_mac_filter(vsi, &mac_addr); 1664 if (ret != ICE_SUCCESS) 1665 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1666 } 1667 1668 /* At the beginning, only TC0. */ 1669 /* What we need here is the maximam number of the TX queues. 1670 * Currently vsi->nb_qps means it. 1671 * Correct it if any change. 1672 */ 1673 max_txqs[0] = vsi->nb_qps; 1674 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1675 tc_bitmap, max_txqs); 1676 if (ret != ICE_SUCCESS) 1677 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1678 1679 return vsi; 1680 fail_mem: 1681 rte_free(vsi); 1682 pf->next_vsi_idx--; 1683 return NULL; 1684 } 1685 1686 static int 1687 ice_send_driver_ver(struct ice_hw *hw) 1688 { 1689 struct ice_driver_ver dv; 1690 1691 /* we don't have driver version use 0 for dummy */ 1692 dv.major_ver = 0; 1693 dv.minor_ver = 0; 1694 dv.build_ver = 0; 1695 dv.subbuild_ver = 0; 1696 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1697 1698 return ice_aq_send_driver_ver(hw, &dv, NULL); 1699 } 1700 1701 static int 1702 ice_pf_setup(struct ice_pf *pf) 1703 { 1704 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1705 struct ice_vsi *vsi; 1706 uint16_t unused; 1707 1708 /* Clear all stats counters */ 1709 pf->offset_loaded = false; 1710 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1711 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1712 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1713 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1714 1715 /* force guaranteed filter pool for PF */ 1716 ice_alloc_fd_guar_item(hw, &unused, 1717 hw->func_caps.fd_fltr_guar); 1718 /* force shared filter pool for PF */ 1719 ice_alloc_fd_shrd_item(hw, &unused, 1720 hw->func_caps.fd_fltr_best_effort); 1721 1722 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1723 if (!vsi) { 1724 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1725 return -EINVAL; 1726 } 1727 1728 pf->main_vsi = vsi; 1729 1730 return 0; 1731 } 1732 1733 /* PCIe configuration space setting */ 1734 #define PCI_CFG_SPACE_SIZE 256 1735 #define PCI_CFG_SPACE_EXP_SIZE 4096 1736 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff) 1737 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) 1738 #define PCI_EXT_CAP_ID_DSN 0x03 1739 1740 static int 1741 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) 1742 { 1743 uint32_t header; 1744 int ttl; 1745 int pos = PCI_CFG_SPACE_SIZE; 1746 1747 /* minimum 8 bytes per capability */ 1748 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 1749 1750 if (rte_pci_read_config(dev, &header, 4, pos) < 0) { 1751 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); 1752 return -1; 1753 } 1754 1755 /* 1756 * If we have no capabilities, this is indicated by cap ID, 1757 * cap version and next pointer all being 0. 1758 */ 1759 if (header == 0) 1760 return 0; 1761 1762 while (ttl-- > 0) { 1763 if (PCI_EXT_CAP_ID(header) == cap) 1764 return pos; 1765 1766 pos = PCI_EXT_CAP_NEXT(header); 1767 1768 if (pos < PCI_CFG_SPACE_SIZE) 1769 break; 1770 1771 if (rte_pci_read_config(dev, &header, 4, pos) < 0) { 1772 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); 1773 return -1; 1774 } 1775 } 1776 1777 return 0; 1778 } 1779 1780 /* 1781 * Extract device serial number from PCIe Configuration Space and 1782 * determine the pkg file path according to the DSN. 1783 */ 1784 static int 1785 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file) 1786 { 1787 int pos; 1788 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; 1789 uint32_t dsn_low, dsn_high; 1790 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); 1791 1792 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN); 1793 1794 if (pos) { 1795 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4); 1796 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8); 1797 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, 1798 "ice-%08x%08x.pkg", dsn_high, dsn_low); 1799 } else { 1800 PMD_INIT_LOG(ERR, "Failed to read device serial number\n"); 1801 goto fail_dsn; 1802 } 1803 1804 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, 1805 ICE_MAX_PKG_FILENAME_SIZE); 1806 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1807 return 0; 1808 1809 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, 1810 ICE_MAX_PKG_FILENAME_SIZE); 1811 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1812 return 0; 1813 1814 fail_dsn: 1815 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); 1816 if (!access(pkg_file, 0)) 1817 return 0; 1818 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); 1819 return 0; 1820 } 1821 1822 enum ice_pkg_type 1823 ice_load_pkg_type(struct ice_hw *hw) 1824 { 1825 enum ice_pkg_type package_type; 1826 1827 /* store the activated package type (OS default or Comms) */ 1828 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME, 1829 ICE_PKG_NAME_SIZE)) 1830 package_type = ICE_PKG_TYPE_OS_DEFAULT; 1831 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, 1832 ICE_PKG_NAME_SIZE)) 1833 package_type = ICE_PKG_TYPE_COMMS; 1834 else 1835 package_type = ICE_PKG_TYPE_UNKNOWN; 1836 1837 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s", 1838 hw->active_pkg_ver.major, hw->active_pkg_ver.minor, 1839 hw->active_pkg_ver.update, hw->active_pkg_ver.draft, 1840 hw->active_pkg_name); 1841 1842 return package_type; 1843 } 1844 1845 static int ice_load_pkg(struct rte_eth_dev *dev) 1846 { 1847 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1848 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE]; 1849 int err; 1850 uint8_t *buf; 1851 int buf_len; 1852 FILE *file; 1853 struct stat fstat; 1854 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1855 struct ice_adapter *ad = 1856 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1857 1858 ice_pkg_file_search_path(pci_dev, pkg_file); 1859 1860 file = fopen(pkg_file, "rb"); 1861 if (!file) { 1862 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); 1863 return -1; 1864 } 1865 1866 err = stat(pkg_file, &fstat); 1867 if (err) { 1868 PMD_INIT_LOG(ERR, "failed to get file stats\n"); 1869 fclose(file); 1870 return err; 1871 } 1872 1873 buf_len = fstat.st_size; 1874 buf = rte_malloc(NULL, buf_len, 0); 1875 1876 if (!buf) { 1877 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", 1878 buf_len); 1879 fclose(file); 1880 return -1; 1881 } 1882 1883 err = fread(buf, buf_len, 1, file); 1884 if (err != 1) { 1885 PMD_INIT_LOG(ERR, "failed to read package data\n"); 1886 fclose(file); 1887 err = -1; 1888 goto fail_exit; 1889 } 1890 1891 fclose(file); 1892 1893 err = ice_copy_and_init_pkg(hw, buf, buf_len); 1894 if (err) { 1895 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1896 goto fail_exit; 1897 } 1898 1899 /* store the loaded pkg type info */ 1900 ad->active_pkg_type = ice_load_pkg_type(hw); 1901 1902 err = ice_init_hw_tbls(hw); 1903 if (err) { 1904 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); 1905 goto fail_init_tbls; 1906 } 1907 1908 return 0; 1909 1910 fail_init_tbls: 1911 rte_free(hw->pkg_copy); 1912 fail_exit: 1913 rte_free(buf); 1914 return err; 1915 } 1916 1917 static void 1918 ice_base_queue_get(struct ice_pf *pf) 1919 { 1920 uint32_t reg; 1921 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1922 1923 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); 1924 if (reg & PFLAN_RX_QALLOC_VALID_M) { 1925 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; 1926 } else { 1927 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" 1928 " index"); 1929 } 1930 } 1931 1932 static int 1933 parse_bool(const char *key, const char *value, void *args) 1934 { 1935 int *i = (int *)args; 1936 char *end; 1937 int num; 1938 1939 num = strtoul(value, &end, 10); 1940 1941 if (num != 0 && num != 1) { 1942 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 1943 "value must be 0 or 1", 1944 value, key); 1945 return -1; 1946 } 1947 1948 *i = num; 1949 return 0; 1950 } 1951 1952 static int ice_parse_devargs(struct rte_eth_dev *dev) 1953 { 1954 struct ice_adapter *ad = 1955 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1956 struct rte_devargs *devargs = dev->device->devargs; 1957 struct rte_kvargs *kvlist; 1958 int ret; 1959 1960 if (devargs == NULL) 1961 return 0; 1962 1963 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args); 1964 if (kvlist == NULL) { 1965 PMD_INIT_LOG(ERR, "Invalid kvargs key\n"); 1966 return -EINVAL; 1967 } 1968 1969 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE; 1970 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE, 1971 sizeof(ad->devargs.proto_xtr)); 1972 1973 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG, 1974 &handle_proto_xtr_arg, &ad->devargs); 1975 if (ret) 1976 goto bail; 1977 1978 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, 1979 &parse_bool, &ad->devargs.safe_mode_support); 1980 if (ret) 1981 goto bail; 1982 1983 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, 1984 &parse_bool, &ad->devargs.pipe_mode_support); 1985 if (ret) 1986 goto bail; 1987 1988 ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG, 1989 &parse_bool, &ad->devargs.flow_mark_support); 1990 if (ret) 1991 goto bail; 1992 1993 bail: 1994 rte_kvargs_free(kvlist); 1995 return ret; 1996 } 1997 1998 /* Forward LLDP packets to default VSI by set switch rules */ 1999 static int 2000 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on) 2001 { 2002 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2003 struct ice_fltr_list_entry *s_list_itr = NULL; 2004 struct LIST_HEAD_TYPE list_head; 2005 int ret = 0; 2006 2007 INIT_LIST_HEAD(&list_head); 2008 2009 s_list_itr = (struct ice_fltr_list_entry *) 2010 ice_malloc(hw, sizeof(*s_list_itr)); 2011 if (!s_list_itr) 2012 return -ENOMEM; 2013 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE; 2014 s_list_itr->fltr_info.vsi_handle = vsi->idx; 2015 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype = 2016 RTE_ETHER_TYPE_LLDP; 2017 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 2018 s_list_itr->fltr_info.flag = ICE_FLTR_RX; 2019 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT; 2020 LIST_ADD(&s_list_itr->list_entry, &list_head); 2021 if (on) 2022 ret = ice_add_eth_mac(hw, &list_head); 2023 else 2024 ret = ice_remove_eth_mac(hw, &list_head); 2025 2026 rte_free(s_list_itr); 2027 return ret; 2028 } 2029 2030 static enum ice_status 2031 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, 2032 uint16_t num, uint16_t desc_id, 2033 uint16_t *prof_buf, uint16_t *num_prof) 2034 { 2035 struct ice_aqc_get_allocd_res_desc_resp *resp_buf; 2036 int ret; 2037 uint16_t buf_len; 2038 bool res_shared = 1; 2039 struct ice_aq_desc aq_desc; 2040 struct ice_sq_cd *cd = NULL; 2041 struct ice_aqc_get_allocd_res_desc *cmd = 2042 &aq_desc.params.get_res_desc; 2043 2044 buf_len = sizeof(resp_buf->elem) * num; 2045 resp_buf = ice_malloc(hw, buf_len); 2046 if (!resp_buf) 2047 return -ENOMEM; 2048 2049 ice_fill_dflt_direct_cmd_desc(&aq_desc, 2050 ice_aqc_opc_get_allocd_res_desc); 2051 2052 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) & 2053 ICE_AQC_RES_TYPE_M) | (res_shared ? 2054 ICE_AQC_RES_TYPE_FLAG_SHARED : 0)); 2055 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id); 2056 2057 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd); 2058 if (!ret) 2059 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc); 2060 else 2061 goto exit; 2062 2063 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) * 2064 (*num_prof), ICE_NONDMA_TO_NONDMA); 2065 2066 exit: 2067 rte_free(resp_buf); 2068 return ret; 2069 } 2070 static int 2071 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type) 2072 { 2073 int ret; 2074 uint16_t prof_id; 2075 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM]; 2076 uint16_t first_desc = 1; 2077 uint16_t num_prof = 0; 2078 2079 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM, 2080 first_desc, prof_buf, &num_prof); 2081 if (ret) { 2082 PMD_INIT_LOG(ERR, "Failed to get fxp resource"); 2083 return ret; 2084 } 2085 2086 for (prof_id = 0; prof_id < num_prof; prof_id++) { 2087 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]); 2088 if (ret) { 2089 PMD_INIT_LOG(ERR, "Failed to free fxp resource"); 2090 return ret; 2091 } 2092 } 2093 return 0; 2094 } 2095 2096 static int 2097 ice_reset_fxp_resource(struct ice_hw *hw) 2098 { 2099 int ret; 2100 2101 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID); 2102 if (ret) { 2103 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource"); 2104 return ret; 2105 } 2106 2107 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID); 2108 if (ret) { 2109 PMD_INIT_LOG(ERR, "Failed to clearup rss resource"); 2110 return ret; 2111 } 2112 2113 return 0; 2114 } 2115 2116 static int 2117 ice_dev_init(struct rte_eth_dev *dev) 2118 { 2119 struct rte_pci_device *pci_dev; 2120 struct rte_intr_handle *intr_handle; 2121 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2122 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2123 struct ice_adapter *ad = 2124 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2125 struct ice_vsi *vsi; 2126 int ret; 2127 2128 dev->dev_ops = &ice_eth_dev_ops; 2129 dev->rx_pkt_burst = ice_recv_pkts; 2130 dev->tx_pkt_burst = ice_xmit_pkts; 2131 dev->tx_pkt_prepare = ice_prep_pkts; 2132 2133 /* for secondary processes, we don't initialise any further as primary 2134 * has already done this work. 2135 */ 2136 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2137 ice_set_rx_function(dev); 2138 ice_set_tx_function(dev); 2139 return 0; 2140 } 2141 2142 ice_set_default_ptype_table(dev); 2143 pci_dev = RTE_DEV_TO_PCI(dev->device); 2144 intr_handle = &pci_dev->intr_handle; 2145 2146 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2147 pf->adapter->eth_dev = dev; 2148 pf->dev_data = dev->data; 2149 hw->back = pf->adapter; 2150 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 2151 hw->vendor_id = pci_dev->id.vendor_id; 2152 hw->device_id = pci_dev->id.device_id; 2153 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2154 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 2155 hw->bus.device = pci_dev->addr.devid; 2156 hw->bus.func = pci_dev->addr.function; 2157 2158 ret = ice_parse_devargs(dev); 2159 if (ret) { 2160 PMD_INIT_LOG(ERR, "Failed to parse devargs"); 2161 return -EINVAL; 2162 } 2163 2164 ice_init_controlq_parameter(hw); 2165 2166 ret = ice_init_hw(hw); 2167 if (ret) { 2168 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 2169 return -EINVAL; 2170 } 2171 2172 ret = ice_load_pkg(dev); 2173 if (ret) { 2174 if (ad->devargs.safe_mode_support == 0) { 2175 PMD_INIT_LOG(ERR, "Failed to load the DDP package," 2176 "Use safe-mode-support=1 to enter Safe Mode"); 2177 return ret; 2178 } 2179 2180 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 2181 "Entering Safe Mode"); 2182 ad->is_safe_mode = 1; 2183 } 2184 2185 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 2186 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 2187 hw->api_maj_ver, hw->api_min_ver); 2188 2189 ice_pf_sw_init(dev); 2190 ret = ice_init_mac_address(dev); 2191 if (ret) { 2192 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 2193 goto err_init_mac; 2194 } 2195 2196 /* Pass the information to the rte_eth_dev_close() that it should also 2197 * release the private port resources. 2198 */ 2199 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 2200 2201 ret = ice_res_pool_init(&pf->msix_pool, 1, 2202 hw->func_caps.common_cap.num_msix_vectors - 1); 2203 if (ret) { 2204 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 2205 goto err_msix_pool_init; 2206 } 2207 2208 ret = ice_pf_setup(pf); 2209 if (ret) { 2210 PMD_INIT_LOG(ERR, "Failed to setup PF"); 2211 goto err_pf_setup; 2212 } 2213 2214 ret = ice_send_driver_ver(hw); 2215 if (ret) { 2216 PMD_INIT_LOG(ERR, "Failed to send driver version"); 2217 goto err_pf_setup; 2218 } 2219 2220 vsi = pf->main_vsi; 2221 2222 /* Disable double vlan by default */ 2223 ice_vsi_config_double_vlan(vsi, false); 2224 2225 ret = ice_aq_stop_lldp(hw, true, false, NULL); 2226 if (ret != ICE_SUCCESS) 2227 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 2228 ret = ice_init_dcb(hw, true); 2229 if (ret != ICE_SUCCESS) 2230 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n"); 2231 /* Forward LLDP packets to default VSI */ 2232 ret = ice_vsi_config_sw_lldp(vsi, true); 2233 if (ret != ICE_SUCCESS) 2234 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n"); 2235 /* register callback func to eal lib */ 2236 rte_intr_callback_register(intr_handle, 2237 ice_interrupt_handler, dev); 2238 2239 ice_pf_enable_irq0(hw); 2240 2241 /* enable uio intr after callback register */ 2242 rte_intr_enable(intr_handle); 2243 2244 /* get base queue pairs index in the device */ 2245 ice_base_queue_get(pf); 2246 2247 if (!ad->is_safe_mode) { 2248 ret = ice_flow_init(ad); 2249 if (ret) { 2250 PMD_INIT_LOG(ERR, "Failed to initialize flow"); 2251 return ret; 2252 } 2253 } 2254 2255 ret = ice_reset_fxp_resource(hw); 2256 if (ret) { 2257 PMD_INIT_LOG(ERR, "Failed to reset fxp resource"); 2258 return ret; 2259 } 2260 2261 return 0; 2262 2263 err_pf_setup: 2264 ice_res_pool_destroy(&pf->msix_pool); 2265 err_msix_pool_init: 2266 rte_free(dev->data->mac_addrs); 2267 dev->data->mac_addrs = NULL; 2268 err_init_mac: 2269 ice_sched_cleanup_all(hw); 2270 rte_free(hw->port_info); 2271 ice_shutdown_all_ctrlq(hw); 2272 rte_free(pf->proto_xtr); 2273 2274 return ret; 2275 } 2276 2277 int 2278 ice_release_vsi(struct ice_vsi *vsi) 2279 { 2280 struct ice_hw *hw; 2281 struct ice_vsi_ctx vsi_ctx; 2282 enum ice_status ret; 2283 2284 if (!vsi) 2285 return 0; 2286 2287 hw = ICE_VSI_TO_HW(vsi); 2288 2289 ice_remove_all_mac_vlan_filters(vsi); 2290 2291 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 2292 2293 vsi_ctx.vsi_num = vsi->vsi_id; 2294 vsi_ctx.info = vsi->info; 2295 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 2296 if (ret != ICE_SUCCESS) { 2297 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 2298 rte_free(vsi); 2299 return -1; 2300 } 2301 2302 rte_free(vsi); 2303 return 0; 2304 } 2305 2306 void 2307 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 2308 { 2309 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2310 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2311 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2312 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2313 uint16_t msix_intr, i; 2314 2315 /* disable interrupt and also clear all the exist config */ 2316 for (i = 0; i < vsi->nb_qps; i++) { 2317 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2318 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2319 rte_wmb(); 2320 } 2321 2322 if (rte_intr_allow_others(intr_handle)) 2323 /* vfio-pci */ 2324 for (i = 0; i < vsi->nb_msix; i++) { 2325 msix_intr = vsi->msix_intr + i; 2326 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2327 GLINT_DYN_CTL_WB_ON_ITR_M); 2328 } 2329 else 2330 /* igb_uio */ 2331 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 2332 } 2333 2334 static void 2335 ice_dev_stop(struct rte_eth_dev *dev) 2336 { 2337 struct rte_eth_dev_data *data = dev->data; 2338 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2339 struct ice_vsi *main_vsi = pf->main_vsi; 2340 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2341 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2342 uint16_t i; 2343 2344 /* avoid stopping again */ 2345 if (pf->adapter_stopped) 2346 return; 2347 2348 /* stop and clear all Rx queues */ 2349 for (i = 0; i < data->nb_rx_queues; i++) 2350 ice_rx_queue_stop(dev, i); 2351 2352 /* stop and clear all Tx queues */ 2353 for (i = 0; i < data->nb_tx_queues; i++) 2354 ice_tx_queue_stop(dev, i); 2355 2356 /* disable all queue interrupts */ 2357 ice_vsi_disable_queues_intr(main_vsi); 2358 2359 if (pf->init_link_up) 2360 ice_dev_set_link_up(dev); 2361 else 2362 ice_dev_set_link_down(dev); 2363 2364 /* Clean datapath event and queue/vec mapping */ 2365 rte_intr_efd_disable(intr_handle); 2366 if (intr_handle->intr_vec) { 2367 rte_free(intr_handle->intr_vec); 2368 intr_handle->intr_vec = NULL; 2369 } 2370 2371 pf->adapter_stopped = true; 2372 } 2373 2374 static void 2375 ice_dev_close(struct rte_eth_dev *dev) 2376 { 2377 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2378 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2379 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2380 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2381 struct ice_adapter *ad = 2382 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2383 2384 /* Since stop will make link down, then the link event will be 2385 * triggered, disable the irq firstly to avoid the port_infoe etc 2386 * resources deallocation causing the interrupt service thread 2387 * crash. 2388 */ 2389 ice_pf_disable_irq0(hw); 2390 2391 ice_dev_stop(dev); 2392 2393 if (!ad->is_safe_mode) 2394 ice_flow_uninit(ad); 2395 2396 /* release all queue resource */ 2397 ice_free_queues(dev); 2398 2399 ice_res_pool_destroy(&pf->msix_pool); 2400 ice_release_vsi(pf->main_vsi); 2401 ice_sched_cleanup_all(hw); 2402 ice_free_hw_tbls(hw); 2403 rte_free(hw->port_info); 2404 hw->port_info = NULL; 2405 ice_shutdown_all_ctrlq(hw); 2406 rte_free(pf->proto_xtr); 2407 pf->proto_xtr = NULL; 2408 2409 dev->dev_ops = NULL; 2410 dev->rx_pkt_burst = NULL; 2411 dev->tx_pkt_burst = NULL; 2412 2413 rte_free(dev->data->mac_addrs); 2414 dev->data->mac_addrs = NULL; 2415 2416 /* disable uio intr before callback unregister */ 2417 rte_intr_disable(intr_handle); 2418 2419 /* unregister callback func from eal lib */ 2420 rte_intr_callback_unregister(intr_handle, 2421 ice_interrupt_handler, dev); 2422 } 2423 2424 static int 2425 ice_dev_uninit(struct rte_eth_dev *dev) 2426 { 2427 ice_dev_close(dev); 2428 2429 return 0; 2430 } 2431 2432 static void 2433 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf) 2434 { 2435 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2436 struct ice_vsi *vsi = pf->main_vsi; 2437 int ret; 2438 2439 /* Configure RSS for IPv4 with src/dst addr as input set */ 2440 if (rss_hf & ETH_RSS_IPV4) { 2441 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 2442 ICE_FLOW_SEG_HDR_IPV4 | 2443 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2444 if (ret) 2445 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", 2446 __func__, ret); 2447 } 2448 2449 /* Configure RSS for IPv6 with src/dst addr as input set */ 2450 if (rss_hf & ETH_RSS_IPV6) { 2451 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 2452 ICE_FLOW_SEG_HDR_IPV6 | 2453 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2454 if (ret) 2455 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", 2456 __func__, ret); 2457 } 2458 2459 /* Configure RSS for udp4 with src/dst addr and port as input set */ 2460 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 2461 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4, 2462 ICE_FLOW_SEG_HDR_UDP | 2463 ICE_FLOW_SEG_HDR_IPV4 | 2464 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2465 if (ret) 2466 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", 2467 __func__, ret); 2468 } 2469 2470 /* Configure RSS for udp6 with src/dst addr and port as input set */ 2471 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 2472 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6, 2473 ICE_FLOW_SEG_HDR_UDP | 2474 ICE_FLOW_SEG_HDR_IPV6 | 2475 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2476 if (ret) 2477 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", 2478 __func__, ret); 2479 } 2480 2481 /* Configure RSS for tcp4 with src/dst addr and port as input set */ 2482 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 2483 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4, 2484 ICE_FLOW_SEG_HDR_TCP | 2485 ICE_FLOW_SEG_HDR_IPV4 | 2486 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2487 if (ret) 2488 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", 2489 __func__, ret); 2490 } 2491 2492 /* Configure RSS for tcp6 with src/dst addr and port as input set */ 2493 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 2494 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6, 2495 ICE_FLOW_SEG_HDR_TCP | 2496 ICE_FLOW_SEG_HDR_IPV6 | 2497 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2498 if (ret) 2499 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", 2500 __func__, ret); 2501 } 2502 2503 /* Configure RSS for sctp4 with src/dst addr and port as input set */ 2504 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) { 2505 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 2506 ICE_FLOW_SEG_HDR_SCTP | 2507 ICE_FLOW_SEG_HDR_IPV4 | 2508 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2509 if (ret) 2510 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 2511 __func__, ret); 2512 } 2513 2514 /* Configure RSS for sctp6 with src/dst addr and port as input set */ 2515 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) { 2516 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 2517 ICE_FLOW_SEG_HDR_SCTP | 2518 ICE_FLOW_SEG_HDR_IPV6 | 2519 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2520 if (ret) 2521 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 2522 __func__, ret); 2523 } 2524 2525 if (rss_hf & ETH_RSS_IPV4) { 2526 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 2527 ICE_FLOW_SEG_HDR_GTPU_IP, 0); 2528 if (ret) 2529 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d", 2530 __func__, ret); 2531 2532 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 2533 ICE_FLOW_SEG_HDR_PPPOE, 0); 2534 if (ret) 2535 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d", 2536 __func__, ret); 2537 } 2538 2539 if (rss_hf & ETH_RSS_IPV6) { 2540 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 2541 ICE_FLOW_SEG_HDR_GTPU_IP, 0); 2542 if (ret) 2543 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d", 2544 __func__, ret); 2545 2546 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 2547 ICE_FLOW_SEG_HDR_PPPOE, 0); 2548 if (ret) 2549 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d", 2550 __func__, ret); 2551 } 2552 2553 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 2554 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4, 2555 ICE_FLOW_SEG_HDR_PPPOE, 0); 2556 if (ret) 2557 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d", 2558 __func__, ret); 2559 } 2560 2561 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 2562 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6, 2563 ICE_FLOW_SEG_HDR_PPPOE, 0); 2564 if (ret) 2565 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d", 2566 __func__, ret); 2567 } 2568 2569 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 2570 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4, 2571 ICE_FLOW_SEG_HDR_PPPOE, 0); 2572 if (ret) 2573 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d", 2574 __func__, ret); 2575 } 2576 2577 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 2578 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6, 2579 ICE_FLOW_SEG_HDR_PPPOE, 0); 2580 if (ret) 2581 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d", 2582 __func__, ret); 2583 } 2584 2585 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) { 2586 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_SCTP_IPV4, 2587 ICE_FLOW_SEG_HDR_PPPOE, 0); 2588 if (ret) 2589 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_SCTP rss flow fail %d", 2590 __func__, ret); 2591 } 2592 2593 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) { 2594 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_SCTP_IPV6, 2595 ICE_FLOW_SEG_HDR_PPPOE, 0); 2596 if (ret) 2597 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_SCTP rss flow fail %d", 2598 __func__, ret); 2599 } 2600 } 2601 2602 static int ice_init_rss(struct ice_pf *pf) 2603 { 2604 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2605 struct ice_vsi *vsi = pf->main_vsi; 2606 struct rte_eth_dev *dev = pf->adapter->eth_dev; 2607 struct rte_eth_rss_conf *rss_conf; 2608 struct ice_aqc_get_set_rss_keys key; 2609 uint16_t i, nb_q; 2610 int ret = 0; 2611 bool is_safe_mode = pf->adapter->is_safe_mode; 2612 uint32_t reg; 2613 2614 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 2615 nb_q = dev->data->nb_rx_queues; 2616 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 2617 vsi->rss_lut_size = pf->hash_lut_size; 2618 2619 if (is_safe_mode) { 2620 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 2621 return 0; 2622 } 2623 2624 if (!vsi->rss_key) 2625 vsi->rss_key = rte_zmalloc(NULL, 2626 vsi->rss_key_size, 0); 2627 if (!vsi->rss_lut) 2628 vsi->rss_lut = rte_zmalloc(NULL, 2629 vsi->rss_lut_size, 0); 2630 2631 /* configure RSS key */ 2632 if (!rss_conf->rss_key) { 2633 /* Calculate the default hash key */ 2634 for (i = 0; i <= vsi->rss_key_size; i++) 2635 vsi->rss_key[i] = (uint8_t)rte_rand(); 2636 } else { 2637 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 2638 RTE_MIN(rss_conf->rss_key_len, 2639 vsi->rss_key_size)); 2640 } 2641 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 2642 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 2643 if (ret) 2644 return -EINVAL; 2645 2646 /* init RSS LUT table */ 2647 for (i = 0; i < vsi->rss_lut_size; i++) 2648 vsi->rss_lut[i] = i % nb_q; 2649 2650 ret = ice_aq_set_rss_lut(hw, vsi->idx, 2651 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, 2652 vsi->rss_lut, vsi->rss_lut_size); 2653 if (ret) 2654 return -EINVAL; 2655 2656 /* Enable registers for symmetric_toeplitz function. */ 2657 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id)); 2658 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) | 2659 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S); 2660 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg); 2661 2662 /* RSS hash configuration */ 2663 ice_rss_hash_set(pf, rss_conf->rss_hf); 2664 2665 return 0; 2666 } 2667 2668 static int 2669 ice_dev_configure(struct rte_eth_dev *dev) 2670 { 2671 struct ice_adapter *ad = 2672 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2673 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2674 int ret; 2675 2676 /* Initialize to TRUE. If any of Rx queues doesn't meet the 2677 * bulk allocation or vector Rx preconditions we will reset it. 2678 */ 2679 ad->rx_bulk_alloc_allowed = true; 2680 ad->tx_simple_allowed = true; 2681 2682 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 2683 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2684 2685 ret = ice_init_rss(pf); 2686 if (ret) { 2687 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 2688 return ret; 2689 } 2690 2691 return 0; 2692 } 2693 2694 static void 2695 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 2696 int base_queue, int nb_queue) 2697 { 2698 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2699 uint32_t val, val_tx; 2700 int i; 2701 2702 for (i = 0; i < nb_queue; i++) { 2703 /*do actual bind*/ 2704 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 2705 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 2706 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 2707 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 2708 2709 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 2710 base_queue + i, msix_vect); 2711 /* set ITR0 value */ 2712 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); 2713 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 2714 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 2715 } 2716 } 2717 2718 void 2719 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 2720 { 2721 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2722 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2723 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2724 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2725 uint16_t msix_vect = vsi->msix_intr; 2726 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 2727 uint16_t queue_idx = 0; 2728 int record = 0; 2729 int i; 2730 2731 /* clear Rx/Tx queue interrupt */ 2732 for (i = 0; i < vsi->nb_used_qps; i++) { 2733 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2734 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2735 } 2736 2737 /* PF bind interrupt */ 2738 if (rte_intr_dp_is_en(intr_handle)) { 2739 queue_idx = 0; 2740 record = 1; 2741 } 2742 2743 for (i = 0; i < vsi->nb_used_qps; i++) { 2744 if (nb_msix <= 1) { 2745 if (!rte_intr_allow_others(intr_handle)) 2746 msix_vect = ICE_MISC_VEC_ID; 2747 2748 /* uio mapping all queue to one msix_vect */ 2749 __vsi_queues_bind_intr(vsi, msix_vect, 2750 vsi->base_queue + i, 2751 vsi->nb_used_qps - i); 2752 2753 for (; !!record && i < vsi->nb_used_qps; i++) 2754 intr_handle->intr_vec[queue_idx + i] = 2755 msix_vect; 2756 break; 2757 } 2758 2759 /* vfio 1:1 queue/msix_vect mapping */ 2760 __vsi_queues_bind_intr(vsi, msix_vect, 2761 vsi->base_queue + i, 1); 2762 2763 if (!!record) 2764 intr_handle->intr_vec[queue_idx + i] = msix_vect; 2765 2766 msix_vect++; 2767 nb_msix--; 2768 } 2769 } 2770 2771 void 2772 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 2773 { 2774 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2775 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2776 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2777 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2778 uint16_t msix_intr, i; 2779 2780 if (rte_intr_allow_others(intr_handle)) 2781 for (i = 0; i < vsi->nb_used_qps; i++) { 2782 msix_intr = vsi->msix_intr + i; 2783 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2784 GLINT_DYN_CTL_INTENA_M | 2785 GLINT_DYN_CTL_CLEARPBA_M | 2786 GLINT_DYN_CTL_ITR_INDX_M | 2787 GLINT_DYN_CTL_WB_ON_ITR_M); 2788 } 2789 else 2790 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 2791 GLINT_DYN_CTL_INTENA_M | 2792 GLINT_DYN_CTL_CLEARPBA_M | 2793 GLINT_DYN_CTL_ITR_INDX_M | 2794 GLINT_DYN_CTL_WB_ON_ITR_M); 2795 } 2796 2797 static int 2798 ice_rxq_intr_setup(struct rte_eth_dev *dev) 2799 { 2800 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2801 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2802 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2803 struct ice_vsi *vsi = pf->main_vsi; 2804 uint32_t intr_vector = 0; 2805 2806 rte_intr_disable(intr_handle); 2807 2808 /* check and configure queue intr-vector mapping */ 2809 if ((rte_intr_cap_multiple(intr_handle) || 2810 !RTE_ETH_DEV_SRIOV(dev).active) && 2811 dev->data->dev_conf.intr_conf.rxq != 0) { 2812 intr_vector = dev->data->nb_rx_queues; 2813 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 2814 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 2815 ICE_MAX_INTR_QUEUE_NUM); 2816 return -ENOTSUP; 2817 } 2818 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2819 return -1; 2820 } 2821 2822 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2823 intr_handle->intr_vec = 2824 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 2825 0); 2826 if (!intr_handle->intr_vec) { 2827 PMD_DRV_LOG(ERR, 2828 "Failed to allocate %d rx_queues intr_vec", 2829 dev->data->nb_rx_queues); 2830 return -ENOMEM; 2831 } 2832 } 2833 2834 /* Map queues with MSIX interrupt */ 2835 vsi->nb_used_qps = dev->data->nb_rx_queues; 2836 ice_vsi_queues_bind_intr(vsi); 2837 2838 /* Enable interrupts for all the queues */ 2839 ice_vsi_enable_queues_intr(vsi); 2840 2841 rte_intr_enable(intr_handle); 2842 2843 return 0; 2844 } 2845 2846 static void 2847 ice_get_init_link_status(struct rte_eth_dev *dev) 2848 { 2849 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2850 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2851 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2852 struct ice_link_status link_status; 2853 int ret; 2854 2855 ret = ice_aq_get_link_info(hw->port_info, enable_lse, 2856 &link_status, NULL); 2857 if (ret != ICE_SUCCESS) { 2858 PMD_DRV_LOG(ERR, "Failed to get link info"); 2859 pf->init_link_up = false; 2860 return; 2861 } 2862 2863 if (link_status.link_info & ICE_AQ_LINK_UP) 2864 pf->init_link_up = true; 2865 } 2866 2867 static int 2868 ice_dev_start(struct rte_eth_dev *dev) 2869 { 2870 struct rte_eth_dev_data *data = dev->data; 2871 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2872 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2873 struct ice_vsi *vsi = pf->main_vsi; 2874 uint16_t nb_rxq = 0; 2875 uint16_t nb_txq, i; 2876 uint16_t max_frame_size; 2877 int mask, ret; 2878 2879 /* program Tx queues' context in hardware */ 2880 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 2881 ret = ice_tx_queue_start(dev, nb_txq); 2882 if (ret) { 2883 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 2884 goto tx_err; 2885 } 2886 } 2887 2888 /* program Rx queues' context in hardware*/ 2889 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 2890 ret = ice_rx_queue_start(dev, nb_rxq); 2891 if (ret) { 2892 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 2893 goto rx_err; 2894 } 2895 } 2896 2897 ice_set_rx_function(dev); 2898 ice_set_tx_function(dev); 2899 2900 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2901 ETH_VLAN_EXTEND_MASK; 2902 ret = ice_vlan_offload_set(dev, mask); 2903 if (ret) { 2904 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2905 goto rx_err; 2906 } 2907 2908 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 2909 if (ice_rxq_intr_setup(dev)) 2910 return -EIO; 2911 2912 /* Enable receiving broadcast packets and transmitting packets */ 2913 ret = ice_set_vsi_promisc(hw, vsi->idx, 2914 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 2915 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 2916 0); 2917 if (ret != ICE_SUCCESS) 2918 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2919 2920 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 2921 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 2922 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 2923 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 2924 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 2925 ICE_AQ_LINK_EVENT_AN_COMPLETED | 2926 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 2927 NULL); 2928 if (ret != ICE_SUCCESS) 2929 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 2930 2931 ice_get_init_link_status(dev); 2932 2933 ice_dev_set_link_up(dev); 2934 2935 /* Call get_link_info aq commond to enable/disable LSE */ 2936 ice_link_update(dev, 0); 2937 2938 pf->adapter_stopped = false; 2939 2940 /* Set the max frame size to default value*/ 2941 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ? 2942 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len : 2943 ICE_FRAME_SIZE_MAX; 2944 2945 /* Set the max frame size to HW*/ 2946 ice_aq_set_mac_cfg(hw, max_frame_size, NULL); 2947 2948 return 0; 2949 2950 /* stop the started queues if failed to start all queues */ 2951 rx_err: 2952 for (i = 0; i < nb_rxq; i++) 2953 ice_rx_queue_stop(dev, i); 2954 tx_err: 2955 for (i = 0; i < nb_txq; i++) 2956 ice_tx_queue_stop(dev, i); 2957 2958 return -EIO; 2959 } 2960 2961 static int 2962 ice_dev_reset(struct rte_eth_dev *dev) 2963 { 2964 int ret; 2965 2966 if (dev->data->sriov.active) 2967 return -ENOTSUP; 2968 2969 ret = ice_dev_uninit(dev); 2970 if (ret) { 2971 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 2972 return -ENXIO; 2973 } 2974 2975 ret = ice_dev_init(dev); 2976 if (ret) { 2977 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 2978 return -ENXIO; 2979 } 2980 2981 return 0; 2982 } 2983 2984 static int 2985 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2986 { 2987 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2988 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2989 struct ice_vsi *vsi = pf->main_vsi; 2990 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 2991 bool is_safe_mode = pf->adapter->is_safe_mode; 2992 u64 phy_type_low; 2993 u64 phy_type_high; 2994 2995 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 2996 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 2997 dev_info->max_rx_queues = vsi->nb_qps; 2998 dev_info->max_tx_queues = vsi->nb_qps; 2999 dev_info->max_mac_addrs = vsi->max_macaddrs; 3000 dev_info->max_vfs = pci_dev->max_vfs; 3001 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 3002 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3003 3004 dev_info->rx_offload_capa = 3005 DEV_RX_OFFLOAD_VLAN_STRIP | 3006 DEV_RX_OFFLOAD_JUMBO_FRAME | 3007 DEV_RX_OFFLOAD_KEEP_CRC | 3008 DEV_RX_OFFLOAD_SCATTER | 3009 DEV_RX_OFFLOAD_VLAN_FILTER; 3010 dev_info->tx_offload_capa = 3011 DEV_TX_OFFLOAD_VLAN_INSERT | 3012 DEV_TX_OFFLOAD_TCP_TSO | 3013 DEV_TX_OFFLOAD_MULTI_SEGS | 3014 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3015 dev_info->flow_type_rss_offloads = 0; 3016 3017 if (!is_safe_mode) { 3018 dev_info->rx_offload_capa |= 3019 DEV_RX_OFFLOAD_IPV4_CKSUM | 3020 DEV_RX_OFFLOAD_UDP_CKSUM | 3021 DEV_RX_OFFLOAD_TCP_CKSUM | 3022 DEV_RX_OFFLOAD_QINQ_STRIP | 3023 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3024 DEV_RX_OFFLOAD_VLAN_EXTEND | 3025 DEV_RX_OFFLOAD_RSS_HASH; 3026 dev_info->tx_offload_capa |= 3027 DEV_TX_OFFLOAD_QINQ_INSERT | 3028 DEV_TX_OFFLOAD_IPV4_CKSUM | 3029 DEV_TX_OFFLOAD_UDP_CKSUM | 3030 DEV_TX_OFFLOAD_TCP_CKSUM | 3031 DEV_TX_OFFLOAD_SCTP_CKSUM | 3032 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3033 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 3034 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 3035 } 3036 3037 dev_info->rx_queue_offload_capa = 0; 3038 dev_info->tx_queue_offload_capa = 0; 3039 3040 dev_info->reta_size = pf->hash_lut_size; 3041 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 3042 3043 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3044 .rx_thresh = { 3045 .pthresh = ICE_DEFAULT_RX_PTHRESH, 3046 .hthresh = ICE_DEFAULT_RX_HTHRESH, 3047 .wthresh = ICE_DEFAULT_RX_WTHRESH, 3048 }, 3049 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 3050 .rx_drop_en = 0, 3051 .offloads = 0, 3052 }; 3053 3054 dev_info->default_txconf = (struct rte_eth_txconf) { 3055 .tx_thresh = { 3056 .pthresh = ICE_DEFAULT_TX_PTHRESH, 3057 .hthresh = ICE_DEFAULT_TX_HTHRESH, 3058 .wthresh = ICE_DEFAULT_TX_WTHRESH, 3059 }, 3060 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 3061 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 3062 .offloads = 0, 3063 }; 3064 3065 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3066 .nb_max = ICE_MAX_RING_DESC, 3067 .nb_min = ICE_MIN_RING_DESC, 3068 .nb_align = ICE_ALIGN_RING_DESC, 3069 }; 3070 3071 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3072 .nb_max = ICE_MAX_RING_DESC, 3073 .nb_min = ICE_MIN_RING_DESC, 3074 .nb_align = ICE_ALIGN_RING_DESC, 3075 }; 3076 3077 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3078 ETH_LINK_SPEED_100M | 3079 ETH_LINK_SPEED_1G | 3080 ETH_LINK_SPEED_2_5G | 3081 ETH_LINK_SPEED_5G | 3082 ETH_LINK_SPEED_10G | 3083 ETH_LINK_SPEED_20G | 3084 ETH_LINK_SPEED_25G; 3085 3086 phy_type_low = hw->port_info->phy.phy_type_low; 3087 phy_type_high = hw->port_info->phy.phy_type_high; 3088 3089 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 3090 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 3091 3092 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 3093 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 3094 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 3095 3096 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 3097 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 3098 3099 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 3100 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 3101 dev_info->default_rxportconf.nb_queues = 1; 3102 dev_info->default_txportconf.nb_queues = 1; 3103 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 3104 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 3105 3106 return 0; 3107 } 3108 3109 static inline int 3110 ice_atomic_read_link_status(struct rte_eth_dev *dev, 3111 struct rte_eth_link *link) 3112 { 3113 struct rte_eth_link *dst = link; 3114 struct rte_eth_link *src = &dev->data->dev_link; 3115 3116 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3117 *(uint64_t *)src) == 0) 3118 return -1; 3119 3120 return 0; 3121 } 3122 3123 static inline int 3124 ice_atomic_write_link_status(struct rte_eth_dev *dev, 3125 struct rte_eth_link *link) 3126 { 3127 struct rte_eth_link *dst = &dev->data->dev_link; 3128 struct rte_eth_link *src = link; 3129 3130 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3131 *(uint64_t *)src) == 0) 3132 return -1; 3133 3134 return 0; 3135 } 3136 3137 static int 3138 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 3139 { 3140 #define CHECK_INTERVAL 100 /* 100ms */ 3141 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 3142 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3143 struct ice_link_status link_status; 3144 struct rte_eth_link link, old; 3145 int status; 3146 unsigned int rep_cnt = MAX_REPEAT_TIME; 3147 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3148 3149 memset(&link, 0, sizeof(link)); 3150 memset(&old, 0, sizeof(old)); 3151 memset(&link_status, 0, sizeof(link_status)); 3152 ice_atomic_read_link_status(dev, &old); 3153 3154 do { 3155 /* Get link status information from hardware */ 3156 status = ice_aq_get_link_info(hw->port_info, enable_lse, 3157 &link_status, NULL); 3158 if (status != ICE_SUCCESS) { 3159 link.link_speed = ETH_SPEED_NUM_100M; 3160 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3161 PMD_DRV_LOG(ERR, "Failed to get link info"); 3162 goto out; 3163 } 3164 3165 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 3166 if (!wait_to_complete || link.link_status) 3167 break; 3168 3169 rte_delay_ms(CHECK_INTERVAL); 3170 } while (--rep_cnt); 3171 3172 if (!link.link_status) 3173 goto out; 3174 3175 /* Full-duplex operation at all supported speeds */ 3176 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3177 3178 /* Parse the link status */ 3179 switch (link_status.link_speed) { 3180 case ICE_AQ_LINK_SPEED_10MB: 3181 link.link_speed = ETH_SPEED_NUM_10M; 3182 break; 3183 case ICE_AQ_LINK_SPEED_100MB: 3184 link.link_speed = ETH_SPEED_NUM_100M; 3185 break; 3186 case ICE_AQ_LINK_SPEED_1000MB: 3187 link.link_speed = ETH_SPEED_NUM_1G; 3188 break; 3189 case ICE_AQ_LINK_SPEED_2500MB: 3190 link.link_speed = ETH_SPEED_NUM_2_5G; 3191 break; 3192 case ICE_AQ_LINK_SPEED_5GB: 3193 link.link_speed = ETH_SPEED_NUM_5G; 3194 break; 3195 case ICE_AQ_LINK_SPEED_10GB: 3196 link.link_speed = ETH_SPEED_NUM_10G; 3197 break; 3198 case ICE_AQ_LINK_SPEED_20GB: 3199 link.link_speed = ETH_SPEED_NUM_20G; 3200 break; 3201 case ICE_AQ_LINK_SPEED_25GB: 3202 link.link_speed = ETH_SPEED_NUM_25G; 3203 break; 3204 case ICE_AQ_LINK_SPEED_40GB: 3205 link.link_speed = ETH_SPEED_NUM_40G; 3206 break; 3207 case ICE_AQ_LINK_SPEED_50GB: 3208 link.link_speed = ETH_SPEED_NUM_50G; 3209 break; 3210 case ICE_AQ_LINK_SPEED_100GB: 3211 link.link_speed = ETH_SPEED_NUM_100G; 3212 break; 3213 case ICE_AQ_LINK_SPEED_UNKNOWN: 3214 default: 3215 PMD_DRV_LOG(ERR, "Unknown link speed"); 3216 link.link_speed = ETH_SPEED_NUM_NONE; 3217 break; 3218 } 3219 3220 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 3221 ETH_LINK_SPEED_FIXED); 3222 3223 out: 3224 ice_atomic_write_link_status(dev, &link); 3225 if (link.link_status == old.link_status) 3226 return -1; 3227 3228 return 0; 3229 } 3230 3231 /* Force the physical link state by getting the current PHY capabilities from 3232 * hardware and setting the PHY config based on the determined capabilities. If 3233 * link changes, link event will be triggered because both the Enable Automatic 3234 * Link Update and LESM Enable bits are set when setting the PHY capabilities. 3235 */ 3236 static enum ice_status 3237 ice_force_phys_link_state(struct ice_hw *hw, bool link_up) 3238 { 3239 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3240 struct ice_aqc_get_phy_caps_data *pcaps; 3241 struct ice_port_info *pi; 3242 enum ice_status status; 3243 3244 if (!hw || !hw->port_info) 3245 return ICE_ERR_PARAM; 3246 3247 pi = hw->port_info; 3248 3249 pcaps = (struct ice_aqc_get_phy_caps_data *) 3250 ice_malloc(hw, sizeof(*pcaps)); 3251 if (!pcaps) 3252 return ICE_ERR_NO_MEMORY; 3253 3254 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 3255 NULL); 3256 if (status) 3257 goto out; 3258 3259 /* No change in link */ 3260 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) && 3261 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) 3262 goto out; 3263 3264 cfg.phy_type_low = pcaps->phy_type_low; 3265 cfg.phy_type_high = pcaps->phy_type_high; 3266 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3267 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an; 3268 cfg.eee_cap = pcaps->eee_cap; 3269 cfg.eeer_value = pcaps->eeer_value; 3270 cfg.link_fec_opt = pcaps->link_fec_options; 3271 if (link_up) 3272 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 3273 else 3274 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 3275 3276 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3277 3278 out: 3279 ice_free(hw, pcaps); 3280 return status; 3281 } 3282 3283 static int 3284 ice_dev_set_link_up(struct rte_eth_dev *dev) 3285 { 3286 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3287 3288 return ice_force_phys_link_state(hw, true); 3289 } 3290 3291 static int 3292 ice_dev_set_link_down(struct rte_eth_dev *dev) 3293 { 3294 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3295 3296 return ice_force_phys_link_state(hw, false); 3297 } 3298 3299 static int 3300 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3301 { 3302 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3303 struct rte_eth_dev_data *dev_data = pf->dev_data; 3304 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 3305 3306 /* check if mtu is within the allowed range */ 3307 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 3308 return -EINVAL; 3309 3310 /* mtu setting is forbidden if port is start */ 3311 if (dev_data->dev_started) { 3312 PMD_DRV_LOG(ERR, 3313 "port %d must be stopped before configuration", 3314 dev_data->port_id); 3315 return -EBUSY; 3316 } 3317 3318 if (frame_size > RTE_ETHER_MAX_LEN) 3319 dev_data->dev_conf.rxmode.offloads |= 3320 DEV_RX_OFFLOAD_JUMBO_FRAME; 3321 else 3322 dev_data->dev_conf.rxmode.offloads &= 3323 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 3324 3325 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3326 3327 return 0; 3328 } 3329 3330 static int ice_macaddr_set(struct rte_eth_dev *dev, 3331 struct rte_ether_addr *mac_addr) 3332 { 3333 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3334 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3335 struct ice_vsi *vsi = pf->main_vsi; 3336 struct ice_mac_filter *f; 3337 uint8_t flags = 0; 3338 int ret; 3339 3340 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 3341 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 3342 return -EINVAL; 3343 } 3344 3345 TAILQ_FOREACH(f, &vsi->mac_list, next) { 3346 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 3347 break; 3348 } 3349 3350 if (!f) { 3351 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 3352 return -EIO; 3353 } 3354 3355 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 3356 if (ret != ICE_SUCCESS) { 3357 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 3358 return -EIO; 3359 } 3360 ret = ice_add_mac_filter(vsi, mac_addr); 3361 if (ret != ICE_SUCCESS) { 3362 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 3363 return -EIO; 3364 } 3365 rte_ether_addr_copy(mac_addr, &pf->dev_addr); 3366 3367 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 3368 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 3369 if (ret != ICE_SUCCESS) 3370 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 3371 3372 return 0; 3373 } 3374 3375 /* Add a MAC address, and update filters */ 3376 static int 3377 ice_macaddr_add(struct rte_eth_dev *dev, 3378 struct rte_ether_addr *mac_addr, 3379 __rte_unused uint32_t index, 3380 __rte_unused uint32_t pool) 3381 { 3382 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3383 struct ice_vsi *vsi = pf->main_vsi; 3384 int ret; 3385 3386 ret = ice_add_mac_filter(vsi, mac_addr); 3387 if (ret != ICE_SUCCESS) { 3388 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 3389 return -EINVAL; 3390 } 3391 3392 return ICE_SUCCESS; 3393 } 3394 3395 /* Remove a MAC address, and update filters */ 3396 static void 3397 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 3398 { 3399 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3400 struct ice_vsi *vsi = pf->main_vsi; 3401 struct rte_eth_dev_data *data = dev->data; 3402 struct rte_ether_addr *macaddr; 3403 int ret; 3404 3405 macaddr = &data->mac_addrs[index]; 3406 ret = ice_remove_mac_filter(vsi, macaddr); 3407 if (ret) { 3408 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 3409 return; 3410 } 3411 } 3412 3413 static int 3414 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3415 { 3416 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3417 struct ice_vsi *vsi = pf->main_vsi; 3418 int ret; 3419 3420 PMD_INIT_FUNC_TRACE(); 3421 3422 if (on) { 3423 ret = ice_add_vlan_filter(vsi, vlan_id); 3424 if (ret < 0) { 3425 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 3426 return -EINVAL; 3427 } 3428 } else { 3429 ret = ice_remove_vlan_filter(vsi, vlan_id); 3430 if (ret < 0) { 3431 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 3432 return -EINVAL; 3433 } 3434 } 3435 3436 return 0; 3437 } 3438 3439 /* Configure vlan filter on or off */ 3440 static int 3441 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 3442 { 3443 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3444 struct ice_vsi_ctx ctxt; 3445 uint8_t sec_flags, sw_flags2; 3446 int ret = 0; 3447 3448 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 3449 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 3450 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 3451 3452 if (on) { 3453 vsi->info.sec_flags |= sec_flags; 3454 vsi->info.sw_flags2 |= sw_flags2; 3455 } else { 3456 vsi->info.sec_flags &= ~sec_flags; 3457 vsi->info.sw_flags2 &= ~sw_flags2; 3458 } 3459 vsi->info.sw_id = hw->port_info->sw_id; 3460 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 3461 ctxt.info.valid_sections = 3462 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 3463 ICE_AQ_VSI_PROP_SECURITY_VALID); 3464 ctxt.vsi_num = vsi->vsi_id; 3465 3466 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 3467 if (ret) { 3468 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 3469 on ? "enable" : "disable"); 3470 return -EINVAL; 3471 } else { 3472 vsi->info.valid_sections |= 3473 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 3474 ICE_AQ_VSI_PROP_SECURITY_VALID); 3475 } 3476 3477 /* consist with other drivers, allow untagged packet when vlan filter on */ 3478 if (on) 3479 ret = ice_add_vlan_filter(vsi, 0); 3480 else 3481 ret = ice_remove_vlan_filter(vsi, 0); 3482 3483 return 0; 3484 } 3485 3486 static int 3487 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 3488 { 3489 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3490 struct ice_vsi_ctx ctxt; 3491 uint8_t vlan_flags; 3492 int ret = 0; 3493 3494 /* Check if it has been already on or off */ 3495 if (vsi->info.valid_sections & 3496 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 3497 if (on) { 3498 if ((vsi->info.vlan_flags & 3499 ICE_AQ_VSI_VLAN_EMOD_M) == 3500 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) 3501 return 0; /* already on */ 3502 } else { 3503 if ((vsi->info.vlan_flags & 3504 ICE_AQ_VSI_VLAN_EMOD_M) == 3505 ICE_AQ_VSI_VLAN_EMOD_NOTHING) 3506 return 0; /* already off */ 3507 } 3508 } 3509 3510 if (on) 3511 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; 3512 else 3513 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; 3514 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); 3515 vsi->info.vlan_flags |= vlan_flags; 3516 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 3517 ctxt.info.valid_sections = 3518 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3519 ctxt.vsi_num = vsi->vsi_id; 3520 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 3521 if (ret) { 3522 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 3523 on ? "enable" : "disable"); 3524 return -EINVAL; 3525 } 3526 3527 vsi->info.valid_sections |= 3528 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3529 3530 return ret; 3531 } 3532 3533 static int 3534 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 3535 { 3536 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3537 struct ice_vsi *vsi = pf->main_vsi; 3538 struct rte_eth_rxmode *rxmode; 3539 3540 rxmode = &dev->data->dev_conf.rxmode; 3541 if (mask & ETH_VLAN_FILTER_MASK) { 3542 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 3543 ice_vsi_config_vlan_filter(vsi, true); 3544 else 3545 ice_vsi_config_vlan_filter(vsi, false); 3546 } 3547 3548 if (mask & ETH_VLAN_STRIP_MASK) { 3549 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 3550 ice_vsi_config_vlan_stripping(vsi, true); 3551 else 3552 ice_vsi_config_vlan_stripping(vsi, false); 3553 } 3554 3555 if (mask & ETH_VLAN_EXTEND_MASK) { 3556 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 3557 ice_vsi_config_double_vlan(vsi, true); 3558 else 3559 ice_vsi_config_double_vlan(vsi, false); 3560 } 3561 3562 return 0; 3563 } 3564 3565 static int 3566 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 3567 { 3568 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 3569 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3570 int ret; 3571 3572 if (!lut) 3573 return -EINVAL; 3574 3575 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 3576 ret = ice_aq_get_rss_lut(hw, vsi->idx, 3577 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); 3578 if (ret) { 3579 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 3580 return -EINVAL; 3581 } 3582 } else { 3583 uint64_t *lut_dw = (uint64_t *)lut; 3584 uint16_t i, lut_size_dw = lut_size / 4; 3585 3586 for (i = 0; i < lut_size_dw; i++) 3587 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 3588 } 3589 3590 return 0; 3591 } 3592 3593 static int 3594 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 3595 { 3596 struct ice_pf *pf; 3597 struct ice_hw *hw; 3598 int ret; 3599 3600 if (!vsi || !lut) 3601 return -EINVAL; 3602 3603 pf = ICE_VSI_TO_PF(vsi); 3604 hw = ICE_VSI_TO_HW(vsi); 3605 3606 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 3607 ret = ice_aq_set_rss_lut(hw, vsi->idx, 3608 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); 3609 if (ret) { 3610 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 3611 return -EINVAL; 3612 } 3613 } else { 3614 uint64_t *lut_dw = (uint64_t *)lut; 3615 uint16_t i, lut_size_dw = lut_size / 4; 3616 3617 for (i = 0; i < lut_size_dw; i++) 3618 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 3619 3620 ice_flush(hw); 3621 } 3622 3623 return 0; 3624 } 3625 3626 static int 3627 ice_rss_reta_update(struct rte_eth_dev *dev, 3628 struct rte_eth_rss_reta_entry64 *reta_conf, 3629 uint16_t reta_size) 3630 { 3631 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3632 uint16_t i, lut_size = pf->hash_lut_size; 3633 uint16_t idx, shift; 3634 uint8_t *lut; 3635 int ret; 3636 3637 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 3638 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 3639 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 3640 PMD_DRV_LOG(ERR, 3641 "The size of hash lookup table configured (%d)" 3642 "doesn't match the number hardware can " 3643 "supported (128, 512, 2048)", 3644 reta_size); 3645 return -EINVAL; 3646 } 3647 3648 /* It MUST use the current LUT size to get the RSS lookup table, 3649 * otherwise if will fail with -100 error code. 3650 */ 3651 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 3652 if (!lut) { 3653 PMD_DRV_LOG(ERR, "No memory can be allocated"); 3654 return -ENOMEM; 3655 } 3656 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 3657 if (ret) 3658 goto out; 3659 3660 for (i = 0; i < reta_size; i++) { 3661 idx = i / RTE_RETA_GROUP_SIZE; 3662 shift = i % RTE_RETA_GROUP_SIZE; 3663 if (reta_conf[idx].mask & (1ULL << shift)) 3664 lut[i] = reta_conf[idx].reta[shift]; 3665 } 3666 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 3667 if (ret == 0 && lut_size != reta_size) { 3668 PMD_DRV_LOG(INFO, 3669 "The size of hash lookup table is changed from (%d) to (%d)", 3670 lut_size, reta_size); 3671 pf->hash_lut_size = reta_size; 3672 } 3673 3674 out: 3675 rte_free(lut); 3676 3677 return ret; 3678 } 3679 3680 static int 3681 ice_rss_reta_query(struct rte_eth_dev *dev, 3682 struct rte_eth_rss_reta_entry64 *reta_conf, 3683 uint16_t reta_size) 3684 { 3685 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3686 uint16_t i, lut_size = pf->hash_lut_size; 3687 uint16_t idx, shift; 3688 uint8_t *lut; 3689 int ret; 3690 3691 if (reta_size != lut_size) { 3692 PMD_DRV_LOG(ERR, 3693 "The size of hash lookup table configured (%d)" 3694 "doesn't match the number hardware can " 3695 "supported (%d)", 3696 reta_size, lut_size); 3697 return -EINVAL; 3698 } 3699 3700 lut = rte_zmalloc(NULL, reta_size, 0); 3701 if (!lut) { 3702 PMD_DRV_LOG(ERR, "No memory can be allocated"); 3703 return -ENOMEM; 3704 } 3705 3706 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 3707 if (ret) 3708 goto out; 3709 3710 for (i = 0; i < reta_size; i++) { 3711 idx = i / RTE_RETA_GROUP_SIZE; 3712 shift = i % RTE_RETA_GROUP_SIZE; 3713 if (reta_conf[idx].mask & (1ULL << shift)) 3714 reta_conf[idx].reta[shift] = lut[i]; 3715 } 3716 3717 out: 3718 rte_free(lut); 3719 3720 return ret; 3721 } 3722 3723 static int 3724 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 3725 { 3726 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3727 int ret = 0; 3728 3729 if (!key || key_len == 0) { 3730 PMD_DRV_LOG(DEBUG, "No key to be configured"); 3731 return 0; 3732 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 3733 sizeof(uint32_t)) { 3734 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 3735 return -EINVAL; 3736 } 3737 3738 struct ice_aqc_get_set_rss_keys *key_dw = 3739 (struct ice_aqc_get_set_rss_keys *)key; 3740 3741 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 3742 if (ret) { 3743 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 3744 ret = -EINVAL; 3745 } 3746 3747 return ret; 3748 } 3749 3750 static int 3751 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 3752 { 3753 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3754 int ret; 3755 3756 if (!key || !key_len) 3757 return -EINVAL; 3758 3759 ret = ice_aq_get_rss_key 3760 (hw, vsi->idx, 3761 (struct ice_aqc_get_set_rss_keys *)key); 3762 if (ret) { 3763 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 3764 return -EINVAL; 3765 } 3766 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 3767 3768 return 0; 3769 } 3770 3771 static int 3772 ice_rss_hash_update(struct rte_eth_dev *dev, 3773 struct rte_eth_rss_conf *rss_conf) 3774 { 3775 enum ice_status status = ICE_SUCCESS; 3776 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3777 struct ice_vsi *vsi = pf->main_vsi; 3778 3779 /* set hash key */ 3780 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 3781 if (status) 3782 return status; 3783 3784 if (rss_conf->rss_hf == 0) 3785 return 0; 3786 3787 /* RSS hash configuration */ 3788 ice_rss_hash_set(pf, rss_conf->rss_hf); 3789 3790 return 0; 3791 } 3792 3793 static int 3794 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 3795 struct rte_eth_rss_conf *rss_conf) 3796 { 3797 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3798 struct ice_vsi *vsi = pf->main_vsi; 3799 3800 ice_get_rss_key(vsi, rss_conf->rss_key, 3801 &rss_conf->rss_key_len); 3802 3803 /* TODO: default set to 0 as hf config is not supported now */ 3804 rss_conf->rss_hf = 0; 3805 return 0; 3806 } 3807 3808 static int 3809 ice_promisc_enable(struct rte_eth_dev *dev) 3810 { 3811 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3812 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3813 struct ice_vsi *vsi = pf->main_vsi; 3814 enum ice_status status; 3815 uint8_t pmask; 3816 int ret = 0; 3817 3818 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 3819 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3820 3821 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 3822 switch (status) { 3823 case ICE_ERR_ALREADY_EXISTS: 3824 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 3825 case ICE_SUCCESS: 3826 break; 3827 default: 3828 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 3829 ret = -EAGAIN; 3830 } 3831 3832 return ret; 3833 } 3834 3835 static int 3836 ice_promisc_disable(struct rte_eth_dev *dev) 3837 { 3838 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3839 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3840 struct ice_vsi *vsi = pf->main_vsi; 3841 enum ice_status status; 3842 uint8_t pmask; 3843 int ret = 0; 3844 3845 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 3846 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3847 3848 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 3849 if (status != ICE_SUCCESS) { 3850 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 3851 ret = -EAGAIN; 3852 } 3853 3854 return ret; 3855 } 3856 3857 static int 3858 ice_allmulti_enable(struct rte_eth_dev *dev) 3859 { 3860 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3861 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3862 struct ice_vsi *vsi = pf->main_vsi; 3863 enum ice_status status; 3864 uint8_t pmask; 3865 int ret = 0; 3866 3867 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3868 3869 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 3870 3871 switch (status) { 3872 case ICE_ERR_ALREADY_EXISTS: 3873 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled"); 3874 case ICE_SUCCESS: 3875 break; 3876 default: 3877 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 3878 ret = -EAGAIN; 3879 } 3880 3881 return ret; 3882 } 3883 3884 static int 3885 ice_allmulti_disable(struct rte_eth_dev *dev) 3886 { 3887 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3888 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3889 struct ice_vsi *vsi = pf->main_vsi; 3890 enum ice_status status; 3891 uint8_t pmask; 3892 int ret = 0; 3893 3894 if (dev->data->promiscuous == 1) 3895 return 0; /* must remain in all_multicast mode */ 3896 3897 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3898 3899 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 3900 if (status != ICE_SUCCESS) { 3901 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 3902 ret = -EAGAIN; 3903 } 3904 3905 return ret; 3906 } 3907 3908 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 3909 uint16_t queue_id) 3910 { 3911 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3912 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3913 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3914 uint32_t val; 3915 uint16_t msix_intr; 3916 3917 msix_intr = intr_handle->intr_vec[queue_id]; 3918 3919 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 3920 GLINT_DYN_CTL_ITR_INDX_M; 3921 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 3922 3923 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 3924 rte_intr_ack(&pci_dev->intr_handle); 3925 3926 return 0; 3927 } 3928 3929 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 3930 uint16_t queue_id) 3931 { 3932 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3933 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3934 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3935 uint16_t msix_intr; 3936 3937 msix_intr = intr_handle->intr_vec[queue_id]; 3938 3939 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 3940 3941 return 0; 3942 } 3943 3944 static int 3945 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3946 { 3947 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3948 u8 ver, patch; 3949 u16 build; 3950 int ret; 3951 3952 ver = hw->nvm.orom.major; 3953 patch = hw->nvm.orom.patch; 3954 build = hw->nvm.orom.build; 3955 3956 ret = snprintf(fw_version, fw_size, 3957 "%d.%d 0x%08x %d.%d.%d", 3958 hw->nvm.major_ver, 3959 hw->nvm.minor_ver, 3960 hw->nvm.eetrack, 3961 ver, build, patch); 3962 3963 /* add the size of '\0' */ 3964 ret += 1; 3965 if (fw_size < (u32)ret) 3966 return ret; 3967 else 3968 return 0; 3969 } 3970 3971 static int 3972 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 3973 { 3974 struct ice_hw *hw; 3975 struct ice_vsi_ctx ctxt; 3976 uint8_t vlan_flags = 0; 3977 int ret; 3978 3979 if (!vsi || !info) { 3980 PMD_DRV_LOG(ERR, "invalid parameters"); 3981 return -EINVAL; 3982 } 3983 3984 if (info->on) { 3985 vsi->info.pvid = info->config.pvid; 3986 /** 3987 * If insert pvid is enabled, only tagged pkts are 3988 * allowed to be sent out. 3989 */ 3990 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | 3991 ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 3992 } else { 3993 vsi->info.pvid = 0; 3994 if (info->config.reject.tagged == 0) 3995 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; 3996 3997 if (info->config.reject.untagged == 0) 3998 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 3999 } 4000 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | 4001 ICE_AQ_VSI_VLAN_MODE_M); 4002 vsi->info.vlan_flags |= vlan_flags; 4003 memset(&ctxt, 0, sizeof(ctxt)); 4004 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4005 ctxt.info.valid_sections = 4006 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4007 ctxt.vsi_num = vsi->vsi_id; 4008 4009 hw = ICE_VSI_TO_HW(vsi); 4010 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4011 if (ret != ICE_SUCCESS) { 4012 PMD_DRV_LOG(ERR, 4013 "update VSI for VLAN insert failed, err %d", 4014 ret); 4015 return -EINVAL; 4016 } 4017 4018 vsi->info.valid_sections |= 4019 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4020 4021 return ret; 4022 } 4023 4024 static int 4025 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 4026 { 4027 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4028 struct ice_vsi *vsi = pf->main_vsi; 4029 struct rte_eth_dev_data *data = pf->dev_data; 4030 struct ice_vsi_vlan_pvid_info info; 4031 int ret; 4032 4033 memset(&info, 0, sizeof(info)); 4034 info.on = on; 4035 if (info.on) { 4036 info.config.pvid = pvid; 4037 } else { 4038 info.config.reject.tagged = 4039 data->dev_conf.txmode.hw_vlan_reject_tagged; 4040 info.config.reject.untagged = 4041 data->dev_conf.txmode.hw_vlan_reject_untagged; 4042 } 4043 4044 ret = ice_vsi_vlan_pvid_set(vsi, &info); 4045 if (ret < 0) { 4046 PMD_DRV_LOG(ERR, "Failed to set pvid."); 4047 return -EINVAL; 4048 } 4049 4050 return 0; 4051 } 4052 4053 static int 4054 ice_get_eeprom_length(struct rte_eth_dev *dev) 4055 { 4056 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4057 4058 return hw->nvm.flash_size; 4059 } 4060 4061 static int 4062 ice_get_eeprom(struct rte_eth_dev *dev, 4063 struct rte_dev_eeprom_info *eeprom) 4064 { 4065 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4066 enum ice_status status = ICE_SUCCESS; 4067 uint8_t *data = eeprom->data; 4068 4069 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4070 4071 status = ice_acquire_nvm(hw, ICE_RES_READ); 4072 if (status) { 4073 PMD_DRV_LOG(ERR, "acquire nvm failed."); 4074 return -EIO; 4075 } 4076 4077 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length, 4078 data, false); 4079 4080 ice_release_nvm(hw); 4081 4082 if (status) { 4083 PMD_DRV_LOG(ERR, "EEPROM read failed."); 4084 return -EIO; 4085 } 4086 4087 return 0; 4088 } 4089 4090 static void 4091 ice_stat_update_32(struct ice_hw *hw, 4092 uint32_t reg, 4093 bool offset_loaded, 4094 uint64_t *offset, 4095 uint64_t *stat) 4096 { 4097 uint64_t new_data; 4098 4099 new_data = (uint64_t)ICE_READ_REG(hw, reg); 4100 if (!offset_loaded) 4101 *offset = new_data; 4102 4103 if (new_data >= *offset) 4104 *stat = (uint64_t)(new_data - *offset); 4105 else 4106 *stat = (uint64_t)((new_data + 4107 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 4108 - *offset); 4109 } 4110 4111 static void 4112 ice_stat_update_40(struct ice_hw *hw, 4113 uint32_t hireg, 4114 uint32_t loreg, 4115 bool offset_loaded, 4116 uint64_t *offset, 4117 uint64_t *stat) 4118 { 4119 uint64_t new_data; 4120 4121 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 4122 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 4123 ICE_32_BIT_WIDTH; 4124 4125 if (!offset_loaded) 4126 *offset = new_data; 4127 4128 if (new_data >= *offset) 4129 *stat = new_data - *offset; 4130 else 4131 *stat = (uint64_t)((new_data + 4132 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 4133 *offset); 4134 4135 *stat &= ICE_40_BIT_MASK; 4136 } 4137 4138 /* Get all the statistics of a VSI */ 4139 static void 4140 ice_update_vsi_stats(struct ice_vsi *vsi) 4141 { 4142 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 4143 struct ice_eth_stats *nes = &vsi->eth_stats; 4144 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4145 int idx = rte_le_to_cpu_16(vsi->vsi_id); 4146 4147 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 4148 vsi->offset_loaded, &oes->rx_bytes, 4149 &nes->rx_bytes); 4150 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 4151 vsi->offset_loaded, &oes->rx_unicast, 4152 &nes->rx_unicast); 4153 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 4154 vsi->offset_loaded, &oes->rx_multicast, 4155 &nes->rx_multicast); 4156 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 4157 vsi->offset_loaded, &oes->rx_broadcast, 4158 &nes->rx_broadcast); 4159 /* exclude CRC bytes */ 4160 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 4161 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 4162 4163 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 4164 &oes->rx_discards, &nes->rx_discards); 4165 /* GLV_REPC not supported */ 4166 /* GLV_RMPC not supported */ 4167 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 4168 &oes->rx_unknown_protocol, 4169 &nes->rx_unknown_protocol); 4170 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 4171 vsi->offset_loaded, &oes->tx_bytes, 4172 &nes->tx_bytes); 4173 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 4174 vsi->offset_loaded, &oes->tx_unicast, 4175 &nes->tx_unicast); 4176 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 4177 vsi->offset_loaded, &oes->tx_multicast, 4178 &nes->tx_multicast); 4179 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 4180 vsi->offset_loaded, &oes->tx_broadcast, 4181 &nes->tx_broadcast); 4182 /* GLV_TDPC not supported */ 4183 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 4184 &oes->tx_errors, &nes->tx_errors); 4185 vsi->offset_loaded = true; 4186 4187 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 4188 vsi->vsi_id); 4189 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 4190 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 4191 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 4192 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 4193 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 4194 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 4195 nes->rx_unknown_protocol); 4196 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 4197 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 4198 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 4199 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 4200 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 4201 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 4202 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 4203 vsi->vsi_id); 4204 } 4205 4206 static void 4207 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 4208 { 4209 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 4210 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 4211 4212 /* Get statistics of struct ice_eth_stats */ 4213 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 4214 GLPRT_GORCL(hw->port_info->lport), 4215 pf->offset_loaded, &os->eth.rx_bytes, 4216 &ns->eth.rx_bytes); 4217 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 4218 GLPRT_UPRCL(hw->port_info->lport), 4219 pf->offset_loaded, &os->eth.rx_unicast, 4220 &ns->eth.rx_unicast); 4221 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 4222 GLPRT_MPRCL(hw->port_info->lport), 4223 pf->offset_loaded, &os->eth.rx_multicast, 4224 &ns->eth.rx_multicast); 4225 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 4226 GLPRT_BPRCL(hw->port_info->lport), 4227 pf->offset_loaded, &os->eth.rx_broadcast, 4228 &ns->eth.rx_broadcast); 4229 ice_stat_update_32(hw, PRTRPB_RDPC, 4230 pf->offset_loaded, &os->eth.rx_discards, 4231 &ns->eth.rx_discards); 4232 4233 /* Workaround: CRC size should not be included in byte statistics, 4234 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 4235 * packet. 4236 */ 4237 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 4238 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 4239 4240 /* GLPRT_REPC not supported */ 4241 /* GLPRT_RMPC not supported */ 4242 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 4243 pf->offset_loaded, 4244 &os->eth.rx_unknown_protocol, 4245 &ns->eth.rx_unknown_protocol); 4246 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 4247 GLPRT_GOTCL(hw->port_info->lport), 4248 pf->offset_loaded, &os->eth.tx_bytes, 4249 &ns->eth.tx_bytes); 4250 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 4251 GLPRT_UPTCL(hw->port_info->lport), 4252 pf->offset_loaded, &os->eth.tx_unicast, 4253 &ns->eth.tx_unicast); 4254 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 4255 GLPRT_MPTCL(hw->port_info->lport), 4256 pf->offset_loaded, &os->eth.tx_multicast, 4257 &ns->eth.tx_multicast); 4258 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 4259 GLPRT_BPTCL(hw->port_info->lport), 4260 pf->offset_loaded, &os->eth.tx_broadcast, 4261 &ns->eth.tx_broadcast); 4262 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 4263 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 4264 4265 /* GLPRT_TEPC not supported */ 4266 4267 /* additional port specific stats */ 4268 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 4269 pf->offset_loaded, &os->tx_dropped_link_down, 4270 &ns->tx_dropped_link_down); 4271 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 4272 pf->offset_loaded, &os->crc_errors, 4273 &ns->crc_errors); 4274 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 4275 pf->offset_loaded, &os->illegal_bytes, 4276 &ns->illegal_bytes); 4277 /* GLPRT_ERRBC not supported */ 4278 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 4279 pf->offset_loaded, &os->mac_local_faults, 4280 &ns->mac_local_faults); 4281 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 4282 pf->offset_loaded, &os->mac_remote_faults, 4283 &ns->mac_remote_faults); 4284 4285 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 4286 pf->offset_loaded, &os->rx_len_errors, 4287 &ns->rx_len_errors); 4288 4289 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 4290 pf->offset_loaded, &os->link_xon_rx, 4291 &ns->link_xon_rx); 4292 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 4293 pf->offset_loaded, &os->link_xoff_rx, 4294 &ns->link_xoff_rx); 4295 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 4296 pf->offset_loaded, &os->link_xon_tx, 4297 &ns->link_xon_tx); 4298 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 4299 pf->offset_loaded, &os->link_xoff_tx, 4300 &ns->link_xoff_tx); 4301 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 4302 GLPRT_PRC64L(hw->port_info->lport), 4303 pf->offset_loaded, &os->rx_size_64, 4304 &ns->rx_size_64); 4305 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 4306 GLPRT_PRC127L(hw->port_info->lport), 4307 pf->offset_loaded, &os->rx_size_127, 4308 &ns->rx_size_127); 4309 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 4310 GLPRT_PRC255L(hw->port_info->lport), 4311 pf->offset_loaded, &os->rx_size_255, 4312 &ns->rx_size_255); 4313 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 4314 GLPRT_PRC511L(hw->port_info->lport), 4315 pf->offset_loaded, &os->rx_size_511, 4316 &ns->rx_size_511); 4317 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 4318 GLPRT_PRC1023L(hw->port_info->lport), 4319 pf->offset_loaded, &os->rx_size_1023, 4320 &ns->rx_size_1023); 4321 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 4322 GLPRT_PRC1522L(hw->port_info->lport), 4323 pf->offset_loaded, &os->rx_size_1522, 4324 &ns->rx_size_1522); 4325 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 4326 GLPRT_PRC9522L(hw->port_info->lport), 4327 pf->offset_loaded, &os->rx_size_big, 4328 &ns->rx_size_big); 4329 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 4330 pf->offset_loaded, &os->rx_undersize, 4331 &ns->rx_undersize); 4332 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 4333 pf->offset_loaded, &os->rx_fragments, 4334 &ns->rx_fragments); 4335 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 4336 pf->offset_loaded, &os->rx_oversize, 4337 &ns->rx_oversize); 4338 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 4339 pf->offset_loaded, &os->rx_jabber, 4340 &ns->rx_jabber); 4341 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 4342 GLPRT_PTC64L(hw->port_info->lport), 4343 pf->offset_loaded, &os->tx_size_64, 4344 &ns->tx_size_64); 4345 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 4346 GLPRT_PTC127L(hw->port_info->lport), 4347 pf->offset_loaded, &os->tx_size_127, 4348 &ns->tx_size_127); 4349 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 4350 GLPRT_PTC255L(hw->port_info->lport), 4351 pf->offset_loaded, &os->tx_size_255, 4352 &ns->tx_size_255); 4353 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 4354 GLPRT_PTC511L(hw->port_info->lport), 4355 pf->offset_loaded, &os->tx_size_511, 4356 &ns->tx_size_511); 4357 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 4358 GLPRT_PTC1023L(hw->port_info->lport), 4359 pf->offset_loaded, &os->tx_size_1023, 4360 &ns->tx_size_1023); 4361 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 4362 GLPRT_PTC1522L(hw->port_info->lport), 4363 pf->offset_loaded, &os->tx_size_1522, 4364 &ns->tx_size_1522); 4365 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 4366 GLPRT_PTC9522L(hw->port_info->lport), 4367 pf->offset_loaded, &os->tx_size_big, 4368 &ns->tx_size_big); 4369 4370 /* GLPRT_MSPDC not supported */ 4371 /* GLPRT_XEC not supported */ 4372 4373 pf->offset_loaded = true; 4374 4375 if (pf->main_vsi) 4376 ice_update_vsi_stats(pf->main_vsi); 4377 } 4378 4379 /* Get all statistics of a port */ 4380 static int 4381 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 4382 { 4383 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4384 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4385 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 4386 4387 /* call read registers - updates values, now write them to struct */ 4388 ice_read_stats_registers(pf, hw); 4389 4390 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 4391 pf->main_vsi->eth_stats.rx_multicast + 4392 pf->main_vsi->eth_stats.rx_broadcast - 4393 pf->main_vsi->eth_stats.rx_discards; 4394 stats->opackets = ns->eth.tx_unicast + 4395 ns->eth.tx_multicast + 4396 ns->eth.tx_broadcast; 4397 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 4398 stats->obytes = ns->eth.tx_bytes; 4399 stats->oerrors = ns->eth.tx_errors + 4400 pf->main_vsi->eth_stats.tx_errors; 4401 4402 /* Rx Errors */ 4403 stats->imissed = ns->eth.rx_discards + 4404 pf->main_vsi->eth_stats.rx_discards; 4405 stats->ierrors = ns->crc_errors + 4406 ns->rx_undersize + 4407 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 4408 4409 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 4410 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 4411 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 4412 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 4413 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 4414 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 4415 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 4416 pf->main_vsi->eth_stats.rx_discards); 4417 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 4418 ns->eth.rx_unknown_protocol); 4419 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 4420 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 4421 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 4422 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 4423 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 4424 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 4425 pf->main_vsi->eth_stats.tx_discards); 4426 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 4427 4428 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 4429 ns->tx_dropped_link_down); 4430 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 4431 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 4432 ns->illegal_bytes); 4433 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 4434 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 4435 ns->mac_local_faults); 4436 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 4437 ns->mac_remote_faults); 4438 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 4439 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 4440 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 4441 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 4442 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 4443 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 4444 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 4445 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 4446 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 4447 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 4448 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 4449 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 4450 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 4451 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 4452 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 4453 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 4454 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 4455 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 4456 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 4457 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 4458 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 4459 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 4460 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 4461 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 4462 return 0; 4463 } 4464 4465 /* Reset the statistics */ 4466 static int 4467 ice_stats_reset(struct rte_eth_dev *dev) 4468 { 4469 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4470 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4471 4472 /* Mark PF and VSI stats to update the offset, aka "reset" */ 4473 pf->offset_loaded = false; 4474 if (pf->main_vsi) 4475 pf->main_vsi->offset_loaded = false; 4476 4477 /* read the stats, reading current register values into offset */ 4478 ice_read_stats_registers(pf, hw); 4479 4480 return 0; 4481 } 4482 4483 static uint32_t 4484 ice_xstats_calc_num(void) 4485 { 4486 uint32_t num; 4487 4488 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 4489 4490 return num; 4491 } 4492 4493 static int 4494 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 4495 unsigned int n) 4496 { 4497 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4498 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4499 unsigned int i; 4500 unsigned int count; 4501 struct ice_hw_port_stats *hw_stats = &pf->stats; 4502 4503 count = ice_xstats_calc_num(); 4504 if (n < count) 4505 return count; 4506 4507 ice_read_stats_registers(pf, hw); 4508 4509 if (!xstats) 4510 return 0; 4511 4512 count = 0; 4513 4514 /* Get stats from ice_eth_stats struct */ 4515 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 4516 xstats[count].value = 4517 *(uint64_t *)((char *)&hw_stats->eth + 4518 ice_stats_strings[i].offset); 4519 xstats[count].id = count; 4520 count++; 4521 } 4522 4523 /* Get individiual stats from ice_hw_port struct */ 4524 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 4525 xstats[count].value = 4526 *(uint64_t *)((char *)hw_stats + 4527 ice_hw_port_strings[i].offset); 4528 xstats[count].id = count; 4529 count++; 4530 } 4531 4532 return count; 4533 } 4534 4535 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 4536 struct rte_eth_xstat_name *xstats_names, 4537 __rte_unused unsigned int limit) 4538 { 4539 unsigned int count = 0; 4540 unsigned int i; 4541 4542 if (!xstats_names) 4543 return ice_xstats_calc_num(); 4544 4545 /* Note: limit checked in rte_eth_xstats_names() */ 4546 4547 /* Get stats from ice_eth_stats struct */ 4548 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 4549 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 4550 sizeof(xstats_names[count].name)); 4551 count++; 4552 } 4553 4554 /* Get individiual stats from ice_hw_port struct */ 4555 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 4556 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 4557 sizeof(xstats_names[count].name)); 4558 count++; 4559 } 4560 4561 return count; 4562 } 4563 4564 static int 4565 ice_dev_filter_ctrl(struct rte_eth_dev *dev, 4566 enum rte_filter_type filter_type, 4567 enum rte_filter_op filter_op, 4568 void *arg) 4569 { 4570 int ret = 0; 4571 4572 if (!dev) 4573 return -EINVAL; 4574 4575 switch (filter_type) { 4576 case RTE_ETH_FILTER_GENERIC: 4577 if (filter_op != RTE_ETH_FILTER_GET) 4578 return -EINVAL; 4579 *(const void **)arg = &ice_flow_ops; 4580 break; 4581 default: 4582 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 4583 filter_type); 4584 ret = -EINVAL; 4585 break; 4586 } 4587 4588 return ret; 4589 } 4590 4591 /* Add UDP tunneling port */ 4592 static int 4593 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 4594 struct rte_eth_udp_tunnel *udp_tunnel) 4595 { 4596 int ret = 0; 4597 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4598 4599 if (udp_tunnel == NULL) 4600 return -EINVAL; 4601 4602 switch (udp_tunnel->prot_type) { 4603 case RTE_TUNNEL_TYPE_VXLAN: 4604 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); 4605 break; 4606 default: 4607 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4608 ret = -EINVAL; 4609 break; 4610 } 4611 4612 return ret; 4613 } 4614 4615 /* Delete UDP tunneling port */ 4616 static int 4617 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 4618 struct rte_eth_udp_tunnel *udp_tunnel) 4619 { 4620 int ret = 0; 4621 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4622 4623 if (udp_tunnel == NULL) 4624 return -EINVAL; 4625 4626 switch (udp_tunnel->prot_type) { 4627 case RTE_TUNNEL_TYPE_VXLAN: 4628 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); 4629 break; 4630 default: 4631 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4632 ret = -EINVAL; 4633 break; 4634 } 4635 4636 return ret; 4637 } 4638 4639 static int 4640 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 4641 struct rte_pci_device *pci_dev) 4642 { 4643 return rte_eth_dev_pci_generic_probe(pci_dev, 4644 sizeof(struct ice_adapter), 4645 ice_dev_init); 4646 } 4647 4648 static int 4649 ice_pci_remove(struct rte_pci_device *pci_dev) 4650 { 4651 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 4652 } 4653 4654 static struct rte_pci_driver rte_ice_pmd = { 4655 .id_table = pci_id_ice_map, 4656 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 4657 .probe = ice_pci_probe, 4658 .remove = ice_pci_remove, 4659 }; 4660 4661 /** 4662 * Driver initialization routine. 4663 * Invoked once at EAL init time. 4664 * Register itself as the [Poll Mode] Driver of PCI devices. 4665 */ 4666 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 4667 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 4668 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 4669 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 4670 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>" 4671 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" 4672 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>" 4673 ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>"); 4674 4675 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE); 4676 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE); 4677 #ifdef RTE_LIBRTE_ICE_DEBUG_RX 4678 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG); 4679 #endif 4680 #ifdef RTE_LIBRTE_ICE_DEBUG_TX 4681 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG); 4682 #endif 4683 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE 4684 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG); 4685 #endif 4686