1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <rte_ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include "base/ice_sched.h" 14 #include "base/ice_flow.h" 15 #include "base/ice_dcb.h" 16 #include "ice_ethdev.h" 17 #include "ice_rxtx.h" 18 19 #define ICE_MAX_QP_NUM "max_queue_pair_num" 20 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 21 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg" 22 23 int ice_logtype_init; 24 int ice_logtype_driver; 25 26 static int ice_dev_configure(struct rte_eth_dev *dev); 27 static int ice_dev_start(struct rte_eth_dev *dev); 28 static void ice_dev_stop(struct rte_eth_dev *dev); 29 static void ice_dev_close(struct rte_eth_dev *dev); 30 static int ice_dev_reset(struct rte_eth_dev *dev); 31 static void ice_dev_info_get(struct rte_eth_dev *dev, 32 struct rte_eth_dev_info *dev_info); 33 static int ice_link_update(struct rte_eth_dev *dev, 34 int wait_to_complete); 35 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 36 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 37 38 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 39 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 40 static int ice_vlan_tpid_set(struct rte_eth_dev *dev, 41 enum rte_vlan_type vlan_type, 42 uint16_t tpid); 43 static int ice_rss_reta_update(struct rte_eth_dev *dev, 44 struct rte_eth_rss_reta_entry64 *reta_conf, 45 uint16_t reta_size); 46 static int ice_rss_reta_query(struct rte_eth_dev *dev, 47 struct rte_eth_rss_reta_entry64 *reta_conf, 48 uint16_t reta_size); 49 static int ice_rss_hash_update(struct rte_eth_dev *dev, 50 struct rte_eth_rss_conf *rss_conf); 51 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 52 struct rte_eth_rss_conf *rss_conf); 53 static void ice_promisc_enable(struct rte_eth_dev *dev); 54 static void ice_promisc_disable(struct rte_eth_dev *dev); 55 static void ice_allmulti_enable(struct rte_eth_dev *dev); 56 static void ice_allmulti_disable(struct rte_eth_dev *dev); 57 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 58 uint16_t vlan_id, 59 int on); 60 static int ice_macaddr_set(struct rte_eth_dev *dev, 61 struct rte_ether_addr *mac_addr); 62 static int ice_macaddr_add(struct rte_eth_dev *dev, 63 struct rte_ether_addr *mac_addr, 64 __rte_unused uint32_t index, 65 uint32_t pool); 66 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 67 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 68 uint16_t queue_id); 69 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 70 uint16_t queue_id); 71 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 72 size_t fw_size); 73 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 74 uint16_t pvid, int on); 75 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 76 static int ice_get_eeprom(struct rte_eth_dev *dev, 77 struct rte_dev_eeprom_info *eeprom); 78 static int ice_stats_get(struct rte_eth_dev *dev, 79 struct rte_eth_stats *stats); 80 static void ice_stats_reset(struct rte_eth_dev *dev); 81 static int ice_xstats_get(struct rte_eth_dev *dev, 82 struct rte_eth_xstat *xstats, unsigned int n); 83 static int ice_xstats_get_names(struct rte_eth_dev *dev, 84 struct rte_eth_xstat_name *xstats_names, 85 unsigned int limit); 86 87 static const struct rte_pci_id pci_id_ice_map[] = { 88 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 89 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 90 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 91 { .vendor_id = 0, /* sentinel */ }, 92 }; 93 94 static const struct eth_dev_ops ice_eth_dev_ops = { 95 .dev_configure = ice_dev_configure, 96 .dev_start = ice_dev_start, 97 .dev_stop = ice_dev_stop, 98 .dev_close = ice_dev_close, 99 .dev_reset = ice_dev_reset, 100 .dev_set_link_up = ice_dev_set_link_up, 101 .dev_set_link_down = ice_dev_set_link_down, 102 .rx_queue_start = ice_rx_queue_start, 103 .rx_queue_stop = ice_rx_queue_stop, 104 .tx_queue_start = ice_tx_queue_start, 105 .tx_queue_stop = ice_tx_queue_stop, 106 .rx_queue_setup = ice_rx_queue_setup, 107 .rx_queue_release = ice_rx_queue_release, 108 .tx_queue_setup = ice_tx_queue_setup, 109 .tx_queue_release = ice_tx_queue_release, 110 .dev_infos_get = ice_dev_info_get, 111 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 112 .link_update = ice_link_update, 113 .mtu_set = ice_mtu_set, 114 .mac_addr_set = ice_macaddr_set, 115 .mac_addr_add = ice_macaddr_add, 116 .mac_addr_remove = ice_macaddr_remove, 117 .vlan_filter_set = ice_vlan_filter_set, 118 .vlan_offload_set = ice_vlan_offload_set, 119 .vlan_tpid_set = ice_vlan_tpid_set, 120 .reta_update = ice_rss_reta_update, 121 .reta_query = ice_rss_reta_query, 122 .rss_hash_update = ice_rss_hash_update, 123 .rss_hash_conf_get = ice_rss_hash_conf_get, 124 .promiscuous_enable = ice_promisc_enable, 125 .promiscuous_disable = ice_promisc_disable, 126 .allmulticast_enable = ice_allmulti_enable, 127 .allmulticast_disable = ice_allmulti_disable, 128 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 129 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 130 .fw_version_get = ice_fw_version_get, 131 .vlan_pvid_set = ice_vlan_pvid_set, 132 .rxq_info_get = ice_rxq_info_get, 133 .txq_info_get = ice_txq_info_get, 134 .get_eeprom_length = ice_get_eeprom_length, 135 .get_eeprom = ice_get_eeprom, 136 .rx_queue_count = ice_rx_queue_count, 137 .rx_descriptor_status = ice_rx_descriptor_status, 138 .tx_descriptor_status = ice_tx_descriptor_status, 139 .stats_get = ice_stats_get, 140 .stats_reset = ice_stats_reset, 141 .xstats_get = ice_xstats_get, 142 .xstats_get_names = ice_xstats_get_names, 143 .xstats_reset = ice_stats_reset, 144 }; 145 146 /* store statistics names and its offset in stats structure */ 147 struct ice_xstats_name_off { 148 char name[RTE_ETH_XSTATS_NAME_SIZE]; 149 unsigned int offset; 150 }; 151 152 static const struct ice_xstats_name_off ice_stats_strings[] = { 153 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 154 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 155 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 156 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 157 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 158 rx_unknown_protocol)}, 159 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 160 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 161 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 162 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 163 }; 164 165 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 166 sizeof(ice_stats_strings[0])) 167 168 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 169 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 170 tx_dropped_link_down)}, 171 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 172 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 173 illegal_bytes)}, 174 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 175 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 176 mac_local_faults)}, 177 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 178 mac_remote_faults)}, 179 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 180 rx_len_errors)}, 181 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 182 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 183 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 184 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 185 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 186 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 187 rx_size_127)}, 188 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 189 rx_size_255)}, 190 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 191 rx_size_511)}, 192 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 193 rx_size_1023)}, 194 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 195 rx_size_1522)}, 196 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 197 rx_size_big)}, 198 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 199 rx_undersize)}, 200 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 201 rx_oversize)}, 202 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 203 mac_short_pkt_dropped)}, 204 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 205 rx_fragments)}, 206 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 207 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 208 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 209 tx_size_127)}, 210 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 211 tx_size_255)}, 212 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 213 tx_size_511)}, 214 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 215 tx_size_1023)}, 216 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 217 tx_size_1522)}, 218 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 219 tx_size_big)}, 220 }; 221 222 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 223 sizeof(ice_hw_port_strings[0])) 224 225 static void 226 ice_init_controlq_parameter(struct ice_hw *hw) 227 { 228 /* fields for adminq */ 229 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 230 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 231 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 232 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 233 234 /* fields for mailboxq, DPDK used as PF host */ 235 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 236 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 237 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 238 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 239 } 240 241 static int 242 ice_check_qp_num(const char *key, const char *qp_value, 243 __rte_unused void *opaque) 244 { 245 char *end = NULL; 246 int num = 0; 247 248 while (isblank(*qp_value)) 249 qp_value++; 250 251 num = strtoul(qp_value, &end, 10); 252 253 if (!num || (*end == '-') || errno) { 254 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 255 "value must be > 0", 256 qp_value, key); 257 return -1; 258 } 259 260 return num; 261 } 262 263 static int 264 ice_config_max_queue_pair_num(struct rte_devargs *devargs) 265 { 266 struct rte_kvargs *kvlist; 267 const char *queue_num_key = ICE_MAX_QP_NUM; 268 int ret; 269 270 if (!devargs) 271 return 0; 272 273 kvlist = rte_kvargs_parse(devargs->args, NULL); 274 if (!kvlist) 275 return 0; 276 277 if (!rte_kvargs_count(kvlist, queue_num_key)) { 278 rte_kvargs_free(kvlist); 279 return 0; 280 } 281 282 if (rte_kvargs_process(kvlist, queue_num_key, 283 ice_check_qp_num, NULL) < 0) { 284 rte_kvargs_free(kvlist); 285 return 0; 286 } 287 ret = rte_kvargs_process(kvlist, queue_num_key, 288 ice_check_qp_num, NULL); 289 rte_kvargs_free(kvlist); 290 291 return ret; 292 } 293 294 static int 295 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 296 uint32_t num) 297 { 298 struct pool_entry *entry; 299 300 if (!pool || !num) 301 return -EINVAL; 302 303 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 304 if (!entry) { 305 PMD_INIT_LOG(ERR, 306 "Failed to allocate memory for resource pool"); 307 return -ENOMEM; 308 } 309 310 /* queue heap initialize */ 311 pool->num_free = num; 312 pool->num_alloc = 0; 313 pool->base = base; 314 LIST_INIT(&pool->alloc_list); 315 LIST_INIT(&pool->free_list); 316 317 /* Initialize element */ 318 entry->base = 0; 319 entry->len = num; 320 321 LIST_INSERT_HEAD(&pool->free_list, entry, next); 322 return 0; 323 } 324 325 static int 326 ice_res_pool_alloc(struct ice_res_pool_info *pool, 327 uint16_t num) 328 { 329 struct pool_entry *entry, *valid_entry; 330 331 if (!pool || !num) { 332 PMD_INIT_LOG(ERR, "Invalid parameter"); 333 return -EINVAL; 334 } 335 336 if (pool->num_free < num) { 337 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 338 num, pool->num_free); 339 return -ENOMEM; 340 } 341 342 valid_entry = NULL; 343 /* Lookup in free list and find most fit one */ 344 LIST_FOREACH(entry, &pool->free_list, next) { 345 if (entry->len >= num) { 346 /* Find best one */ 347 if (entry->len == num) { 348 valid_entry = entry; 349 break; 350 } 351 if (!valid_entry || 352 valid_entry->len > entry->len) 353 valid_entry = entry; 354 } 355 } 356 357 /* Not find one to satisfy the request, return */ 358 if (!valid_entry) { 359 PMD_INIT_LOG(ERR, "No valid entry found"); 360 return -ENOMEM; 361 } 362 /** 363 * The entry have equal queue number as requested, 364 * remove it from alloc_list. 365 */ 366 if (valid_entry->len == num) { 367 LIST_REMOVE(valid_entry, next); 368 } else { 369 /** 370 * The entry have more numbers than requested, 371 * create a new entry for alloc_list and minus its 372 * queue base and number in free_list. 373 */ 374 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 375 if (!entry) { 376 PMD_INIT_LOG(ERR, 377 "Failed to allocate memory for " 378 "resource pool"); 379 return -ENOMEM; 380 } 381 entry->base = valid_entry->base; 382 entry->len = num; 383 valid_entry->base += num; 384 valid_entry->len -= num; 385 valid_entry = entry; 386 } 387 388 /* Insert it into alloc list, not sorted */ 389 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 390 391 pool->num_free -= valid_entry->len; 392 pool->num_alloc += valid_entry->len; 393 394 return valid_entry->base + pool->base; 395 } 396 397 static void 398 ice_res_pool_destroy(struct ice_res_pool_info *pool) 399 { 400 struct pool_entry *entry, *next_entry; 401 402 if (!pool) 403 return; 404 405 for (entry = LIST_FIRST(&pool->alloc_list); 406 entry && (next_entry = LIST_NEXT(entry, next), 1); 407 entry = next_entry) { 408 LIST_REMOVE(entry, next); 409 rte_free(entry); 410 } 411 412 for (entry = LIST_FIRST(&pool->free_list); 413 entry && (next_entry = LIST_NEXT(entry, next), 1); 414 entry = next_entry) { 415 LIST_REMOVE(entry, next); 416 rte_free(entry); 417 } 418 419 pool->num_free = 0; 420 pool->num_alloc = 0; 421 pool->base = 0; 422 LIST_INIT(&pool->alloc_list); 423 LIST_INIT(&pool->free_list); 424 } 425 426 static void 427 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 428 { 429 /* Set VSI LUT selection */ 430 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 431 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 432 /* Set Hash scheme */ 433 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 434 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 435 /* enable TC */ 436 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 437 } 438 439 static enum ice_status 440 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 441 struct ice_aqc_vsi_props *info, 442 uint8_t enabled_tcmap) 443 { 444 uint16_t bsf, qp_idx; 445 446 /* default tc 0 now. Multi-TC supporting need to be done later. 447 * Configure TC and queue mapping parameters, for enabled TC, 448 * allocate qpnum_per_tc queues to this traffic. 449 */ 450 if (enabled_tcmap != 0x01) { 451 PMD_INIT_LOG(ERR, "only TC0 is supported"); 452 return -ENOTSUP; 453 } 454 455 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 456 bsf = rte_bsf32(vsi->nb_qps); 457 /* Adjust the queue number to actual queues that can be applied */ 458 vsi->nb_qps = 0x1 << bsf; 459 460 qp_idx = 0; 461 /* Set tc and queue mapping with VSI */ 462 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 463 ICE_AQ_VSI_TC_Q_OFFSET_S) | 464 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 465 466 /* Associate queue number with VSI */ 467 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 468 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 469 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 470 info->valid_sections |= 471 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 472 /* Set the info.ingress_table and info.egress_table 473 * for UP translate table. Now just set it to 1:1 map by default 474 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 475 */ 476 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 477 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 478 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 479 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 480 return 0; 481 } 482 483 static int 484 ice_init_mac_address(struct rte_eth_dev *dev) 485 { 486 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 487 488 if (!rte_is_unicast_ether_addr 489 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 490 PMD_INIT_LOG(ERR, "Invalid MAC address"); 491 return -EINVAL; 492 } 493 494 rte_ether_addr_copy( 495 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 496 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 497 498 dev->data->mac_addrs = 499 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0); 500 if (!dev->data->mac_addrs) { 501 PMD_INIT_LOG(ERR, 502 "Failed to allocate memory to store mac address"); 503 return -ENOMEM; 504 } 505 /* store it to dev data */ 506 rte_ether_addr_copy( 507 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 508 &dev->data->mac_addrs[0]); 509 return 0; 510 } 511 512 /* Find out specific MAC filter */ 513 static struct ice_mac_filter * 514 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 515 { 516 struct ice_mac_filter *f; 517 518 TAILQ_FOREACH(f, &vsi->mac_list, next) { 519 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 520 return f; 521 } 522 523 return NULL; 524 } 525 526 static int 527 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 528 { 529 struct ice_fltr_list_entry *m_list_itr = NULL; 530 struct ice_mac_filter *f; 531 struct LIST_HEAD_TYPE list_head; 532 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 533 int ret = 0; 534 535 /* If it's added and configured, return */ 536 f = ice_find_mac_filter(vsi, mac_addr); 537 if (f) { 538 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 539 return 0; 540 } 541 542 INIT_LIST_HEAD(&list_head); 543 544 m_list_itr = (struct ice_fltr_list_entry *) 545 ice_malloc(hw, sizeof(*m_list_itr)); 546 if (!m_list_itr) { 547 ret = -ENOMEM; 548 goto DONE; 549 } 550 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 551 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 552 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 553 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 554 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 555 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 556 m_list_itr->fltr_info.vsi_handle = vsi->idx; 557 558 LIST_ADD(&m_list_itr->list_entry, &list_head); 559 560 /* Add the mac */ 561 ret = ice_add_mac(hw, &list_head); 562 if (ret != ICE_SUCCESS) { 563 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 564 ret = -EINVAL; 565 goto DONE; 566 } 567 /* Add the mac addr into mac list */ 568 f = rte_zmalloc(NULL, sizeof(*f), 0); 569 if (!f) { 570 PMD_DRV_LOG(ERR, "failed to allocate memory"); 571 ret = -ENOMEM; 572 goto DONE; 573 } 574 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN); 575 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 576 vsi->mac_num++; 577 578 ret = 0; 579 580 DONE: 581 rte_free(m_list_itr); 582 return ret; 583 } 584 585 static int 586 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 587 { 588 struct ice_fltr_list_entry *m_list_itr = NULL; 589 struct ice_mac_filter *f; 590 struct LIST_HEAD_TYPE list_head; 591 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 592 int ret = 0; 593 594 /* Can't find it, return an error */ 595 f = ice_find_mac_filter(vsi, mac_addr); 596 if (!f) 597 return -EINVAL; 598 599 INIT_LIST_HEAD(&list_head); 600 601 m_list_itr = (struct ice_fltr_list_entry *) 602 ice_malloc(hw, sizeof(*m_list_itr)); 603 if (!m_list_itr) { 604 ret = -ENOMEM; 605 goto DONE; 606 } 607 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 608 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 609 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 610 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 611 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 612 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 613 m_list_itr->fltr_info.vsi_handle = vsi->idx; 614 615 LIST_ADD(&m_list_itr->list_entry, &list_head); 616 617 /* remove the mac filter */ 618 ret = ice_remove_mac(hw, &list_head); 619 if (ret != ICE_SUCCESS) { 620 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 621 ret = -EINVAL; 622 goto DONE; 623 } 624 625 /* Remove the mac addr from mac list */ 626 TAILQ_REMOVE(&vsi->mac_list, f, next); 627 rte_free(f); 628 vsi->mac_num--; 629 630 ret = 0; 631 DONE: 632 rte_free(m_list_itr); 633 return ret; 634 } 635 636 /* Find out specific VLAN filter */ 637 static struct ice_vlan_filter * 638 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 639 { 640 struct ice_vlan_filter *f; 641 642 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 643 if (vlan_id == f->vlan_info.vlan_id) 644 return f; 645 } 646 647 return NULL; 648 } 649 650 static int 651 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 652 { 653 struct ice_fltr_list_entry *v_list_itr = NULL; 654 struct ice_vlan_filter *f; 655 struct LIST_HEAD_TYPE list_head; 656 struct ice_hw *hw; 657 int ret = 0; 658 659 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID) 660 return -EINVAL; 661 662 hw = ICE_VSI_TO_HW(vsi); 663 664 /* If it's added and configured, return. */ 665 f = ice_find_vlan_filter(vsi, vlan_id); 666 if (f) { 667 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 668 return 0; 669 } 670 671 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 672 return 0; 673 674 INIT_LIST_HEAD(&list_head); 675 676 v_list_itr = (struct ice_fltr_list_entry *) 677 ice_malloc(hw, sizeof(*v_list_itr)); 678 if (!v_list_itr) { 679 ret = -ENOMEM; 680 goto DONE; 681 } 682 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 683 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 684 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 685 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 686 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 687 v_list_itr->fltr_info.vsi_handle = vsi->idx; 688 689 LIST_ADD(&v_list_itr->list_entry, &list_head); 690 691 /* Add the vlan */ 692 ret = ice_add_vlan(hw, &list_head); 693 if (ret != ICE_SUCCESS) { 694 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 695 ret = -EINVAL; 696 goto DONE; 697 } 698 699 /* Add vlan into vlan list */ 700 f = rte_zmalloc(NULL, sizeof(*f), 0); 701 if (!f) { 702 PMD_DRV_LOG(ERR, "failed to allocate memory"); 703 ret = -ENOMEM; 704 goto DONE; 705 } 706 f->vlan_info.vlan_id = vlan_id; 707 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 708 vsi->vlan_num++; 709 710 ret = 0; 711 712 DONE: 713 rte_free(v_list_itr); 714 return ret; 715 } 716 717 static int 718 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 719 { 720 struct ice_fltr_list_entry *v_list_itr = NULL; 721 struct ice_vlan_filter *f; 722 struct LIST_HEAD_TYPE list_head; 723 struct ice_hw *hw; 724 int ret = 0; 725 726 /** 727 * Vlan 0 is the generic filter for untagged packets 728 * and can't be removed. 729 */ 730 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID) 731 return -EINVAL; 732 733 hw = ICE_VSI_TO_HW(vsi); 734 735 /* Can't find it, return an error */ 736 f = ice_find_vlan_filter(vsi, vlan_id); 737 if (!f) 738 return -EINVAL; 739 740 INIT_LIST_HEAD(&list_head); 741 742 v_list_itr = (struct ice_fltr_list_entry *) 743 ice_malloc(hw, sizeof(*v_list_itr)); 744 if (!v_list_itr) { 745 ret = -ENOMEM; 746 goto DONE; 747 } 748 749 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 750 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 751 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 752 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 753 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 754 v_list_itr->fltr_info.vsi_handle = vsi->idx; 755 756 LIST_ADD(&v_list_itr->list_entry, &list_head); 757 758 /* remove the vlan filter */ 759 ret = ice_remove_vlan(hw, &list_head); 760 if (ret != ICE_SUCCESS) { 761 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 762 ret = -EINVAL; 763 goto DONE; 764 } 765 766 /* Remove the vlan id from vlan list */ 767 TAILQ_REMOVE(&vsi->vlan_list, f, next); 768 rte_free(f); 769 vsi->vlan_num--; 770 771 ret = 0; 772 DONE: 773 rte_free(v_list_itr); 774 return ret; 775 } 776 777 static int 778 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 779 { 780 struct ice_mac_filter *m_f; 781 struct ice_vlan_filter *v_f; 782 int ret = 0; 783 784 if (!vsi || !vsi->mac_num) 785 return -EINVAL; 786 787 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 788 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 789 if (ret != ICE_SUCCESS) { 790 ret = -EINVAL; 791 goto DONE; 792 } 793 } 794 795 if (vsi->vlan_num == 0) 796 return 0; 797 798 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 799 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 800 if (ret != ICE_SUCCESS) { 801 ret = -EINVAL; 802 goto DONE; 803 } 804 } 805 806 DONE: 807 return ret; 808 } 809 810 static int 811 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 812 { 813 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 814 struct ice_vsi_ctx ctxt; 815 uint8_t qinq_flags; 816 int ret = 0; 817 818 /* Check if it has been already on or off */ 819 if (vsi->info.valid_sections & 820 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 821 if (on) { 822 if ((vsi->info.outer_tag_flags & 823 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == 824 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) 825 return 0; /* already on */ 826 } else { 827 if (!(vsi->info.outer_tag_flags & 828 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) 829 return 0; /* already off */ 830 } 831 } 832 833 if (on) 834 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; 835 else 836 qinq_flags = 0; 837 /* clear global insertion and use per packet insertion */ 838 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); 839 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); 840 vsi->info.outer_tag_flags |= qinq_flags; 841 /* use default vlan type 0x8100 */ 842 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 843 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 844 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 845 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 846 ctxt.info.valid_sections = 847 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 848 ctxt.vsi_num = vsi->vsi_id; 849 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 850 if (ret) { 851 PMD_DRV_LOG(INFO, 852 "Update VSI failed to %s qinq stripping", 853 on ? "enable" : "disable"); 854 return -EINVAL; 855 } 856 857 vsi->info.valid_sections |= 858 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 859 860 return ret; 861 } 862 863 static int 864 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 865 { 866 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 867 struct ice_vsi_ctx ctxt; 868 uint8_t qinq_flags; 869 int ret = 0; 870 871 /* Check if it has been already on or off */ 872 if (vsi->info.valid_sections & 873 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 874 if (on) { 875 if ((vsi->info.outer_tag_flags & 876 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 877 ICE_AQ_VSI_OUTER_TAG_COPY) 878 return 0; /* already on */ 879 } else { 880 if ((vsi->info.outer_tag_flags & 881 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 882 ICE_AQ_VSI_OUTER_TAG_NOTHING) 883 return 0; /* already off */ 884 } 885 } 886 887 if (on) 888 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; 889 else 890 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; 891 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); 892 vsi->info.outer_tag_flags |= qinq_flags; 893 /* use default vlan type 0x8100 */ 894 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 895 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 896 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 897 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 898 ctxt.info.valid_sections = 899 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 900 ctxt.vsi_num = vsi->vsi_id; 901 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 902 if (ret) { 903 PMD_DRV_LOG(INFO, 904 "Update VSI failed to %s qinq stripping", 905 on ? "enable" : "disable"); 906 return -EINVAL; 907 } 908 909 vsi->info.valid_sections |= 910 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 911 912 return ret; 913 } 914 915 static int 916 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 917 { 918 int ret; 919 920 ret = ice_vsi_config_qinq_stripping(vsi, on); 921 if (ret) 922 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 923 924 ret = ice_vsi_config_qinq_insertion(vsi, on); 925 if (ret) 926 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 927 928 return ret; 929 } 930 931 /* Enable IRQ0 */ 932 static void 933 ice_pf_enable_irq0(struct ice_hw *hw) 934 { 935 /* reset the registers */ 936 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 937 ICE_READ_REG(hw, PFINT_OICR); 938 939 #ifdef ICE_LSE_SPT 940 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 941 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 942 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 943 944 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 945 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 946 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 947 PFINT_OICR_CTL_ITR_INDX_M) | 948 PFINT_OICR_CTL_CAUSE_ENA_M); 949 950 ICE_WRITE_REG(hw, PFINT_FW_CTL, 951 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 952 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 953 PFINT_FW_CTL_ITR_INDX_M) | 954 PFINT_FW_CTL_CAUSE_ENA_M); 955 #else 956 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 957 #endif 958 959 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 960 GLINT_DYN_CTL_INTENA_M | 961 GLINT_DYN_CTL_CLEARPBA_M | 962 GLINT_DYN_CTL_ITR_INDX_M); 963 964 ice_flush(hw); 965 } 966 967 /* Disable IRQ0 */ 968 static void 969 ice_pf_disable_irq0(struct ice_hw *hw) 970 { 971 /* Disable all interrupt types */ 972 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 973 ice_flush(hw); 974 } 975 976 #ifdef ICE_LSE_SPT 977 static void 978 ice_handle_aq_msg(struct rte_eth_dev *dev) 979 { 980 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 981 struct ice_ctl_q_info *cq = &hw->adminq; 982 struct ice_rq_event_info event; 983 uint16_t pending, opcode; 984 int ret; 985 986 event.buf_len = ICE_AQ_MAX_BUF_LEN; 987 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 988 if (!event.msg_buf) { 989 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 990 return; 991 } 992 993 pending = 1; 994 while (pending) { 995 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 996 997 if (ret != ICE_SUCCESS) { 998 PMD_DRV_LOG(INFO, 999 "Failed to read msg from AdminQ, " 1000 "adminq_err: %u", 1001 hw->adminq.sq_last_status); 1002 break; 1003 } 1004 opcode = rte_le_to_cpu_16(event.desc.opcode); 1005 1006 switch (opcode) { 1007 case ice_aqc_opc_get_link_status: 1008 ret = ice_link_update(dev, 0); 1009 if (!ret) 1010 _rte_eth_dev_callback_process 1011 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1012 break; 1013 default: 1014 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1015 opcode); 1016 break; 1017 } 1018 } 1019 rte_free(event.msg_buf); 1020 } 1021 #endif 1022 1023 /** 1024 * Interrupt handler triggered by NIC for handling 1025 * specific interrupt. 1026 * 1027 * @param handle 1028 * Pointer to interrupt handle. 1029 * @param param 1030 * The address of parameter (struct rte_eth_dev *) regsitered before. 1031 * 1032 * @return 1033 * void 1034 */ 1035 static void 1036 ice_interrupt_handler(void *param) 1037 { 1038 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1039 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1040 uint32_t oicr; 1041 uint32_t reg; 1042 uint8_t pf_num; 1043 uint8_t event; 1044 uint16_t queue; 1045 #ifdef ICE_LSE_SPT 1046 uint32_t int_fw_ctl; 1047 #endif 1048 1049 /* Disable interrupt */ 1050 ice_pf_disable_irq0(hw); 1051 1052 /* read out interrupt causes */ 1053 oicr = ICE_READ_REG(hw, PFINT_OICR); 1054 #ifdef ICE_LSE_SPT 1055 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1056 #endif 1057 1058 /* No interrupt event indicated */ 1059 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1060 PMD_DRV_LOG(INFO, "No interrupt event"); 1061 goto done; 1062 } 1063 1064 #ifdef ICE_LSE_SPT 1065 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1066 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1067 ice_handle_aq_msg(dev); 1068 } 1069 #else 1070 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1071 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1072 ice_link_update(dev, 0); 1073 } 1074 #endif 1075 1076 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1077 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1078 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1079 if (reg & GL_MDET_TX_PQM_VALID_M) { 1080 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1081 GL_MDET_TX_PQM_PF_NUM_S; 1082 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1083 GL_MDET_TX_PQM_MAL_TYPE_S; 1084 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1085 GL_MDET_TX_PQM_QNUM_S; 1086 1087 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1088 "%d by PQM on TX queue %d PF# %d", 1089 event, queue, pf_num); 1090 } 1091 1092 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1093 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1094 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1095 GL_MDET_TX_TCLAN_PF_NUM_S; 1096 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1097 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1098 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1099 GL_MDET_TX_TCLAN_QNUM_S; 1100 1101 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1102 "%d by TCLAN on TX queue %d PF# %d", 1103 event, queue, pf_num); 1104 } 1105 } 1106 done: 1107 /* Enable interrupt */ 1108 ice_pf_enable_irq0(hw); 1109 rte_intr_enable(dev->intr_handle); 1110 } 1111 1112 /* Initialize SW parameters of PF */ 1113 static int 1114 ice_pf_sw_init(struct rte_eth_dev *dev) 1115 { 1116 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1117 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1118 1119 if (ice_config_max_queue_pair_num(dev->device->devargs) > 0) 1120 pf->lan_nb_qp_max = 1121 ice_config_max_queue_pair_num(dev->device->devargs); 1122 else 1123 pf->lan_nb_qp_max = 1124 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1125 hw->func_caps.common_cap.num_rxq); 1126 1127 pf->lan_nb_qps = pf->lan_nb_qp_max; 1128 1129 return 0; 1130 } 1131 1132 static struct ice_vsi * 1133 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1134 { 1135 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1136 struct ice_vsi *vsi = NULL; 1137 struct ice_vsi_ctx vsi_ctx; 1138 int ret; 1139 struct rte_ether_addr broadcast = { 1140 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1141 struct rte_ether_addr mac_addr; 1142 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1143 uint8_t tc_bitmap = 0x1; 1144 1145 /* hw->num_lports = 1 in NIC mode */ 1146 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1147 if (!vsi) 1148 return NULL; 1149 1150 vsi->idx = pf->next_vsi_idx; 1151 pf->next_vsi_idx++; 1152 vsi->type = type; 1153 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1154 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1155 vsi->vlan_anti_spoof_on = 0; 1156 vsi->vlan_filter_on = 1; 1157 TAILQ_INIT(&vsi->mac_list); 1158 TAILQ_INIT(&vsi->vlan_list); 1159 1160 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ 1161 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1162 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : 1163 hw->func_caps.common_cap.rss_table_size; 1164 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1165 1166 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1167 /* base_queue in used in queue mapping of VSI add/update command. 1168 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ 1169 * cases in the first stage. Only Main VSI. 1170 */ 1171 vsi->base_queue = 0; 1172 switch (type) { 1173 case ICE_VSI_PF: 1174 vsi->nb_qps = pf->lan_nb_qps; 1175 ice_vsi_config_default_rss(&vsi_ctx.info); 1176 vsi_ctx.alloc_from_pool = true; 1177 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1178 /* switch_id is queried by get_switch_config aq, which is done 1179 * by ice_init_hw 1180 */ 1181 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1182 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1183 /* Allow all untagged or tagged packets */ 1184 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; 1185 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; 1186 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1187 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1188 /* Enable VLAN/UP trip */ 1189 ret = ice_vsi_config_tc_queue_mapping(vsi, 1190 &vsi_ctx.info, 1191 ICE_DEFAULT_TCMAP); 1192 if (ret) { 1193 PMD_INIT_LOG(ERR, 1194 "tc queue mapping with vsi failed, " 1195 "err = %d", 1196 ret); 1197 goto fail_mem; 1198 } 1199 1200 break; 1201 default: 1202 /* for other types of VSI */ 1203 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1204 goto fail_mem; 1205 } 1206 1207 /* VF has MSIX interrupt in VF range, don't allocate here */ 1208 if (type == ICE_VSI_PF) { 1209 ret = ice_res_pool_alloc(&pf->msix_pool, 1210 RTE_MIN(vsi->nb_qps, 1211 RTE_MAX_RXTX_INTR_VEC_ID)); 1212 if (ret < 0) { 1213 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1214 vsi->vsi_id, ret); 1215 } 1216 vsi->msix_intr = ret; 1217 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1218 } else { 1219 vsi->msix_intr = 0; 1220 vsi->nb_msix = 0; 1221 } 1222 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1223 if (ret != ICE_SUCCESS) { 1224 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1225 goto fail_mem; 1226 } 1227 /* store vsi information is SW structure */ 1228 vsi->vsi_id = vsi_ctx.vsi_num; 1229 vsi->info = vsi_ctx.info; 1230 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1231 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1232 1233 /* MAC configuration */ 1234 rte_memcpy(pf->dev_addr.addr_bytes, 1235 hw->port_info->mac.perm_addr, 1236 ETH_ADDR_LEN); 1237 1238 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN); 1239 ret = ice_add_mac_filter(vsi, &mac_addr); 1240 if (ret != ICE_SUCCESS) 1241 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1242 1243 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN); 1244 ret = ice_add_mac_filter(vsi, &mac_addr); 1245 if (ret != ICE_SUCCESS) 1246 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1247 1248 /* At the beginning, only TC0. */ 1249 /* What we need here is the maximam number of the TX queues. 1250 * Currently vsi->nb_qps means it. 1251 * Correct it if any change. 1252 */ 1253 max_txqs[0] = vsi->nb_qps; 1254 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1255 tc_bitmap, max_txqs); 1256 if (ret != ICE_SUCCESS) 1257 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1258 1259 return vsi; 1260 fail_mem: 1261 rte_free(vsi); 1262 pf->next_vsi_idx--; 1263 return NULL; 1264 } 1265 1266 static int 1267 ice_send_driver_ver(struct ice_hw *hw) 1268 { 1269 struct ice_driver_ver dv; 1270 1271 /* we don't have driver version use 0 for dummy */ 1272 dv.major_ver = 0; 1273 dv.minor_ver = 0; 1274 dv.build_ver = 0; 1275 dv.subbuild_ver = 0; 1276 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1277 1278 return ice_aq_send_driver_ver(hw, &dv, NULL); 1279 } 1280 1281 static int 1282 ice_pf_setup(struct ice_pf *pf) 1283 { 1284 struct ice_vsi *vsi; 1285 1286 /* Clear all stats counters */ 1287 pf->offset_loaded = FALSE; 1288 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1289 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1290 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1291 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1292 1293 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1294 if (!vsi) { 1295 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1296 return -EINVAL; 1297 } 1298 1299 pf->main_vsi = vsi; 1300 1301 return 0; 1302 } 1303 1304 static int ice_load_pkg(struct rte_eth_dev *dev) 1305 { 1306 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1307 const char *pkg_file = ICE_DFLT_PKG_FILE; 1308 int err; 1309 uint8_t *buf; 1310 int buf_len; 1311 FILE *file; 1312 struct stat fstat; 1313 1314 file = fopen(pkg_file, "rb"); 1315 if (!file) { 1316 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); 1317 return -1; 1318 } 1319 1320 err = stat(pkg_file, &fstat); 1321 if (err) { 1322 PMD_INIT_LOG(ERR, "failed to get file stats\n"); 1323 fclose(file); 1324 return err; 1325 } 1326 1327 buf_len = fstat.st_size; 1328 buf = rte_malloc(NULL, buf_len, 0); 1329 1330 if (!buf) { 1331 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", 1332 buf_len); 1333 fclose(file); 1334 return -1; 1335 } 1336 1337 err = fread(buf, buf_len, 1, file); 1338 if (err != 1) { 1339 PMD_INIT_LOG(ERR, "failed to read package data\n"); 1340 fclose(file); 1341 err = -1; 1342 goto fail_exit; 1343 } 1344 1345 fclose(file); 1346 1347 err = ice_copy_and_init_pkg(hw, buf, buf_len); 1348 if (err) { 1349 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1350 goto fail_exit; 1351 } 1352 err = ice_init_hw_tbls(hw); 1353 if (err) { 1354 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); 1355 goto fail_init_tbls; 1356 } 1357 1358 return 0; 1359 1360 fail_init_tbls: 1361 rte_free(hw->pkg_copy); 1362 fail_exit: 1363 rte_free(buf); 1364 return err; 1365 } 1366 1367 static int 1368 ice_dev_init(struct rte_eth_dev *dev) 1369 { 1370 struct rte_pci_device *pci_dev; 1371 struct rte_intr_handle *intr_handle; 1372 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1373 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1374 struct ice_adapter *ad = 1375 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1376 struct ice_vsi *vsi; 1377 int ret; 1378 1379 dev->dev_ops = &ice_eth_dev_ops; 1380 dev->rx_pkt_burst = ice_recv_pkts; 1381 dev->tx_pkt_burst = ice_xmit_pkts; 1382 dev->tx_pkt_prepare = ice_prep_pkts; 1383 1384 ice_set_default_ptype_table(dev); 1385 pci_dev = RTE_DEV_TO_PCI(dev->device); 1386 intr_handle = &pci_dev->intr_handle; 1387 1388 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1389 pf->adapter->eth_dev = dev; 1390 pf->dev_data = dev->data; 1391 hw->back = pf->adapter; 1392 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 1393 hw->vendor_id = pci_dev->id.vendor_id; 1394 hw->device_id = pci_dev->id.device_id; 1395 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1396 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1397 hw->bus.device = pci_dev->addr.devid; 1398 hw->bus.func = pci_dev->addr.function; 1399 1400 ice_init_controlq_parameter(hw); 1401 1402 ret = ice_init_hw(hw); 1403 if (ret) { 1404 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 1405 return -EINVAL; 1406 } 1407 1408 ret = ice_load_pkg(dev); 1409 if (ret) { 1410 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 1411 "Entering Safe Mode"); 1412 ad->is_safe_mode = 1; 1413 } 1414 1415 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 1416 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 1417 hw->api_maj_ver, hw->api_min_ver); 1418 1419 ice_pf_sw_init(dev); 1420 ret = ice_init_mac_address(dev); 1421 if (ret) { 1422 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 1423 goto err_init_mac; 1424 } 1425 1426 ret = ice_res_pool_init(&pf->msix_pool, 1, 1427 hw->func_caps.common_cap.num_msix_vectors - 1); 1428 if (ret) { 1429 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 1430 goto err_msix_pool_init; 1431 } 1432 1433 ret = ice_pf_setup(pf); 1434 if (ret) { 1435 PMD_INIT_LOG(ERR, "Failed to setup PF"); 1436 goto err_pf_setup; 1437 } 1438 1439 ret = ice_send_driver_ver(hw); 1440 if (ret) { 1441 PMD_INIT_LOG(ERR, "Failed to send driver version"); 1442 goto err_pf_setup; 1443 } 1444 1445 vsi = pf->main_vsi; 1446 1447 /* Disable double vlan by default */ 1448 ice_vsi_config_double_vlan(vsi, FALSE); 1449 1450 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL); 1451 if (ret != ICE_SUCCESS) 1452 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 1453 1454 /* register callback func to eal lib */ 1455 rte_intr_callback_register(intr_handle, 1456 ice_interrupt_handler, dev); 1457 1458 ice_pf_enable_irq0(hw); 1459 1460 /* enable uio intr after callback register */ 1461 rte_intr_enable(intr_handle); 1462 1463 return 0; 1464 1465 err_pf_setup: 1466 ice_res_pool_destroy(&pf->msix_pool); 1467 err_msix_pool_init: 1468 rte_free(dev->data->mac_addrs); 1469 dev->data->mac_addrs = NULL; 1470 err_init_mac: 1471 ice_sched_cleanup_all(hw); 1472 rte_free(hw->port_info); 1473 ice_shutdown_all_ctrlq(hw); 1474 1475 return ret; 1476 } 1477 1478 static int 1479 ice_release_vsi(struct ice_vsi *vsi) 1480 { 1481 struct ice_hw *hw; 1482 struct ice_vsi_ctx vsi_ctx; 1483 enum ice_status ret; 1484 1485 if (!vsi) 1486 return 0; 1487 1488 hw = ICE_VSI_TO_HW(vsi); 1489 1490 ice_remove_all_mac_vlan_filters(vsi); 1491 1492 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1493 1494 vsi_ctx.vsi_num = vsi->vsi_id; 1495 vsi_ctx.info = vsi->info; 1496 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 1497 if (ret != ICE_SUCCESS) { 1498 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 1499 rte_free(vsi); 1500 return -1; 1501 } 1502 1503 rte_free(vsi); 1504 return 0; 1505 } 1506 1507 static void 1508 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 1509 { 1510 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1511 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1512 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1513 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1514 uint16_t msix_intr, i; 1515 1516 /* disable interrupt and also clear all the exist config */ 1517 for (i = 0; i < vsi->nb_qps; i++) { 1518 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 1519 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 1520 rte_wmb(); 1521 } 1522 1523 if (rte_intr_allow_others(intr_handle)) 1524 /* vfio-pci */ 1525 for (i = 0; i < vsi->nb_msix; i++) { 1526 msix_intr = vsi->msix_intr + i; 1527 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 1528 GLINT_DYN_CTL_WB_ON_ITR_M); 1529 } 1530 else 1531 /* igb_uio */ 1532 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1533 } 1534 1535 static void 1536 ice_dev_stop(struct rte_eth_dev *dev) 1537 { 1538 struct rte_eth_dev_data *data = dev->data; 1539 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1540 struct ice_vsi *main_vsi = pf->main_vsi; 1541 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1542 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1543 uint16_t i; 1544 1545 /* avoid stopping again */ 1546 if (pf->adapter_stopped) 1547 return; 1548 1549 /* stop and clear all Rx queues */ 1550 for (i = 0; i < data->nb_rx_queues; i++) 1551 ice_rx_queue_stop(dev, i); 1552 1553 /* stop and clear all Tx queues */ 1554 for (i = 0; i < data->nb_tx_queues; i++) 1555 ice_tx_queue_stop(dev, i); 1556 1557 /* disable all queue interrupts */ 1558 ice_vsi_disable_queues_intr(main_vsi); 1559 1560 /* Clear all queues and release mbufs */ 1561 ice_clear_queues(dev); 1562 1563 ice_dev_set_link_down(dev); 1564 1565 /* Clean datapath event and queue/vec mapping */ 1566 rte_intr_efd_disable(intr_handle); 1567 if (intr_handle->intr_vec) { 1568 rte_free(intr_handle->intr_vec); 1569 intr_handle->intr_vec = NULL; 1570 } 1571 1572 pf->adapter_stopped = true; 1573 } 1574 1575 static void 1576 ice_dev_close(struct rte_eth_dev *dev) 1577 { 1578 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1579 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1580 1581 /* Since stop will make link down, then the link event will be 1582 * triggered, disable the irq firstly to avoid the port_infoe etc 1583 * resources deallocation causing the interrupt service thread 1584 * crash. 1585 */ 1586 ice_pf_disable_irq0(hw); 1587 1588 ice_dev_stop(dev); 1589 1590 /* release all queue resource */ 1591 ice_free_queues(dev); 1592 1593 ice_res_pool_destroy(&pf->msix_pool); 1594 ice_release_vsi(pf->main_vsi); 1595 ice_sched_cleanup_all(hw); 1596 rte_free(hw->port_info); 1597 hw->port_info = NULL; 1598 ice_shutdown_all_ctrlq(hw); 1599 } 1600 1601 static int 1602 ice_dev_uninit(struct rte_eth_dev *dev) 1603 { 1604 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1605 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1606 1607 ice_dev_close(dev); 1608 1609 dev->dev_ops = NULL; 1610 dev->rx_pkt_burst = NULL; 1611 dev->tx_pkt_burst = NULL; 1612 1613 rte_free(dev->data->mac_addrs); 1614 dev->data->mac_addrs = NULL; 1615 1616 /* disable uio intr before callback unregister */ 1617 rte_intr_disable(intr_handle); 1618 1619 /* unregister callback func from eal lib */ 1620 rte_intr_callback_unregister(intr_handle, 1621 ice_interrupt_handler, dev); 1622 1623 return 0; 1624 } 1625 1626 static int 1627 ice_dev_configure(__rte_unused struct rte_eth_dev *dev) 1628 { 1629 struct ice_adapter *ad = 1630 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1631 1632 /* Initialize to TRUE. If any of Rx queues doesn't meet the 1633 * bulk allocation or vector Rx preconditions we will reset it. 1634 */ 1635 ad->rx_bulk_alloc_allowed = true; 1636 ad->tx_simple_allowed = true; 1637 1638 return 0; 1639 } 1640 1641 static int ice_init_rss(struct ice_pf *pf) 1642 { 1643 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1644 struct ice_vsi *vsi = pf->main_vsi; 1645 struct rte_eth_dev *dev = pf->adapter->eth_dev; 1646 struct rte_eth_rss_conf *rss_conf; 1647 struct ice_aqc_get_set_rss_keys key; 1648 uint16_t i, nb_q; 1649 int ret = 0; 1650 bool is_safe_mode = pf->adapter->is_safe_mode; 1651 1652 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 1653 nb_q = dev->data->nb_rx_queues; 1654 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 1655 vsi->rss_lut_size = pf->hash_lut_size; 1656 1657 if (is_safe_mode) { 1658 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 1659 return 0; 1660 } 1661 1662 if (!vsi->rss_key) 1663 vsi->rss_key = rte_zmalloc(NULL, 1664 vsi->rss_key_size, 0); 1665 if (!vsi->rss_lut) 1666 vsi->rss_lut = rte_zmalloc(NULL, 1667 vsi->rss_lut_size, 0); 1668 1669 /* configure RSS key */ 1670 if (!rss_conf->rss_key) { 1671 /* Calculate the default hash key */ 1672 for (i = 0; i <= vsi->rss_key_size; i++) 1673 vsi->rss_key[i] = (uint8_t)rte_rand(); 1674 } else { 1675 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 1676 RTE_MIN(rss_conf->rss_key_len, 1677 vsi->rss_key_size)); 1678 } 1679 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 1680 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 1681 if (ret) 1682 return -EINVAL; 1683 1684 /* init RSS LUT table */ 1685 for (i = 0; i < vsi->rss_lut_size; i++) 1686 vsi->rss_lut[i] = i % nb_q; 1687 1688 ret = ice_aq_set_rss_lut(hw, vsi->idx, 1689 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, 1690 vsi->rss_lut, vsi->rss_lut_size); 1691 if (ret) 1692 return -EINVAL; 1693 1694 /* configure RSS for IPv4 with input set IPv4 src/dst */ 1695 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 1696 ICE_FLOW_SEG_HDR_IPV4); 1697 if (ret) 1698 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret); 1699 1700 /* configure RSS for IPv6 with input set IPv6 src/dst */ 1701 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 1702 ICE_FLOW_SEG_HDR_IPV6); 1703 if (ret) 1704 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret); 1705 1706 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */ 1707 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6, 1708 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6); 1709 if (ret) 1710 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret); 1711 1712 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */ 1713 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6, 1714 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6); 1715 if (ret) 1716 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret); 1717 1718 /* configure RSS for sctp6 with input set IPv6 src/dst */ 1719 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 1720 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6); 1721 if (ret) 1722 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 1723 __func__, ret); 1724 1725 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */ 1726 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4, 1727 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4); 1728 if (ret) 1729 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret); 1730 1731 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */ 1732 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4, 1733 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4); 1734 if (ret) 1735 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret); 1736 1737 /* configure RSS for sctp4 with input set IP src/dst */ 1738 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 1739 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4); 1740 if (ret) 1741 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 1742 __func__, ret); 1743 1744 return 0; 1745 } 1746 1747 static void 1748 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 1749 int base_queue, int nb_queue) 1750 { 1751 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1752 uint32_t val, val_tx; 1753 int i; 1754 1755 for (i = 0; i < nb_queue; i++) { 1756 /*do actual bind*/ 1757 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 1758 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 1759 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 1760 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 1761 1762 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 1763 base_queue + i, msix_vect); 1764 /* set ITR0 value */ 1765 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); 1766 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 1767 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 1768 } 1769 } 1770 1771 static void 1772 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 1773 { 1774 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1775 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1776 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1777 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1778 uint16_t msix_vect = vsi->msix_intr; 1779 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 1780 uint16_t queue_idx = 0; 1781 int record = 0; 1782 int i; 1783 1784 /* clear Rx/Tx queue interrupt */ 1785 for (i = 0; i < vsi->nb_used_qps; i++) { 1786 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 1787 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 1788 } 1789 1790 /* PF bind interrupt */ 1791 if (rte_intr_dp_is_en(intr_handle)) { 1792 queue_idx = 0; 1793 record = 1; 1794 } 1795 1796 for (i = 0; i < vsi->nb_used_qps; i++) { 1797 if (nb_msix <= 1) { 1798 if (!rte_intr_allow_others(intr_handle)) 1799 msix_vect = ICE_MISC_VEC_ID; 1800 1801 /* uio mapping all queue to one msix_vect */ 1802 __vsi_queues_bind_intr(vsi, msix_vect, 1803 vsi->base_queue + i, 1804 vsi->nb_used_qps - i); 1805 1806 for (; !!record && i < vsi->nb_used_qps; i++) 1807 intr_handle->intr_vec[queue_idx + i] = 1808 msix_vect; 1809 break; 1810 } 1811 1812 /* vfio 1:1 queue/msix_vect mapping */ 1813 __vsi_queues_bind_intr(vsi, msix_vect, 1814 vsi->base_queue + i, 1); 1815 1816 if (!!record) 1817 intr_handle->intr_vec[queue_idx + i] = msix_vect; 1818 1819 msix_vect++; 1820 nb_msix--; 1821 } 1822 } 1823 1824 static void 1825 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 1826 { 1827 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1828 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1829 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1830 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1831 uint16_t msix_intr, i; 1832 1833 if (rte_intr_allow_others(intr_handle)) 1834 for (i = 0; i < vsi->nb_used_qps; i++) { 1835 msix_intr = vsi->msix_intr + i; 1836 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 1837 GLINT_DYN_CTL_INTENA_M | 1838 GLINT_DYN_CTL_CLEARPBA_M | 1839 GLINT_DYN_CTL_ITR_INDX_M | 1840 GLINT_DYN_CTL_WB_ON_ITR_M); 1841 } 1842 else 1843 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1844 GLINT_DYN_CTL_INTENA_M | 1845 GLINT_DYN_CTL_CLEARPBA_M | 1846 GLINT_DYN_CTL_ITR_INDX_M | 1847 GLINT_DYN_CTL_WB_ON_ITR_M); 1848 } 1849 1850 static int 1851 ice_rxq_intr_setup(struct rte_eth_dev *dev) 1852 { 1853 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1854 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1855 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1856 struct ice_vsi *vsi = pf->main_vsi; 1857 uint32_t intr_vector = 0; 1858 1859 rte_intr_disable(intr_handle); 1860 1861 /* check and configure queue intr-vector mapping */ 1862 if ((rte_intr_cap_multiple(intr_handle) || 1863 !RTE_ETH_DEV_SRIOV(dev).active) && 1864 dev->data->dev_conf.intr_conf.rxq != 0) { 1865 intr_vector = dev->data->nb_rx_queues; 1866 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 1867 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 1868 ICE_MAX_INTR_QUEUE_NUM); 1869 return -ENOTSUP; 1870 } 1871 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1872 return -1; 1873 } 1874 1875 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1876 intr_handle->intr_vec = 1877 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 1878 0); 1879 if (!intr_handle->intr_vec) { 1880 PMD_DRV_LOG(ERR, 1881 "Failed to allocate %d rx_queues intr_vec", 1882 dev->data->nb_rx_queues); 1883 return -ENOMEM; 1884 } 1885 } 1886 1887 /* Map queues with MSIX interrupt */ 1888 vsi->nb_used_qps = dev->data->nb_rx_queues; 1889 ice_vsi_queues_bind_intr(vsi); 1890 1891 /* Enable interrupts for all the queues */ 1892 ice_vsi_enable_queues_intr(vsi); 1893 1894 rte_intr_enable(intr_handle); 1895 1896 return 0; 1897 } 1898 1899 static int 1900 ice_dev_start(struct rte_eth_dev *dev) 1901 { 1902 struct rte_eth_dev_data *data = dev->data; 1903 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1904 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1905 struct ice_vsi *vsi = pf->main_vsi; 1906 uint16_t nb_rxq = 0; 1907 uint16_t nb_txq, i; 1908 int mask, ret; 1909 1910 /* program Tx queues' context in hardware */ 1911 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 1912 ret = ice_tx_queue_start(dev, nb_txq); 1913 if (ret) { 1914 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 1915 goto tx_err; 1916 } 1917 } 1918 1919 /* program Rx queues' context in hardware*/ 1920 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 1921 ret = ice_rx_queue_start(dev, nb_rxq); 1922 if (ret) { 1923 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 1924 goto rx_err; 1925 } 1926 } 1927 1928 ret = ice_init_rss(pf); 1929 if (ret) { 1930 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 1931 goto rx_err; 1932 } 1933 1934 ice_set_rx_function(dev); 1935 ice_set_tx_function(dev); 1936 1937 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 1938 ETH_VLAN_EXTEND_MASK; 1939 ret = ice_vlan_offload_set(dev, mask); 1940 if (ret) { 1941 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 1942 goto rx_err; 1943 } 1944 1945 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 1946 if (ice_rxq_intr_setup(dev)) 1947 return -EIO; 1948 1949 /* Enable receiving broadcast packets and transmitting packets */ 1950 ret = ice_set_vsi_promisc(hw, vsi->idx, 1951 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 1952 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 1953 0); 1954 if (ret != ICE_SUCCESS) 1955 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 1956 1957 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 1958 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 1959 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 1960 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 1961 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 1962 ICE_AQ_LINK_EVENT_AN_COMPLETED | 1963 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 1964 NULL); 1965 if (ret != ICE_SUCCESS) 1966 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 1967 1968 ice_dev_set_link_up(dev); 1969 1970 /* Call get_link_info aq commond to enable/disable LSE */ 1971 ice_link_update(dev, 0); 1972 1973 pf->adapter_stopped = false; 1974 1975 return 0; 1976 1977 /* stop the started queues if failed to start all queues */ 1978 rx_err: 1979 for (i = 0; i < nb_rxq; i++) 1980 ice_rx_queue_stop(dev, i); 1981 tx_err: 1982 for (i = 0; i < nb_txq; i++) 1983 ice_tx_queue_stop(dev, i); 1984 1985 return -EIO; 1986 } 1987 1988 static int 1989 ice_dev_reset(struct rte_eth_dev *dev) 1990 { 1991 int ret; 1992 1993 if (dev->data->sriov.active) 1994 return -ENOTSUP; 1995 1996 ret = ice_dev_uninit(dev); 1997 if (ret) { 1998 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 1999 return -ENXIO; 2000 } 2001 2002 ret = ice_dev_init(dev); 2003 if (ret) { 2004 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 2005 return -ENXIO; 2006 } 2007 2008 return 0; 2009 } 2010 2011 static void 2012 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2013 { 2014 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2015 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2016 struct ice_vsi *vsi = pf->main_vsi; 2017 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 2018 bool is_safe_mode = pf->adapter->is_safe_mode; 2019 u64 phy_type_low; 2020 u64 phy_type_high; 2021 2022 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 2023 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 2024 dev_info->max_rx_queues = vsi->nb_qps; 2025 dev_info->max_tx_queues = vsi->nb_qps; 2026 dev_info->max_mac_addrs = vsi->max_macaddrs; 2027 dev_info->max_vfs = pci_dev->max_vfs; 2028 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 2029 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 2030 2031 dev_info->rx_offload_capa = 2032 DEV_RX_OFFLOAD_VLAN_STRIP | 2033 DEV_RX_OFFLOAD_JUMBO_FRAME | 2034 DEV_RX_OFFLOAD_KEEP_CRC | 2035 DEV_RX_OFFLOAD_SCATTER | 2036 DEV_RX_OFFLOAD_VLAN_FILTER; 2037 dev_info->tx_offload_capa = 2038 DEV_TX_OFFLOAD_VLAN_INSERT | 2039 DEV_TX_OFFLOAD_TCP_TSO | 2040 DEV_TX_OFFLOAD_MULTI_SEGS | 2041 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 2042 dev_info->flow_type_rss_offloads = 0; 2043 2044 if (!is_safe_mode) { 2045 dev_info->rx_offload_capa |= 2046 DEV_RX_OFFLOAD_IPV4_CKSUM | 2047 DEV_RX_OFFLOAD_UDP_CKSUM | 2048 DEV_RX_OFFLOAD_TCP_CKSUM | 2049 DEV_RX_OFFLOAD_QINQ_STRIP | 2050 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2051 DEV_RX_OFFLOAD_VLAN_EXTEND; 2052 dev_info->tx_offload_capa |= 2053 DEV_TX_OFFLOAD_QINQ_INSERT | 2054 DEV_TX_OFFLOAD_IPV4_CKSUM | 2055 DEV_TX_OFFLOAD_UDP_CKSUM | 2056 DEV_TX_OFFLOAD_TCP_CKSUM | 2057 DEV_TX_OFFLOAD_SCTP_CKSUM | 2058 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2059 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 2060 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 2061 } 2062 2063 dev_info->rx_queue_offload_capa = 0; 2064 dev_info->tx_queue_offload_capa = 0; 2065 2066 dev_info->reta_size = pf->hash_lut_size; 2067 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2068 2069 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2070 .rx_thresh = { 2071 .pthresh = ICE_DEFAULT_RX_PTHRESH, 2072 .hthresh = ICE_DEFAULT_RX_HTHRESH, 2073 .wthresh = ICE_DEFAULT_RX_WTHRESH, 2074 }, 2075 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 2076 .rx_drop_en = 0, 2077 .offloads = 0, 2078 }; 2079 2080 dev_info->default_txconf = (struct rte_eth_txconf) { 2081 .tx_thresh = { 2082 .pthresh = ICE_DEFAULT_TX_PTHRESH, 2083 .hthresh = ICE_DEFAULT_TX_HTHRESH, 2084 .wthresh = ICE_DEFAULT_TX_WTHRESH, 2085 }, 2086 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 2087 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 2088 .offloads = 0, 2089 }; 2090 2091 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 2092 .nb_max = ICE_MAX_RING_DESC, 2093 .nb_min = ICE_MIN_RING_DESC, 2094 .nb_align = ICE_ALIGN_RING_DESC, 2095 }; 2096 2097 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 2098 .nb_max = ICE_MAX_RING_DESC, 2099 .nb_min = ICE_MIN_RING_DESC, 2100 .nb_align = ICE_ALIGN_RING_DESC, 2101 }; 2102 2103 dev_info->speed_capa = ETH_LINK_SPEED_10M | 2104 ETH_LINK_SPEED_100M | 2105 ETH_LINK_SPEED_1G | 2106 ETH_LINK_SPEED_2_5G | 2107 ETH_LINK_SPEED_5G | 2108 ETH_LINK_SPEED_10G | 2109 ETH_LINK_SPEED_20G | 2110 ETH_LINK_SPEED_25G; 2111 2112 phy_type_low = hw->port_info->phy.phy_type_low; 2113 phy_type_high = hw->port_info->phy.phy_type_high; 2114 2115 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 2116 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 2117 2118 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 2119 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 2120 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 2121 2122 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 2123 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 2124 2125 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 2126 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 2127 dev_info->default_rxportconf.nb_queues = 1; 2128 dev_info->default_txportconf.nb_queues = 1; 2129 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 2130 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 2131 } 2132 2133 static inline int 2134 ice_atomic_read_link_status(struct rte_eth_dev *dev, 2135 struct rte_eth_link *link) 2136 { 2137 struct rte_eth_link *dst = link; 2138 struct rte_eth_link *src = &dev->data->dev_link; 2139 2140 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 2141 *(uint64_t *)src) == 0) 2142 return -1; 2143 2144 return 0; 2145 } 2146 2147 static inline int 2148 ice_atomic_write_link_status(struct rte_eth_dev *dev, 2149 struct rte_eth_link *link) 2150 { 2151 struct rte_eth_link *dst = &dev->data->dev_link; 2152 struct rte_eth_link *src = link; 2153 2154 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 2155 *(uint64_t *)src) == 0) 2156 return -1; 2157 2158 return 0; 2159 } 2160 2161 static int 2162 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2163 { 2164 #define CHECK_INTERVAL 100 /* 100ms */ 2165 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 2166 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2167 struct ice_link_status link_status; 2168 struct rte_eth_link link, old; 2169 int status; 2170 unsigned int rep_cnt = MAX_REPEAT_TIME; 2171 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2172 2173 memset(&link, 0, sizeof(link)); 2174 memset(&old, 0, sizeof(old)); 2175 memset(&link_status, 0, sizeof(link_status)); 2176 ice_atomic_read_link_status(dev, &old); 2177 2178 do { 2179 /* Get link status information from hardware */ 2180 status = ice_aq_get_link_info(hw->port_info, enable_lse, 2181 &link_status, NULL); 2182 if (status != ICE_SUCCESS) { 2183 link.link_speed = ETH_SPEED_NUM_100M; 2184 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2185 PMD_DRV_LOG(ERR, "Failed to get link info"); 2186 goto out; 2187 } 2188 2189 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 2190 if (!wait_to_complete || link.link_status) 2191 break; 2192 2193 rte_delay_ms(CHECK_INTERVAL); 2194 } while (--rep_cnt); 2195 2196 if (!link.link_status) 2197 goto out; 2198 2199 /* Full-duplex operation at all supported speeds */ 2200 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2201 2202 /* Parse the link status */ 2203 switch (link_status.link_speed) { 2204 case ICE_AQ_LINK_SPEED_10MB: 2205 link.link_speed = ETH_SPEED_NUM_10M; 2206 break; 2207 case ICE_AQ_LINK_SPEED_100MB: 2208 link.link_speed = ETH_SPEED_NUM_100M; 2209 break; 2210 case ICE_AQ_LINK_SPEED_1000MB: 2211 link.link_speed = ETH_SPEED_NUM_1G; 2212 break; 2213 case ICE_AQ_LINK_SPEED_2500MB: 2214 link.link_speed = ETH_SPEED_NUM_2_5G; 2215 break; 2216 case ICE_AQ_LINK_SPEED_5GB: 2217 link.link_speed = ETH_SPEED_NUM_5G; 2218 break; 2219 case ICE_AQ_LINK_SPEED_10GB: 2220 link.link_speed = ETH_SPEED_NUM_10G; 2221 break; 2222 case ICE_AQ_LINK_SPEED_20GB: 2223 link.link_speed = ETH_SPEED_NUM_20G; 2224 break; 2225 case ICE_AQ_LINK_SPEED_25GB: 2226 link.link_speed = ETH_SPEED_NUM_25G; 2227 break; 2228 case ICE_AQ_LINK_SPEED_40GB: 2229 link.link_speed = ETH_SPEED_NUM_40G; 2230 break; 2231 case ICE_AQ_LINK_SPEED_50GB: 2232 link.link_speed = ETH_SPEED_NUM_50G; 2233 break; 2234 case ICE_AQ_LINK_SPEED_100GB: 2235 link.link_speed = ETH_SPEED_NUM_100G; 2236 break; 2237 case ICE_AQ_LINK_SPEED_UNKNOWN: 2238 default: 2239 PMD_DRV_LOG(ERR, "Unknown link speed"); 2240 link.link_speed = ETH_SPEED_NUM_NONE; 2241 break; 2242 } 2243 2244 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2245 ETH_LINK_SPEED_FIXED); 2246 2247 out: 2248 ice_atomic_write_link_status(dev, &link); 2249 if (link.link_status == old.link_status) 2250 return -1; 2251 2252 return 0; 2253 } 2254 2255 /* Force the physical link state by getting the current PHY capabilities from 2256 * hardware and setting the PHY config based on the determined capabilities. If 2257 * link changes, link event will be triggered because both the Enable Automatic 2258 * Link Update and LESM Enable bits are set when setting the PHY capabilities. 2259 */ 2260 static enum ice_status 2261 ice_force_phys_link_state(struct ice_hw *hw, bool link_up) 2262 { 2263 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2264 struct ice_aqc_get_phy_caps_data *pcaps; 2265 struct ice_port_info *pi; 2266 enum ice_status status; 2267 2268 if (!hw || !hw->port_info) 2269 return ICE_ERR_PARAM; 2270 2271 pi = hw->port_info; 2272 2273 pcaps = (struct ice_aqc_get_phy_caps_data *) 2274 ice_malloc(hw, sizeof(*pcaps)); 2275 if (!pcaps) 2276 return ICE_ERR_NO_MEMORY; 2277 2278 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2279 NULL); 2280 if (status) 2281 goto out; 2282 2283 /* No change in link */ 2284 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) && 2285 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) 2286 goto out; 2287 2288 cfg.phy_type_low = pcaps->phy_type_low; 2289 cfg.phy_type_high = pcaps->phy_type_high; 2290 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2291 cfg.low_power_ctrl = pcaps->low_power_ctrl; 2292 cfg.eee_cap = pcaps->eee_cap; 2293 cfg.eeer_value = pcaps->eeer_value; 2294 cfg.link_fec_opt = pcaps->link_fec_options; 2295 if (link_up) 2296 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 2297 else 2298 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 2299 2300 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2301 2302 out: 2303 ice_free(hw, pcaps); 2304 return status; 2305 } 2306 2307 static int 2308 ice_dev_set_link_up(struct rte_eth_dev *dev) 2309 { 2310 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2311 2312 return ice_force_phys_link_state(hw, true); 2313 } 2314 2315 static int 2316 ice_dev_set_link_down(struct rte_eth_dev *dev) 2317 { 2318 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2319 2320 return ice_force_phys_link_state(hw, false); 2321 } 2322 2323 static int 2324 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2325 { 2326 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2327 struct rte_eth_dev_data *dev_data = pf->dev_data; 2328 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 2329 2330 /* check if mtu is within the allowed range */ 2331 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 2332 return -EINVAL; 2333 2334 /* mtu setting is forbidden if port is start */ 2335 if (dev_data->dev_started) { 2336 PMD_DRV_LOG(ERR, 2337 "port %d must be stopped before configuration", 2338 dev_data->port_id); 2339 return -EBUSY; 2340 } 2341 2342 if (frame_size > RTE_ETHER_MAX_LEN) 2343 dev_data->dev_conf.rxmode.offloads |= 2344 DEV_RX_OFFLOAD_JUMBO_FRAME; 2345 else 2346 dev_data->dev_conf.rxmode.offloads &= 2347 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2348 2349 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2350 2351 return 0; 2352 } 2353 2354 static int ice_macaddr_set(struct rte_eth_dev *dev, 2355 struct rte_ether_addr *mac_addr) 2356 { 2357 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2358 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2359 struct ice_vsi *vsi = pf->main_vsi; 2360 struct ice_mac_filter *f; 2361 uint8_t flags = 0; 2362 int ret; 2363 2364 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 2365 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 2366 return -EINVAL; 2367 } 2368 2369 TAILQ_FOREACH(f, &vsi->mac_list, next) { 2370 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 2371 break; 2372 } 2373 2374 if (!f) { 2375 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 2376 return -EIO; 2377 } 2378 2379 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 2380 if (ret != ICE_SUCCESS) { 2381 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 2382 return -EIO; 2383 } 2384 ret = ice_add_mac_filter(vsi, mac_addr); 2385 if (ret != ICE_SUCCESS) { 2386 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 2387 return -EIO; 2388 } 2389 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN); 2390 2391 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 2392 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 2393 if (ret != ICE_SUCCESS) 2394 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 2395 2396 return 0; 2397 } 2398 2399 /* Add a MAC address, and update filters */ 2400 static int 2401 ice_macaddr_add(struct rte_eth_dev *dev, 2402 struct rte_ether_addr *mac_addr, 2403 __rte_unused uint32_t index, 2404 __rte_unused uint32_t pool) 2405 { 2406 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2407 struct ice_vsi *vsi = pf->main_vsi; 2408 int ret; 2409 2410 ret = ice_add_mac_filter(vsi, mac_addr); 2411 if (ret != ICE_SUCCESS) { 2412 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 2413 return -EINVAL; 2414 } 2415 2416 return ICE_SUCCESS; 2417 } 2418 2419 /* Remove a MAC address, and update filters */ 2420 static void 2421 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 2422 { 2423 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2424 struct ice_vsi *vsi = pf->main_vsi; 2425 struct rte_eth_dev_data *data = dev->data; 2426 struct rte_ether_addr *macaddr; 2427 int ret; 2428 2429 macaddr = &data->mac_addrs[index]; 2430 ret = ice_remove_mac_filter(vsi, macaddr); 2431 if (ret) { 2432 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 2433 return; 2434 } 2435 } 2436 2437 static int 2438 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 2439 { 2440 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2441 struct ice_vsi *vsi = pf->main_vsi; 2442 int ret; 2443 2444 PMD_INIT_FUNC_TRACE(); 2445 2446 if (on) { 2447 ret = ice_add_vlan_filter(vsi, vlan_id); 2448 if (ret < 0) { 2449 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 2450 return -EINVAL; 2451 } 2452 } else { 2453 ret = ice_remove_vlan_filter(vsi, vlan_id); 2454 if (ret < 0) { 2455 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 2456 return -EINVAL; 2457 } 2458 } 2459 2460 return 0; 2461 } 2462 2463 /* Configure vlan filter on or off */ 2464 static int 2465 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 2466 { 2467 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2468 struct ice_vsi_ctx ctxt; 2469 uint8_t sec_flags, sw_flags2; 2470 int ret = 0; 2471 2472 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 2473 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 2474 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 2475 2476 if (on) { 2477 vsi->info.sec_flags |= sec_flags; 2478 vsi->info.sw_flags2 |= sw_flags2; 2479 } else { 2480 vsi->info.sec_flags &= ~sec_flags; 2481 vsi->info.sw_flags2 &= ~sw_flags2; 2482 } 2483 vsi->info.sw_id = hw->port_info->sw_id; 2484 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2485 ctxt.info.valid_sections = 2486 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 2487 ICE_AQ_VSI_PROP_SECURITY_VALID); 2488 ctxt.vsi_num = vsi->vsi_id; 2489 2490 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2491 if (ret) { 2492 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 2493 on ? "enable" : "disable"); 2494 return -EINVAL; 2495 } else { 2496 vsi->info.valid_sections |= 2497 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 2498 ICE_AQ_VSI_PROP_SECURITY_VALID); 2499 } 2500 2501 /* consist with other drivers, allow untagged packet when vlan filter on */ 2502 if (on) 2503 ret = ice_add_vlan_filter(vsi, 0); 2504 else 2505 ret = ice_remove_vlan_filter(vsi, 0); 2506 2507 return 0; 2508 } 2509 2510 static int 2511 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 2512 { 2513 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2514 struct ice_vsi_ctx ctxt; 2515 uint8_t vlan_flags; 2516 int ret = 0; 2517 2518 /* Check if it has been already on or off */ 2519 if (vsi->info.valid_sections & 2520 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 2521 if (on) { 2522 if ((vsi->info.vlan_flags & 2523 ICE_AQ_VSI_VLAN_EMOD_M) == 2524 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) 2525 return 0; /* already on */ 2526 } else { 2527 if ((vsi->info.vlan_flags & 2528 ICE_AQ_VSI_VLAN_EMOD_M) == 2529 ICE_AQ_VSI_VLAN_EMOD_NOTHING) 2530 return 0; /* already off */ 2531 } 2532 } 2533 2534 if (on) 2535 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; 2536 else 2537 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; 2538 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); 2539 vsi->info.vlan_flags |= vlan_flags; 2540 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2541 ctxt.info.valid_sections = 2542 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2543 ctxt.vsi_num = vsi->vsi_id; 2544 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2545 if (ret) { 2546 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 2547 on ? "enable" : "disable"); 2548 return -EINVAL; 2549 } 2550 2551 vsi->info.valid_sections |= 2552 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2553 2554 return ret; 2555 } 2556 2557 static int 2558 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2559 { 2560 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2561 struct ice_vsi *vsi = pf->main_vsi; 2562 struct rte_eth_rxmode *rxmode; 2563 2564 rxmode = &dev->data->dev_conf.rxmode; 2565 if (mask & ETH_VLAN_FILTER_MASK) { 2566 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2567 ice_vsi_config_vlan_filter(vsi, TRUE); 2568 else 2569 ice_vsi_config_vlan_filter(vsi, FALSE); 2570 } 2571 2572 if (mask & ETH_VLAN_STRIP_MASK) { 2573 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2574 ice_vsi_config_vlan_stripping(vsi, TRUE); 2575 else 2576 ice_vsi_config_vlan_stripping(vsi, FALSE); 2577 } 2578 2579 if (mask & ETH_VLAN_EXTEND_MASK) { 2580 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2581 ice_vsi_config_double_vlan(vsi, TRUE); 2582 else 2583 ice_vsi_config_double_vlan(vsi, FALSE); 2584 } 2585 2586 return 0; 2587 } 2588 2589 static int 2590 ice_vlan_tpid_set(struct rte_eth_dev *dev, 2591 enum rte_vlan_type vlan_type, 2592 uint16_t tpid) 2593 { 2594 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2595 uint64_t reg_r = 0, reg_w = 0; 2596 uint16_t reg_id = 0; 2597 int ret = 0; 2598 int qinq = dev->data->dev_conf.rxmode.offloads & 2599 DEV_RX_OFFLOAD_VLAN_EXTEND; 2600 2601 switch (vlan_type) { 2602 case ETH_VLAN_TYPE_OUTER: 2603 if (qinq) 2604 reg_id = 3; 2605 else 2606 reg_id = 5; 2607 break; 2608 case ETH_VLAN_TYPE_INNER: 2609 if (qinq) { 2610 reg_id = 5; 2611 } else { 2612 PMD_DRV_LOG(ERR, 2613 "Unsupported vlan type in single vlan."); 2614 return -EINVAL; 2615 } 2616 break; 2617 default: 2618 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type); 2619 return -EINVAL; 2620 } 2621 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id)); 2622 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: " 2623 "0x%08"PRIx64"", reg_id, reg_r); 2624 2625 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M)); 2626 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S); 2627 if (reg_r == reg_w) { 2628 PMD_DRV_LOG(DEBUG, "No need to write"); 2629 return 0; 2630 } 2631 2632 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w); 2633 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to " 2634 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id); 2635 2636 return ret; 2637 } 2638 2639 static int 2640 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2641 { 2642 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 2643 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2644 int ret; 2645 2646 if (!lut) 2647 return -EINVAL; 2648 2649 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 2650 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE, 2651 lut, lut_size); 2652 if (ret) { 2653 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 2654 return -EINVAL; 2655 } 2656 } else { 2657 uint64_t *lut_dw = (uint64_t *)lut; 2658 uint16_t i, lut_size_dw = lut_size / 4; 2659 2660 for (i = 0; i < lut_size_dw; i++) 2661 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 2662 } 2663 2664 return 0; 2665 } 2666 2667 static int 2668 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2669 { 2670 struct ice_pf *pf; 2671 struct ice_hw *hw; 2672 int ret; 2673 2674 if (!vsi || !lut) 2675 return -EINVAL; 2676 2677 pf = ICE_VSI_TO_PF(vsi); 2678 hw = ICE_VSI_TO_HW(vsi); 2679 2680 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 2681 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE, 2682 lut, lut_size); 2683 if (ret) { 2684 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 2685 return -EINVAL; 2686 } 2687 } else { 2688 uint64_t *lut_dw = (uint64_t *)lut; 2689 uint16_t i, lut_size_dw = lut_size / 4; 2690 2691 for (i = 0; i < lut_size_dw; i++) 2692 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 2693 2694 ice_flush(hw); 2695 } 2696 2697 return 0; 2698 } 2699 2700 static int 2701 ice_rss_reta_update(struct rte_eth_dev *dev, 2702 struct rte_eth_rss_reta_entry64 *reta_conf, 2703 uint16_t reta_size) 2704 { 2705 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2706 uint16_t i, lut_size = pf->hash_lut_size; 2707 uint16_t idx, shift; 2708 uint8_t *lut; 2709 int ret; 2710 2711 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 2712 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 2713 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 2714 PMD_DRV_LOG(ERR, 2715 "The size of hash lookup table configured (%d)" 2716 "doesn't match the number hardware can " 2717 "supported (128, 512, 2048)", 2718 reta_size); 2719 return -EINVAL; 2720 } 2721 2722 /* It MUST use the current LUT size to get the RSS lookup table, 2723 * otherwise if will fail with -100 error code. 2724 */ 2725 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 2726 if (!lut) { 2727 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2728 return -ENOMEM; 2729 } 2730 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 2731 if (ret) 2732 goto out; 2733 2734 for (i = 0; i < reta_size; i++) { 2735 idx = i / RTE_RETA_GROUP_SIZE; 2736 shift = i % RTE_RETA_GROUP_SIZE; 2737 if (reta_conf[idx].mask & (1ULL << shift)) 2738 lut[i] = reta_conf[idx].reta[shift]; 2739 } 2740 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 2741 if (ret == 0 && lut_size != reta_size) { 2742 PMD_DRV_LOG(INFO, 2743 "The size of hash lookup table is changed from (%d) to (%d)", 2744 lut_size, reta_size); 2745 pf->hash_lut_size = reta_size; 2746 } 2747 2748 out: 2749 rte_free(lut); 2750 2751 return ret; 2752 } 2753 2754 static int 2755 ice_rss_reta_query(struct rte_eth_dev *dev, 2756 struct rte_eth_rss_reta_entry64 *reta_conf, 2757 uint16_t reta_size) 2758 { 2759 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2760 uint16_t i, lut_size = pf->hash_lut_size; 2761 uint16_t idx, shift; 2762 uint8_t *lut; 2763 int ret; 2764 2765 if (reta_size != lut_size) { 2766 PMD_DRV_LOG(ERR, 2767 "The size of hash lookup table configured (%d)" 2768 "doesn't match the number hardware can " 2769 "supported (%d)", 2770 reta_size, lut_size); 2771 return -EINVAL; 2772 } 2773 2774 lut = rte_zmalloc(NULL, reta_size, 0); 2775 if (!lut) { 2776 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2777 return -ENOMEM; 2778 } 2779 2780 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 2781 if (ret) 2782 goto out; 2783 2784 for (i = 0; i < reta_size; i++) { 2785 idx = i / RTE_RETA_GROUP_SIZE; 2786 shift = i % RTE_RETA_GROUP_SIZE; 2787 if (reta_conf[idx].mask & (1ULL << shift)) 2788 reta_conf[idx].reta[shift] = lut[i]; 2789 } 2790 2791 out: 2792 rte_free(lut); 2793 2794 return ret; 2795 } 2796 2797 static int 2798 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 2799 { 2800 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2801 int ret = 0; 2802 2803 if (!key || key_len == 0) { 2804 PMD_DRV_LOG(DEBUG, "No key to be configured"); 2805 return 0; 2806 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 2807 sizeof(uint32_t)) { 2808 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 2809 return -EINVAL; 2810 } 2811 2812 struct ice_aqc_get_set_rss_keys *key_dw = 2813 (struct ice_aqc_get_set_rss_keys *)key; 2814 2815 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 2816 if (ret) { 2817 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 2818 ret = -EINVAL; 2819 } 2820 2821 return ret; 2822 } 2823 2824 static int 2825 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 2826 { 2827 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2828 int ret; 2829 2830 if (!key || !key_len) 2831 return -EINVAL; 2832 2833 ret = ice_aq_get_rss_key 2834 (hw, vsi->idx, 2835 (struct ice_aqc_get_set_rss_keys *)key); 2836 if (ret) { 2837 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 2838 return -EINVAL; 2839 } 2840 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2841 2842 return 0; 2843 } 2844 2845 static int 2846 ice_rss_hash_update(struct rte_eth_dev *dev, 2847 struct rte_eth_rss_conf *rss_conf) 2848 { 2849 enum ice_status status = ICE_SUCCESS; 2850 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2851 struct ice_vsi *vsi = pf->main_vsi; 2852 2853 /* set hash key */ 2854 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 2855 if (status) 2856 return status; 2857 2858 /* TODO: hash enable config, ice_add_rss_cfg */ 2859 return 0; 2860 } 2861 2862 static int 2863 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 2864 struct rte_eth_rss_conf *rss_conf) 2865 { 2866 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2867 struct ice_vsi *vsi = pf->main_vsi; 2868 2869 ice_get_rss_key(vsi, rss_conf->rss_key, 2870 &rss_conf->rss_key_len); 2871 2872 /* TODO: default set to 0 as hf config is not supported now */ 2873 rss_conf->rss_hf = 0; 2874 return 0; 2875 } 2876 2877 static void 2878 ice_promisc_enable(struct rte_eth_dev *dev) 2879 { 2880 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2881 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2882 struct ice_vsi *vsi = pf->main_vsi; 2883 enum ice_status status; 2884 uint8_t pmask; 2885 2886 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 2887 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2888 2889 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 2890 if (status == ICE_ERR_ALREADY_EXISTS) 2891 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 2892 else if (status != ICE_SUCCESS) 2893 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 2894 } 2895 2896 static void 2897 ice_promisc_disable(struct rte_eth_dev *dev) 2898 { 2899 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2900 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2901 struct ice_vsi *vsi = pf->main_vsi; 2902 enum ice_status status; 2903 uint8_t pmask; 2904 2905 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 2906 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2907 2908 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 2909 if (status != ICE_SUCCESS) 2910 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 2911 } 2912 2913 static void 2914 ice_allmulti_enable(struct rte_eth_dev *dev) 2915 { 2916 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2917 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2918 struct ice_vsi *vsi = pf->main_vsi; 2919 enum ice_status status; 2920 uint8_t pmask; 2921 2922 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2923 2924 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 2925 if (status != ICE_SUCCESS) 2926 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 2927 } 2928 2929 static void 2930 ice_allmulti_disable(struct rte_eth_dev *dev) 2931 { 2932 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2933 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2934 struct ice_vsi *vsi = pf->main_vsi; 2935 enum ice_status status; 2936 uint8_t pmask; 2937 2938 if (dev->data->promiscuous == 1) 2939 return; /* must remain in all_multicast mode */ 2940 2941 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2942 2943 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 2944 if (status != ICE_SUCCESS) 2945 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 2946 } 2947 2948 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 2949 uint16_t queue_id) 2950 { 2951 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2952 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2953 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2954 uint32_t val; 2955 uint16_t msix_intr; 2956 2957 msix_intr = intr_handle->intr_vec[queue_id]; 2958 2959 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 2960 GLINT_DYN_CTL_ITR_INDX_M; 2961 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 2962 2963 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 2964 rte_intr_enable(&pci_dev->intr_handle); 2965 2966 return 0; 2967 } 2968 2969 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 2970 uint16_t queue_id) 2971 { 2972 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2973 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2974 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2975 uint16_t msix_intr; 2976 2977 msix_intr = intr_handle->intr_vec[queue_id]; 2978 2979 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 2980 2981 return 0; 2982 } 2983 2984 static int 2985 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2986 { 2987 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2988 u32 full_ver; 2989 u8 ver, patch; 2990 u16 build; 2991 int ret; 2992 2993 full_ver = hw->nvm.oem_ver; 2994 ver = (u8)(full_ver >> 24); 2995 build = (u16)((full_ver >> 8) & 0xffff); 2996 patch = (u8)(full_ver & 0xff); 2997 2998 ret = snprintf(fw_version, fw_size, 2999 "%d.%d%d 0x%08x %d.%d.%d", 3000 ((hw->nvm.ver >> 12) & 0xf), 3001 ((hw->nvm.ver >> 4) & 0xff), 3002 (hw->nvm.ver & 0xf), hw->nvm.eetrack, 3003 ver, build, patch); 3004 3005 /* add the size of '\0' */ 3006 ret += 1; 3007 if (fw_size < (u32)ret) 3008 return ret; 3009 else 3010 return 0; 3011 } 3012 3013 static int 3014 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 3015 { 3016 struct ice_hw *hw; 3017 struct ice_vsi_ctx ctxt; 3018 uint8_t vlan_flags = 0; 3019 int ret; 3020 3021 if (!vsi || !info) { 3022 PMD_DRV_LOG(ERR, "invalid parameters"); 3023 return -EINVAL; 3024 } 3025 3026 if (info->on) { 3027 vsi->info.pvid = info->config.pvid; 3028 /** 3029 * If insert pvid is enabled, only tagged pkts are 3030 * allowed to be sent out. 3031 */ 3032 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | 3033 ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 3034 } else { 3035 vsi->info.pvid = 0; 3036 if (info->config.reject.tagged == 0) 3037 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; 3038 3039 if (info->config.reject.untagged == 0) 3040 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 3041 } 3042 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | 3043 ICE_AQ_VSI_VLAN_MODE_M); 3044 vsi->info.vlan_flags |= vlan_flags; 3045 memset(&ctxt, 0, sizeof(ctxt)); 3046 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 3047 ctxt.info.valid_sections = 3048 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3049 ctxt.vsi_num = vsi->vsi_id; 3050 3051 hw = ICE_VSI_TO_HW(vsi); 3052 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 3053 if (ret != ICE_SUCCESS) { 3054 PMD_DRV_LOG(ERR, 3055 "update VSI for VLAN insert failed, err %d", 3056 ret); 3057 return -EINVAL; 3058 } 3059 3060 vsi->info.valid_sections |= 3061 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3062 3063 return ret; 3064 } 3065 3066 static int 3067 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 3068 { 3069 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3070 struct ice_vsi *vsi = pf->main_vsi; 3071 struct rte_eth_dev_data *data = pf->dev_data; 3072 struct ice_vsi_vlan_pvid_info info; 3073 int ret; 3074 3075 memset(&info, 0, sizeof(info)); 3076 info.on = on; 3077 if (info.on) { 3078 info.config.pvid = pvid; 3079 } else { 3080 info.config.reject.tagged = 3081 data->dev_conf.txmode.hw_vlan_reject_tagged; 3082 info.config.reject.untagged = 3083 data->dev_conf.txmode.hw_vlan_reject_untagged; 3084 } 3085 3086 ret = ice_vsi_vlan_pvid_set(vsi, &info); 3087 if (ret < 0) { 3088 PMD_DRV_LOG(ERR, "Failed to set pvid."); 3089 return -EINVAL; 3090 } 3091 3092 return 0; 3093 } 3094 3095 static int 3096 ice_get_eeprom_length(struct rte_eth_dev *dev) 3097 { 3098 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3099 3100 /* Convert word count to byte count */ 3101 return hw->nvm.sr_words << 1; 3102 } 3103 3104 static int 3105 ice_get_eeprom(struct rte_eth_dev *dev, 3106 struct rte_dev_eeprom_info *eeprom) 3107 { 3108 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3109 uint16_t *data = eeprom->data; 3110 uint16_t first_word, last_word, nwords; 3111 enum ice_status status = ICE_SUCCESS; 3112 3113 first_word = eeprom->offset >> 1; 3114 last_word = (eeprom->offset + eeprom->length - 1) >> 1; 3115 nwords = last_word - first_word + 1; 3116 3117 if (first_word >= hw->nvm.sr_words || 3118 last_word >= hw->nvm.sr_words) { 3119 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 3120 return -EINVAL; 3121 } 3122 3123 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 3124 3125 status = ice_read_sr_buf(hw, first_word, &nwords, data); 3126 if (status) { 3127 PMD_DRV_LOG(ERR, "EEPROM read failed."); 3128 eeprom->length = sizeof(uint16_t) * nwords; 3129 return -EIO; 3130 } 3131 3132 return 0; 3133 } 3134 3135 static void 3136 ice_stat_update_32(struct ice_hw *hw, 3137 uint32_t reg, 3138 bool offset_loaded, 3139 uint64_t *offset, 3140 uint64_t *stat) 3141 { 3142 uint64_t new_data; 3143 3144 new_data = (uint64_t)ICE_READ_REG(hw, reg); 3145 if (!offset_loaded) 3146 *offset = new_data; 3147 3148 if (new_data >= *offset) 3149 *stat = (uint64_t)(new_data - *offset); 3150 else 3151 *stat = (uint64_t)((new_data + 3152 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 3153 - *offset); 3154 } 3155 3156 static void 3157 ice_stat_update_40(struct ice_hw *hw, 3158 uint32_t hireg, 3159 uint32_t loreg, 3160 bool offset_loaded, 3161 uint64_t *offset, 3162 uint64_t *stat) 3163 { 3164 uint64_t new_data; 3165 3166 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 3167 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 3168 ICE_32_BIT_WIDTH; 3169 3170 if (!offset_loaded) 3171 *offset = new_data; 3172 3173 if (new_data >= *offset) 3174 *stat = new_data - *offset; 3175 else 3176 *stat = (uint64_t)((new_data + 3177 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 3178 *offset); 3179 3180 *stat &= ICE_40_BIT_MASK; 3181 } 3182 3183 /* Get all the statistics of a VSI */ 3184 static void 3185 ice_update_vsi_stats(struct ice_vsi *vsi) 3186 { 3187 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 3188 struct ice_eth_stats *nes = &vsi->eth_stats; 3189 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3190 int idx = rte_le_to_cpu_16(vsi->vsi_id); 3191 3192 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 3193 vsi->offset_loaded, &oes->rx_bytes, 3194 &nes->rx_bytes); 3195 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 3196 vsi->offset_loaded, &oes->rx_unicast, 3197 &nes->rx_unicast); 3198 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 3199 vsi->offset_loaded, &oes->rx_multicast, 3200 &nes->rx_multicast); 3201 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 3202 vsi->offset_loaded, &oes->rx_broadcast, 3203 &nes->rx_broadcast); 3204 /* exclude CRC bytes */ 3205 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 3206 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 3207 3208 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 3209 &oes->rx_discards, &nes->rx_discards); 3210 /* GLV_REPC not supported */ 3211 /* GLV_RMPC not supported */ 3212 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 3213 &oes->rx_unknown_protocol, 3214 &nes->rx_unknown_protocol); 3215 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 3216 vsi->offset_loaded, &oes->tx_bytes, 3217 &nes->tx_bytes); 3218 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 3219 vsi->offset_loaded, &oes->tx_unicast, 3220 &nes->tx_unicast); 3221 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 3222 vsi->offset_loaded, &oes->tx_multicast, 3223 &nes->tx_multicast); 3224 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 3225 vsi->offset_loaded, &oes->tx_broadcast, 3226 &nes->tx_broadcast); 3227 /* GLV_TDPC not supported */ 3228 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 3229 &oes->tx_errors, &nes->tx_errors); 3230 vsi->offset_loaded = true; 3231 3232 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 3233 vsi->vsi_id); 3234 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 3235 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 3236 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 3237 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 3238 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 3239 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3240 nes->rx_unknown_protocol); 3241 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 3242 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 3243 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 3244 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 3245 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 3246 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 3247 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 3248 vsi->vsi_id); 3249 } 3250 3251 static void 3252 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 3253 { 3254 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 3255 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 3256 3257 /* Get statistics of struct ice_eth_stats */ 3258 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 3259 GLPRT_GORCL(hw->port_info->lport), 3260 pf->offset_loaded, &os->eth.rx_bytes, 3261 &ns->eth.rx_bytes); 3262 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 3263 GLPRT_UPRCL(hw->port_info->lport), 3264 pf->offset_loaded, &os->eth.rx_unicast, 3265 &ns->eth.rx_unicast); 3266 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 3267 GLPRT_MPRCL(hw->port_info->lport), 3268 pf->offset_loaded, &os->eth.rx_multicast, 3269 &ns->eth.rx_multicast); 3270 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 3271 GLPRT_BPRCL(hw->port_info->lport), 3272 pf->offset_loaded, &os->eth.rx_broadcast, 3273 &ns->eth.rx_broadcast); 3274 ice_stat_update_32(hw, PRTRPB_RDPC, 3275 pf->offset_loaded, &os->eth.rx_discards, 3276 &ns->eth.rx_discards); 3277 3278 /* Workaround: CRC size should not be included in byte statistics, 3279 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 3280 * packet. 3281 */ 3282 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 3283 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 3284 3285 /* GLPRT_REPC not supported */ 3286 /* GLPRT_RMPC not supported */ 3287 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 3288 pf->offset_loaded, 3289 &os->eth.rx_unknown_protocol, 3290 &ns->eth.rx_unknown_protocol); 3291 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 3292 GLPRT_GOTCL(hw->port_info->lport), 3293 pf->offset_loaded, &os->eth.tx_bytes, 3294 &ns->eth.tx_bytes); 3295 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 3296 GLPRT_UPTCL(hw->port_info->lport), 3297 pf->offset_loaded, &os->eth.tx_unicast, 3298 &ns->eth.tx_unicast); 3299 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 3300 GLPRT_MPTCL(hw->port_info->lport), 3301 pf->offset_loaded, &os->eth.tx_multicast, 3302 &ns->eth.tx_multicast); 3303 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 3304 GLPRT_BPTCL(hw->port_info->lport), 3305 pf->offset_loaded, &os->eth.tx_broadcast, 3306 &ns->eth.tx_broadcast); 3307 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 3308 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 3309 3310 /* GLPRT_TEPC not supported */ 3311 3312 /* additional port specific stats */ 3313 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 3314 pf->offset_loaded, &os->tx_dropped_link_down, 3315 &ns->tx_dropped_link_down); 3316 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 3317 pf->offset_loaded, &os->crc_errors, 3318 &ns->crc_errors); 3319 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 3320 pf->offset_loaded, &os->illegal_bytes, 3321 &ns->illegal_bytes); 3322 /* GLPRT_ERRBC not supported */ 3323 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 3324 pf->offset_loaded, &os->mac_local_faults, 3325 &ns->mac_local_faults); 3326 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 3327 pf->offset_loaded, &os->mac_remote_faults, 3328 &ns->mac_remote_faults); 3329 3330 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 3331 pf->offset_loaded, &os->rx_len_errors, 3332 &ns->rx_len_errors); 3333 3334 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 3335 pf->offset_loaded, &os->link_xon_rx, 3336 &ns->link_xon_rx); 3337 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 3338 pf->offset_loaded, &os->link_xoff_rx, 3339 &ns->link_xoff_rx); 3340 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 3341 pf->offset_loaded, &os->link_xon_tx, 3342 &ns->link_xon_tx); 3343 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 3344 pf->offset_loaded, &os->link_xoff_tx, 3345 &ns->link_xoff_tx); 3346 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 3347 GLPRT_PRC64L(hw->port_info->lport), 3348 pf->offset_loaded, &os->rx_size_64, 3349 &ns->rx_size_64); 3350 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 3351 GLPRT_PRC127L(hw->port_info->lport), 3352 pf->offset_loaded, &os->rx_size_127, 3353 &ns->rx_size_127); 3354 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 3355 GLPRT_PRC255L(hw->port_info->lport), 3356 pf->offset_loaded, &os->rx_size_255, 3357 &ns->rx_size_255); 3358 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 3359 GLPRT_PRC511L(hw->port_info->lport), 3360 pf->offset_loaded, &os->rx_size_511, 3361 &ns->rx_size_511); 3362 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 3363 GLPRT_PRC1023L(hw->port_info->lport), 3364 pf->offset_loaded, &os->rx_size_1023, 3365 &ns->rx_size_1023); 3366 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 3367 GLPRT_PRC1522L(hw->port_info->lport), 3368 pf->offset_loaded, &os->rx_size_1522, 3369 &ns->rx_size_1522); 3370 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 3371 GLPRT_PRC9522L(hw->port_info->lport), 3372 pf->offset_loaded, &os->rx_size_big, 3373 &ns->rx_size_big); 3374 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 3375 pf->offset_loaded, &os->rx_undersize, 3376 &ns->rx_undersize); 3377 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 3378 pf->offset_loaded, &os->rx_fragments, 3379 &ns->rx_fragments); 3380 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 3381 pf->offset_loaded, &os->rx_oversize, 3382 &ns->rx_oversize); 3383 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 3384 pf->offset_loaded, &os->rx_jabber, 3385 &ns->rx_jabber); 3386 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 3387 GLPRT_PTC64L(hw->port_info->lport), 3388 pf->offset_loaded, &os->tx_size_64, 3389 &ns->tx_size_64); 3390 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 3391 GLPRT_PTC127L(hw->port_info->lport), 3392 pf->offset_loaded, &os->tx_size_127, 3393 &ns->tx_size_127); 3394 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 3395 GLPRT_PTC255L(hw->port_info->lport), 3396 pf->offset_loaded, &os->tx_size_255, 3397 &ns->tx_size_255); 3398 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 3399 GLPRT_PTC511L(hw->port_info->lport), 3400 pf->offset_loaded, &os->tx_size_511, 3401 &ns->tx_size_511); 3402 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 3403 GLPRT_PTC1023L(hw->port_info->lport), 3404 pf->offset_loaded, &os->tx_size_1023, 3405 &ns->tx_size_1023); 3406 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 3407 GLPRT_PTC1522L(hw->port_info->lport), 3408 pf->offset_loaded, &os->tx_size_1522, 3409 &ns->tx_size_1522); 3410 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 3411 GLPRT_PTC9522L(hw->port_info->lport), 3412 pf->offset_loaded, &os->tx_size_big, 3413 &ns->tx_size_big); 3414 3415 /* GLPRT_MSPDC not supported */ 3416 /* GLPRT_XEC not supported */ 3417 3418 pf->offset_loaded = true; 3419 3420 if (pf->main_vsi) 3421 ice_update_vsi_stats(pf->main_vsi); 3422 } 3423 3424 /* Get all statistics of a port */ 3425 static int 3426 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3427 { 3428 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3429 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3430 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 3431 3432 /* call read registers - updates values, now write them to struct */ 3433 ice_read_stats_registers(pf, hw); 3434 3435 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 3436 pf->main_vsi->eth_stats.rx_multicast + 3437 pf->main_vsi->eth_stats.rx_broadcast - 3438 pf->main_vsi->eth_stats.rx_discards; 3439 stats->opackets = ns->eth.tx_unicast + 3440 ns->eth.tx_multicast + 3441 ns->eth.tx_broadcast; 3442 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 3443 stats->obytes = ns->eth.tx_bytes; 3444 stats->oerrors = ns->eth.tx_errors + 3445 pf->main_vsi->eth_stats.tx_errors; 3446 3447 /* Rx Errors */ 3448 stats->imissed = ns->eth.rx_discards + 3449 pf->main_vsi->eth_stats.rx_discards; 3450 stats->ierrors = ns->crc_errors + 3451 ns->rx_undersize + 3452 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 3453 3454 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 3455 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 3456 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 3457 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 3458 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 3459 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 3460 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 3461 pf->main_vsi->eth_stats.rx_discards); 3462 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3463 ns->eth.rx_unknown_protocol); 3464 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 3465 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 3466 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 3467 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 3468 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 3469 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 3470 pf->main_vsi->eth_stats.tx_discards); 3471 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 3472 3473 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 3474 ns->tx_dropped_link_down); 3475 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 3476 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 3477 ns->illegal_bytes); 3478 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 3479 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 3480 ns->mac_local_faults); 3481 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 3482 ns->mac_remote_faults); 3483 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 3484 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 3485 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 3486 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 3487 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 3488 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 3489 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 3490 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 3491 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 3492 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 3493 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 3494 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 3495 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 3496 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 3497 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 3498 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 3499 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 3500 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 3501 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 3502 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 3503 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 3504 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 3505 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 3506 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 3507 return 0; 3508 } 3509 3510 /* Reset the statistics */ 3511 static void 3512 ice_stats_reset(struct rte_eth_dev *dev) 3513 { 3514 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3515 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3516 3517 /* Mark PF and VSI stats to update the offset, aka "reset" */ 3518 pf->offset_loaded = false; 3519 if (pf->main_vsi) 3520 pf->main_vsi->offset_loaded = false; 3521 3522 /* read the stats, reading current register values into offset */ 3523 ice_read_stats_registers(pf, hw); 3524 } 3525 3526 static uint32_t 3527 ice_xstats_calc_num(void) 3528 { 3529 uint32_t num; 3530 3531 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 3532 3533 return num; 3534 } 3535 3536 static int 3537 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3538 unsigned int n) 3539 { 3540 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3541 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3542 unsigned int i; 3543 unsigned int count; 3544 struct ice_hw_port_stats *hw_stats = &pf->stats; 3545 3546 count = ice_xstats_calc_num(); 3547 if (n < count) 3548 return count; 3549 3550 ice_read_stats_registers(pf, hw); 3551 3552 if (!xstats) 3553 return 0; 3554 3555 count = 0; 3556 3557 /* Get stats from ice_eth_stats struct */ 3558 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 3559 xstats[count].value = 3560 *(uint64_t *)((char *)&hw_stats->eth + 3561 ice_stats_strings[i].offset); 3562 xstats[count].id = count; 3563 count++; 3564 } 3565 3566 /* Get individiual stats from ice_hw_port struct */ 3567 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 3568 xstats[count].value = 3569 *(uint64_t *)((char *)hw_stats + 3570 ice_hw_port_strings[i].offset); 3571 xstats[count].id = count; 3572 count++; 3573 } 3574 3575 return count; 3576 } 3577 3578 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3579 struct rte_eth_xstat_name *xstats_names, 3580 __rte_unused unsigned int limit) 3581 { 3582 unsigned int count = 0; 3583 unsigned int i; 3584 3585 if (!xstats_names) 3586 return ice_xstats_calc_num(); 3587 3588 /* Note: limit checked in rte_eth_xstats_names() */ 3589 3590 /* Get stats from ice_eth_stats struct */ 3591 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 3592 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 3593 sizeof(xstats_names[count].name)); 3594 count++; 3595 } 3596 3597 /* Get individiual stats from ice_hw_port struct */ 3598 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 3599 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 3600 sizeof(xstats_names[count].name)); 3601 count++; 3602 } 3603 3604 return count; 3605 } 3606 3607 static int 3608 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3609 struct rte_pci_device *pci_dev) 3610 { 3611 return rte_eth_dev_pci_generic_probe(pci_dev, 3612 sizeof(struct ice_adapter), 3613 ice_dev_init); 3614 } 3615 3616 static int 3617 ice_pci_remove(struct rte_pci_device *pci_dev) 3618 { 3619 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 3620 } 3621 3622 static struct rte_pci_driver rte_ice_pmd = { 3623 .id_table = pci_id_ice_map, 3624 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 3625 RTE_PCI_DRV_IOVA_AS_VA, 3626 .probe = ice_pci_probe, 3627 .remove = ice_pci_remove, 3628 }; 3629 3630 /** 3631 * Driver initialization routine. 3632 * Invoked once at EAL init time. 3633 * Register itself as the [Poll Mode] Driver of PCI devices. 3634 */ 3635 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 3636 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 3637 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 3638 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 3639 ICE_MAX_QP_NUM "=<int>"); 3640 3641 RTE_INIT(ice_init_log) 3642 { 3643 ice_logtype_init = rte_log_register("pmd.net.ice.init"); 3644 if (ice_logtype_init >= 0) 3645 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE); 3646 ice_logtype_driver = rte_log_register("pmd.net.ice.driver"); 3647 if (ice_logtype_driver >= 0) 3648 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE); 3649 } 3650