1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <rte_ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include "base/ice_sched.h" 14 #include "base/ice_flow.h" 15 #include "base/ice_dcb.h" 16 #include "ice_ethdev.h" 17 #include "ice_rxtx.h" 18 #include "ice_switch_filter.h" 19 20 /* devargs */ 21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" 22 23 static const char * const ice_valid_args[] = { 24 ICE_SAFE_MODE_SUPPORT_ARG, 25 NULL 26 }; 27 28 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 29 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg" 30 31 int ice_logtype_init; 32 int ice_logtype_driver; 33 34 static int ice_dev_configure(struct rte_eth_dev *dev); 35 static int ice_dev_start(struct rte_eth_dev *dev); 36 static void ice_dev_stop(struct rte_eth_dev *dev); 37 static void ice_dev_close(struct rte_eth_dev *dev); 38 static int ice_dev_reset(struct rte_eth_dev *dev); 39 static void ice_dev_info_get(struct rte_eth_dev *dev, 40 struct rte_eth_dev_info *dev_info); 41 static int ice_link_update(struct rte_eth_dev *dev, 42 int wait_to_complete); 43 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 44 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 45 46 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 47 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 48 static int ice_vlan_tpid_set(struct rte_eth_dev *dev, 49 enum rte_vlan_type vlan_type, 50 uint16_t tpid); 51 static int ice_rss_reta_update(struct rte_eth_dev *dev, 52 struct rte_eth_rss_reta_entry64 *reta_conf, 53 uint16_t reta_size); 54 static int ice_rss_reta_query(struct rte_eth_dev *dev, 55 struct rte_eth_rss_reta_entry64 *reta_conf, 56 uint16_t reta_size); 57 static int ice_rss_hash_update(struct rte_eth_dev *dev, 58 struct rte_eth_rss_conf *rss_conf); 59 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 60 struct rte_eth_rss_conf *rss_conf); 61 static void ice_promisc_enable(struct rte_eth_dev *dev); 62 static void ice_promisc_disable(struct rte_eth_dev *dev); 63 static void ice_allmulti_enable(struct rte_eth_dev *dev); 64 static void ice_allmulti_disable(struct rte_eth_dev *dev); 65 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 66 uint16_t vlan_id, 67 int on); 68 static int ice_macaddr_set(struct rte_eth_dev *dev, 69 struct rte_ether_addr *mac_addr); 70 static int ice_macaddr_add(struct rte_eth_dev *dev, 71 struct rte_ether_addr *mac_addr, 72 __rte_unused uint32_t index, 73 uint32_t pool); 74 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 75 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 76 uint16_t queue_id); 77 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 78 uint16_t queue_id); 79 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 80 size_t fw_size); 81 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 82 uint16_t pvid, int on); 83 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 84 static int ice_get_eeprom(struct rte_eth_dev *dev, 85 struct rte_dev_eeprom_info *eeprom); 86 static int ice_stats_get(struct rte_eth_dev *dev, 87 struct rte_eth_stats *stats); 88 static void ice_stats_reset(struct rte_eth_dev *dev); 89 static int ice_xstats_get(struct rte_eth_dev *dev, 90 struct rte_eth_xstat *xstats, unsigned int n); 91 static int ice_xstats_get_names(struct rte_eth_dev *dev, 92 struct rte_eth_xstat_name *xstats_names, 93 unsigned int limit); 94 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, 95 enum rte_filter_type filter_type, 96 enum rte_filter_op filter_op, 97 void *arg); 98 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 99 struct rte_eth_udp_tunnel *udp_tunnel); 100 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 101 struct rte_eth_udp_tunnel *udp_tunnel); 102 103 static const struct rte_pci_id pci_id_ice_map[] = { 104 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 105 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 106 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 107 { .vendor_id = 0, /* sentinel */ }, 108 }; 109 110 static const struct eth_dev_ops ice_eth_dev_ops = { 111 .dev_configure = ice_dev_configure, 112 .dev_start = ice_dev_start, 113 .dev_stop = ice_dev_stop, 114 .dev_close = ice_dev_close, 115 .dev_reset = ice_dev_reset, 116 .dev_set_link_up = ice_dev_set_link_up, 117 .dev_set_link_down = ice_dev_set_link_down, 118 .rx_queue_start = ice_rx_queue_start, 119 .rx_queue_stop = ice_rx_queue_stop, 120 .tx_queue_start = ice_tx_queue_start, 121 .tx_queue_stop = ice_tx_queue_stop, 122 .rx_queue_setup = ice_rx_queue_setup, 123 .rx_queue_release = ice_rx_queue_release, 124 .tx_queue_setup = ice_tx_queue_setup, 125 .tx_queue_release = ice_tx_queue_release, 126 .dev_infos_get = ice_dev_info_get, 127 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 128 .link_update = ice_link_update, 129 .mtu_set = ice_mtu_set, 130 .mac_addr_set = ice_macaddr_set, 131 .mac_addr_add = ice_macaddr_add, 132 .mac_addr_remove = ice_macaddr_remove, 133 .vlan_filter_set = ice_vlan_filter_set, 134 .vlan_offload_set = ice_vlan_offload_set, 135 .vlan_tpid_set = ice_vlan_tpid_set, 136 .reta_update = ice_rss_reta_update, 137 .reta_query = ice_rss_reta_query, 138 .rss_hash_update = ice_rss_hash_update, 139 .rss_hash_conf_get = ice_rss_hash_conf_get, 140 .promiscuous_enable = ice_promisc_enable, 141 .promiscuous_disable = ice_promisc_disable, 142 .allmulticast_enable = ice_allmulti_enable, 143 .allmulticast_disable = ice_allmulti_disable, 144 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 145 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 146 .fw_version_get = ice_fw_version_get, 147 .vlan_pvid_set = ice_vlan_pvid_set, 148 .rxq_info_get = ice_rxq_info_get, 149 .txq_info_get = ice_txq_info_get, 150 .get_eeprom_length = ice_get_eeprom_length, 151 .get_eeprom = ice_get_eeprom, 152 .rx_queue_count = ice_rx_queue_count, 153 .rx_descriptor_status = ice_rx_descriptor_status, 154 .tx_descriptor_status = ice_tx_descriptor_status, 155 .stats_get = ice_stats_get, 156 .stats_reset = ice_stats_reset, 157 .xstats_get = ice_xstats_get, 158 .xstats_get_names = ice_xstats_get_names, 159 .xstats_reset = ice_stats_reset, 160 .filter_ctrl = ice_dev_filter_ctrl, 161 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, 162 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, 163 }; 164 165 /* store statistics names and its offset in stats structure */ 166 struct ice_xstats_name_off { 167 char name[RTE_ETH_XSTATS_NAME_SIZE]; 168 unsigned int offset; 169 }; 170 171 static const struct ice_xstats_name_off ice_stats_strings[] = { 172 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 173 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 174 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 175 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 176 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 177 rx_unknown_protocol)}, 178 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 179 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 180 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 181 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 182 }; 183 184 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 185 sizeof(ice_stats_strings[0])) 186 187 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 188 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 189 tx_dropped_link_down)}, 190 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 191 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 192 illegal_bytes)}, 193 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 194 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 195 mac_local_faults)}, 196 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 197 mac_remote_faults)}, 198 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 199 rx_len_errors)}, 200 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 201 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 202 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 203 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 204 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 205 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 206 rx_size_127)}, 207 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 208 rx_size_255)}, 209 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 210 rx_size_511)}, 211 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 212 rx_size_1023)}, 213 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 214 rx_size_1522)}, 215 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 216 rx_size_big)}, 217 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 218 rx_undersize)}, 219 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 220 rx_oversize)}, 221 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 222 mac_short_pkt_dropped)}, 223 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 224 rx_fragments)}, 225 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 226 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 227 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 228 tx_size_127)}, 229 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 230 tx_size_255)}, 231 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 232 tx_size_511)}, 233 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 234 tx_size_1023)}, 235 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 236 tx_size_1522)}, 237 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 238 tx_size_big)}, 239 }; 240 241 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 242 sizeof(ice_hw_port_strings[0])) 243 244 static void 245 ice_init_controlq_parameter(struct ice_hw *hw) 246 { 247 /* fields for adminq */ 248 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 249 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 250 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 251 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 252 253 /* fields for mailboxq, DPDK used as PF host */ 254 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 255 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 256 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 257 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 258 } 259 260 static int 261 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 262 uint32_t num) 263 { 264 struct pool_entry *entry; 265 266 if (!pool || !num) 267 return -EINVAL; 268 269 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 270 if (!entry) { 271 PMD_INIT_LOG(ERR, 272 "Failed to allocate memory for resource pool"); 273 return -ENOMEM; 274 } 275 276 /* queue heap initialize */ 277 pool->num_free = num; 278 pool->num_alloc = 0; 279 pool->base = base; 280 LIST_INIT(&pool->alloc_list); 281 LIST_INIT(&pool->free_list); 282 283 /* Initialize element */ 284 entry->base = 0; 285 entry->len = num; 286 287 LIST_INSERT_HEAD(&pool->free_list, entry, next); 288 return 0; 289 } 290 291 static int 292 ice_res_pool_alloc(struct ice_res_pool_info *pool, 293 uint16_t num) 294 { 295 struct pool_entry *entry, *valid_entry; 296 297 if (!pool || !num) { 298 PMD_INIT_LOG(ERR, "Invalid parameter"); 299 return -EINVAL; 300 } 301 302 if (pool->num_free < num) { 303 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 304 num, pool->num_free); 305 return -ENOMEM; 306 } 307 308 valid_entry = NULL; 309 /* Lookup in free list and find most fit one */ 310 LIST_FOREACH(entry, &pool->free_list, next) { 311 if (entry->len >= num) { 312 /* Find best one */ 313 if (entry->len == num) { 314 valid_entry = entry; 315 break; 316 } 317 if (!valid_entry || 318 valid_entry->len > entry->len) 319 valid_entry = entry; 320 } 321 } 322 323 /* Not find one to satisfy the request, return */ 324 if (!valid_entry) { 325 PMD_INIT_LOG(ERR, "No valid entry found"); 326 return -ENOMEM; 327 } 328 /** 329 * The entry have equal queue number as requested, 330 * remove it from alloc_list. 331 */ 332 if (valid_entry->len == num) { 333 LIST_REMOVE(valid_entry, next); 334 } else { 335 /** 336 * The entry have more numbers than requested, 337 * create a new entry for alloc_list and minus its 338 * queue base and number in free_list. 339 */ 340 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 341 if (!entry) { 342 PMD_INIT_LOG(ERR, 343 "Failed to allocate memory for " 344 "resource pool"); 345 return -ENOMEM; 346 } 347 entry->base = valid_entry->base; 348 entry->len = num; 349 valid_entry->base += num; 350 valid_entry->len -= num; 351 valid_entry = entry; 352 } 353 354 /* Insert it into alloc list, not sorted */ 355 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 356 357 pool->num_free -= valid_entry->len; 358 pool->num_alloc += valid_entry->len; 359 360 return valid_entry->base + pool->base; 361 } 362 363 static void 364 ice_res_pool_destroy(struct ice_res_pool_info *pool) 365 { 366 struct pool_entry *entry, *next_entry; 367 368 if (!pool) 369 return; 370 371 for (entry = LIST_FIRST(&pool->alloc_list); 372 entry && (next_entry = LIST_NEXT(entry, next), 1); 373 entry = next_entry) { 374 LIST_REMOVE(entry, next); 375 rte_free(entry); 376 } 377 378 for (entry = LIST_FIRST(&pool->free_list); 379 entry && (next_entry = LIST_NEXT(entry, next), 1); 380 entry = next_entry) { 381 LIST_REMOVE(entry, next); 382 rte_free(entry); 383 } 384 385 pool->num_free = 0; 386 pool->num_alloc = 0; 387 pool->base = 0; 388 LIST_INIT(&pool->alloc_list); 389 LIST_INIT(&pool->free_list); 390 } 391 392 static void 393 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 394 { 395 /* Set VSI LUT selection */ 396 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 397 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 398 /* Set Hash scheme */ 399 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 400 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 401 /* enable TC */ 402 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 403 } 404 405 static enum ice_status 406 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 407 struct ice_aqc_vsi_props *info, 408 uint8_t enabled_tcmap) 409 { 410 uint16_t bsf, qp_idx; 411 412 /* default tc 0 now. Multi-TC supporting need to be done later. 413 * Configure TC and queue mapping parameters, for enabled TC, 414 * allocate qpnum_per_tc queues to this traffic. 415 */ 416 if (enabled_tcmap != 0x01) { 417 PMD_INIT_LOG(ERR, "only TC0 is supported"); 418 return -ENOTSUP; 419 } 420 421 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 422 bsf = rte_bsf32(vsi->nb_qps); 423 /* Adjust the queue number to actual queues that can be applied */ 424 vsi->nb_qps = 0x1 << bsf; 425 426 qp_idx = 0; 427 /* Set tc and queue mapping with VSI */ 428 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 429 ICE_AQ_VSI_TC_Q_OFFSET_S) | 430 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 431 432 /* Associate queue number with VSI */ 433 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 434 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 435 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 436 info->valid_sections |= 437 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 438 /* Set the info.ingress_table and info.egress_table 439 * for UP translate table. Now just set it to 1:1 map by default 440 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 441 */ 442 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 443 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 444 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 445 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 446 return 0; 447 } 448 449 static int 450 ice_init_mac_address(struct rte_eth_dev *dev) 451 { 452 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 453 454 if (!rte_is_unicast_ether_addr 455 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 456 PMD_INIT_LOG(ERR, "Invalid MAC address"); 457 return -EINVAL; 458 } 459 460 rte_ether_addr_copy( 461 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 462 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 463 464 dev->data->mac_addrs = 465 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0); 466 if (!dev->data->mac_addrs) { 467 PMD_INIT_LOG(ERR, 468 "Failed to allocate memory to store mac address"); 469 return -ENOMEM; 470 } 471 /* store it to dev data */ 472 rte_ether_addr_copy( 473 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 474 &dev->data->mac_addrs[0]); 475 return 0; 476 } 477 478 /* Find out specific MAC filter */ 479 static struct ice_mac_filter * 480 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 481 { 482 struct ice_mac_filter *f; 483 484 TAILQ_FOREACH(f, &vsi->mac_list, next) { 485 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 486 return f; 487 } 488 489 return NULL; 490 } 491 492 static int 493 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 494 { 495 struct ice_fltr_list_entry *m_list_itr = NULL; 496 struct ice_mac_filter *f; 497 struct LIST_HEAD_TYPE list_head; 498 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 499 int ret = 0; 500 501 /* If it's added and configured, return */ 502 f = ice_find_mac_filter(vsi, mac_addr); 503 if (f) { 504 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 505 return 0; 506 } 507 508 INIT_LIST_HEAD(&list_head); 509 510 m_list_itr = (struct ice_fltr_list_entry *) 511 ice_malloc(hw, sizeof(*m_list_itr)); 512 if (!m_list_itr) { 513 ret = -ENOMEM; 514 goto DONE; 515 } 516 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 517 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 518 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 519 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 520 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 521 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 522 m_list_itr->fltr_info.vsi_handle = vsi->idx; 523 524 LIST_ADD(&m_list_itr->list_entry, &list_head); 525 526 /* Add the mac */ 527 ret = ice_add_mac(hw, &list_head); 528 if (ret != ICE_SUCCESS) { 529 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 530 ret = -EINVAL; 531 goto DONE; 532 } 533 /* Add the mac addr into mac list */ 534 f = rte_zmalloc(NULL, sizeof(*f), 0); 535 if (!f) { 536 PMD_DRV_LOG(ERR, "failed to allocate memory"); 537 ret = -ENOMEM; 538 goto DONE; 539 } 540 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN); 541 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 542 vsi->mac_num++; 543 544 ret = 0; 545 546 DONE: 547 rte_free(m_list_itr); 548 return ret; 549 } 550 551 static int 552 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 553 { 554 struct ice_fltr_list_entry *m_list_itr = NULL; 555 struct ice_mac_filter *f; 556 struct LIST_HEAD_TYPE list_head; 557 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 558 int ret = 0; 559 560 /* Can't find it, return an error */ 561 f = ice_find_mac_filter(vsi, mac_addr); 562 if (!f) 563 return -EINVAL; 564 565 INIT_LIST_HEAD(&list_head); 566 567 m_list_itr = (struct ice_fltr_list_entry *) 568 ice_malloc(hw, sizeof(*m_list_itr)); 569 if (!m_list_itr) { 570 ret = -ENOMEM; 571 goto DONE; 572 } 573 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 574 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 575 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 576 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 577 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 578 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 579 m_list_itr->fltr_info.vsi_handle = vsi->idx; 580 581 LIST_ADD(&m_list_itr->list_entry, &list_head); 582 583 /* remove the mac filter */ 584 ret = ice_remove_mac(hw, &list_head); 585 if (ret != ICE_SUCCESS) { 586 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 587 ret = -EINVAL; 588 goto DONE; 589 } 590 591 /* Remove the mac addr from mac list */ 592 TAILQ_REMOVE(&vsi->mac_list, f, next); 593 rte_free(f); 594 vsi->mac_num--; 595 596 ret = 0; 597 DONE: 598 rte_free(m_list_itr); 599 return ret; 600 } 601 602 /* Find out specific VLAN filter */ 603 static struct ice_vlan_filter * 604 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 605 { 606 struct ice_vlan_filter *f; 607 608 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 609 if (vlan_id == f->vlan_info.vlan_id) 610 return f; 611 } 612 613 return NULL; 614 } 615 616 static int 617 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 618 { 619 struct ice_fltr_list_entry *v_list_itr = NULL; 620 struct ice_vlan_filter *f; 621 struct LIST_HEAD_TYPE list_head; 622 struct ice_hw *hw; 623 int ret = 0; 624 625 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID) 626 return -EINVAL; 627 628 hw = ICE_VSI_TO_HW(vsi); 629 630 /* If it's added and configured, return. */ 631 f = ice_find_vlan_filter(vsi, vlan_id); 632 if (f) { 633 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 634 return 0; 635 } 636 637 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 638 return 0; 639 640 INIT_LIST_HEAD(&list_head); 641 642 v_list_itr = (struct ice_fltr_list_entry *) 643 ice_malloc(hw, sizeof(*v_list_itr)); 644 if (!v_list_itr) { 645 ret = -ENOMEM; 646 goto DONE; 647 } 648 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 649 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 650 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 651 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 652 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 653 v_list_itr->fltr_info.vsi_handle = vsi->idx; 654 655 LIST_ADD(&v_list_itr->list_entry, &list_head); 656 657 /* Add the vlan */ 658 ret = ice_add_vlan(hw, &list_head); 659 if (ret != ICE_SUCCESS) { 660 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 661 ret = -EINVAL; 662 goto DONE; 663 } 664 665 /* Add vlan into vlan list */ 666 f = rte_zmalloc(NULL, sizeof(*f), 0); 667 if (!f) { 668 PMD_DRV_LOG(ERR, "failed to allocate memory"); 669 ret = -ENOMEM; 670 goto DONE; 671 } 672 f->vlan_info.vlan_id = vlan_id; 673 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 674 vsi->vlan_num++; 675 676 ret = 0; 677 678 DONE: 679 rte_free(v_list_itr); 680 return ret; 681 } 682 683 static int 684 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 685 { 686 struct ice_fltr_list_entry *v_list_itr = NULL; 687 struct ice_vlan_filter *f; 688 struct LIST_HEAD_TYPE list_head; 689 struct ice_hw *hw; 690 int ret = 0; 691 692 /** 693 * Vlan 0 is the generic filter for untagged packets 694 * and can't be removed. 695 */ 696 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID) 697 return -EINVAL; 698 699 hw = ICE_VSI_TO_HW(vsi); 700 701 /* Can't find it, return an error */ 702 f = ice_find_vlan_filter(vsi, vlan_id); 703 if (!f) 704 return -EINVAL; 705 706 INIT_LIST_HEAD(&list_head); 707 708 v_list_itr = (struct ice_fltr_list_entry *) 709 ice_malloc(hw, sizeof(*v_list_itr)); 710 if (!v_list_itr) { 711 ret = -ENOMEM; 712 goto DONE; 713 } 714 715 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 716 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 717 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 718 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 719 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 720 v_list_itr->fltr_info.vsi_handle = vsi->idx; 721 722 LIST_ADD(&v_list_itr->list_entry, &list_head); 723 724 /* remove the vlan filter */ 725 ret = ice_remove_vlan(hw, &list_head); 726 if (ret != ICE_SUCCESS) { 727 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 728 ret = -EINVAL; 729 goto DONE; 730 } 731 732 /* Remove the vlan id from vlan list */ 733 TAILQ_REMOVE(&vsi->vlan_list, f, next); 734 rte_free(f); 735 vsi->vlan_num--; 736 737 ret = 0; 738 DONE: 739 rte_free(v_list_itr); 740 return ret; 741 } 742 743 static int 744 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 745 { 746 struct ice_mac_filter *m_f; 747 struct ice_vlan_filter *v_f; 748 int ret = 0; 749 750 if (!vsi || !vsi->mac_num) 751 return -EINVAL; 752 753 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 754 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 755 if (ret != ICE_SUCCESS) { 756 ret = -EINVAL; 757 goto DONE; 758 } 759 } 760 761 if (vsi->vlan_num == 0) 762 return 0; 763 764 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 765 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 766 if (ret != ICE_SUCCESS) { 767 ret = -EINVAL; 768 goto DONE; 769 } 770 } 771 772 DONE: 773 return ret; 774 } 775 776 static int 777 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 778 { 779 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 780 struct ice_vsi_ctx ctxt; 781 uint8_t qinq_flags; 782 int ret = 0; 783 784 /* Check if it has been already on or off */ 785 if (vsi->info.valid_sections & 786 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 787 if (on) { 788 if ((vsi->info.outer_tag_flags & 789 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == 790 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) 791 return 0; /* already on */ 792 } else { 793 if (!(vsi->info.outer_tag_flags & 794 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) 795 return 0; /* already off */ 796 } 797 } 798 799 if (on) 800 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; 801 else 802 qinq_flags = 0; 803 /* clear global insertion and use per packet insertion */ 804 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); 805 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); 806 vsi->info.outer_tag_flags |= qinq_flags; 807 /* use default vlan type 0x8100 */ 808 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 809 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 810 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 811 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 812 ctxt.info.valid_sections = 813 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 814 ctxt.vsi_num = vsi->vsi_id; 815 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 816 if (ret) { 817 PMD_DRV_LOG(INFO, 818 "Update VSI failed to %s qinq stripping", 819 on ? "enable" : "disable"); 820 return -EINVAL; 821 } 822 823 vsi->info.valid_sections |= 824 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 825 826 return ret; 827 } 828 829 static int 830 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 831 { 832 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 833 struct ice_vsi_ctx ctxt; 834 uint8_t qinq_flags; 835 int ret = 0; 836 837 /* Check if it has been already on or off */ 838 if (vsi->info.valid_sections & 839 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 840 if (on) { 841 if ((vsi->info.outer_tag_flags & 842 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 843 ICE_AQ_VSI_OUTER_TAG_COPY) 844 return 0; /* already on */ 845 } else { 846 if ((vsi->info.outer_tag_flags & 847 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 848 ICE_AQ_VSI_OUTER_TAG_NOTHING) 849 return 0; /* already off */ 850 } 851 } 852 853 if (on) 854 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; 855 else 856 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; 857 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); 858 vsi->info.outer_tag_flags |= qinq_flags; 859 /* use default vlan type 0x8100 */ 860 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 861 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 862 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 863 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 864 ctxt.info.valid_sections = 865 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 866 ctxt.vsi_num = vsi->vsi_id; 867 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 868 if (ret) { 869 PMD_DRV_LOG(INFO, 870 "Update VSI failed to %s qinq stripping", 871 on ? "enable" : "disable"); 872 return -EINVAL; 873 } 874 875 vsi->info.valid_sections |= 876 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 877 878 return ret; 879 } 880 881 static int 882 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 883 { 884 int ret; 885 886 ret = ice_vsi_config_qinq_stripping(vsi, on); 887 if (ret) 888 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 889 890 ret = ice_vsi_config_qinq_insertion(vsi, on); 891 if (ret) 892 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 893 894 return ret; 895 } 896 897 /* Enable IRQ0 */ 898 static void 899 ice_pf_enable_irq0(struct ice_hw *hw) 900 { 901 /* reset the registers */ 902 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 903 ICE_READ_REG(hw, PFINT_OICR); 904 905 #ifdef ICE_LSE_SPT 906 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 907 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 908 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 909 910 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 911 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 912 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 913 PFINT_OICR_CTL_ITR_INDX_M) | 914 PFINT_OICR_CTL_CAUSE_ENA_M); 915 916 ICE_WRITE_REG(hw, PFINT_FW_CTL, 917 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 918 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 919 PFINT_FW_CTL_ITR_INDX_M) | 920 PFINT_FW_CTL_CAUSE_ENA_M); 921 #else 922 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 923 #endif 924 925 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 926 GLINT_DYN_CTL_INTENA_M | 927 GLINT_DYN_CTL_CLEARPBA_M | 928 GLINT_DYN_CTL_ITR_INDX_M); 929 930 ice_flush(hw); 931 } 932 933 /* Disable IRQ0 */ 934 static void 935 ice_pf_disable_irq0(struct ice_hw *hw) 936 { 937 /* Disable all interrupt types */ 938 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 939 ice_flush(hw); 940 } 941 942 #ifdef ICE_LSE_SPT 943 static void 944 ice_handle_aq_msg(struct rte_eth_dev *dev) 945 { 946 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 947 struct ice_ctl_q_info *cq = &hw->adminq; 948 struct ice_rq_event_info event; 949 uint16_t pending, opcode; 950 int ret; 951 952 event.buf_len = ICE_AQ_MAX_BUF_LEN; 953 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 954 if (!event.msg_buf) { 955 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 956 return; 957 } 958 959 pending = 1; 960 while (pending) { 961 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 962 963 if (ret != ICE_SUCCESS) { 964 PMD_DRV_LOG(INFO, 965 "Failed to read msg from AdminQ, " 966 "adminq_err: %u", 967 hw->adminq.sq_last_status); 968 break; 969 } 970 opcode = rte_le_to_cpu_16(event.desc.opcode); 971 972 switch (opcode) { 973 case ice_aqc_opc_get_link_status: 974 ret = ice_link_update(dev, 0); 975 if (!ret) 976 _rte_eth_dev_callback_process 977 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 978 break; 979 default: 980 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 981 opcode); 982 break; 983 } 984 } 985 rte_free(event.msg_buf); 986 } 987 #endif 988 989 /** 990 * Interrupt handler triggered by NIC for handling 991 * specific interrupt. 992 * 993 * @param handle 994 * Pointer to interrupt handle. 995 * @param param 996 * The address of parameter (struct rte_eth_dev *) regsitered before. 997 * 998 * @return 999 * void 1000 */ 1001 static void 1002 ice_interrupt_handler(void *param) 1003 { 1004 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1005 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1006 uint32_t oicr; 1007 uint32_t reg; 1008 uint8_t pf_num; 1009 uint8_t event; 1010 uint16_t queue; 1011 #ifdef ICE_LSE_SPT 1012 uint32_t int_fw_ctl; 1013 #endif 1014 1015 /* Disable interrupt */ 1016 ice_pf_disable_irq0(hw); 1017 1018 /* read out interrupt causes */ 1019 oicr = ICE_READ_REG(hw, PFINT_OICR); 1020 #ifdef ICE_LSE_SPT 1021 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1022 #endif 1023 1024 /* No interrupt event indicated */ 1025 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1026 PMD_DRV_LOG(INFO, "No interrupt event"); 1027 goto done; 1028 } 1029 1030 #ifdef ICE_LSE_SPT 1031 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1032 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1033 ice_handle_aq_msg(dev); 1034 } 1035 #else 1036 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1037 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1038 ice_link_update(dev, 0); 1039 } 1040 #endif 1041 1042 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1043 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1044 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1045 if (reg & GL_MDET_TX_PQM_VALID_M) { 1046 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1047 GL_MDET_TX_PQM_PF_NUM_S; 1048 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1049 GL_MDET_TX_PQM_MAL_TYPE_S; 1050 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1051 GL_MDET_TX_PQM_QNUM_S; 1052 1053 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1054 "%d by PQM on TX queue %d PF# %d", 1055 event, queue, pf_num); 1056 } 1057 1058 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1059 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1060 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1061 GL_MDET_TX_TCLAN_PF_NUM_S; 1062 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1063 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1064 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1065 GL_MDET_TX_TCLAN_QNUM_S; 1066 1067 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1068 "%d by TCLAN on TX queue %d PF# %d", 1069 event, queue, pf_num); 1070 } 1071 } 1072 done: 1073 /* Enable interrupt */ 1074 ice_pf_enable_irq0(hw); 1075 rte_intr_ack(dev->intr_handle); 1076 } 1077 1078 /* Initialize SW parameters of PF */ 1079 static int 1080 ice_pf_sw_init(struct rte_eth_dev *dev) 1081 { 1082 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1083 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1084 1085 pf->lan_nb_qp_max = 1086 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1087 hw->func_caps.common_cap.num_rxq); 1088 1089 pf->lan_nb_qps = pf->lan_nb_qp_max; 1090 1091 return 0; 1092 } 1093 1094 static struct ice_vsi * 1095 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1096 { 1097 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1098 struct ice_vsi *vsi = NULL; 1099 struct ice_vsi_ctx vsi_ctx; 1100 int ret; 1101 struct rte_ether_addr broadcast = { 1102 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1103 struct rte_ether_addr mac_addr; 1104 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1105 uint8_t tc_bitmap = 0x1; 1106 1107 /* hw->num_lports = 1 in NIC mode */ 1108 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1109 if (!vsi) 1110 return NULL; 1111 1112 vsi->idx = pf->next_vsi_idx; 1113 pf->next_vsi_idx++; 1114 vsi->type = type; 1115 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1116 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1117 vsi->vlan_anti_spoof_on = 0; 1118 vsi->vlan_filter_on = 1; 1119 TAILQ_INIT(&vsi->mac_list); 1120 TAILQ_INIT(&vsi->vlan_list); 1121 1122 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ 1123 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1124 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : 1125 hw->func_caps.common_cap.rss_table_size; 1126 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1127 1128 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1129 /* base_queue in used in queue mapping of VSI add/update command. 1130 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ 1131 * cases in the first stage. Only Main VSI. 1132 */ 1133 vsi->base_queue = 0; 1134 switch (type) { 1135 case ICE_VSI_PF: 1136 vsi->nb_qps = pf->lan_nb_qps; 1137 ice_vsi_config_default_rss(&vsi_ctx.info); 1138 vsi_ctx.alloc_from_pool = true; 1139 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1140 /* switch_id is queried by get_switch_config aq, which is done 1141 * by ice_init_hw 1142 */ 1143 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1144 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1145 /* Allow all untagged or tagged packets */ 1146 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; 1147 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; 1148 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1149 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1150 /* Enable VLAN/UP trip */ 1151 ret = ice_vsi_config_tc_queue_mapping(vsi, 1152 &vsi_ctx.info, 1153 ICE_DEFAULT_TCMAP); 1154 if (ret) { 1155 PMD_INIT_LOG(ERR, 1156 "tc queue mapping with vsi failed, " 1157 "err = %d", 1158 ret); 1159 goto fail_mem; 1160 } 1161 1162 break; 1163 default: 1164 /* for other types of VSI */ 1165 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1166 goto fail_mem; 1167 } 1168 1169 /* VF has MSIX interrupt in VF range, don't allocate here */ 1170 if (type == ICE_VSI_PF) { 1171 ret = ice_res_pool_alloc(&pf->msix_pool, 1172 RTE_MIN(vsi->nb_qps, 1173 RTE_MAX_RXTX_INTR_VEC_ID)); 1174 if (ret < 0) { 1175 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1176 vsi->vsi_id, ret); 1177 } 1178 vsi->msix_intr = ret; 1179 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1180 } else { 1181 vsi->msix_intr = 0; 1182 vsi->nb_msix = 0; 1183 } 1184 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1185 if (ret != ICE_SUCCESS) { 1186 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1187 goto fail_mem; 1188 } 1189 /* store vsi information is SW structure */ 1190 vsi->vsi_id = vsi_ctx.vsi_num; 1191 vsi->info = vsi_ctx.info; 1192 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1193 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1194 1195 /* MAC configuration */ 1196 rte_memcpy(pf->dev_addr.addr_bytes, 1197 hw->port_info->mac.perm_addr, 1198 ETH_ADDR_LEN); 1199 1200 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN); 1201 ret = ice_add_mac_filter(vsi, &mac_addr); 1202 if (ret != ICE_SUCCESS) 1203 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1204 1205 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN); 1206 ret = ice_add_mac_filter(vsi, &mac_addr); 1207 if (ret != ICE_SUCCESS) 1208 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1209 1210 /* At the beginning, only TC0. */ 1211 /* What we need here is the maximam number of the TX queues. 1212 * Currently vsi->nb_qps means it. 1213 * Correct it if any change. 1214 */ 1215 max_txqs[0] = vsi->nb_qps; 1216 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1217 tc_bitmap, max_txqs); 1218 if (ret != ICE_SUCCESS) 1219 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1220 1221 return vsi; 1222 fail_mem: 1223 rte_free(vsi); 1224 pf->next_vsi_idx--; 1225 return NULL; 1226 } 1227 1228 static int 1229 ice_send_driver_ver(struct ice_hw *hw) 1230 { 1231 struct ice_driver_ver dv; 1232 1233 /* we don't have driver version use 0 for dummy */ 1234 dv.major_ver = 0; 1235 dv.minor_ver = 0; 1236 dv.build_ver = 0; 1237 dv.subbuild_ver = 0; 1238 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1239 1240 return ice_aq_send_driver_ver(hw, &dv, NULL); 1241 } 1242 1243 static int 1244 ice_pf_setup(struct ice_pf *pf) 1245 { 1246 struct ice_vsi *vsi; 1247 1248 /* Clear all stats counters */ 1249 pf->offset_loaded = FALSE; 1250 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1251 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1252 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1253 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1254 1255 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1256 if (!vsi) { 1257 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1258 return -EINVAL; 1259 } 1260 1261 pf->main_vsi = vsi; 1262 1263 return 0; 1264 } 1265 1266 static int ice_load_pkg(struct rte_eth_dev *dev) 1267 { 1268 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1269 const char *pkg_file = ICE_DFLT_PKG_FILE; 1270 int err; 1271 uint8_t *buf; 1272 int buf_len; 1273 FILE *file; 1274 struct stat fstat; 1275 1276 file = fopen(pkg_file, "rb"); 1277 if (!file) { 1278 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); 1279 return -1; 1280 } 1281 1282 err = stat(pkg_file, &fstat); 1283 if (err) { 1284 PMD_INIT_LOG(ERR, "failed to get file stats\n"); 1285 fclose(file); 1286 return err; 1287 } 1288 1289 buf_len = fstat.st_size; 1290 buf = rte_malloc(NULL, buf_len, 0); 1291 1292 if (!buf) { 1293 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", 1294 buf_len); 1295 fclose(file); 1296 return -1; 1297 } 1298 1299 err = fread(buf, buf_len, 1, file); 1300 if (err != 1) { 1301 PMD_INIT_LOG(ERR, "failed to read package data\n"); 1302 fclose(file); 1303 err = -1; 1304 goto fail_exit; 1305 } 1306 1307 fclose(file); 1308 1309 err = ice_copy_and_init_pkg(hw, buf, buf_len); 1310 if (err) { 1311 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1312 goto fail_exit; 1313 } 1314 err = ice_init_hw_tbls(hw); 1315 if (err) { 1316 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); 1317 goto fail_init_tbls; 1318 } 1319 1320 return 0; 1321 1322 fail_init_tbls: 1323 rte_free(hw->pkg_copy); 1324 fail_exit: 1325 rte_free(buf); 1326 return err; 1327 } 1328 1329 static void 1330 ice_base_queue_get(struct ice_pf *pf) 1331 { 1332 uint32_t reg; 1333 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1334 1335 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); 1336 if (reg & PFLAN_RX_QALLOC_VALID_M) { 1337 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; 1338 } else { 1339 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" 1340 " index"); 1341 } 1342 } 1343 1344 static int 1345 parse_bool(const char *key, const char *value, void *args) 1346 { 1347 int *i = (int *)args; 1348 char *end; 1349 int num; 1350 1351 num = strtoul(value, &end, 10); 1352 1353 if (num != 0 && num != 1) { 1354 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 1355 "value must be 0 or 1", 1356 value, key); 1357 return -1; 1358 } 1359 1360 *i = num; 1361 return 0; 1362 } 1363 1364 static int ice_parse_devargs(struct rte_eth_dev *dev) 1365 { 1366 struct ice_adapter *ad = 1367 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1368 struct rte_devargs *devargs = dev->device->devargs; 1369 struct rte_kvargs *kvlist; 1370 int ret; 1371 1372 if (devargs == NULL) 1373 return 0; 1374 1375 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args); 1376 if (kvlist == NULL) { 1377 PMD_INIT_LOG(ERR, "Invalid kvargs key\n"); 1378 return -EINVAL; 1379 } 1380 1381 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, 1382 &parse_bool, &ad->devargs.safe_mode_support); 1383 1384 rte_kvargs_free(kvlist); 1385 return ret; 1386 } 1387 1388 /* Forward LLDP packets to default VSI by set switch rules */ 1389 static int 1390 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on) 1391 { 1392 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1393 struct ice_fltr_list_entry *s_list_itr = NULL; 1394 struct LIST_HEAD_TYPE list_head; 1395 int ret = 0; 1396 1397 INIT_LIST_HEAD(&list_head); 1398 1399 s_list_itr = (struct ice_fltr_list_entry *) 1400 ice_malloc(hw, sizeof(*s_list_itr)); 1401 if (!s_list_itr) 1402 return -ENOMEM; 1403 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE; 1404 s_list_itr->fltr_info.vsi_handle = vsi->idx; 1405 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype = 1406 RTE_ETHER_TYPE_LLDP; 1407 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1408 s_list_itr->fltr_info.flag = ICE_FLTR_RX; 1409 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT; 1410 LIST_ADD(&s_list_itr->list_entry, &list_head); 1411 if (on) 1412 ret = ice_add_eth_mac(hw, &list_head); 1413 else 1414 ret = ice_remove_eth_mac(hw, &list_head); 1415 1416 rte_free(s_list_itr); 1417 return ret; 1418 } 1419 1420 static int 1421 ice_dev_init(struct rte_eth_dev *dev) 1422 { 1423 struct rte_pci_device *pci_dev; 1424 struct rte_intr_handle *intr_handle; 1425 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1426 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1427 struct ice_adapter *ad = 1428 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1429 struct ice_vsi *vsi; 1430 int ret; 1431 1432 dev->dev_ops = &ice_eth_dev_ops; 1433 dev->rx_pkt_burst = ice_recv_pkts; 1434 dev->tx_pkt_burst = ice_xmit_pkts; 1435 dev->tx_pkt_prepare = ice_prep_pkts; 1436 1437 /* for secondary processes, we don't initialise any further as primary 1438 * has already done this work. 1439 */ 1440 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1441 ice_set_rx_function(dev); 1442 ice_set_tx_function(dev); 1443 return 0; 1444 } 1445 1446 ice_set_default_ptype_table(dev); 1447 pci_dev = RTE_DEV_TO_PCI(dev->device); 1448 intr_handle = &pci_dev->intr_handle; 1449 1450 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1451 pf->adapter->eth_dev = dev; 1452 pf->dev_data = dev->data; 1453 hw->back = pf->adapter; 1454 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 1455 hw->vendor_id = pci_dev->id.vendor_id; 1456 hw->device_id = pci_dev->id.device_id; 1457 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1458 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1459 hw->bus.device = pci_dev->addr.devid; 1460 hw->bus.func = pci_dev->addr.function; 1461 1462 ret = ice_parse_devargs(dev); 1463 if (ret) { 1464 PMD_INIT_LOG(ERR, "Failed to parse devargs"); 1465 return -EINVAL; 1466 } 1467 1468 ice_init_controlq_parameter(hw); 1469 1470 ret = ice_init_hw(hw); 1471 if (ret) { 1472 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 1473 return -EINVAL; 1474 } 1475 1476 ret = ice_load_pkg(dev); 1477 if (ret) { 1478 if (ad->devargs.safe_mode_support == 0) { 1479 PMD_INIT_LOG(ERR, "Failed to load the DDP package," 1480 "Use safe-mode-support=1 to enter Safe Mode"); 1481 return ret; 1482 } 1483 1484 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 1485 "Entering Safe Mode"); 1486 ad->is_safe_mode = 1; 1487 } 1488 1489 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 1490 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 1491 hw->api_maj_ver, hw->api_min_ver); 1492 1493 ice_pf_sw_init(dev); 1494 ret = ice_init_mac_address(dev); 1495 if (ret) { 1496 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 1497 goto err_init_mac; 1498 } 1499 1500 ret = ice_res_pool_init(&pf->msix_pool, 1, 1501 hw->func_caps.common_cap.num_msix_vectors - 1); 1502 if (ret) { 1503 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 1504 goto err_msix_pool_init; 1505 } 1506 1507 ret = ice_pf_setup(pf); 1508 if (ret) { 1509 PMD_INIT_LOG(ERR, "Failed to setup PF"); 1510 goto err_pf_setup; 1511 } 1512 1513 ret = ice_send_driver_ver(hw); 1514 if (ret) { 1515 PMD_INIT_LOG(ERR, "Failed to send driver version"); 1516 goto err_pf_setup; 1517 } 1518 1519 vsi = pf->main_vsi; 1520 1521 /* Disable double vlan by default */ 1522 ice_vsi_config_double_vlan(vsi, FALSE); 1523 1524 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL); 1525 if (ret != ICE_SUCCESS) 1526 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 1527 ret = ice_init_dcb(hw, TRUE); 1528 if (ret != ICE_SUCCESS) 1529 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n"); 1530 /* Forward LLDP packets to default VSI */ 1531 ret = ice_vsi_config_sw_lldp(vsi, TRUE); 1532 if (ret != ICE_SUCCESS) 1533 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n"); 1534 /* register callback func to eal lib */ 1535 rte_intr_callback_register(intr_handle, 1536 ice_interrupt_handler, dev); 1537 1538 ice_pf_enable_irq0(hw); 1539 1540 /* enable uio intr after callback register */ 1541 rte_intr_enable(intr_handle); 1542 1543 /* get base queue pairs index in the device */ 1544 ice_base_queue_get(pf); 1545 1546 TAILQ_INIT(&pf->flow_list); 1547 1548 return 0; 1549 1550 err_pf_setup: 1551 ice_res_pool_destroy(&pf->msix_pool); 1552 err_msix_pool_init: 1553 rte_free(dev->data->mac_addrs); 1554 dev->data->mac_addrs = NULL; 1555 err_init_mac: 1556 ice_sched_cleanup_all(hw); 1557 rte_free(hw->port_info); 1558 ice_shutdown_all_ctrlq(hw); 1559 1560 return ret; 1561 } 1562 1563 static int 1564 ice_release_vsi(struct ice_vsi *vsi) 1565 { 1566 struct ice_hw *hw; 1567 struct ice_vsi_ctx vsi_ctx; 1568 enum ice_status ret; 1569 1570 if (!vsi) 1571 return 0; 1572 1573 hw = ICE_VSI_TO_HW(vsi); 1574 1575 ice_remove_all_mac_vlan_filters(vsi); 1576 1577 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1578 1579 vsi_ctx.vsi_num = vsi->vsi_id; 1580 vsi_ctx.info = vsi->info; 1581 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 1582 if (ret != ICE_SUCCESS) { 1583 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 1584 rte_free(vsi); 1585 return -1; 1586 } 1587 1588 rte_free(vsi); 1589 return 0; 1590 } 1591 1592 static void 1593 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 1594 { 1595 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1596 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1597 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1598 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1599 uint16_t msix_intr, i; 1600 1601 /* disable interrupt and also clear all the exist config */ 1602 for (i = 0; i < vsi->nb_qps; i++) { 1603 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 1604 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 1605 rte_wmb(); 1606 } 1607 1608 if (rte_intr_allow_others(intr_handle)) 1609 /* vfio-pci */ 1610 for (i = 0; i < vsi->nb_msix; i++) { 1611 msix_intr = vsi->msix_intr + i; 1612 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 1613 GLINT_DYN_CTL_WB_ON_ITR_M); 1614 } 1615 else 1616 /* igb_uio */ 1617 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1618 } 1619 1620 static void 1621 ice_dev_stop(struct rte_eth_dev *dev) 1622 { 1623 struct rte_eth_dev_data *data = dev->data; 1624 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1625 struct ice_vsi *main_vsi = pf->main_vsi; 1626 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1627 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1628 uint16_t i; 1629 1630 /* avoid stopping again */ 1631 if (pf->adapter_stopped) 1632 return; 1633 1634 /* stop and clear all Rx queues */ 1635 for (i = 0; i < data->nb_rx_queues; i++) 1636 ice_rx_queue_stop(dev, i); 1637 1638 /* stop and clear all Tx queues */ 1639 for (i = 0; i < data->nb_tx_queues; i++) 1640 ice_tx_queue_stop(dev, i); 1641 1642 /* disable all queue interrupts */ 1643 ice_vsi_disable_queues_intr(main_vsi); 1644 1645 /* Clear all queues and release mbufs */ 1646 ice_clear_queues(dev); 1647 1648 ice_dev_set_link_down(dev); 1649 1650 /* Clean datapath event and queue/vec mapping */ 1651 rte_intr_efd_disable(intr_handle); 1652 if (intr_handle->intr_vec) { 1653 rte_free(intr_handle->intr_vec); 1654 intr_handle->intr_vec = NULL; 1655 } 1656 1657 pf->adapter_stopped = true; 1658 } 1659 1660 static void 1661 ice_dev_close(struct rte_eth_dev *dev) 1662 { 1663 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1664 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1665 1666 /* Since stop will make link down, then the link event will be 1667 * triggered, disable the irq firstly to avoid the port_infoe etc 1668 * resources deallocation causing the interrupt service thread 1669 * crash. 1670 */ 1671 ice_pf_disable_irq0(hw); 1672 1673 ice_dev_stop(dev); 1674 1675 /* release all queue resource */ 1676 ice_free_queues(dev); 1677 1678 ice_res_pool_destroy(&pf->msix_pool); 1679 ice_release_vsi(pf->main_vsi); 1680 ice_sched_cleanup_all(hw); 1681 rte_free(hw->port_info); 1682 hw->port_info = NULL; 1683 ice_shutdown_all_ctrlq(hw); 1684 } 1685 1686 static int 1687 ice_dev_uninit(struct rte_eth_dev *dev) 1688 { 1689 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1690 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1691 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1692 struct rte_flow *p_flow; 1693 1694 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1695 return 0; 1696 1697 ice_dev_close(dev); 1698 1699 dev->dev_ops = NULL; 1700 dev->rx_pkt_burst = NULL; 1701 dev->tx_pkt_burst = NULL; 1702 1703 rte_free(dev->data->mac_addrs); 1704 dev->data->mac_addrs = NULL; 1705 1706 /* disable uio intr before callback unregister */ 1707 rte_intr_disable(intr_handle); 1708 1709 /* unregister callback func from eal lib */ 1710 rte_intr_callback_unregister(intr_handle, 1711 ice_interrupt_handler, dev); 1712 1713 /* Remove all flows */ 1714 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) { 1715 TAILQ_REMOVE(&pf->flow_list, p_flow, node); 1716 ice_free_switch_filter_rule(p_flow->rule); 1717 rte_free(p_flow); 1718 } 1719 1720 return 0; 1721 } 1722 1723 static int 1724 ice_dev_configure(struct rte_eth_dev *dev) 1725 { 1726 struct ice_adapter *ad = 1727 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1728 1729 /* Initialize to TRUE. If any of Rx queues doesn't meet the 1730 * bulk allocation or vector Rx preconditions we will reset it. 1731 */ 1732 ad->rx_bulk_alloc_allowed = true; 1733 ad->tx_simple_allowed = true; 1734 1735 return 0; 1736 } 1737 1738 static int ice_init_rss(struct ice_pf *pf) 1739 { 1740 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1741 struct ice_vsi *vsi = pf->main_vsi; 1742 struct rte_eth_dev *dev = pf->adapter->eth_dev; 1743 struct rte_eth_rss_conf *rss_conf; 1744 struct ice_aqc_get_set_rss_keys key; 1745 uint16_t i, nb_q; 1746 int ret = 0; 1747 bool is_safe_mode = pf->adapter->is_safe_mode; 1748 1749 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 1750 nb_q = dev->data->nb_rx_queues; 1751 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 1752 vsi->rss_lut_size = pf->hash_lut_size; 1753 1754 if (is_safe_mode) { 1755 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 1756 return 0; 1757 } 1758 1759 if (!vsi->rss_key) 1760 vsi->rss_key = rte_zmalloc(NULL, 1761 vsi->rss_key_size, 0); 1762 if (!vsi->rss_lut) 1763 vsi->rss_lut = rte_zmalloc(NULL, 1764 vsi->rss_lut_size, 0); 1765 1766 /* configure RSS key */ 1767 if (!rss_conf->rss_key) { 1768 /* Calculate the default hash key */ 1769 for (i = 0; i <= vsi->rss_key_size; i++) 1770 vsi->rss_key[i] = (uint8_t)rte_rand(); 1771 } else { 1772 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 1773 RTE_MIN(rss_conf->rss_key_len, 1774 vsi->rss_key_size)); 1775 } 1776 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 1777 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 1778 if (ret) 1779 return -EINVAL; 1780 1781 /* init RSS LUT table */ 1782 for (i = 0; i < vsi->rss_lut_size; i++) 1783 vsi->rss_lut[i] = i % nb_q; 1784 1785 ret = ice_aq_set_rss_lut(hw, vsi->idx, 1786 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, 1787 vsi->rss_lut, vsi->rss_lut_size); 1788 if (ret) 1789 return -EINVAL; 1790 1791 /* configure RSS for IPv4 with input set IPv4 src/dst */ 1792 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 1793 ICE_FLOW_SEG_HDR_IPV4); 1794 if (ret) 1795 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret); 1796 1797 /* configure RSS for IPv6 with input set IPv6 src/dst */ 1798 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 1799 ICE_FLOW_SEG_HDR_IPV6); 1800 if (ret) 1801 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret); 1802 1803 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */ 1804 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6, 1805 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6); 1806 if (ret) 1807 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret); 1808 1809 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */ 1810 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6, 1811 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6); 1812 if (ret) 1813 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret); 1814 1815 /* configure RSS for sctp6 with input set IPv6 src/dst */ 1816 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 1817 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6); 1818 if (ret) 1819 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 1820 __func__, ret); 1821 1822 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */ 1823 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4, 1824 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4); 1825 if (ret) 1826 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret); 1827 1828 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */ 1829 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4, 1830 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4); 1831 if (ret) 1832 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret); 1833 1834 /* configure RSS for sctp4 with input set IP src/dst */ 1835 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 1836 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4); 1837 if (ret) 1838 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 1839 __func__, ret); 1840 1841 return 0; 1842 } 1843 1844 static void 1845 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 1846 int base_queue, int nb_queue) 1847 { 1848 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1849 uint32_t val, val_tx; 1850 int i; 1851 1852 for (i = 0; i < nb_queue; i++) { 1853 /*do actual bind*/ 1854 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 1855 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 1856 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 1857 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 1858 1859 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 1860 base_queue + i, msix_vect); 1861 /* set ITR0 value */ 1862 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); 1863 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 1864 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 1865 } 1866 } 1867 1868 static void 1869 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 1870 { 1871 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1872 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1873 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1874 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1875 uint16_t msix_vect = vsi->msix_intr; 1876 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 1877 uint16_t queue_idx = 0; 1878 int record = 0; 1879 int i; 1880 1881 /* clear Rx/Tx queue interrupt */ 1882 for (i = 0; i < vsi->nb_used_qps; i++) { 1883 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 1884 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 1885 } 1886 1887 /* PF bind interrupt */ 1888 if (rte_intr_dp_is_en(intr_handle)) { 1889 queue_idx = 0; 1890 record = 1; 1891 } 1892 1893 for (i = 0; i < vsi->nb_used_qps; i++) { 1894 if (nb_msix <= 1) { 1895 if (!rte_intr_allow_others(intr_handle)) 1896 msix_vect = ICE_MISC_VEC_ID; 1897 1898 /* uio mapping all queue to one msix_vect */ 1899 __vsi_queues_bind_intr(vsi, msix_vect, 1900 vsi->base_queue + i, 1901 vsi->nb_used_qps - i); 1902 1903 for (; !!record && i < vsi->nb_used_qps; i++) 1904 intr_handle->intr_vec[queue_idx + i] = 1905 msix_vect; 1906 break; 1907 } 1908 1909 /* vfio 1:1 queue/msix_vect mapping */ 1910 __vsi_queues_bind_intr(vsi, msix_vect, 1911 vsi->base_queue + i, 1); 1912 1913 if (!!record) 1914 intr_handle->intr_vec[queue_idx + i] = msix_vect; 1915 1916 msix_vect++; 1917 nb_msix--; 1918 } 1919 } 1920 1921 static void 1922 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 1923 { 1924 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1925 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1926 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1927 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1928 uint16_t msix_intr, i; 1929 1930 if (rte_intr_allow_others(intr_handle)) 1931 for (i = 0; i < vsi->nb_used_qps; i++) { 1932 msix_intr = vsi->msix_intr + i; 1933 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 1934 GLINT_DYN_CTL_INTENA_M | 1935 GLINT_DYN_CTL_CLEARPBA_M | 1936 GLINT_DYN_CTL_ITR_INDX_M | 1937 GLINT_DYN_CTL_WB_ON_ITR_M); 1938 } 1939 else 1940 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1941 GLINT_DYN_CTL_INTENA_M | 1942 GLINT_DYN_CTL_CLEARPBA_M | 1943 GLINT_DYN_CTL_ITR_INDX_M | 1944 GLINT_DYN_CTL_WB_ON_ITR_M); 1945 } 1946 1947 static int 1948 ice_rxq_intr_setup(struct rte_eth_dev *dev) 1949 { 1950 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1951 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1952 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1953 struct ice_vsi *vsi = pf->main_vsi; 1954 uint32_t intr_vector = 0; 1955 1956 rte_intr_disable(intr_handle); 1957 1958 /* check and configure queue intr-vector mapping */ 1959 if ((rte_intr_cap_multiple(intr_handle) || 1960 !RTE_ETH_DEV_SRIOV(dev).active) && 1961 dev->data->dev_conf.intr_conf.rxq != 0) { 1962 intr_vector = dev->data->nb_rx_queues; 1963 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 1964 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 1965 ICE_MAX_INTR_QUEUE_NUM); 1966 return -ENOTSUP; 1967 } 1968 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1969 return -1; 1970 } 1971 1972 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1973 intr_handle->intr_vec = 1974 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 1975 0); 1976 if (!intr_handle->intr_vec) { 1977 PMD_DRV_LOG(ERR, 1978 "Failed to allocate %d rx_queues intr_vec", 1979 dev->data->nb_rx_queues); 1980 return -ENOMEM; 1981 } 1982 } 1983 1984 /* Map queues with MSIX interrupt */ 1985 vsi->nb_used_qps = dev->data->nb_rx_queues; 1986 ice_vsi_queues_bind_intr(vsi); 1987 1988 /* Enable interrupts for all the queues */ 1989 ice_vsi_enable_queues_intr(vsi); 1990 1991 rte_intr_enable(intr_handle); 1992 1993 return 0; 1994 } 1995 1996 static int 1997 ice_dev_start(struct rte_eth_dev *dev) 1998 { 1999 struct rte_eth_dev_data *data = dev->data; 2000 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2001 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2002 struct ice_vsi *vsi = pf->main_vsi; 2003 uint16_t nb_rxq = 0; 2004 uint16_t nb_txq, i; 2005 int mask, ret; 2006 2007 /* program Tx queues' context in hardware */ 2008 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 2009 ret = ice_tx_queue_start(dev, nb_txq); 2010 if (ret) { 2011 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 2012 goto tx_err; 2013 } 2014 } 2015 2016 /* program Rx queues' context in hardware*/ 2017 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 2018 ret = ice_rx_queue_start(dev, nb_rxq); 2019 if (ret) { 2020 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 2021 goto rx_err; 2022 } 2023 } 2024 2025 ret = ice_init_rss(pf); 2026 if (ret) { 2027 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 2028 goto rx_err; 2029 } 2030 2031 ice_set_rx_function(dev); 2032 ice_set_tx_function(dev); 2033 2034 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2035 ETH_VLAN_EXTEND_MASK; 2036 ret = ice_vlan_offload_set(dev, mask); 2037 if (ret) { 2038 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2039 goto rx_err; 2040 } 2041 2042 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 2043 if (ice_rxq_intr_setup(dev)) 2044 return -EIO; 2045 2046 /* Enable receiving broadcast packets and transmitting packets */ 2047 ret = ice_set_vsi_promisc(hw, vsi->idx, 2048 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 2049 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 2050 0); 2051 if (ret != ICE_SUCCESS) 2052 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2053 2054 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 2055 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 2056 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 2057 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 2058 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 2059 ICE_AQ_LINK_EVENT_AN_COMPLETED | 2060 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 2061 NULL); 2062 if (ret != ICE_SUCCESS) 2063 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 2064 2065 ice_dev_set_link_up(dev); 2066 2067 /* Call get_link_info aq commond to enable/disable LSE */ 2068 ice_link_update(dev, 0); 2069 2070 pf->adapter_stopped = false; 2071 2072 return 0; 2073 2074 /* stop the started queues if failed to start all queues */ 2075 rx_err: 2076 for (i = 0; i < nb_rxq; i++) 2077 ice_rx_queue_stop(dev, i); 2078 tx_err: 2079 for (i = 0; i < nb_txq; i++) 2080 ice_tx_queue_stop(dev, i); 2081 2082 return -EIO; 2083 } 2084 2085 static int 2086 ice_dev_reset(struct rte_eth_dev *dev) 2087 { 2088 int ret; 2089 2090 if (dev->data->sriov.active) 2091 return -ENOTSUP; 2092 2093 ret = ice_dev_uninit(dev); 2094 if (ret) { 2095 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 2096 return -ENXIO; 2097 } 2098 2099 ret = ice_dev_init(dev); 2100 if (ret) { 2101 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 2102 return -ENXIO; 2103 } 2104 2105 return 0; 2106 } 2107 2108 static void 2109 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2110 { 2111 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2112 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2113 struct ice_vsi *vsi = pf->main_vsi; 2114 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 2115 bool is_safe_mode = pf->adapter->is_safe_mode; 2116 u64 phy_type_low; 2117 u64 phy_type_high; 2118 2119 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 2120 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 2121 dev_info->max_rx_queues = vsi->nb_qps; 2122 dev_info->max_tx_queues = vsi->nb_qps; 2123 dev_info->max_mac_addrs = vsi->max_macaddrs; 2124 dev_info->max_vfs = pci_dev->max_vfs; 2125 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 2126 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 2127 2128 dev_info->rx_offload_capa = 2129 DEV_RX_OFFLOAD_VLAN_STRIP | 2130 DEV_RX_OFFLOAD_JUMBO_FRAME | 2131 DEV_RX_OFFLOAD_KEEP_CRC | 2132 DEV_RX_OFFLOAD_SCATTER | 2133 DEV_RX_OFFLOAD_VLAN_FILTER; 2134 dev_info->tx_offload_capa = 2135 DEV_TX_OFFLOAD_VLAN_INSERT | 2136 DEV_TX_OFFLOAD_TCP_TSO | 2137 DEV_TX_OFFLOAD_MULTI_SEGS | 2138 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 2139 dev_info->flow_type_rss_offloads = 0; 2140 2141 if (!is_safe_mode) { 2142 dev_info->rx_offload_capa |= 2143 DEV_RX_OFFLOAD_IPV4_CKSUM | 2144 DEV_RX_OFFLOAD_UDP_CKSUM | 2145 DEV_RX_OFFLOAD_TCP_CKSUM | 2146 DEV_RX_OFFLOAD_QINQ_STRIP | 2147 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2148 DEV_RX_OFFLOAD_VLAN_EXTEND; 2149 dev_info->tx_offload_capa |= 2150 DEV_TX_OFFLOAD_QINQ_INSERT | 2151 DEV_TX_OFFLOAD_IPV4_CKSUM | 2152 DEV_TX_OFFLOAD_UDP_CKSUM | 2153 DEV_TX_OFFLOAD_TCP_CKSUM | 2154 DEV_TX_OFFLOAD_SCTP_CKSUM | 2155 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2156 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 2157 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 2158 } 2159 2160 dev_info->rx_queue_offload_capa = 0; 2161 dev_info->tx_queue_offload_capa = 0; 2162 2163 dev_info->reta_size = pf->hash_lut_size; 2164 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2165 2166 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2167 .rx_thresh = { 2168 .pthresh = ICE_DEFAULT_RX_PTHRESH, 2169 .hthresh = ICE_DEFAULT_RX_HTHRESH, 2170 .wthresh = ICE_DEFAULT_RX_WTHRESH, 2171 }, 2172 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 2173 .rx_drop_en = 0, 2174 .offloads = 0, 2175 }; 2176 2177 dev_info->default_txconf = (struct rte_eth_txconf) { 2178 .tx_thresh = { 2179 .pthresh = ICE_DEFAULT_TX_PTHRESH, 2180 .hthresh = ICE_DEFAULT_TX_HTHRESH, 2181 .wthresh = ICE_DEFAULT_TX_WTHRESH, 2182 }, 2183 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 2184 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 2185 .offloads = 0, 2186 }; 2187 2188 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 2189 .nb_max = ICE_MAX_RING_DESC, 2190 .nb_min = ICE_MIN_RING_DESC, 2191 .nb_align = ICE_ALIGN_RING_DESC, 2192 }; 2193 2194 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 2195 .nb_max = ICE_MAX_RING_DESC, 2196 .nb_min = ICE_MIN_RING_DESC, 2197 .nb_align = ICE_ALIGN_RING_DESC, 2198 }; 2199 2200 dev_info->speed_capa = ETH_LINK_SPEED_10M | 2201 ETH_LINK_SPEED_100M | 2202 ETH_LINK_SPEED_1G | 2203 ETH_LINK_SPEED_2_5G | 2204 ETH_LINK_SPEED_5G | 2205 ETH_LINK_SPEED_10G | 2206 ETH_LINK_SPEED_20G | 2207 ETH_LINK_SPEED_25G; 2208 2209 phy_type_low = hw->port_info->phy.phy_type_low; 2210 phy_type_high = hw->port_info->phy.phy_type_high; 2211 2212 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 2213 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 2214 2215 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 2216 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 2217 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 2218 2219 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 2220 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 2221 2222 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 2223 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 2224 dev_info->default_rxportconf.nb_queues = 1; 2225 dev_info->default_txportconf.nb_queues = 1; 2226 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 2227 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 2228 } 2229 2230 static inline int 2231 ice_atomic_read_link_status(struct rte_eth_dev *dev, 2232 struct rte_eth_link *link) 2233 { 2234 struct rte_eth_link *dst = link; 2235 struct rte_eth_link *src = &dev->data->dev_link; 2236 2237 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 2238 *(uint64_t *)src) == 0) 2239 return -1; 2240 2241 return 0; 2242 } 2243 2244 static inline int 2245 ice_atomic_write_link_status(struct rte_eth_dev *dev, 2246 struct rte_eth_link *link) 2247 { 2248 struct rte_eth_link *dst = &dev->data->dev_link; 2249 struct rte_eth_link *src = link; 2250 2251 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 2252 *(uint64_t *)src) == 0) 2253 return -1; 2254 2255 return 0; 2256 } 2257 2258 static int 2259 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2260 { 2261 #define CHECK_INTERVAL 100 /* 100ms */ 2262 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 2263 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2264 struct ice_link_status link_status; 2265 struct rte_eth_link link, old; 2266 int status; 2267 unsigned int rep_cnt = MAX_REPEAT_TIME; 2268 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2269 2270 memset(&link, 0, sizeof(link)); 2271 memset(&old, 0, sizeof(old)); 2272 memset(&link_status, 0, sizeof(link_status)); 2273 ice_atomic_read_link_status(dev, &old); 2274 2275 do { 2276 /* Get link status information from hardware */ 2277 status = ice_aq_get_link_info(hw->port_info, enable_lse, 2278 &link_status, NULL); 2279 if (status != ICE_SUCCESS) { 2280 link.link_speed = ETH_SPEED_NUM_100M; 2281 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2282 PMD_DRV_LOG(ERR, "Failed to get link info"); 2283 goto out; 2284 } 2285 2286 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 2287 if (!wait_to_complete || link.link_status) 2288 break; 2289 2290 rte_delay_ms(CHECK_INTERVAL); 2291 } while (--rep_cnt); 2292 2293 if (!link.link_status) 2294 goto out; 2295 2296 /* Full-duplex operation at all supported speeds */ 2297 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2298 2299 /* Parse the link status */ 2300 switch (link_status.link_speed) { 2301 case ICE_AQ_LINK_SPEED_10MB: 2302 link.link_speed = ETH_SPEED_NUM_10M; 2303 break; 2304 case ICE_AQ_LINK_SPEED_100MB: 2305 link.link_speed = ETH_SPEED_NUM_100M; 2306 break; 2307 case ICE_AQ_LINK_SPEED_1000MB: 2308 link.link_speed = ETH_SPEED_NUM_1G; 2309 break; 2310 case ICE_AQ_LINK_SPEED_2500MB: 2311 link.link_speed = ETH_SPEED_NUM_2_5G; 2312 break; 2313 case ICE_AQ_LINK_SPEED_5GB: 2314 link.link_speed = ETH_SPEED_NUM_5G; 2315 break; 2316 case ICE_AQ_LINK_SPEED_10GB: 2317 link.link_speed = ETH_SPEED_NUM_10G; 2318 break; 2319 case ICE_AQ_LINK_SPEED_20GB: 2320 link.link_speed = ETH_SPEED_NUM_20G; 2321 break; 2322 case ICE_AQ_LINK_SPEED_25GB: 2323 link.link_speed = ETH_SPEED_NUM_25G; 2324 break; 2325 case ICE_AQ_LINK_SPEED_40GB: 2326 link.link_speed = ETH_SPEED_NUM_40G; 2327 break; 2328 case ICE_AQ_LINK_SPEED_50GB: 2329 link.link_speed = ETH_SPEED_NUM_50G; 2330 break; 2331 case ICE_AQ_LINK_SPEED_100GB: 2332 link.link_speed = ETH_SPEED_NUM_100G; 2333 break; 2334 case ICE_AQ_LINK_SPEED_UNKNOWN: 2335 default: 2336 PMD_DRV_LOG(ERR, "Unknown link speed"); 2337 link.link_speed = ETH_SPEED_NUM_NONE; 2338 break; 2339 } 2340 2341 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2342 ETH_LINK_SPEED_FIXED); 2343 2344 out: 2345 ice_atomic_write_link_status(dev, &link); 2346 if (link.link_status == old.link_status) 2347 return -1; 2348 2349 return 0; 2350 } 2351 2352 /* Force the physical link state by getting the current PHY capabilities from 2353 * hardware and setting the PHY config based on the determined capabilities. If 2354 * link changes, link event will be triggered because both the Enable Automatic 2355 * Link Update and LESM Enable bits are set when setting the PHY capabilities. 2356 */ 2357 static enum ice_status 2358 ice_force_phys_link_state(struct ice_hw *hw, bool link_up) 2359 { 2360 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2361 struct ice_aqc_get_phy_caps_data *pcaps; 2362 struct ice_port_info *pi; 2363 enum ice_status status; 2364 2365 if (!hw || !hw->port_info) 2366 return ICE_ERR_PARAM; 2367 2368 pi = hw->port_info; 2369 2370 pcaps = (struct ice_aqc_get_phy_caps_data *) 2371 ice_malloc(hw, sizeof(*pcaps)); 2372 if (!pcaps) 2373 return ICE_ERR_NO_MEMORY; 2374 2375 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2376 NULL); 2377 if (status) 2378 goto out; 2379 2380 /* No change in link */ 2381 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) && 2382 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) 2383 goto out; 2384 2385 cfg.phy_type_low = pcaps->phy_type_low; 2386 cfg.phy_type_high = pcaps->phy_type_high; 2387 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2388 cfg.low_power_ctrl = pcaps->low_power_ctrl; 2389 cfg.eee_cap = pcaps->eee_cap; 2390 cfg.eeer_value = pcaps->eeer_value; 2391 cfg.link_fec_opt = pcaps->link_fec_options; 2392 if (link_up) 2393 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 2394 else 2395 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 2396 2397 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2398 2399 out: 2400 ice_free(hw, pcaps); 2401 return status; 2402 } 2403 2404 static int 2405 ice_dev_set_link_up(struct rte_eth_dev *dev) 2406 { 2407 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2408 2409 return ice_force_phys_link_state(hw, true); 2410 } 2411 2412 static int 2413 ice_dev_set_link_down(struct rte_eth_dev *dev) 2414 { 2415 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2416 2417 return ice_force_phys_link_state(hw, false); 2418 } 2419 2420 static int 2421 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2422 { 2423 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2424 struct rte_eth_dev_data *dev_data = pf->dev_data; 2425 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 2426 2427 /* check if mtu is within the allowed range */ 2428 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 2429 return -EINVAL; 2430 2431 /* mtu setting is forbidden if port is start */ 2432 if (dev_data->dev_started) { 2433 PMD_DRV_LOG(ERR, 2434 "port %d must be stopped before configuration", 2435 dev_data->port_id); 2436 return -EBUSY; 2437 } 2438 2439 if (frame_size > RTE_ETHER_MAX_LEN) 2440 dev_data->dev_conf.rxmode.offloads |= 2441 DEV_RX_OFFLOAD_JUMBO_FRAME; 2442 else 2443 dev_data->dev_conf.rxmode.offloads &= 2444 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2445 2446 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2447 2448 return 0; 2449 } 2450 2451 static int ice_macaddr_set(struct rte_eth_dev *dev, 2452 struct rte_ether_addr *mac_addr) 2453 { 2454 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2455 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2456 struct ice_vsi *vsi = pf->main_vsi; 2457 struct ice_mac_filter *f; 2458 uint8_t flags = 0; 2459 int ret; 2460 2461 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 2462 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 2463 return -EINVAL; 2464 } 2465 2466 TAILQ_FOREACH(f, &vsi->mac_list, next) { 2467 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 2468 break; 2469 } 2470 2471 if (!f) { 2472 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 2473 return -EIO; 2474 } 2475 2476 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 2477 if (ret != ICE_SUCCESS) { 2478 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 2479 return -EIO; 2480 } 2481 ret = ice_add_mac_filter(vsi, mac_addr); 2482 if (ret != ICE_SUCCESS) { 2483 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 2484 return -EIO; 2485 } 2486 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN); 2487 2488 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 2489 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 2490 if (ret != ICE_SUCCESS) 2491 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 2492 2493 return 0; 2494 } 2495 2496 /* Add a MAC address, and update filters */ 2497 static int 2498 ice_macaddr_add(struct rte_eth_dev *dev, 2499 struct rte_ether_addr *mac_addr, 2500 __rte_unused uint32_t index, 2501 __rte_unused uint32_t pool) 2502 { 2503 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2504 struct ice_vsi *vsi = pf->main_vsi; 2505 int ret; 2506 2507 ret = ice_add_mac_filter(vsi, mac_addr); 2508 if (ret != ICE_SUCCESS) { 2509 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 2510 return -EINVAL; 2511 } 2512 2513 return ICE_SUCCESS; 2514 } 2515 2516 /* Remove a MAC address, and update filters */ 2517 static void 2518 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 2519 { 2520 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2521 struct ice_vsi *vsi = pf->main_vsi; 2522 struct rte_eth_dev_data *data = dev->data; 2523 struct rte_ether_addr *macaddr; 2524 int ret; 2525 2526 macaddr = &data->mac_addrs[index]; 2527 ret = ice_remove_mac_filter(vsi, macaddr); 2528 if (ret) { 2529 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 2530 return; 2531 } 2532 } 2533 2534 static int 2535 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 2536 { 2537 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2538 struct ice_vsi *vsi = pf->main_vsi; 2539 int ret; 2540 2541 PMD_INIT_FUNC_TRACE(); 2542 2543 if (on) { 2544 ret = ice_add_vlan_filter(vsi, vlan_id); 2545 if (ret < 0) { 2546 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 2547 return -EINVAL; 2548 } 2549 } else { 2550 ret = ice_remove_vlan_filter(vsi, vlan_id); 2551 if (ret < 0) { 2552 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 2553 return -EINVAL; 2554 } 2555 } 2556 2557 return 0; 2558 } 2559 2560 /* Configure vlan filter on or off */ 2561 static int 2562 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 2563 { 2564 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2565 struct ice_vsi_ctx ctxt; 2566 uint8_t sec_flags, sw_flags2; 2567 int ret = 0; 2568 2569 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 2570 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 2571 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 2572 2573 if (on) { 2574 vsi->info.sec_flags |= sec_flags; 2575 vsi->info.sw_flags2 |= sw_flags2; 2576 } else { 2577 vsi->info.sec_flags &= ~sec_flags; 2578 vsi->info.sw_flags2 &= ~sw_flags2; 2579 } 2580 vsi->info.sw_id = hw->port_info->sw_id; 2581 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2582 ctxt.info.valid_sections = 2583 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 2584 ICE_AQ_VSI_PROP_SECURITY_VALID); 2585 ctxt.vsi_num = vsi->vsi_id; 2586 2587 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2588 if (ret) { 2589 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 2590 on ? "enable" : "disable"); 2591 return -EINVAL; 2592 } else { 2593 vsi->info.valid_sections |= 2594 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 2595 ICE_AQ_VSI_PROP_SECURITY_VALID); 2596 } 2597 2598 /* consist with other drivers, allow untagged packet when vlan filter on */ 2599 if (on) 2600 ret = ice_add_vlan_filter(vsi, 0); 2601 else 2602 ret = ice_remove_vlan_filter(vsi, 0); 2603 2604 return 0; 2605 } 2606 2607 static int 2608 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 2609 { 2610 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2611 struct ice_vsi_ctx ctxt; 2612 uint8_t vlan_flags; 2613 int ret = 0; 2614 2615 /* Check if it has been already on or off */ 2616 if (vsi->info.valid_sections & 2617 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 2618 if (on) { 2619 if ((vsi->info.vlan_flags & 2620 ICE_AQ_VSI_VLAN_EMOD_M) == 2621 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) 2622 return 0; /* already on */ 2623 } else { 2624 if ((vsi->info.vlan_flags & 2625 ICE_AQ_VSI_VLAN_EMOD_M) == 2626 ICE_AQ_VSI_VLAN_EMOD_NOTHING) 2627 return 0; /* already off */ 2628 } 2629 } 2630 2631 if (on) 2632 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; 2633 else 2634 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; 2635 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); 2636 vsi->info.vlan_flags |= vlan_flags; 2637 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2638 ctxt.info.valid_sections = 2639 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2640 ctxt.vsi_num = vsi->vsi_id; 2641 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2642 if (ret) { 2643 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 2644 on ? "enable" : "disable"); 2645 return -EINVAL; 2646 } 2647 2648 vsi->info.valid_sections |= 2649 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2650 2651 return ret; 2652 } 2653 2654 static int 2655 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2656 { 2657 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2658 struct ice_vsi *vsi = pf->main_vsi; 2659 struct rte_eth_rxmode *rxmode; 2660 2661 rxmode = &dev->data->dev_conf.rxmode; 2662 if (mask & ETH_VLAN_FILTER_MASK) { 2663 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2664 ice_vsi_config_vlan_filter(vsi, TRUE); 2665 else 2666 ice_vsi_config_vlan_filter(vsi, FALSE); 2667 } 2668 2669 if (mask & ETH_VLAN_STRIP_MASK) { 2670 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2671 ice_vsi_config_vlan_stripping(vsi, TRUE); 2672 else 2673 ice_vsi_config_vlan_stripping(vsi, FALSE); 2674 } 2675 2676 if (mask & ETH_VLAN_EXTEND_MASK) { 2677 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2678 ice_vsi_config_double_vlan(vsi, TRUE); 2679 else 2680 ice_vsi_config_double_vlan(vsi, FALSE); 2681 } 2682 2683 return 0; 2684 } 2685 2686 static int 2687 ice_vlan_tpid_set(struct rte_eth_dev *dev, 2688 enum rte_vlan_type vlan_type, 2689 uint16_t tpid) 2690 { 2691 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2692 uint64_t reg_r = 0, reg_w = 0; 2693 uint16_t reg_id = 0; 2694 int ret = 0; 2695 int qinq = dev->data->dev_conf.rxmode.offloads & 2696 DEV_RX_OFFLOAD_VLAN_EXTEND; 2697 2698 switch (vlan_type) { 2699 case ETH_VLAN_TYPE_OUTER: 2700 if (qinq) 2701 reg_id = 3; 2702 else 2703 reg_id = 5; 2704 break; 2705 case ETH_VLAN_TYPE_INNER: 2706 if (qinq) { 2707 reg_id = 5; 2708 } else { 2709 PMD_DRV_LOG(ERR, 2710 "Unsupported vlan type in single vlan."); 2711 return -EINVAL; 2712 } 2713 break; 2714 default: 2715 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type); 2716 return -EINVAL; 2717 } 2718 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id)); 2719 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: " 2720 "0x%08"PRIx64"", reg_id, reg_r); 2721 2722 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M)); 2723 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S); 2724 if (reg_r == reg_w) { 2725 PMD_DRV_LOG(DEBUG, "No need to write"); 2726 return 0; 2727 } 2728 2729 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w); 2730 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to " 2731 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id); 2732 2733 return ret; 2734 } 2735 2736 static int 2737 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2738 { 2739 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 2740 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2741 int ret; 2742 2743 if (!lut) 2744 return -EINVAL; 2745 2746 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 2747 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE, 2748 lut, lut_size); 2749 if (ret) { 2750 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 2751 return -EINVAL; 2752 } 2753 } else { 2754 uint64_t *lut_dw = (uint64_t *)lut; 2755 uint16_t i, lut_size_dw = lut_size / 4; 2756 2757 for (i = 0; i < lut_size_dw; i++) 2758 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 2759 } 2760 2761 return 0; 2762 } 2763 2764 static int 2765 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2766 { 2767 struct ice_pf *pf; 2768 struct ice_hw *hw; 2769 int ret; 2770 2771 if (!vsi || !lut) 2772 return -EINVAL; 2773 2774 pf = ICE_VSI_TO_PF(vsi); 2775 hw = ICE_VSI_TO_HW(vsi); 2776 2777 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 2778 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE, 2779 lut, lut_size); 2780 if (ret) { 2781 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 2782 return -EINVAL; 2783 } 2784 } else { 2785 uint64_t *lut_dw = (uint64_t *)lut; 2786 uint16_t i, lut_size_dw = lut_size / 4; 2787 2788 for (i = 0; i < lut_size_dw; i++) 2789 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 2790 2791 ice_flush(hw); 2792 } 2793 2794 return 0; 2795 } 2796 2797 static int 2798 ice_rss_reta_update(struct rte_eth_dev *dev, 2799 struct rte_eth_rss_reta_entry64 *reta_conf, 2800 uint16_t reta_size) 2801 { 2802 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2803 uint16_t i, lut_size = pf->hash_lut_size; 2804 uint16_t idx, shift; 2805 uint8_t *lut; 2806 int ret; 2807 2808 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 2809 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 2810 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 2811 PMD_DRV_LOG(ERR, 2812 "The size of hash lookup table configured (%d)" 2813 "doesn't match the number hardware can " 2814 "supported (128, 512, 2048)", 2815 reta_size); 2816 return -EINVAL; 2817 } 2818 2819 /* It MUST use the current LUT size to get the RSS lookup table, 2820 * otherwise if will fail with -100 error code. 2821 */ 2822 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 2823 if (!lut) { 2824 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2825 return -ENOMEM; 2826 } 2827 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 2828 if (ret) 2829 goto out; 2830 2831 for (i = 0; i < reta_size; i++) { 2832 idx = i / RTE_RETA_GROUP_SIZE; 2833 shift = i % RTE_RETA_GROUP_SIZE; 2834 if (reta_conf[idx].mask & (1ULL << shift)) 2835 lut[i] = reta_conf[idx].reta[shift]; 2836 } 2837 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 2838 if (ret == 0 && lut_size != reta_size) { 2839 PMD_DRV_LOG(INFO, 2840 "The size of hash lookup table is changed from (%d) to (%d)", 2841 lut_size, reta_size); 2842 pf->hash_lut_size = reta_size; 2843 } 2844 2845 out: 2846 rte_free(lut); 2847 2848 return ret; 2849 } 2850 2851 static int 2852 ice_rss_reta_query(struct rte_eth_dev *dev, 2853 struct rte_eth_rss_reta_entry64 *reta_conf, 2854 uint16_t reta_size) 2855 { 2856 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2857 uint16_t i, lut_size = pf->hash_lut_size; 2858 uint16_t idx, shift; 2859 uint8_t *lut; 2860 int ret; 2861 2862 if (reta_size != lut_size) { 2863 PMD_DRV_LOG(ERR, 2864 "The size of hash lookup table configured (%d)" 2865 "doesn't match the number hardware can " 2866 "supported (%d)", 2867 reta_size, lut_size); 2868 return -EINVAL; 2869 } 2870 2871 lut = rte_zmalloc(NULL, reta_size, 0); 2872 if (!lut) { 2873 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2874 return -ENOMEM; 2875 } 2876 2877 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 2878 if (ret) 2879 goto out; 2880 2881 for (i = 0; i < reta_size; i++) { 2882 idx = i / RTE_RETA_GROUP_SIZE; 2883 shift = i % RTE_RETA_GROUP_SIZE; 2884 if (reta_conf[idx].mask & (1ULL << shift)) 2885 reta_conf[idx].reta[shift] = lut[i]; 2886 } 2887 2888 out: 2889 rte_free(lut); 2890 2891 return ret; 2892 } 2893 2894 static int 2895 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 2896 { 2897 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2898 int ret = 0; 2899 2900 if (!key || key_len == 0) { 2901 PMD_DRV_LOG(DEBUG, "No key to be configured"); 2902 return 0; 2903 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 2904 sizeof(uint32_t)) { 2905 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 2906 return -EINVAL; 2907 } 2908 2909 struct ice_aqc_get_set_rss_keys *key_dw = 2910 (struct ice_aqc_get_set_rss_keys *)key; 2911 2912 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 2913 if (ret) { 2914 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 2915 ret = -EINVAL; 2916 } 2917 2918 return ret; 2919 } 2920 2921 static int 2922 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 2923 { 2924 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2925 int ret; 2926 2927 if (!key || !key_len) 2928 return -EINVAL; 2929 2930 ret = ice_aq_get_rss_key 2931 (hw, vsi->idx, 2932 (struct ice_aqc_get_set_rss_keys *)key); 2933 if (ret) { 2934 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 2935 return -EINVAL; 2936 } 2937 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2938 2939 return 0; 2940 } 2941 2942 static int 2943 ice_rss_hash_update(struct rte_eth_dev *dev, 2944 struct rte_eth_rss_conf *rss_conf) 2945 { 2946 enum ice_status status = ICE_SUCCESS; 2947 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2948 struct ice_vsi *vsi = pf->main_vsi; 2949 2950 /* set hash key */ 2951 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 2952 if (status) 2953 return status; 2954 2955 /* TODO: hash enable config, ice_add_rss_cfg */ 2956 return 0; 2957 } 2958 2959 static int 2960 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 2961 struct rte_eth_rss_conf *rss_conf) 2962 { 2963 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2964 struct ice_vsi *vsi = pf->main_vsi; 2965 2966 ice_get_rss_key(vsi, rss_conf->rss_key, 2967 &rss_conf->rss_key_len); 2968 2969 /* TODO: default set to 0 as hf config is not supported now */ 2970 rss_conf->rss_hf = 0; 2971 return 0; 2972 } 2973 2974 static void 2975 ice_promisc_enable(struct rte_eth_dev *dev) 2976 { 2977 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2978 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2979 struct ice_vsi *vsi = pf->main_vsi; 2980 enum ice_status status; 2981 uint8_t pmask; 2982 2983 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 2984 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2985 2986 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 2987 if (status == ICE_ERR_ALREADY_EXISTS) 2988 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 2989 else if (status != ICE_SUCCESS) 2990 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 2991 } 2992 2993 static void 2994 ice_promisc_disable(struct rte_eth_dev *dev) 2995 { 2996 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2997 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2998 struct ice_vsi *vsi = pf->main_vsi; 2999 enum ice_status status; 3000 uint8_t pmask; 3001 3002 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 3003 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3004 3005 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 3006 if (status != ICE_SUCCESS) 3007 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 3008 } 3009 3010 static void 3011 ice_allmulti_enable(struct rte_eth_dev *dev) 3012 { 3013 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3014 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3015 struct ice_vsi *vsi = pf->main_vsi; 3016 enum ice_status status; 3017 uint8_t pmask; 3018 3019 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3020 3021 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 3022 if (status != ICE_SUCCESS) 3023 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 3024 } 3025 3026 static void 3027 ice_allmulti_disable(struct rte_eth_dev *dev) 3028 { 3029 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3030 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3031 struct ice_vsi *vsi = pf->main_vsi; 3032 enum ice_status status; 3033 uint8_t pmask; 3034 3035 if (dev->data->promiscuous == 1) 3036 return; /* must remain in all_multicast mode */ 3037 3038 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3039 3040 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 3041 if (status != ICE_SUCCESS) 3042 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 3043 } 3044 3045 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 3046 uint16_t queue_id) 3047 { 3048 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3049 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3050 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3051 uint32_t val; 3052 uint16_t msix_intr; 3053 3054 msix_intr = intr_handle->intr_vec[queue_id]; 3055 3056 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 3057 GLINT_DYN_CTL_ITR_INDX_M; 3058 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 3059 3060 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 3061 rte_intr_ack(&pci_dev->intr_handle); 3062 3063 return 0; 3064 } 3065 3066 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 3067 uint16_t queue_id) 3068 { 3069 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3070 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3071 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3072 uint16_t msix_intr; 3073 3074 msix_intr = intr_handle->intr_vec[queue_id]; 3075 3076 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 3077 3078 return 0; 3079 } 3080 3081 static int 3082 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3083 { 3084 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3085 u32 full_ver; 3086 u8 ver, patch; 3087 u16 build; 3088 int ret; 3089 3090 full_ver = hw->nvm.oem_ver; 3091 ver = (u8)(full_ver >> 24); 3092 build = (u16)((full_ver >> 8) & 0xffff); 3093 patch = (u8)(full_ver & 0xff); 3094 3095 ret = snprintf(fw_version, fw_size, 3096 "%d.%d%d 0x%08x %d.%d.%d", 3097 ((hw->nvm.ver >> 12) & 0xf), 3098 ((hw->nvm.ver >> 4) & 0xff), 3099 (hw->nvm.ver & 0xf), hw->nvm.eetrack, 3100 ver, build, patch); 3101 3102 /* add the size of '\0' */ 3103 ret += 1; 3104 if (fw_size < (u32)ret) 3105 return ret; 3106 else 3107 return 0; 3108 } 3109 3110 static int 3111 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 3112 { 3113 struct ice_hw *hw; 3114 struct ice_vsi_ctx ctxt; 3115 uint8_t vlan_flags = 0; 3116 int ret; 3117 3118 if (!vsi || !info) { 3119 PMD_DRV_LOG(ERR, "invalid parameters"); 3120 return -EINVAL; 3121 } 3122 3123 if (info->on) { 3124 vsi->info.pvid = info->config.pvid; 3125 /** 3126 * If insert pvid is enabled, only tagged pkts are 3127 * allowed to be sent out. 3128 */ 3129 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | 3130 ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 3131 } else { 3132 vsi->info.pvid = 0; 3133 if (info->config.reject.tagged == 0) 3134 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; 3135 3136 if (info->config.reject.untagged == 0) 3137 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 3138 } 3139 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | 3140 ICE_AQ_VSI_VLAN_MODE_M); 3141 vsi->info.vlan_flags |= vlan_flags; 3142 memset(&ctxt, 0, sizeof(ctxt)); 3143 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 3144 ctxt.info.valid_sections = 3145 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3146 ctxt.vsi_num = vsi->vsi_id; 3147 3148 hw = ICE_VSI_TO_HW(vsi); 3149 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 3150 if (ret != ICE_SUCCESS) { 3151 PMD_DRV_LOG(ERR, 3152 "update VSI for VLAN insert failed, err %d", 3153 ret); 3154 return -EINVAL; 3155 } 3156 3157 vsi->info.valid_sections |= 3158 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3159 3160 return ret; 3161 } 3162 3163 static int 3164 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 3165 { 3166 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3167 struct ice_vsi *vsi = pf->main_vsi; 3168 struct rte_eth_dev_data *data = pf->dev_data; 3169 struct ice_vsi_vlan_pvid_info info; 3170 int ret; 3171 3172 memset(&info, 0, sizeof(info)); 3173 info.on = on; 3174 if (info.on) { 3175 info.config.pvid = pvid; 3176 } else { 3177 info.config.reject.tagged = 3178 data->dev_conf.txmode.hw_vlan_reject_tagged; 3179 info.config.reject.untagged = 3180 data->dev_conf.txmode.hw_vlan_reject_untagged; 3181 } 3182 3183 ret = ice_vsi_vlan_pvid_set(vsi, &info); 3184 if (ret < 0) { 3185 PMD_DRV_LOG(ERR, "Failed to set pvid."); 3186 return -EINVAL; 3187 } 3188 3189 return 0; 3190 } 3191 3192 static int 3193 ice_get_eeprom_length(struct rte_eth_dev *dev) 3194 { 3195 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3196 3197 /* Convert word count to byte count */ 3198 return hw->nvm.sr_words << 1; 3199 } 3200 3201 static int 3202 ice_get_eeprom(struct rte_eth_dev *dev, 3203 struct rte_dev_eeprom_info *eeprom) 3204 { 3205 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3206 uint16_t *data = eeprom->data; 3207 uint16_t first_word, last_word, nwords; 3208 enum ice_status status = ICE_SUCCESS; 3209 3210 first_word = eeprom->offset >> 1; 3211 last_word = (eeprom->offset + eeprom->length - 1) >> 1; 3212 nwords = last_word - first_word + 1; 3213 3214 if (first_word >= hw->nvm.sr_words || 3215 last_word >= hw->nvm.sr_words) { 3216 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 3217 return -EINVAL; 3218 } 3219 3220 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 3221 3222 status = ice_read_sr_buf(hw, first_word, &nwords, data); 3223 if (status) { 3224 PMD_DRV_LOG(ERR, "EEPROM read failed."); 3225 eeprom->length = sizeof(uint16_t) * nwords; 3226 return -EIO; 3227 } 3228 3229 return 0; 3230 } 3231 3232 static void 3233 ice_stat_update_32(struct ice_hw *hw, 3234 uint32_t reg, 3235 bool offset_loaded, 3236 uint64_t *offset, 3237 uint64_t *stat) 3238 { 3239 uint64_t new_data; 3240 3241 new_data = (uint64_t)ICE_READ_REG(hw, reg); 3242 if (!offset_loaded) 3243 *offset = new_data; 3244 3245 if (new_data >= *offset) 3246 *stat = (uint64_t)(new_data - *offset); 3247 else 3248 *stat = (uint64_t)((new_data + 3249 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 3250 - *offset); 3251 } 3252 3253 static void 3254 ice_stat_update_40(struct ice_hw *hw, 3255 uint32_t hireg, 3256 uint32_t loreg, 3257 bool offset_loaded, 3258 uint64_t *offset, 3259 uint64_t *stat) 3260 { 3261 uint64_t new_data; 3262 3263 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 3264 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 3265 ICE_32_BIT_WIDTH; 3266 3267 if (!offset_loaded) 3268 *offset = new_data; 3269 3270 if (new_data >= *offset) 3271 *stat = new_data - *offset; 3272 else 3273 *stat = (uint64_t)((new_data + 3274 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 3275 *offset); 3276 3277 *stat &= ICE_40_BIT_MASK; 3278 } 3279 3280 /* Get all the statistics of a VSI */ 3281 static void 3282 ice_update_vsi_stats(struct ice_vsi *vsi) 3283 { 3284 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 3285 struct ice_eth_stats *nes = &vsi->eth_stats; 3286 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3287 int idx = rte_le_to_cpu_16(vsi->vsi_id); 3288 3289 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 3290 vsi->offset_loaded, &oes->rx_bytes, 3291 &nes->rx_bytes); 3292 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 3293 vsi->offset_loaded, &oes->rx_unicast, 3294 &nes->rx_unicast); 3295 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 3296 vsi->offset_loaded, &oes->rx_multicast, 3297 &nes->rx_multicast); 3298 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 3299 vsi->offset_loaded, &oes->rx_broadcast, 3300 &nes->rx_broadcast); 3301 /* exclude CRC bytes */ 3302 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 3303 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 3304 3305 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 3306 &oes->rx_discards, &nes->rx_discards); 3307 /* GLV_REPC not supported */ 3308 /* GLV_RMPC not supported */ 3309 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 3310 &oes->rx_unknown_protocol, 3311 &nes->rx_unknown_protocol); 3312 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 3313 vsi->offset_loaded, &oes->tx_bytes, 3314 &nes->tx_bytes); 3315 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 3316 vsi->offset_loaded, &oes->tx_unicast, 3317 &nes->tx_unicast); 3318 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 3319 vsi->offset_loaded, &oes->tx_multicast, 3320 &nes->tx_multicast); 3321 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 3322 vsi->offset_loaded, &oes->tx_broadcast, 3323 &nes->tx_broadcast); 3324 /* GLV_TDPC not supported */ 3325 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 3326 &oes->tx_errors, &nes->tx_errors); 3327 vsi->offset_loaded = true; 3328 3329 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 3330 vsi->vsi_id); 3331 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 3332 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 3333 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 3334 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 3335 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 3336 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3337 nes->rx_unknown_protocol); 3338 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 3339 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 3340 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 3341 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 3342 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 3343 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 3344 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 3345 vsi->vsi_id); 3346 } 3347 3348 static void 3349 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 3350 { 3351 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 3352 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 3353 3354 /* Get statistics of struct ice_eth_stats */ 3355 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 3356 GLPRT_GORCL(hw->port_info->lport), 3357 pf->offset_loaded, &os->eth.rx_bytes, 3358 &ns->eth.rx_bytes); 3359 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 3360 GLPRT_UPRCL(hw->port_info->lport), 3361 pf->offset_loaded, &os->eth.rx_unicast, 3362 &ns->eth.rx_unicast); 3363 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 3364 GLPRT_MPRCL(hw->port_info->lport), 3365 pf->offset_loaded, &os->eth.rx_multicast, 3366 &ns->eth.rx_multicast); 3367 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 3368 GLPRT_BPRCL(hw->port_info->lport), 3369 pf->offset_loaded, &os->eth.rx_broadcast, 3370 &ns->eth.rx_broadcast); 3371 ice_stat_update_32(hw, PRTRPB_RDPC, 3372 pf->offset_loaded, &os->eth.rx_discards, 3373 &ns->eth.rx_discards); 3374 3375 /* Workaround: CRC size should not be included in byte statistics, 3376 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 3377 * packet. 3378 */ 3379 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 3380 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 3381 3382 /* GLPRT_REPC not supported */ 3383 /* GLPRT_RMPC not supported */ 3384 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 3385 pf->offset_loaded, 3386 &os->eth.rx_unknown_protocol, 3387 &ns->eth.rx_unknown_protocol); 3388 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 3389 GLPRT_GOTCL(hw->port_info->lport), 3390 pf->offset_loaded, &os->eth.tx_bytes, 3391 &ns->eth.tx_bytes); 3392 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 3393 GLPRT_UPTCL(hw->port_info->lport), 3394 pf->offset_loaded, &os->eth.tx_unicast, 3395 &ns->eth.tx_unicast); 3396 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 3397 GLPRT_MPTCL(hw->port_info->lport), 3398 pf->offset_loaded, &os->eth.tx_multicast, 3399 &ns->eth.tx_multicast); 3400 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 3401 GLPRT_BPTCL(hw->port_info->lport), 3402 pf->offset_loaded, &os->eth.tx_broadcast, 3403 &ns->eth.tx_broadcast); 3404 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 3405 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 3406 3407 /* GLPRT_TEPC not supported */ 3408 3409 /* additional port specific stats */ 3410 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 3411 pf->offset_loaded, &os->tx_dropped_link_down, 3412 &ns->tx_dropped_link_down); 3413 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 3414 pf->offset_loaded, &os->crc_errors, 3415 &ns->crc_errors); 3416 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 3417 pf->offset_loaded, &os->illegal_bytes, 3418 &ns->illegal_bytes); 3419 /* GLPRT_ERRBC not supported */ 3420 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 3421 pf->offset_loaded, &os->mac_local_faults, 3422 &ns->mac_local_faults); 3423 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 3424 pf->offset_loaded, &os->mac_remote_faults, 3425 &ns->mac_remote_faults); 3426 3427 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 3428 pf->offset_loaded, &os->rx_len_errors, 3429 &ns->rx_len_errors); 3430 3431 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 3432 pf->offset_loaded, &os->link_xon_rx, 3433 &ns->link_xon_rx); 3434 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 3435 pf->offset_loaded, &os->link_xoff_rx, 3436 &ns->link_xoff_rx); 3437 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 3438 pf->offset_loaded, &os->link_xon_tx, 3439 &ns->link_xon_tx); 3440 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 3441 pf->offset_loaded, &os->link_xoff_tx, 3442 &ns->link_xoff_tx); 3443 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 3444 GLPRT_PRC64L(hw->port_info->lport), 3445 pf->offset_loaded, &os->rx_size_64, 3446 &ns->rx_size_64); 3447 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 3448 GLPRT_PRC127L(hw->port_info->lport), 3449 pf->offset_loaded, &os->rx_size_127, 3450 &ns->rx_size_127); 3451 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 3452 GLPRT_PRC255L(hw->port_info->lport), 3453 pf->offset_loaded, &os->rx_size_255, 3454 &ns->rx_size_255); 3455 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 3456 GLPRT_PRC511L(hw->port_info->lport), 3457 pf->offset_loaded, &os->rx_size_511, 3458 &ns->rx_size_511); 3459 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 3460 GLPRT_PRC1023L(hw->port_info->lport), 3461 pf->offset_loaded, &os->rx_size_1023, 3462 &ns->rx_size_1023); 3463 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 3464 GLPRT_PRC1522L(hw->port_info->lport), 3465 pf->offset_loaded, &os->rx_size_1522, 3466 &ns->rx_size_1522); 3467 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 3468 GLPRT_PRC9522L(hw->port_info->lport), 3469 pf->offset_loaded, &os->rx_size_big, 3470 &ns->rx_size_big); 3471 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 3472 pf->offset_loaded, &os->rx_undersize, 3473 &ns->rx_undersize); 3474 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 3475 pf->offset_loaded, &os->rx_fragments, 3476 &ns->rx_fragments); 3477 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 3478 pf->offset_loaded, &os->rx_oversize, 3479 &ns->rx_oversize); 3480 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 3481 pf->offset_loaded, &os->rx_jabber, 3482 &ns->rx_jabber); 3483 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 3484 GLPRT_PTC64L(hw->port_info->lport), 3485 pf->offset_loaded, &os->tx_size_64, 3486 &ns->tx_size_64); 3487 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 3488 GLPRT_PTC127L(hw->port_info->lport), 3489 pf->offset_loaded, &os->tx_size_127, 3490 &ns->tx_size_127); 3491 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 3492 GLPRT_PTC255L(hw->port_info->lport), 3493 pf->offset_loaded, &os->tx_size_255, 3494 &ns->tx_size_255); 3495 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 3496 GLPRT_PTC511L(hw->port_info->lport), 3497 pf->offset_loaded, &os->tx_size_511, 3498 &ns->tx_size_511); 3499 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 3500 GLPRT_PTC1023L(hw->port_info->lport), 3501 pf->offset_loaded, &os->tx_size_1023, 3502 &ns->tx_size_1023); 3503 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 3504 GLPRT_PTC1522L(hw->port_info->lport), 3505 pf->offset_loaded, &os->tx_size_1522, 3506 &ns->tx_size_1522); 3507 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 3508 GLPRT_PTC9522L(hw->port_info->lport), 3509 pf->offset_loaded, &os->tx_size_big, 3510 &ns->tx_size_big); 3511 3512 /* GLPRT_MSPDC not supported */ 3513 /* GLPRT_XEC not supported */ 3514 3515 pf->offset_loaded = true; 3516 3517 if (pf->main_vsi) 3518 ice_update_vsi_stats(pf->main_vsi); 3519 } 3520 3521 /* Get all statistics of a port */ 3522 static int 3523 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3524 { 3525 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3526 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3527 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 3528 3529 /* call read registers - updates values, now write them to struct */ 3530 ice_read_stats_registers(pf, hw); 3531 3532 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 3533 pf->main_vsi->eth_stats.rx_multicast + 3534 pf->main_vsi->eth_stats.rx_broadcast - 3535 pf->main_vsi->eth_stats.rx_discards; 3536 stats->opackets = ns->eth.tx_unicast + 3537 ns->eth.tx_multicast + 3538 ns->eth.tx_broadcast; 3539 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 3540 stats->obytes = ns->eth.tx_bytes; 3541 stats->oerrors = ns->eth.tx_errors + 3542 pf->main_vsi->eth_stats.tx_errors; 3543 3544 /* Rx Errors */ 3545 stats->imissed = ns->eth.rx_discards + 3546 pf->main_vsi->eth_stats.rx_discards; 3547 stats->ierrors = ns->crc_errors + 3548 ns->rx_undersize + 3549 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 3550 3551 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 3552 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 3553 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 3554 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 3555 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 3556 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 3557 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 3558 pf->main_vsi->eth_stats.rx_discards); 3559 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3560 ns->eth.rx_unknown_protocol); 3561 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 3562 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 3563 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 3564 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 3565 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 3566 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 3567 pf->main_vsi->eth_stats.tx_discards); 3568 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 3569 3570 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 3571 ns->tx_dropped_link_down); 3572 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 3573 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 3574 ns->illegal_bytes); 3575 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 3576 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 3577 ns->mac_local_faults); 3578 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 3579 ns->mac_remote_faults); 3580 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 3581 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 3582 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 3583 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 3584 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 3585 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 3586 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 3587 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 3588 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 3589 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 3590 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 3591 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 3592 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 3593 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 3594 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 3595 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 3596 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 3597 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 3598 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 3599 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 3600 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 3601 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 3602 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 3603 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 3604 return 0; 3605 } 3606 3607 /* Reset the statistics */ 3608 static void 3609 ice_stats_reset(struct rte_eth_dev *dev) 3610 { 3611 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3612 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3613 3614 /* Mark PF and VSI stats to update the offset, aka "reset" */ 3615 pf->offset_loaded = false; 3616 if (pf->main_vsi) 3617 pf->main_vsi->offset_loaded = false; 3618 3619 /* read the stats, reading current register values into offset */ 3620 ice_read_stats_registers(pf, hw); 3621 } 3622 3623 static uint32_t 3624 ice_xstats_calc_num(void) 3625 { 3626 uint32_t num; 3627 3628 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 3629 3630 return num; 3631 } 3632 3633 static int 3634 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3635 unsigned int n) 3636 { 3637 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3638 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3639 unsigned int i; 3640 unsigned int count; 3641 struct ice_hw_port_stats *hw_stats = &pf->stats; 3642 3643 count = ice_xstats_calc_num(); 3644 if (n < count) 3645 return count; 3646 3647 ice_read_stats_registers(pf, hw); 3648 3649 if (!xstats) 3650 return 0; 3651 3652 count = 0; 3653 3654 /* Get stats from ice_eth_stats struct */ 3655 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 3656 xstats[count].value = 3657 *(uint64_t *)((char *)&hw_stats->eth + 3658 ice_stats_strings[i].offset); 3659 xstats[count].id = count; 3660 count++; 3661 } 3662 3663 /* Get individiual stats from ice_hw_port struct */ 3664 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 3665 xstats[count].value = 3666 *(uint64_t *)((char *)hw_stats + 3667 ice_hw_port_strings[i].offset); 3668 xstats[count].id = count; 3669 count++; 3670 } 3671 3672 return count; 3673 } 3674 3675 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3676 struct rte_eth_xstat_name *xstats_names, 3677 __rte_unused unsigned int limit) 3678 { 3679 unsigned int count = 0; 3680 unsigned int i; 3681 3682 if (!xstats_names) 3683 return ice_xstats_calc_num(); 3684 3685 /* Note: limit checked in rte_eth_xstats_names() */ 3686 3687 /* Get stats from ice_eth_stats struct */ 3688 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 3689 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 3690 sizeof(xstats_names[count].name)); 3691 count++; 3692 } 3693 3694 /* Get individiual stats from ice_hw_port struct */ 3695 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 3696 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 3697 sizeof(xstats_names[count].name)); 3698 count++; 3699 } 3700 3701 return count; 3702 } 3703 3704 static int 3705 ice_dev_filter_ctrl(struct rte_eth_dev *dev, 3706 enum rte_filter_type filter_type, 3707 enum rte_filter_op filter_op, 3708 void *arg) 3709 { 3710 int ret = 0; 3711 3712 if (!dev) 3713 return -EINVAL; 3714 3715 switch (filter_type) { 3716 case RTE_ETH_FILTER_GENERIC: 3717 if (filter_op != RTE_ETH_FILTER_GET) 3718 return -EINVAL; 3719 *(const void **)arg = &ice_flow_ops; 3720 break; 3721 default: 3722 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 3723 filter_type); 3724 ret = -EINVAL; 3725 break; 3726 } 3727 3728 return ret; 3729 } 3730 3731 /* Add UDP tunneling port */ 3732 static int 3733 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 3734 struct rte_eth_udp_tunnel *udp_tunnel) 3735 { 3736 int ret = 0; 3737 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3738 3739 if (udp_tunnel == NULL) 3740 return -EINVAL; 3741 3742 switch (udp_tunnel->prot_type) { 3743 case RTE_TUNNEL_TYPE_VXLAN: 3744 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); 3745 break; 3746 default: 3747 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 3748 ret = -EINVAL; 3749 break; 3750 } 3751 3752 return ret; 3753 } 3754 3755 /* Delete UDP tunneling port */ 3756 static int 3757 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 3758 struct rte_eth_udp_tunnel *udp_tunnel) 3759 { 3760 int ret = 0; 3761 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3762 3763 if (udp_tunnel == NULL) 3764 return -EINVAL; 3765 3766 switch (udp_tunnel->prot_type) { 3767 case RTE_TUNNEL_TYPE_VXLAN: 3768 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); 3769 break; 3770 default: 3771 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 3772 ret = -EINVAL; 3773 break; 3774 } 3775 3776 return ret; 3777 } 3778 3779 static int 3780 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3781 struct rte_pci_device *pci_dev) 3782 { 3783 return rte_eth_dev_pci_generic_probe(pci_dev, 3784 sizeof(struct ice_adapter), 3785 ice_dev_init); 3786 } 3787 3788 static int 3789 ice_pci_remove(struct rte_pci_device *pci_dev) 3790 { 3791 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 3792 } 3793 3794 static struct rte_pci_driver rte_ice_pmd = { 3795 .id_table = pci_id_ice_map, 3796 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3797 .probe = ice_pci_probe, 3798 .remove = ice_pci_remove, 3799 }; 3800 3801 /** 3802 * Driver initialization routine. 3803 * Invoked once at EAL init time. 3804 * Register itself as the [Poll Mode] Driver of PCI devices. 3805 */ 3806 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 3807 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 3808 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 3809 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 3810 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"); 3811 3812 RTE_INIT(ice_init_log) 3813 { 3814 ice_logtype_init = rte_log_register("pmd.net.ice.init"); 3815 if (ice_logtype_init >= 0) 3816 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE); 3817 ice_logtype_driver = rte_log_register("pmd.net.ice.driver"); 3818 if (ice_logtype_driver >= 0) 3819 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE); 3820 } 3821