1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_ethdev_pci.h> 6 7 #include "base/ice_sched.h" 8 #include "ice_ethdev.h" 9 #include "ice_rxtx.h" 10 11 #define ICE_MAX_QP_NUM "max_queue_pair_num" 12 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 13 14 int ice_logtype_init; 15 int ice_logtype_driver; 16 17 static int ice_dev_configure(struct rte_eth_dev *dev); 18 static int ice_dev_start(struct rte_eth_dev *dev); 19 static void ice_dev_stop(struct rte_eth_dev *dev); 20 static void ice_dev_close(struct rte_eth_dev *dev); 21 static int ice_dev_reset(struct rte_eth_dev *dev); 22 static void ice_dev_info_get(struct rte_eth_dev *dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ice_link_update(struct rte_eth_dev *dev, 25 int wait_to_complete); 26 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 27 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 28 static int ice_vlan_tpid_set(struct rte_eth_dev *dev, 29 enum rte_vlan_type vlan_type, 30 uint16_t tpid); 31 static int ice_rss_reta_update(struct rte_eth_dev *dev, 32 struct rte_eth_rss_reta_entry64 *reta_conf, 33 uint16_t reta_size); 34 static int ice_rss_reta_query(struct rte_eth_dev *dev, 35 struct rte_eth_rss_reta_entry64 *reta_conf, 36 uint16_t reta_size); 37 static int ice_rss_hash_update(struct rte_eth_dev *dev, 38 struct rte_eth_rss_conf *rss_conf); 39 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 40 struct rte_eth_rss_conf *rss_conf); 41 static void ice_promisc_enable(struct rte_eth_dev *dev); 42 static void ice_promisc_disable(struct rte_eth_dev *dev); 43 static void ice_allmulti_enable(struct rte_eth_dev *dev); 44 static void ice_allmulti_disable(struct rte_eth_dev *dev); 45 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 46 uint16_t vlan_id, 47 int on); 48 static int ice_macaddr_set(struct rte_eth_dev *dev, 49 struct ether_addr *mac_addr); 50 static int ice_macaddr_add(struct rte_eth_dev *dev, 51 struct ether_addr *mac_addr, 52 __rte_unused uint32_t index, 53 uint32_t pool); 54 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 55 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 56 uint16_t queue_id); 57 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 58 uint16_t queue_id); 59 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 60 size_t fw_size); 61 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 62 uint16_t pvid, int on); 63 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 64 static int ice_get_eeprom(struct rte_eth_dev *dev, 65 struct rte_dev_eeprom_info *eeprom); 66 static int ice_stats_get(struct rte_eth_dev *dev, 67 struct rte_eth_stats *stats); 68 static void ice_stats_reset(struct rte_eth_dev *dev); 69 static int ice_xstats_get(struct rte_eth_dev *dev, 70 struct rte_eth_xstat *xstats, unsigned int n); 71 static int ice_xstats_get_names(struct rte_eth_dev *dev, 72 struct rte_eth_xstat_name *xstats_names, 73 unsigned int limit); 74 75 static const struct rte_pci_id pci_id_ice_map[] = { 76 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 77 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 78 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 79 { .vendor_id = 0, /* sentinel */ }, 80 }; 81 82 static const struct eth_dev_ops ice_eth_dev_ops = { 83 .dev_configure = ice_dev_configure, 84 .dev_start = ice_dev_start, 85 .dev_stop = ice_dev_stop, 86 .dev_close = ice_dev_close, 87 .dev_reset = ice_dev_reset, 88 .rx_queue_start = ice_rx_queue_start, 89 .rx_queue_stop = ice_rx_queue_stop, 90 .tx_queue_start = ice_tx_queue_start, 91 .tx_queue_stop = ice_tx_queue_stop, 92 .rx_queue_setup = ice_rx_queue_setup, 93 .rx_queue_release = ice_rx_queue_release, 94 .tx_queue_setup = ice_tx_queue_setup, 95 .tx_queue_release = ice_tx_queue_release, 96 .dev_infos_get = ice_dev_info_get, 97 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 98 .link_update = ice_link_update, 99 .mtu_set = ice_mtu_set, 100 .mac_addr_set = ice_macaddr_set, 101 .mac_addr_add = ice_macaddr_add, 102 .mac_addr_remove = ice_macaddr_remove, 103 .vlan_filter_set = ice_vlan_filter_set, 104 .vlan_offload_set = ice_vlan_offload_set, 105 .vlan_tpid_set = ice_vlan_tpid_set, 106 .reta_update = ice_rss_reta_update, 107 .reta_query = ice_rss_reta_query, 108 .rss_hash_update = ice_rss_hash_update, 109 .rss_hash_conf_get = ice_rss_hash_conf_get, 110 .promiscuous_enable = ice_promisc_enable, 111 .promiscuous_disable = ice_promisc_disable, 112 .allmulticast_enable = ice_allmulti_enable, 113 .allmulticast_disable = ice_allmulti_disable, 114 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 115 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 116 .fw_version_get = ice_fw_version_get, 117 .vlan_pvid_set = ice_vlan_pvid_set, 118 .rxq_info_get = ice_rxq_info_get, 119 .txq_info_get = ice_txq_info_get, 120 .get_eeprom_length = ice_get_eeprom_length, 121 .get_eeprom = ice_get_eeprom, 122 .rx_queue_count = ice_rx_queue_count, 123 .rx_descriptor_status = ice_rx_descriptor_status, 124 .tx_descriptor_status = ice_tx_descriptor_status, 125 .stats_get = ice_stats_get, 126 .stats_reset = ice_stats_reset, 127 .xstats_get = ice_xstats_get, 128 .xstats_get_names = ice_xstats_get_names, 129 .xstats_reset = ice_stats_reset, 130 }; 131 132 /* store statistics names and its offset in stats structure */ 133 struct ice_xstats_name_off { 134 char name[RTE_ETH_XSTATS_NAME_SIZE]; 135 unsigned int offset; 136 }; 137 138 static const struct ice_xstats_name_off ice_stats_strings[] = { 139 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 140 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 141 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 142 {"rx_dropped", offsetof(struct ice_eth_stats, rx_discards)}, 143 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 144 rx_unknown_protocol)}, 145 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 146 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 147 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 148 {"tx_dropped", offsetof(struct ice_eth_stats, tx_discards)}, 149 }; 150 151 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 152 sizeof(ice_stats_strings[0])) 153 154 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 155 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 156 tx_dropped_link_down)}, 157 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 158 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 159 illegal_bytes)}, 160 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 161 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 162 mac_local_faults)}, 163 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 164 mac_remote_faults)}, 165 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 166 rx_len_errors)}, 167 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 168 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 169 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 170 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 171 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 172 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 173 rx_size_127)}, 174 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 175 rx_size_255)}, 176 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 177 rx_size_511)}, 178 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 179 rx_size_1023)}, 180 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 181 rx_size_1522)}, 182 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 183 rx_size_big)}, 184 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 185 rx_undersize)}, 186 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 187 rx_oversize)}, 188 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 189 mac_short_pkt_dropped)}, 190 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 191 rx_fragments)}, 192 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 193 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 194 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 195 tx_size_127)}, 196 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 197 tx_size_255)}, 198 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 199 tx_size_511)}, 200 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 201 tx_size_1023)}, 202 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 203 tx_size_1522)}, 204 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 205 tx_size_big)}, 206 }; 207 208 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 209 sizeof(ice_hw_port_strings[0])) 210 211 static void 212 ice_init_controlq_parameter(struct ice_hw *hw) 213 { 214 /* fields for adminq */ 215 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 216 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 217 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 218 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 219 220 /* fields for mailboxq, DPDK used as PF host */ 221 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 222 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 223 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 224 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 225 } 226 227 static int 228 ice_check_qp_num(const char *key, const char *qp_value, 229 __rte_unused void *opaque) 230 { 231 char *end = NULL; 232 int num = 0; 233 234 while (isblank(*qp_value)) 235 qp_value++; 236 237 num = strtoul(qp_value, &end, 10); 238 239 if (!num || (*end == '-') || errno) { 240 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 241 "value must be > 0", 242 qp_value, key); 243 return -1; 244 } 245 246 return num; 247 } 248 249 static int 250 ice_config_max_queue_pair_num(struct rte_devargs *devargs) 251 { 252 struct rte_kvargs *kvlist; 253 const char *queue_num_key = ICE_MAX_QP_NUM; 254 int ret; 255 256 if (!devargs) 257 return 0; 258 259 kvlist = rte_kvargs_parse(devargs->args, NULL); 260 if (!kvlist) 261 return 0; 262 263 if (!rte_kvargs_count(kvlist, queue_num_key)) { 264 rte_kvargs_free(kvlist); 265 return 0; 266 } 267 268 if (rte_kvargs_process(kvlist, queue_num_key, 269 ice_check_qp_num, NULL) < 0) { 270 rte_kvargs_free(kvlist); 271 return 0; 272 } 273 ret = rte_kvargs_process(kvlist, queue_num_key, 274 ice_check_qp_num, NULL); 275 rte_kvargs_free(kvlist); 276 277 return ret; 278 } 279 280 static int 281 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 282 uint32_t num) 283 { 284 struct pool_entry *entry; 285 286 if (!pool || !num) 287 return -EINVAL; 288 289 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 290 if (!entry) { 291 PMD_INIT_LOG(ERR, 292 "Failed to allocate memory for resource pool"); 293 return -ENOMEM; 294 } 295 296 /* queue heap initialize */ 297 pool->num_free = num; 298 pool->num_alloc = 0; 299 pool->base = base; 300 LIST_INIT(&pool->alloc_list); 301 LIST_INIT(&pool->free_list); 302 303 /* Initialize element */ 304 entry->base = 0; 305 entry->len = num; 306 307 LIST_INSERT_HEAD(&pool->free_list, entry, next); 308 return 0; 309 } 310 311 static int 312 ice_res_pool_alloc(struct ice_res_pool_info *pool, 313 uint16_t num) 314 { 315 struct pool_entry *entry, *valid_entry; 316 317 if (!pool || !num) { 318 PMD_INIT_LOG(ERR, "Invalid parameter"); 319 return -EINVAL; 320 } 321 322 if (pool->num_free < num) { 323 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 324 num, pool->num_free); 325 return -ENOMEM; 326 } 327 328 valid_entry = NULL; 329 /* Lookup in free list and find most fit one */ 330 LIST_FOREACH(entry, &pool->free_list, next) { 331 if (entry->len >= num) { 332 /* Find best one */ 333 if (entry->len == num) { 334 valid_entry = entry; 335 break; 336 } 337 if (!valid_entry || 338 valid_entry->len > entry->len) 339 valid_entry = entry; 340 } 341 } 342 343 /* Not find one to satisfy the request, return */ 344 if (!valid_entry) { 345 PMD_INIT_LOG(ERR, "No valid entry found"); 346 return -ENOMEM; 347 } 348 /** 349 * The entry have equal queue number as requested, 350 * remove it from alloc_list. 351 */ 352 if (valid_entry->len == num) { 353 LIST_REMOVE(valid_entry, next); 354 } else { 355 /** 356 * The entry have more numbers than requested, 357 * create a new entry for alloc_list and minus its 358 * queue base and number in free_list. 359 */ 360 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 361 if (!entry) { 362 PMD_INIT_LOG(ERR, 363 "Failed to allocate memory for " 364 "resource pool"); 365 return -ENOMEM; 366 } 367 entry->base = valid_entry->base; 368 entry->len = num; 369 valid_entry->base += num; 370 valid_entry->len -= num; 371 valid_entry = entry; 372 } 373 374 /* Insert it into alloc list, not sorted */ 375 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 376 377 pool->num_free -= valid_entry->len; 378 pool->num_alloc += valid_entry->len; 379 380 return valid_entry->base + pool->base; 381 } 382 383 static void 384 ice_res_pool_destroy(struct ice_res_pool_info *pool) 385 { 386 struct pool_entry *entry, *next_entry; 387 388 if (!pool) 389 return; 390 391 for (entry = LIST_FIRST(&pool->alloc_list); 392 entry && (next_entry = LIST_NEXT(entry, next), 1); 393 entry = next_entry) { 394 LIST_REMOVE(entry, next); 395 rte_free(entry); 396 } 397 398 for (entry = LIST_FIRST(&pool->free_list); 399 entry && (next_entry = LIST_NEXT(entry, next), 1); 400 entry = next_entry) { 401 LIST_REMOVE(entry, next); 402 rte_free(entry); 403 } 404 405 pool->num_free = 0; 406 pool->num_alloc = 0; 407 pool->base = 0; 408 LIST_INIT(&pool->alloc_list); 409 LIST_INIT(&pool->free_list); 410 } 411 412 static void 413 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 414 { 415 /* Set VSI LUT selection */ 416 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 417 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 418 /* Set Hash scheme */ 419 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 420 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 421 /* enable TC */ 422 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 423 } 424 425 static enum ice_status 426 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 427 struct ice_aqc_vsi_props *info, 428 uint8_t enabled_tcmap) 429 { 430 uint16_t bsf, qp_idx; 431 432 /* default tc 0 now. Multi-TC supporting need to be done later. 433 * Configure TC and queue mapping parameters, for enabled TC, 434 * allocate qpnum_per_tc queues to this traffic. 435 */ 436 if (enabled_tcmap != 0x01) { 437 PMD_INIT_LOG(ERR, "only TC0 is supported"); 438 return -ENOTSUP; 439 } 440 441 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 442 bsf = rte_bsf32(vsi->nb_qps); 443 /* Adjust the queue number to actual queues that can be applied */ 444 vsi->nb_qps = 0x1 << bsf; 445 446 qp_idx = 0; 447 /* Set tc and queue mapping with VSI */ 448 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 449 ICE_AQ_VSI_TC_Q_OFFSET_S) | 450 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 451 452 /* Associate queue number with VSI */ 453 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 454 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 455 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 456 info->valid_sections |= 457 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 458 /* Set the info.ingress_table and info.egress_table 459 * for UP translate table. Now just set it to 1:1 map by default 460 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 461 */ 462 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 463 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 464 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 465 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 466 return 0; 467 } 468 469 static int 470 ice_init_mac_address(struct rte_eth_dev *dev) 471 { 472 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 473 474 if (!is_unicast_ether_addr 475 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) { 476 PMD_INIT_LOG(ERR, "Invalid MAC address"); 477 return -EINVAL; 478 } 479 480 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr, 481 (struct ether_addr *)hw->port_info[0].mac.perm_addr); 482 483 dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0); 484 if (!dev->data->mac_addrs) { 485 PMD_INIT_LOG(ERR, 486 "Failed to allocate memory to store mac address"); 487 return -ENOMEM; 488 } 489 /* store it to dev data */ 490 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr, 491 &dev->data->mac_addrs[0]); 492 return 0; 493 } 494 495 /* Find out specific MAC filter */ 496 static struct ice_mac_filter * 497 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr) 498 { 499 struct ice_mac_filter *f; 500 501 TAILQ_FOREACH(f, &vsi->mac_list, next) { 502 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 503 return f; 504 } 505 506 return NULL; 507 } 508 509 static int 510 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr) 511 { 512 struct ice_fltr_list_entry *m_list_itr = NULL; 513 struct ice_mac_filter *f; 514 struct LIST_HEAD_TYPE list_head; 515 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 516 int ret = 0; 517 518 /* If it's added and configured, return */ 519 f = ice_find_mac_filter(vsi, mac_addr); 520 if (f) { 521 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 522 return 0; 523 } 524 525 INIT_LIST_HEAD(&list_head); 526 527 m_list_itr = (struct ice_fltr_list_entry *) 528 ice_malloc(hw, sizeof(*m_list_itr)); 529 if (!m_list_itr) { 530 ret = -ENOMEM; 531 goto DONE; 532 } 533 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 534 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 535 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 536 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 537 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 538 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 539 m_list_itr->fltr_info.vsi_handle = vsi->idx; 540 541 LIST_ADD(&m_list_itr->list_entry, &list_head); 542 543 /* Add the mac */ 544 ret = ice_add_mac(hw, &list_head); 545 if (ret != ICE_SUCCESS) { 546 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 547 ret = -EINVAL; 548 goto DONE; 549 } 550 /* Add the mac addr into mac list */ 551 f = rte_zmalloc(NULL, sizeof(*f), 0); 552 if (!f) { 553 PMD_DRV_LOG(ERR, "failed to allocate memory"); 554 ret = -ENOMEM; 555 goto DONE; 556 } 557 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN); 558 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 559 vsi->mac_num++; 560 561 ret = 0; 562 563 DONE: 564 rte_free(m_list_itr); 565 return ret; 566 } 567 568 static int 569 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr) 570 { 571 struct ice_fltr_list_entry *m_list_itr = NULL; 572 struct ice_mac_filter *f; 573 struct LIST_HEAD_TYPE list_head; 574 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 575 int ret = 0; 576 577 /* Can't find it, return an error */ 578 f = ice_find_mac_filter(vsi, mac_addr); 579 if (!f) 580 return -EINVAL; 581 582 INIT_LIST_HEAD(&list_head); 583 584 m_list_itr = (struct ice_fltr_list_entry *) 585 ice_malloc(hw, sizeof(*m_list_itr)); 586 if (!m_list_itr) { 587 ret = -ENOMEM; 588 goto DONE; 589 } 590 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 591 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 592 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 593 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 594 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 595 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 596 m_list_itr->fltr_info.vsi_handle = vsi->idx; 597 598 LIST_ADD(&m_list_itr->list_entry, &list_head); 599 600 /* remove the mac filter */ 601 ret = ice_remove_mac(hw, &list_head); 602 if (ret != ICE_SUCCESS) { 603 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 604 ret = -EINVAL; 605 goto DONE; 606 } 607 608 /* Remove the mac addr from mac list */ 609 TAILQ_REMOVE(&vsi->mac_list, f, next); 610 rte_free(f); 611 vsi->mac_num--; 612 613 ret = 0; 614 DONE: 615 rte_free(m_list_itr); 616 return ret; 617 } 618 619 /* Find out specific VLAN filter */ 620 static struct ice_vlan_filter * 621 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 622 { 623 struct ice_vlan_filter *f; 624 625 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 626 if (vlan_id == f->vlan_info.vlan_id) 627 return f; 628 } 629 630 return NULL; 631 } 632 633 static int 634 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 635 { 636 struct ice_fltr_list_entry *v_list_itr = NULL; 637 struct ice_vlan_filter *f; 638 struct LIST_HEAD_TYPE list_head; 639 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 640 int ret = 0; 641 642 if (!vsi || vlan_id > ETHER_MAX_VLAN_ID) 643 return -EINVAL; 644 645 /* If it's added and configured, return. */ 646 f = ice_find_vlan_filter(vsi, vlan_id); 647 if (f) { 648 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 649 return 0; 650 } 651 652 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 653 return 0; 654 655 INIT_LIST_HEAD(&list_head); 656 657 v_list_itr = (struct ice_fltr_list_entry *) 658 ice_malloc(hw, sizeof(*v_list_itr)); 659 if (!v_list_itr) { 660 ret = -ENOMEM; 661 goto DONE; 662 } 663 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 664 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 665 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 666 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 667 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 668 v_list_itr->fltr_info.vsi_handle = vsi->idx; 669 670 LIST_ADD(&v_list_itr->list_entry, &list_head); 671 672 /* Add the vlan */ 673 ret = ice_add_vlan(hw, &list_head); 674 if (ret != ICE_SUCCESS) { 675 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 676 ret = -EINVAL; 677 goto DONE; 678 } 679 680 /* Add vlan into vlan list */ 681 f = rte_zmalloc(NULL, sizeof(*f), 0); 682 if (!f) { 683 PMD_DRV_LOG(ERR, "failed to allocate memory"); 684 ret = -ENOMEM; 685 goto DONE; 686 } 687 f->vlan_info.vlan_id = vlan_id; 688 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 689 vsi->vlan_num++; 690 691 ret = 0; 692 693 DONE: 694 rte_free(v_list_itr); 695 return ret; 696 } 697 698 static int 699 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 700 { 701 struct ice_fltr_list_entry *v_list_itr = NULL; 702 struct ice_vlan_filter *f; 703 struct LIST_HEAD_TYPE list_head; 704 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 705 int ret = 0; 706 707 /** 708 * Vlan 0 is the generic filter for untagged packets 709 * and can't be removed. 710 */ 711 if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID) 712 return -EINVAL; 713 714 /* Can't find it, return an error */ 715 f = ice_find_vlan_filter(vsi, vlan_id); 716 if (!f) 717 return -EINVAL; 718 719 INIT_LIST_HEAD(&list_head); 720 721 v_list_itr = (struct ice_fltr_list_entry *) 722 ice_malloc(hw, sizeof(*v_list_itr)); 723 if (!v_list_itr) { 724 ret = -ENOMEM; 725 goto DONE; 726 } 727 728 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 729 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 730 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 731 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 732 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 733 v_list_itr->fltr_info.vsi_handle = vsi->idx; 734 735 LIST_ADD(&v_list_itr->list_entry, &list_head); 736 737 /* remove the vlan filter */ 738 ret = ice_remove_vlan(hw, &list_head); 739 if (ret != ICE_SUCCESS) { 740 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 741 ret = -EINVAL; 742 goto DONE; 743 } 744 745 /* Remove the vlan id from vlan list */ 746 TAILQ_REMOVE(&vsi->vlan_list, f, next); 747 rte_free(f); 748 vsi->vlan_num--; 749 750 ret = 0; 751 DONE: 752 rte_free(v_list_itr); 753 return ret; 754 } 755 756 static int 757 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 758 { 759 struct ice_mac_filter *m_f; 760 struct ice_vlan_filter *v_f; 761 int ret = 0; 762 763 if (!vsi || !vsi->mac_num) 764 return -EINVAL; 765 766 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 767 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 768 if (ret != ICE_SUCCESS) { 769 ret = -EINVAL; 770 goto DONE; 771 } 772 } 773 774 if (vsi->vlan_num == 0) 775 return 0; 776 777 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 778 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 779 if (ret != ICE_SUCCESS) { 780 ret = -EINVAL; 781 goto DONE; 782 } 783 } 784 785 DONE: 786 return ret; 787 } 788 789 static int 790 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 791 { 792 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 793 struct ice_vsi_ctx ctxt; 794 uint8_t qinq_flags; 795 int ret = 0; 796 797 /* Check if it has been already on or off */ 798 if (vsi->info.valid_sections & 799 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 800 if (on) { 801 if ((vsi->info.outer_tag_flags & 802 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == 803 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) 804 return 0; /* already on */ 805 } else { 806 if (!(vsi->info.outer_tag_flags & 807 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) 808 return 0; /* already off */ 809 } 810 } 811 812 if (on) 813 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; 814 else 815 qinq_flags = 0; 816 /* clear global insertion and use per packet insertion */ 817 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); 818 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); 819 vsi->info.outer_tag_flags |= qinq_flags; 820 /* use default vlan type 0x8100 */ 821 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 822 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 823 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 824 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 825 ctxt.info.valid_sections = 826 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 827 ctxt.vsi_num = vsi->vsi_id; 828 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 829 if (ret) { 830 PMD_DRV_LOG(INFO, 831 "Update VSI failed to %s qinq stripping", 832 on ? "enable" : "disable"); 833 return -EINVAL; 834 } 835 836 vsi->info.valid_sections |= 837 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 838 839 return ret; 840 } 841 842 static int 843 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 844 { 845 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 846 struct ice_vsi_ctx ctxt; 847 uint8_t qinq_flags; 848 int ret = 0; 849 850 /* Check if it has been already on or off */ 851 if (vsi->info.valid_sections & 852 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 853 if (on) { 854 if ((vsi->info.outer_tag_flags & 855 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 856 ICE_AQ_VSI_OUTER_TAG_COPY) 857 return 0; /* already on */ 858 } else { 859 if ((vsi->info.outer_tag_flags & 860 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 861 ICE_AQ_VSI_OUTER_TAG_NOTHING) 862 return 0; /* already off */ 863 } 864 } 865 866 if (on) 867 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; 868 else 869 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; 870 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); 871 vsi->info.outer_tag_flags |= qinq_flags; 872 /* use default vlan type 0x8100 */ 873 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 874 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 875 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 876 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 877 ctxt.info.valid_sections = 878 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 879 ctxt.vsi_num = vsi->vsi_id; 880 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 881 if (ret) { 882 PMD_DRV_LOG(INFO, 883 "Update VSI failed to %s qinq stripping", 884 on ? "enable" : "disable"); 885 return -EINVAL; 886 } 887 888 vsi->info.valid_sections |= 889 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 890 891 return ret; 892 } 893 894 static int 895 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 896 { 897 int ret; 898 899 ret = ice_vsi_config_qinq_stripping(vsi, on); 900 if (ret) 901 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 902 903 ret = ice_vsi_config_qinq_insertion(vsi, on); 904 if (ret) 905 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 906 907 return ret; 908 } 909 910 /* Enable IRQ0 */ 911 static void 912 ice_pf_enable_irq0(struct ice_hw *hw) 913 { 914 /* reset the registers */ 915 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 916 ICE_READ_REG(hw, PFINT_OICR); 917 918 #ifdef ICE_LSE_SPT 919 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 920 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 921 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 922 923 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 924 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 925 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 926 PFINT_OICR_CTL_ITR_INDX_M) | 927 PFINT_OICR_CTL_CAUSE_ENA_M); 928 929 ICE_WRITE_REG(hw, PFINT_FW_CTL, 930 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 931 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 932 PFINT_FW_CTL_ITR_INDX_M) | 933 PFINT_FW_CTL_CAUSE_ENA_M); 934 #else 935 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 936 #endif 937 938 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 939 GLINT_DYN_CTL_INTENA_M | 940 GLINT_DYN_CTL_CLEARPBA_M | 941 GLINT_DYN_CTL_ITR_INDX_M); 942 943 ice_flush(hw); 944 } 945 946 /* Disable IRQ0 */ 947 static void 948 ice_pf_disable_irq0(struct ice_hw *hw) 949 { 950 /* Disable all interrupt types */ 951 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 952 ice_flush(hw); 953 } 954 955 #ifdef ICE_LSE_SPT 956 static void 957 ice_handle_aq_msg(struct rte_eth_dev *dev) 958 { 959 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 960 struct ice_ctl_q_info *cq = &hw->adminq; 961 struct ice_rq_event_info event; 962 uint16_t pending, opcode; 963 int ret; 964 965 event.buf_len = ICE_AQ_MAX_BUF_LEN; 966 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 967 if (!event.msg_buf) { 968 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 969 return; 970 } 971 972 pending = 1; 973 while (pending) { 974 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 975 976 if (ret != ICE_SUCCESS) { 977 PMD_DRV_LOG(INFO, 978 "Failed to read msg from AdminQ, " 979 "adminq_err: %u", 980 hw->adminq.sq_last_status); 981 break; 982 } 983 opcode = rte_le_to_cpu_16(event.desc.opcode); 984 985 switch (opcode) { 986 case ice_aqc_opc_get_link_status: 987 ret = ice_link_update(dev, 0); 988 if (!ret) 989 _rte_eth_dev_callback_process 990 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 991 break; 992 default: 993 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 994 opcode); 995 break; 996 } 997 } 998 rte_free(event.msg_buf); 999 } 1000 #endif 1001 1002 /** 1003 * Interrupt handler triggered by NIC for handling 1004 * specific interrupt. 1005 * 1006 * @param handle 1007 * Pointer to interrupt handle. 1008 * @param param 1009 * The address of parameter (struct rte_eth_dev *) regsitered before. 1010 * 1011 * @return 1012 * void 1013 */ 1014 static void 1015 ice_interrupt_handler(void *param) 1016 { 1017 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1018 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1019 uint32_t oicr; 1020 uint32_t reg; 1021 uint8_t pf_num; 1022 uint8_t event; 1023 uint16_t queue; 1024 #ifdef ICE_LSE_SPT 1025 uint32_t int_fw_ctl; 1026 #endif 1027 1028 /* Disable interrupt */ 1029 ice_pf_disable_irq0(hw); 1030 1031 /* read out interrupt causes */ 1032 oicr = ICE_READ_REG(hw, PFINT_OICR); 1033 #ifdef ICE_LSE_SPT 1034 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1035 #endif 1036 1037 /* No interrupt event indicated */ 1038 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1039 PMD_DRV_LOG(INFO, "No interrupt event"); 1040 goto done; 1041 } 1042 1043 #ifdef ICE_LSE_SPT 1044 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1045 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1046 ice_handle_aq_msg(dev); 1047 } 1048 #else 1049 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1050 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1051 ice_link_update(dev, 0); 1052 } 1053 #endif 1054 1055 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1056 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1057 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1058 if (reg & GL_MDET_TX_PQM_VALID_M) { 1059 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1060 GL_MDET_TX_PQM_PF_NUM_S; 1061 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1062 GL_MDET_TX_PQM_MAL_TYPE_S; 1063 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1064 GL_MDET_TX_PQM_QNUM_S; 1065 1066 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1067 "%d by PQM on TX queue %d PF# %d", 1068 event, queue, pf_num); 1069 } 1070 1071 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1072 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1073 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1074 GL_MDET_TX_TCLAN_PF_NUM_S; 1075 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1076 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1077 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1078 GL_MDET_TX_TCLAN_QNUM_S; 1079 1080 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1081 "%d by TCLAN on TX queue %d PF# %d", 1082 event, queue, pf_num); 1083 } 1084 } 1085 done: 1086 /* Enable interrupt */ 1087 ice_pf_enable_irq0(hw); 1088 rte_intr_enable(dev->intr_handle); 1089 } 1090 1091 /* Initialize SW parameters of PF */ 1092 static int 1093 ice_pf_sw_init(struct rte_eth_dev *dev) 1094 { 1095 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1096 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1097 1098 if (ice_config_max_queue_pair_num(dev->device->devargs) > 0) 1099 pf->lan_nb_qp_max = 1100 ice_config_max_queue_pair_num(dev->device->devargs); 1101 else 1102 pf->lan_nb_qp_max = 1103 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1104 hw->func_caps.common_cap.num_rxq); 1105 1106 pf->lan_nb_qps = pf->lan_nb_qp_max; 1107 1108 return 0; 1109 } 1110 1111 static struct ice_vsi * 1112 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1113 { 1114 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1115 struct ice_vsi *vsi = NULL; 1116 struct ice_vsi_ctx vsi_ctx; 1117 int ret; 1118 struct ether_addr broadcast = { 1119 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1120 struct ether_addr mac_addr; 1121 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1122 uint8_t tc_bitmap = 0x1; 1123 1124 /* hw->num_lports = 1 in NIC mode */ 1125 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1126 if (!vsi) 1127 return NULL; 1128 1129 vsi->idx = pf->next_vsi_idx; 1130 pf->next_vsi_idx++; 1131 vsi->type = type; 1132 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1133 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1134 vsi->vlan_anti_spoof_on = 0; 1135 vsi->vlan_filter_on = 1; 1136 TAILQ_INIT(&vsi->mac_list); 1137 TAILQ_INIT(&vsi->vlan_list); 1138 1139 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1140 /* base_queue in used in queue mapping of VSI add/update command. 1141 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ 1142 * cases in the first stage. Only Main VSI. 1143 */ 1144 vsi->base_queue = 0; 1145 switch (type) { 1146 case ICE_VSI_PF: 1147 vsi->nb_qps = pf->lan_nb_qps; 1148 ice_vsi_config_default_rss(&vsi_ctx.info); 1149 vsi_ctx.alloc_from_pool = true; 1150 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1151 /* switch_id is queried by get_switch_config aq, which is done 1152 * by ice_init_hw 1153 */ 1154 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1155 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1156 /* Allow all untagged or tagged packets */ 1157 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; 1158 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; 1159 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1160 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1161 /* Enable VLAN/UP trip */ 1162 ret = ice_vsi_config_tc_queue_mapping(vsi, 1163 &vsi_ctx.info, 1164 ICE_DEFAULT_TCMAP); 1165 if (ret) { 1166 PMD_INIT_LOG(ERR, 1167 "tc queue mapping with vsi failed, " 1168 "err = %d", 1169 ret); 1170 goto fail_mem; 1171 } 1172 1173 break; 1174 default: 1175 /* for other types of VSI */ 1176 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1177 goto fail_mem; 1178 } 1179 1180 /* VF has MSIX interrupt in VF range, don't allocate here */ 1181 if (type == ICE_VSI_PF) { 1182 ret = ice_res_pool_alloc(&pf->msix_pool, 1183 RTE_MIN(vsi->nb_qps, 1184 RTE_MAX_RXTX_INTR_VEC_ID)); 1185 if (ret < 0) { 1186 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1187 vsi->vsi_id, ret); 1188 } 1189 vsi->msix_intr = ret; 1190 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1191 } else { 1192 vsi->msix_intr = 0; 1193 vsi->nb_msix = 0; 1194 } 1195 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1196 if (ret != ICE_SUCCESS) { 1197 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1198 goto fail_mem; 1199 } 1200 /* store vsi information is SW structure */ 1201 vsi->vsi_id = vsi_ctx.vsi_num; 1202 vsi->info = vsi_ctx.info; 1203 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1204 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1205 1206 /* MAC configuration */ 1207 rte_memcpy(pf->dev_addr.addr_bytes, 1208 hw->port_info->mac.perm_addr, 1209 ETH_ADDR_LEN); 1210 1211 rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN); 1212 ret = ice_add_mac_filter(vsi, &mac_addr); 1213 if (ret != ICE_SUCCESS) 1214 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1215 1216 rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN); 1217 ret = ice_add_mac_filter(vsi, &mac_addr); 1218 if (ret != ICE_SUCCESS) 1219 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1220 1221 /* At the beginning, only TC0. */ 1222 /* What we need here is the maximam number of the TX queues. 1223 * Currently vsi->nb_qps means it. 1224 * Correct it if any change. 1225 */ 1226 max_txqs[0] = vsi->nb_qps; 1227 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1228 tc_bitmap, max_txqs); 1229 if (ret != ICE_SUCCESS) 1230 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1231 1232 return vsi; 1233 fail_mem: 1234 rte_free(vsi); 1235 pf->next_vsi_idx--; 1236 return NULL; 1237 } 1238 1239 static int 1240 ice_pf_setup(struct ice_pf *pf) 1241 { 1242 struct ice_vsi *vsi; 1243 1244 /* Clear all stats counters */ 1245 pf->offset_loaded = FALSE; 1246 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1247 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1248 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1249 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1250 1251 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1252 if (!vsi) { 1253 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1254 return -EINVAL; 1255 } 1256 1257 pf->main_vsi = vsi; 1258 1259 return 0; 1260 } 1261 1262 static int 1263 ice_dev_init(struct rte_eth_dev *dev) 1264 { 1265 struct rte_pci_device *pci_dev; 1266 struct rte_intr_handle *intr_handle; 1267 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1268 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1269 struct ice_vsi *vsi; 1270 int ret; 1271 1272 dev->dev_ops = &ice_eth_dev_ops; 1273 dev->rx_pkt_burst = ice_recv_pkts; 1274 dev->tx_pkt_burst = ice_xmit_pkts; 1275 dev->tx_pkt_prepare = ice_prep_pkts; 1276 1277 ice_set_default_ptype_table(dev); 1278 pci_dev = RTE_DEV_TO_PCI(dev->device); 1279 intr_handle = &pci_dev->intr_handle; 1280 1281 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1282 pf->adapter->eth_dev = dev; 1283 pf->dev_data = dev->data; 1284 hw->back = pf->adapter; 1285 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 1286 hw->vendor_id = pci_dev->id.vendor_id; 1287 hw->device_id = pci_dev->id.device_id; 1288 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1289 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1290 hw->bus.device = pci_dev->addr.devid; 1291 hw->bus.func = pci_dev->addr.function; 1292 1293 ice_init_controlq_parameter(hw); 1294 1295 ret = ice_init_hw(hw); 1296 if (ret) { 1297 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 1298 return -EINVAL; 1299 } 1300 1301 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 1302 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 1303 hw->api_maj_ver, hw->api_min_ver); 1304 1305 ice_pf_sw_init(dev); 1306 ret = ice_init_mac_address(dev); 1307 if (ret) { 1308 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 1309 goto err_init_mac; 1310 } 1311 1312 ret = ice_res_pool_init(&pf->msix_pool, 1, 1313 hw->func_caps.common_cap.num_msix_vectors - 1); 1314 if (ret) { 1315 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 1316 goto err_msix_pool_init; 1317 } 1318 1319 ret = ice_pf_setup(pf); 1320 if (ret) { 1321 PMD_INIT_LOG(ERR, "Failed to setup PF"); 1322 goto err_pf_setup; 1323 } 1324 1325 vsi = pf->main_vsi; 1326 1327 /* Disable double vlan by default */ 1328 ice_vsi_config_double_vlan(vsi, FALSE); 1329 1330 /* register callback func to eal lib */ 1331 rte_intr_callback_register(intr_handle, 1332 ice_interrupt_handler, dev); 1333 1334 ice_pf_enable_irq0(hw); 1335 1336 /* enable uio intr after callback register */ 1337 rte_intr_enable(intr_handle); 1338 1339 return 0; 1340 1341 err_pf_setup: 1342 ice_res_pool_destroy(&pf->msix_pool); 1343 err_msix_pool_init: 1344 rte_free(dev->data->mac_addrs); 1345 err_init_mac: 1346 ice_sched_cleanup_all(hw); 1347 rte_free(hw->port_info); 1348 ice_shutdown_all_ctrlq(hw); 1349 1350 return ret; 1351 } 1352 1353 static int 1354 ice_release_vsi(struct ice_vsi *vsi) 1355 { 1356 struct ice_hw *hw; 1357 struct ice_vsi_ctx vsi_ctx; 1358 enum ice_status ret; 1359 1360 if (!vsi) 1361 return 0; 1362 1363 hw = ICE_VSI_TO_HW(vsi); 1364 1365 ice_remove_all_mac_vlan_filters(vsi); 1366 1367 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1368 1369 vsi_ctx.vsi_num = vsi->vsi_id; 1370 vsi_ctx.info = vsi->info; 1371 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 1372 if (ret != ICE_SUCCESS) { 1373 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 1374 rte_free(vsi); 1375 return -1; 1376 } 1377 1378 rte_free(vsi); 1379 return 0; 1380 } 1381 1382 static void 1383 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 1384 { 1385 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1386 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1387 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1388 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1389 uint16_t msix_intr, i; 1390 1391 /* disable interrupt and also clear all the exist config */ 1392 for (i = 0; i < vsi->nb_qps; i++) { 1393 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 1394 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 1395 rte_wmb(); 1396 } 1397 1398 if (rte_intr_allow_others(intr_handle)) 1399 /* vfio-pci */ 1400 for (i = 0; i < vsi->nb_msix; i++) { 1401 msix_intr = vsi->msix_intr + i; 1402 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 1403 GLINT_DYN_CTL_WB_ON_ITR_M); 1404 } 1405 else 1406 /* igb_uio */ 1407 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1408 } 1409 1410 static void 1411 ice_dev_stop(struct rte_eth_dev *dev) 1412 { 1413 struct rte_eth_dev_data *data = dev->data; 1414 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1415 struct ice_vsi *main_vsi = pf->main_vsi; 1416 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1417 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1418 uint16_t i; 1419 1420 /* avoid stopping again */ 1421 if (pf->adapter_stopped) 1422 return; 1423 1424 /* stop and clear all Rx queues */ 1425 for (i = 0; i < data->nb_rx_queues; i++) 1426 ice_rx_queue_stop(dev, i); 1427 1428 /* stop and clear all Tx queues */ 1429 for (i = 0; i < data->nb_tx_queues; i++) 1430 ice_tx_queue_stop(dev, i); 1431 1432 /* disable all queue interrupts */ 1433 ice_vsi_disable_queues_intr(main_vsi); 1434 1435 /* Clear all queues and release mbufs */ 1436 ice_clear_queues(dev); 1437 1438 /* Clean datapath event and queue/vec mapping */ 1439 rte_intr_efd_disable(intr_handle); 1440 if (intr_handle->intr_vec) { 1441 rte_free(intr_handle->intr_vec); 1442 intr_handle->intr_vec = NULL; 1443 } 1444 1445 pf->adapter_stopped = true; 1446 } 1447 1448 static void 1449 ice_dev_close(struct rte_eth_dev *dev) 1450 { 1451 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1452 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1453 1454 ice_dev_stop(dev); 1455 1456 /* release all queue resource */ 1457 ice_free_queues(dev); 1458 1459 ice_res_pool_destroy(&pf->msix_pool); 1460 ice_release_vsi(pf->main_vsi); 1461 ice_sched_cleanup_all(hw); 1462 rte_free(hw->port_info); 1463 ice_shutdown_all_ctrlq(hw); 1464 } 1465 1466 static int 1467 ice_dev_uninit(struct rte_eth_dev *dev) 1468 { 1469 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1470 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1471 1472 ice_dev_close(dev); 1473 1474 dev->dev_ops = NULL; 1475 dev->rx_pkt_burst = NULL; 1476 dev->tx_pkt_burst = NULL; 1477 1478 rte_free(dev->data->mac_addrs); 1479 dev->data->mac_addrs = NULL; 1480 1481 /* disable uio intr before callback unregister */ 1482 rte_intr_disable(intr_handle); 1483 1484 /* register callback func to eal lib */ 1485 rte_intr_callback_unregister(intr_handle, 1486 ice_interrupt_handler, dev); 1487 1488 return 0; 1489 } 1490 1491 static int 1492 ice_dev_configure(__rte_unused struct rte_eth_dev *dev) 1493 { 1494 struct ice_adapter *ad = 1495 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1496 1497 /* Initialize to TRUE. If any of Rx queues doesn't meet the 1498 * bulk allocation or vector Rx preconditions we will reset it. 1499 */ 1500 ad->rx_bulk_alloc_allowed = true; 1501 ad->tx_simple_allowed = true; 1502 1503 return 0; 1504 } 1505 1506 static int ice_init_rss(struct ice_pf *pf) 1507 { 1508 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1509 struct ice_vsi *vsi = pf->main_vsi; 1510 struct rte_eth_dev *dev = pf->adapter->eth_dev; 1511 struct rte_eth_rss_conf *rss_conf; 1512 struct ice_aqc_get_set_rss_keys key; 1513 uint16_t i, nb_q; 1514 int ret = 0; 1515 1516 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 1517 nb_q = dev->data->nb_rx_queues; 1518 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 1519 vsi->rss_lut_size = hw->func_caps.common_cap.rss_table_size; 1520 1521 if (!vsi->rss_key) 1522 vsi->rss_key = rte_zmalloc(NULL, 1523 vsi->rss_key_size, 0); 1524 if (!vsi->rss_lut) 1525 vsi->rss_lut = rte_zmalloc(NULL, 1526 vsi->rss_lut_size, 0); 1527 1528 /* configure RSS key */ 1529 if (!rss_conf->rss_key) { 1530 /* Calculate the default hash key */ 1531 for (i = 0; i <= vsi->rss_key_size; i++) 1532 vsi->rss_key[i] = (uint8_t)rte_rand(); 1533 } else { 1534 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 1535 RTE_MIN(rss_conf->rss_key_len, 1536 vsi->rss_key_size)); 1537 } 1538 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 1539 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 1540 if (ret) 1541 return -EINVAL; 1542 1543 /* init RSS LUT table */ 1544 for (i = 0; i < vsi->rss_lut_size; i++) 1545 vsi->rss_lut[i] = i % nb_q; 1546 1547 ret = ice_aq_set_rss_lut(hw, vsi->idx, 1548 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, 1549 vsi->rss_lut, vsi->rss_lut_size); 1550 if (ret) 1551 return -EINVAL; 1552 1553 return 0; 1554 } 1555 1556 static void 1557 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 1558 int base_queue, int nb_queue) 1559 { 1560 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1561 uint32_t val, val_tx; 1562 int i; 1563 1564 for (i = 0; i < nb_queue; i++) { 1565 /*do actual bind*/ 1566 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 1567 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 1568 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 1569 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 1570 1571 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 1572 base_queue + i, msix_vect); 1573 /* set ITR0 value */ 1574 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); 1575 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 1576 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 1577 } 1578 } 1579 1580 static void 1581 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 1582 { 1583 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1584 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1585 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1586 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1587 uint16_t msix_vect = vsi->msix_intr; 1588 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 1589 uint16_t queue_idx = 0; 1590 int record = 0; 1591 int i; 1592 1593 /* clear Rx/Tx queue interrupt */ 1594 for (i = 0; i < vsi->nb_used_qps; i++) { 1595 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 1596 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 1597 } 1598 1599 /* PF bind interrupt */ 1600 if (rte_intr_dp_is_en(intr_handle)) { 1601 queue_idx = 0; 1602 record = 1; 1603 } 1604 1605 for (i = 0; i < vsi->nb_used_qps; i++) { 1606 if (nb_msix <= 1) { 1607 if (!rte_intr_allow_others(intr_handle)) 1608 msix_vect = ICE_MISC_VEC_ID; 1609 1610 /* uio mapping all queue to one msix_vect */ 1611 __vsi_queues_bind_intr(vsi, msix_vect, 1612 vsi->base_queue + i, 1613 vsi->nb_used_qps - i); 1614 1615 for (; !!record && i < vsi->nb_used_qps; i++) 1616 intr_handle->intr_vec[queue_idx + i] = 1617 msix_vect; 1618 break; 1619 } 1620 1621 /* vfio 1:1 queue/msix_vect mapping */ 1622 __vsi_queues_bind_intr(vsi, msix_vect, 1623 vsi->base_queue + i, 1); 1624 1625 if (!!record) 1626 intr_handle->intr_vec[queue_idx + i] = msix_vect; 1627 1628 msix_vect++; 1629 nb_msix--; 1630 } 1631 } 1632 1633 static void 1634 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 1635 { 1636 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1637 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1638 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1639 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1640 uint16_t msix_intr, i; 1641 1642 if (rte_intr_allow_others(intr_handle)) 1643 for (i = 0; i < vsi->nb_used_qps; i++) { 1644 msix_intr = vsi->msix_intr + i; 1645 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 1646 GLINT_DYN_CTL_INTENA_M | 1647 GLINT_DYN_CTL_CLEARPBA_M | 1648 GLINT_DYN_CTL_ITR_INDX_M | 1649 GLINT_DYN_CTL_WB_ON_ITR_M); 1650 } 1651 else 1652 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1653 GLINT_DYN_CTL_INTENA_M | 1654 GLINT_DYN_CTL_CLEARPBA_M | 1655 GLINT_DYN_CTL_ITR_INDX_M | 1656 GLINT_DYN_CTL_WB_ON_ITR_M); 1657 } 1658 1659 static int 1660 ice_rxq_intr_setup(struct rte_eth_dev *dev) 1661 { 1662 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1663 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1664 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1665 struct ice_vsi *vsi = pf->main_vsi; 1666 uint32_t intr_vector = 0; 1667 1668 rte_intr_disable(intr_handle); 1669 1670 /* check and configure queue intr-vector mapping */ 1671 if ((rte_intr_cap_multiple(intr_handle) || 1672 !RTE_ETH_DEV_SRIOV(dev).active) && 1673 dev->data->dev_conf.intr_conf.rxq != 0) { 1674 intr_vector = dev->data->nb_rx_queues; 1675 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 1676 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 1677 ICE_MAX_INTR_QUEUE_NUM); 1678 return -ENOTSUP; 1679 } 1680 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1681 return -1; 1682 } 1683 1684 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1685 intr_handle->intr_vec = 1686 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 1687 0); 1688 if (!intr_handle->intr_vec) { 1689 PMD_DRV_LOG(ERR, 1690 "Failed to allocate %d rx_queues intr_vec", 1691 dev->data->nb_rx_queues); 1692 return -ENOMEM; 1693 } 1694 } 1695 1696 /* Map queues with MSIX interrupt */ 1697 vsi->nb_used_qps = dev->data->nb_rx_queues; 1698 ice_vsi_queues_bind_intr(vsi); 1699 1700 /* Enable interrupts for all the queues */ 1701 ice_vsi_enable_queues_intr(vsi); 1702 1703 rte_intr_enable(intr_handle); 1704 1705 return 0; 1706 } 1707 1708 static int 1709 ice_dev_start(struct rte_eth_dev *dev) 1710 { 1711 struct rte_eth_dev_data *data = dev->data; 1712 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1713 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1714 struct ice_vsi *vsi = pf->main_vsi; 1715 uint16_t nb_rxq = 0; 1716 uint16_t nb_txq, i; 1717 int mask, ret; 1718 1719 /* program Tx queues' context in hardware */ 1720 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 1721 ret = ice_tx_queue_start(dev, nb_txq); 1722 if (ret) { 1723 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 1724 goto tx_err; 1725 } 1726 } 1727 1728 /* program Rx queues' context in hardware*/ 1729 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 1730 ret = ice_rx_queue_start(dev, nb_rxq); 1731 if (ret) { 1732 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 1733 goto rx_err; 1734 } 1735 } 1736 1737 ret = ice_init_rss(pf); 1738 if (ret) { 1739 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 1740 goto rx_err; 1741 } 1742 1743 ice_set_rx_function(dev); 1744 1745 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 1746 ETH_VLAN_EXTEND_MASK; 1747 ret = ice_vlan_offload_set(dev, mask); 1748 if (ret) { 1749 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 1750 goto rx_err; 1751 } 1752 1753 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 1754 if (ice_rxq_intr_setup(dev)) 1755 return -EIO; 1756 1757 /* Enable receiving broadcast packets and transmitting packets */ 1758 ret = ice_set_vsi_promisc(hw, vsi->idx, 1759 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 1760 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 1761 0); 1762 if (ret != ICE_SUCCESS) 1763 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 1764 1765 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 1766 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 1767 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 1768 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 1769 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 1770 ICE_AQ_LINK_EVENT_AN_COMPLETED | 1771 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 1772 NULL); 1773 if (ret != ICE_SUCCESS) 1774 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 1775 1776 /* Call get_link_info aq commond to enable/disable LSE */ 1777 ice_link_update(dev, 0); 1778 1779 pf->adapter_stopped = false; 1780 1781 return 0; 1782 1783 /* stop the started queues if failed to start all queues */ 1784 rx_err: 1785 for (i = 0; i < nb_rxq; i++) 1786 ice_rx_queue_stop(dev, i); 1787 tx_err: 1788 for (i = 0; i < nb_txq; i++) 1789 ice_tx_queue_stop(dev, i); 1790 1791 return -EIO; 1792 } 1793 1794 static int 1795 ice_dev_reset(struct rte_eth_dev *dev) 1796 { 1797 int ret; 1798 1799 if (dev->data->sriov.active) 1800 return -ENOTSUP; 1801 1802 ret = ice_dev_uninit(dev); 1803 if (ret) { 1804 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 1805 return -ENXIO; 1806 } 1807 1808 ret = ice_dev_init(dev); 1809 if (ret) { 1810 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 1811 return -ENXIO; 1812 } 1813 1814 return 0; 1815 } 1816 1817 static void 1818 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1819 { 1820 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1821 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1822 struct ice_vsi *vsi = pf->main_vsi; 1823 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1824 1825 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 1826 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 1827 dev_info->max_rx_queues = vsi->nb_qps; 1828 dev_info->max_tx_queues = vsi->nb_qps; 1829 dev_info->max_mac_addrs = vsi->max_macaddrs; 1830 dev_info->max_vfs = pci_dev->max_vfs; 1831 1832 dev_info->rx_offload_capa = 1833 DEV_RX_OFFLOAD_VLAN_STRIP | 1834 DEV_RX_OFFLOAD_IPV4_CKSUM | 1835 DEV_RX_OFFLOAD_UDP_CKSUM | 1836 DEV_RX_OFFLOAD_TCP_CKSUM | 1837 DEV_RX_OFFLOAD_QINQ_STRIP | 1838 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1839 DEV_RX_OFFLOAD_VLAN_EXTEND | 1840 DEV_RX_OFFLOAD_JUMBO_FRAME | 1841 DEV_RX_OFFLOAD_KEEP_CRC | 1842 DEV_RX_OFFLOAD_SCATTER | 1843 DEV_RX_OFFLOAD_VLAN_FILTER; 1844 dev_info->tx_offload_capa = 1845 DEV_TX_OFFLOAD_VLAN_INSERT | 1846 DEV_TX_OFFLOAD_QINQ_INSERT | 1847 DEV_TX_OFFLOAD_IPV4_CKSUM | 1848 DEV_TX_OFFLOAD_UDP_CKSUM | 1849 DEV_TX_OFFLOAD_TCP_CKSUM | 1850 DEV_TX_OFFLOAD_SCTP_CKSUM | 1851 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1852 DEV_TX_OFFLOAD_TCP_TSO | 1853 DEV_TX_OFFLOAD_MULTI_SEGS | 1854 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 1855 dev_info->rx_queue_offload_capa = 0; 1856 dev_info->tx_queue_offload_capa = 0; 1857 1858 dev_info->reta_size = hw->func_caps.common_cap.rss_table_size; 1859 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 1860 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL; 1861 1862 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1863 .rx_thresh = { 1864 .pthresh = ICE_DEFAULT_RX_PTHRESH, 1865 .hthresh = ICE_DEFAULT_RX_HTHRESH, 1866 .wthresh = ICE_DEFAULT_RX_WTHRESH, 1867 }, 1868 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 1869 .rx_drop_en = 0, 1870 .offloads = 0, 1871 }; 1872 1873 dev_info->default_txconf = (struct rte_eth_txconf) { 1874 .tx_thresh = { 1875 .pthresh = ICE_DEFAULT_TX_PTHRESH, 1876 .hthresh = ICE_DEFAULT_TX_HTHRESH, 1877 .wthresh = ICE_DEFAULT_TX_WTHRESH, 1878 }, 1879 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 1880 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 1881 .offloads = 0, 1882 }; 1883 1884 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1885 .nb_max = ICE_MAX_RING_DESC, 1886 .nb_min = ICE_MIN_RING_DESC, 1887 .nb_align = ICE_ALIGN_RING_DESC, 1888 }; 1889 1890 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1891 .nb_max = ICE_MAX_RING_DESC, 1892 .nb_min = ICE_MIN_RING_DESC, 1893 .nb_align = ICE_ALIGN_RING_DESC, 1894 }; 1895 1896 dev_info->speed_capa = ETH_LINK_SPEED_10M | 1897 ETH_LINK_SPEED_100M | 1898 ETH_LINK_SPEED_1G | 1899 ETH_LINK_SPEED_2_5G | 1900 ETH_LINK_SPEED_5G | 1901 ETH_LINK_SPEED_10G | 1902 ETH_LINK_SPEED_20G | 1903 ETH_LINK_SPEED_25G | 1904 ETH_LINK_SPEED_40G | 1905 ETH_LINK_SPEED_50G | 1906 ETH_LINK_SPEED_100G; 1907 1908 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 1909 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 1910 1911 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 1912 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 1913 dev_info->default_rxportconf.nb_queues = 1; 1914 dev_info->default_txportconf.nb_queues = 1; 1915 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 1916 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 1917 } 1918 1919 static inline int 1920 ice_atomic_read_link_status(struct rte_eth_dev *dev, 1921 struct rte_eth_link *link) 1922 { 1923 struct rte_eth_link *dst = link; 1924 struct rte_eth_link *src = &dev->data->dev_link; 1925 1926 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 1927 *(uint64_t *)src) == 0) 1928 return -1; 1929 1930 return 0; 1931 } 1932 1933 static inline int 1934 ice_atomic_write_link_status(struct rte_eth_dev *dev, 1935 struct rte_eth_link *link) 1936 { 1937 struct rte_eth_link *dst = &dev->data->dev_link; 1938 struct rte_eth_link *src = link; 1939 1940 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 1941 *(uint64_t *)src) == 0) 1942 return -1; 1943 1944 return 0; 1945 } 1946 1947 static int 1948 ice_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete) 1949 { 1950 #define CHECK_INTERVAL 100 /* 100ms */ 1951 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 1952 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1953 struct ice_link_status link_status; 1954 struct rte_eth_link link, old; 1955 int status; 1956 unsigned int rep_cnt = MAX_REPEAT_TIME; 1957 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 1958 1959 memset(&link, 0, sizeof(link)); 1960 memset(&old, 0, sizeof(old)); 1961 memset(&link_status, 0, sizeof(link_status)); 1962 ice_atomic_read_link_status(dev, &old); 1963 1964 do { 1965 /* Get link status information from hardware */ 1966 status = ice_aq_get_link_info(hw->port_info, enable_lse, 1967 &link_status, NULL); 1968 if (status != ICE_SUCCESS) { 1969 link.link_speed = ETH_SPEED_NUM_100M; 1970 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1971 PMD_DRV_LOG(ERR, "Failed to get link info"); 1972 goto out; 1973 } 1974 1975 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 1976 if (!wait_to_complete || link.link_status) 1977 break; 1978 1979 rte_delay_ms(CHECK_INTERVAL); 1980 } while (--rep_cnt); 1981 1982 if (!link.link_status) 1983 goto out; 1984 1985 /* Full-duplex operation at all supported speeds */ 1986 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1987 1988 /* Parse the link status */ 1989 switch (link_status.link_speed) { 1990 case ICE_AQ_LINK_SPEED_10MB: 1991 link.link_speed = ETH_SPEED_NUM_10M; 1992 break; 1993 case ICE_AQ_LINK_SPEED_100MB: 1994 link.link_speed = ETH_SPEED_NUM_100M; 1995 break; 1996 case ICE_AQ_LINK_SPEED_1000MB: 1997 link.link_speed = ETH_SPEED_NUM_1G; 1998 break; 1999 case ICE_AQ_LINK_SPEED_2500MB: 2000 link.link_speed = ETH_SPEED_NUM_2_5G; 2001 break; 2002 case ICE_AQ_LINK_SPEED_5GB: 2003 link.link_speed = ETH_SPEED_NUM_5G; 2004 break; 2005 case ICE_AQ_LINK_SPEED_10GB: 2006 link.link_speed = ETH_SPEED_NUM_10G; 2007 break; 2008 case ICE_AQ_LINK_SPEED_20GB: 2009 link.link_speed = ETH_SPEED_NUM_20G; 2010 break; 2011 case ICE_AQ_LINK_SPEED_25GB: 2012 link.link_speed = ETH_SPEED_NUM_25G; 2013 break; 2014 case ICE_AQ_LINK_SPEED_40GB: 2015 link.link_speed = ETH_SPEED_NUM_40G; 2016 break; 2017 case ICE_AQ_LINK_SPEED_50GB: 2018 link.link_speed = ETH_SPEED_NUM_50G; 2019 break; 2020 case ICE_AQ_LINK_SPEED_100GB: 2021 link.link_speed = ETH_SPEED_NUM_100G; 2022 break; 2023 case ICE_AQ_LINK_SPEED_UNKNOWN: 2024 default: 2025 PMD_DRV_LOG(ERR, "Unknown link speed"); 2026 link.link_speed = ETH_SPEED_NUM_NONE; 2027 break; 2028 } 2029 2030 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2031 ETH_LINK_SPEED_FIXED); 2032 2033 out: 2034 ice_atomic_write_link_status(dev, &link); 2035 if (link.link_status == old.link_status) 2036 return -1; 2037 2038 return 0; 2039 } 2040 2041 static int 2042 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2043 { 2044 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2045 struct rte_eth_dev_data *dev_data = pf->dev_data; 2046 uint32_t frame_size = mtu + ETHER_HDR_LEN 2047 + ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE; 2048 2049 /* check if mtu is within the allowed range */ 2050 if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 2051 return -EINVAL; 2052 2053 /* mtu setting is forbidden if port is start */ 2054 if (dev_data->dev_started) { 2055 PMD_DRV_LOG(ERR, 2056 "port %d must be stopped before configuration", 2057 dev_data->port_id); 2058 return -EBUSY; 2059 } 2060 2061 if (frame_size > ETHER_MAX_LEN) 2062 dev_data->dev_conf.rxmode.offloads |= 2063 DEV_RX_OFFLOAD_JUMBO_FRAME; 2064 else 2065 dev_data->dev_conf.rxmode.offloads &= 2066 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2067 2068 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2069 2070 return 0; 2071 } 2072 2073 static int ice_macaddr_set(struct rte_eth_dev *dev, 2074 struct ether_addr *mac_addr) 2075 { 2076 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2077 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2078 struct ice_vsi *vsi = pf->main_vsi; 2079 struct ice_mac_filter *f; 2080 uint8_t flags = 0; 2081 int ret; 2082 2083 if (!is_valid_assigned_ether_addr(mac_addr)) { 2084 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 2085 return -EINVAL; 2086 } 2087 2088 TAILQ_FOREACH(f, &vsi->mac_list, next) { 2089 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 2090 break; 2091 } 2092 2093 if (!f) { 2094 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 2095 return -EIO; 2096 } 2097 2098 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 2099 if (ret != ICE_SUCCESS) { 2100 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 2101 return -EIO; 2102 } 2103 ret = ice_add_mac_filter(vsi, mac_addr); 2104 if (ret != ICE_SUCCESS) { 2105 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 2106 return -EIO; 2107 } 2108 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN); 2109 2110 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 2111 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 2112 if (ret != ICE_SUCCESS) 2113 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 2114 2115 return 0; 2116 } 2117 2118 /* Add a MAC address, and update filters */ 2119 static int 2120 ice_macaddr_add(struct rte_eth_dev *dev, 2121 struct ether_addr *mac_addr, 2122 __rte_unused uint32_t index, 2123 __rte_unused uint32_t pool) 2124 { 2125 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2126 struct ice_vsi *vsi = pf->main_vsi; 2127 int ret; 2128 2129 ret = ice_add_mac_filter(vsi, mac_addr); 2130 if (ret != ICE_SUCCESS) { 2131 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 2132 return -EINVAL; 2133 } 2134 2135 return ICE_SUCCESS; 2136 } 2137 2138 /* Remove a MAC address, and update filters */ 2139 static void 2140 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 2141 { 2142 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2143 struct ice_vsi *vsi = pf->main_vsi; 2144 struct rte_eth_dev_data *data = dev->data; 2145 struct ether_addr *macaddr; 2146 int ret; 2147 2148 macaddr = &data->mac_addrs[index]; 2149 ret = ice_remove_mac_filter(vsi, macaddr); 2150 if (ret) { 2151 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 2152 return; 2153 } 2154 } 2155 2156 static int 2157 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 2158 { 2159 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2160 struct ice_vsi *vsi = pf->main_vsi; 2161 int ret; 2162 2163 PMD_INIT_FUNC_TRACE(); 2164 2165 if (on) { 2166 ret = ice_add_vlan_filter(vsi, vlan_id); 2167 if (ret < 0) { 2168 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 2169 return -EINVAL; 2170 } 2171 } else { 2172 ret = ice_remove_vlan_filter(vsi, vlan_id); 2173 if (ret < 0) { 2174 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 2175 return -EINVAL; 2176 } 2177 } 2178 2179 return 0; 2180 } 2181 2182 /* Configure vlan filter on or off */ 2183 static int 2184 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 2185 { 2186 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2187 struct ice_vsi_ctx ctxt; 2188 uint8_t sec_flags, sw_flags2; 2189 int ret = 0; 2190 2191 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 2192 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 2193 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 2194 2195 if (on) { 2196 vsi->info.sec_flags |= sec_flags; 2197 vsi->info.sw_flags2 |= sw_flags2; 2198 } else { 2199 vsi->info.sec_flags &= ~sec_flags; 2200 vsi->info.sw_flags2 &= ~sw_flags2; 2201 } 2202 vsi->info.sw_id = hw->port_info->sw_id; 2203 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2204 ctxt.info.valid_sections = 2205 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 2206 ICE_AQ_VSI_PROP_SECURITY_VALID); 2207 ctxt.vsi_num = vsi->vsi_id; 2208 2209 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2210 if (ret) { 2211 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 2212 on ? "enable" : "disable"); 2213 return -EINVAL; 2214 } else { 2215 vsi->info.valid_sections |= 2216 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 2217 ICE_AQ_VSI_PROP_SECURITY_VALID); 2218 } 2219 2220 /* consist with other drivers, allow untagged packet when vlan filter on */ 2221 if (on) 2222 ret = ice_add_vlan_filter(vsi, 0); 2223 else 2224 ret = ice_remove_vlan_filter(vsi, 0); 2225 2226 return 0; 2227 } 2228 2229 static int 2230 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 2231 { 2232 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2233 struct ice_vsi_ctx ctxt; 2234 uint8_t vlan_flags; 2235 int ret = 0; 2236 2237 /* Check if it has been already on or off */ 2238 if (vsi->info.valid_sections & 2239 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 2240 if (on) { 2241 if ((vsi->info.vlan_flags & 2242 ICE_AQ_VSI_VLAN_EMOD_M) == 2243 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) 2244 return 0; /* already on */ 2245 } else { 2246 if ((vsi->info.vlan_flags & 2247 ICE_AQ_VSI_VLAN_EMOD_M) == 2248 ICE_AQ_VSI_VLAN_EMOD_NOTHING) 2249 return 0; /* already off */ 2250 } 2251 } 2252 2253 if (on) 2254 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; 2255 else 2256 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; 2257 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); 2258 vsi->info.vlan_flags |= vlan_flags; 2259 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2260 ctxt.info.valid_sections = 2261 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2262 ctxt.vsi_num = vsi->vsi_id; 2263 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2264 if (ret) { 2265 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 2266 on ? "enable" : "disable"); 2267 return -EINVAL; 2268 } 2269 2270 vsi->info.valid_sections |= 2271 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2272 2273 return ret; 2274 } 2275 2276 static int 2277 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2278 { 2279 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2280 struct ice_vsi *vsi = pf->main_vsi; 2281 struct rte_eth_rxmode *rxmode; 2282 2283 rxmode = &dev->data->dev_conf.rxmode; 2284 if (mask & ETH_VLAN_FILTER_MASK) { 2285 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2286 ice_vsi_config_vlan_filter(vsi, TRUE); 2287 else 2288 ice_vsi_config_vlan_filter(vsi, FALSE); 2289 } 2290 2291 if (mask & ETH_VLAN_STRIP_MASK) { 2292 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2293 ice_vsi_config_vlan_stripping(vsi, TRUE); 2294 else 2295 ice_vsi_config_vlan_stripping(vsi, FALSE); 2296 } 2297 2298 if (mask & ETH_VLAN_EXTEND_MASK) { 2299 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2300 ice_vsi_config_double_vlan(vsi, TRUE); 2301 else 2302 ice_vsi_config_double_vlan(vsi, FALSE); 2303 } 2304 2305 return 0; 2306 } 2307 2308 static int 2309 ice_vlan_tpid_set(struct rte_eth_dev *dev, 2310 enum rte_vlan_type vlan_type, 2311 uint16_t tpid) 2312 { 2313 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2314 uint64_t reg_r = 0, reg_w = 0; 2315 uint16_t reg_id = 0; 2316 int ret = 0; 2317 int qinq = dev->data->dev_conf.rxmode.offloads & 2318 DEV_RX_OFFLOAD_VLAN_EXTEND; 2319 2320 switch (vlan_type) { 2321 case ETH_VLAN_TYPE_OUTER: 2322 if (qinq) 2323 reg_id = 3; 2324 else 2325 reg_id = 5; 2326 break; 2327 case ETH_VLAN_TYPE_INNER: 2328 if (qinq) { 2329 reg_id = 5; 2330 } else { 2331 PMD_DRV_LOG(ERR, 2332 "Unsupported vlan type in single vlan."); 2333 return -EINVAL; 2334 } 2335 break; 2336 default: 2337 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type); 2338 return -EINVAL; 2339 } 2340 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id)); 2341 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: " 2342 "0x%08"PRIx64"", reg_id, reg_r); 2343 2344 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M)); 2345 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S); 2346 if (reg_r == reg_w) { 2347 PMD_DRV_LOG(DEBUG, "No need to write"); 2348 return 0; 2349 } 2350 2351 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w); 2352 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to " 2353 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id); 2354 2355 return ret; 2356 } 2357 2358 static int 2359 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2360 { 2361 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 2362 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2363 int ret; 2364 2365 if (!lut) 2366 return -EINVAL; 2367 2368 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 2369 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE, 2370 lut, lut_size); 2371 if (ret) { 2372 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 2373 return -EINVAL; 2374 } 2375 } else { 2376 uint64_t *lut_dw = (uint64_t *)lut; 2377 uint16_t i, lut_size_dw = lut_size / 4; 2378 2379 for (i = 0; i < lut_size_dw; i++) 2380 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 2381 } 2382 2383 return 0; 2384 } 2385 2386 static int 2387 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2388 { 2389 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 2390 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2391 int ret; 2392 2393 if (!vsi || !lut) 2394 return -EINVAL; 2395 2396 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 2397 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE, 2398 lut, lut_size); 2399 if (ret) { 2400 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 2401 return -EINVAL; 2402 } 2403 } else { 2404 uint64_t *lut_dw = (uint64_t *)lut; 2405 uint16_t i, lut_size_dw = lut_size / 4; 2406 2407 for (i = 0; i < lut_size_dw; i++) 2408 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 2409 2410 ice_flush(hw); 2411 } 2412 2413 return 0; 2414 } 2415 2416 static int 2417 ice_rss_reta_update(struct rte_eth_dev *dev, 2418 struct rte_eth_rss_reta_entry64 *reta_conf, 2419 uint16_t reta_size) 2420 { 2421 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2422 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2423 uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size; 2424 uint16_t idx, shift; 2425 uint8_t *lut; 2426 int ret; 2427 2428 if (reta_size != lut_size || 2429 reta_size > ETH_RSS_RETA_SIZE_512) { 2430 PMD_DRV_LOG(ERR, 2431 "The size of hash lookup table configured (%d)" 2432 "doesn't match the number hardware can " 2433 "supported (%d)", 2434 reta_size, lut_size); 2435 return -EINVAL; 2436 } 2437 2438 lut = rte_zmalloc(NULL, reta_size, 0); 2439 if (!lut) { 2440 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2441 return -ENOMEM; 2442 } 2443 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 2444 if (ret) 2445 goto out; 2446 2447 for (i = 0; i < reta_size; i++) { 2448 idx = i / RTE_RETA_GROUP_SIZE; 2449 shift = i % RTE_RETA_GROUP_SIZE; 2450 if (reta_conf[idx].mask & (1ULL << shift)) 2451 lut[i] = reta_conf[idx].reta[shift]; 2452 } 2453 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 2454 2455 out: 2456 rte_free(lut); 2457 2458 return ret; 2459 } 2460 2461 static int 2462 ice_rss_reta_query(struct rte_eth_dev *dev, 2463 struct rte_eth_rss_reta_entry64 *reta_conf, 2464 uint16_t reta_size) 2465 { 2466 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2467 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2468 uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size; 2469 uint16_t idx, shift; 2470 uint8_t *lut; 2471 int ret; 2472 2473 if (reta_size != lut_size || 2474 reta_size > ETH_RSS_RETA_SIZE_512) { 2475 PMD_DRV_LOG(ERR, 2476 "The size of hash lookup table configured (%d)" 2477 "doesn't match the number hardware can " 2478 "supported (%d)", 2479 reta_size, lut_size); 2480 return -EINVAL; 2481 } 2482 2483 lut = rte_zmalloc(NULL, reta_size, 0); 2484 if (!lut) { 2485 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2486 return -ENOMEM; 2487 } 2488 2489 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 2490 if (ret) 2491 goto out; 2492 2493 for (i = 0; i < reta_size; i++) { 2494 idx = i / RTE_RETA_GROUP_SIZE; 2495 shift = i % RTE_RETA_GROUP_SIZE; 2496 if (reta_conf[idx].mask & (1ULL << shift)) 2497 reta_conf[idx].reta[shift] = lut[i]; 2498 } 2499 2500 out: 2501 rte_free(lut); 2502 2503 return ret; 2504 } 2505 2506 static int 2507 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 2508 { 2509 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2510 int ret = 0; 2511 2512 if (!key || key_len == 0) { 2513 PMD_DRV_LOG(DEBUG, "No key to be configured"); 2514 return 0; 2515 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 2516 sizeof(uint32_t)) { 2517 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 2518 return -EINVAL; 2519 } 2520 2521 struct ice_aqc_get_set_rss_keys *key_dw = 2522 (struct ice_aqc_get_set_rss_keys *)key; 2523 2524 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 2525 if (ret) { 2526 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 2527 ret = -EINVAL; 2528 } 2529 2530 return ret; 2531 } 2532 2533 static int 2534 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 2535 { 2536 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2537 int ret; 2538 2539 if (!key || !key_len) 2540 return -EINVAL; 2541 2542 ret = ice_aq_get_rss_key 2543 (hw, vsi->idx, 2544 (struct ice_aqc_get_set_rss_keys *)key); 2545 if (ret) { 2546 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 2547 return -EINVAL; 2548 } 2549 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2550 2551 return 0; 2552 } 2553 2554 static int 2555 ice_rss_hash_update(struct rte_eth_dev *dev, 2556 struct rte_eth_rss_conf *rss_conf) 2557 { 2558 enum ice_status status = ICE_SUCCESS; 2559 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2560 struct ice_vsi *vsi = pf->main_vsi; 2561 2562 /* set hash key */ 2563 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 2564 if (status) 2565 return status; 2566 2567 /* TODO: hash enable config, ice_add_rss_cfg */ 2568 return 0; 2569 } 2570 2571 static int 2572 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 2573 struct rte_eth_rss_conf *rss_conf) 2574 { 2575 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2576 struct ice_vsi *vsi = pf->main_vsi; 2577 2578 ice_get_rss_key(vsi, rss_conf->rss_key, 2579 &rss_conf->rss_key_len); 2580 2581 /* TODO: default set to 0 as hf config is not supported now */ 2582 rss_conf->rss_hf = 0; 2583 return 0; 2584 } 2585 2586 static void 2587 ice_promisc_enable(struct rte_eth_dev *dev) 2588 { 2589 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2590 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2591 struct ice_vsi *vsi = pf->main_vsi; 2592 uint8_t pmask; 2593 uint16_t status; 2594 2595 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 2596 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2597 2598 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 2599 if (status != ICE_SUCCESS) 2600 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 2601 } 2602 2603 static void 2604 ice_promisc_disable(struct rte_eth_dev *dev) 2605 { 2606 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2607 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2608 struct ice_vsi *vsi = pf->main_vsi; 2609 uint16_t status; 2610 uint8_t pmask; 2611 2612 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 2613 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2614 2615 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 2616 if (status != ICE_SUCCESS) 2617 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 2618 } 2619 2620 static void 2621 ice_allmulti_enable(struct rte_eth_dev *dev) 2622 { 2623 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2624 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2625 struct ice_vsi *vsi = pf->main_vsi; 2626 uint8_t pmask; 2627 uint16_t status; 2628 2629 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2630 2631 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 2632 if (status != ICE_SUCCESS) 2633 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 2634 } 2635 2636 static void 2637 ice_allmulti_disable(struct rte_eth_dev *dev) 2638 { 2639 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2640 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2641 struct ice_vsi *vsi = pf->main_vsi; 2642 uint16_t status; 2643 uint8_t pmask; 2644 2645 if (dev->data->promiscuous == 1) 2646 return; /* must remain in all_multicast mode */ 2647 2648 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2649 2650 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 2651 if (status != ICE_SUCCESS) 2652 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 2653 } 2654 2655 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 2656 uint16_t queue_id) 2657 { 2658 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2659 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2660 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2661 uint32_t val; 2662 uint16_t msix_intr; 2663 2664 msix_intr = intr_handle->intr_vec[queue_id]; 2665 2666 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 2667 GLINT_DYN_CTL_ITR_INDX_M; 2668 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 2669 2670 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 2671 rte_intr_enable(&pci_dev->intr_handle); 2672 2673 return 0; 2674 } 2675 2676 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 2677 uint16_t queue_id) 2678 { 2679 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2680 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2681 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2682 uint16_t msix_intr; 2683 2684 msix_intr = intr_handle->intr_vec[queue_id]; 2685 2686 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 2687 2688 return 0; 2689 } 2690 2691 static int 2692 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2693 { 2694 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2695 u32 full_ver; 2696 u8 ver, patch; 2697 u16 build; 2698 int ret; 2699 2700 full_ver = hw->nvm.oem_ver; 2701 ver = (u8)(full_ver >> 24); 2702 build = (u16)((full_ver >> 8) & 0xffff); 2703 patch = (u8)(full_ver & 0xff); 2704 2705 ret = snprintf(fw_version, fw_size, 2706 "%d.%d%d 0x%08x %d.%d.%d", 2707 ((hw->nvm.ver >> 12) & 0xf), 2708 ((hw->nvm.ver >> 4) & 0xff), 2709 (hw->nvm.ver & 0xf), hw->nvm.eetrack, 2710 ver, build, patch); 2711 2712 /* add the size of '\0' */ 2713 ret += 1; 2714 if (fw_size < (u32)ret) 2715 return ret; 2716 else 2717 return 0; 2718 } 2719 2720 static int 2721 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 2722 { 2723 struct ice_hw *hw; 2724 struct ice_vsi_ctx ctxt; 2725 uint8_t vlan_flags = 0; 2726 int ret; 2727 2728 if (!vsi || !info) { 2729 PMD_DRV_LOG(ERR, "invalid parameters"); 2730 return -EINVAL; 2731 } 2732 2733 if (info->on) { 2734 vsi->info.pvid = info->config.pvid; 2735 /** 2736 * If insert pvid is enabled, only tagged pkts are 2737 * allowed to be sent out. 2738 */ 2739 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | 2740 ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 2741 } else { 2742 vsi->info.pvid = 0; 2743 if (info->config.reject.tagged == 0) 2744 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; 2745 2746 if (info->config.reject.untagged == 0) 2747 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 2748 } 2749 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | 2750 ICE_AQ_VSI_VLAN_MODE_M); 2751 vsi->info.vlan_flags |= vlan_flags; 2752 memset(&ctxt, 0, sizeof(ctxt)); 2753 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2754 ctxt.info.valid_sections = 2755 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2756 ctxt.vsi_num = vsi->vsi_id; 2757 2758 hw = ICE_VSI_TO_HW(vsi); 2759 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2760 if (ret != ICE_SUCCESS) { 2761 PMD_DRV_LOG(ERR, 2762 "update VSI for VLAN insert failed, err %d", 2763 ret); 2764 return -EINVAL; 2765 } 2766 2767 vsi->info.valid_sections |= 2768 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2769 2770 return ret; 2771 } 2772 2773 static int 2774 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 2775 { 2776 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2777 struct ice_vsi *vsi = pf->main_vsi; 2778 struct rte_eth_dev_data *data = pf->dev_data; 2779 struct ice_vsi_vlan_pvid_info info; 2780 int ret; 2781 2782 memset(&info, 0, sizeof(info)); 2783 info.on = on; 2784 if (info.on) { 2785 info.config.pvid = pvid; 2786 } else { 2787 info.config.reject.tagged = 2788 data->dev_conf.txmode.hw_vlan_reject_tagged; 2789 info.config.reject.untagged = 2790 data->dev_conf.txmode.hw_vlan_reject_untagged; 2791 } 2792 2793 ret = ice_vsi_vlan_pvid_set(vsi, &info); 2794 if (ret < 0) { 2795 PMD_DRV_LOG(ERR, "Failed to set pvid."); 2796 return -EINVAL; 2797 } 2798 2799 return 0; 2800 } 2801 2802 static int 2803 ice_get_eeprom_length(struct rte_eth_dev *dev) 2804 { 2805 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2806 2807 /* Convert word count to byte count */ 2808 return hw->nvm.sr_words << 1; 2809 } 2810 2811 static int 2812 ice_get_eeprom(struct rte_eth_dev *dev, 2813 struct rte_dev_eeprom_info *eeprom) 2814 { 2815 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2816 uint16_t *data = eeprom->data; 2817 uint16_t offset, length, i; 2818 enum ice_status ret_code = ICE_SUCCESS; 2819 2820 offset = eeprom->offset >> 1; 2821 length = eeprom->length >> 1; 2822 2823 if (offset > hw->nvm.sr_words || 2824 offset + length > hw->nvm.sr_words) { 2825 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 2826 return -EINVAL; 2827 } 2828 2829 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 2830 2831 for (i = 0; i < length; i++) { 2832 ret_code = ice_read_sr_word(hw, offset + i, &data[i]); 2833 if (ret_code != ICE_SUCCESS) { 2834 PMD_DRV_LOG(ERR, "EEPROM read failed."); 2835 return -EIO; 2836 } 2837 } 2838 2839 return 0; 2840 } 2841 2842 static void 2843 ice_stat_update_32(struct ice_hw *hw, 2844 uint32_t reg, 2845 bool offset_loaded, 2846 uint64_t *offset, 2847 uint64_t *stat) 2848 { 2849 uint64_t new_data; 2850 2851 new_data = (uint64_t)ICE_READ_REG(hw, reg); 2852 if (!offset_loaded) 2853 *offset = new_data; 2854 2855 if (new_data >= *offset) 2856 *stat = (uint64_t)(new_data - *offset); 2857 else 2858 *stat = (uint64_t)((new_data + 2859 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 2860 - *offset); 2861 } 2862 2863 static void 2864 ice_stat_update_40(struct ice_hw *hw, 2865 uint32_t hireg, 2866 uint32_t loreg, 2867 bool offset_loaded, 2868 uint64_t *offset, 2869 uint64_t *stat) 2870 { 2871 uint64_t new_data; 2872 2873 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 2874 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 2875 ICE_32_BIT_WIDTH; 2876 2877 if (!offset_loaded) 2878 *offset = new_data; 2879 2880 if (new_data >= *offset) 2881 *stat = new_data - *offset; 2882 else 2883 *stat = (uint64_t)((new_data + 2884 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 2885 *offset); 2886 2887 *stat &= ICE_40_BIT_MASK; 2888 } 2889 2890 /* Get all the statistics of a VSI */ 2891 static void 2892 ice_update_vsi_stats(struct ice_vsi *vsi) 2893 { 2894 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 2895 struct ice_eth_stats *nes = &vsi->eth_stats; 2896 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2897 int idx = rte_le_to_cpu_16(vsi->vsi_id); 2898 2899 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 2900 vsi->offset_loaded, &oes->rx_bytes, 2901 &nes->rx_bytes); 2902 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 2903 vsi->offset_loaded, &oes->rx_unicast, 2904 &nes->rx_unicast); 2905 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 2906 vsi->offset_loaded, &oes->rx_multicast, 2907 &nes->rx_multicast); 2908 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 2909 vsi->offset_loaded, &oes->rx_broadcast, 2910 &nes->rx_broadcast); 2911 /* exclude CRC bytes */ 2912 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 2913 nes->rx_broadcast) * ETHER_CRC_LEN; 2914 2915 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 2916 &oes->rx_discards, &nes->rx_discards); 2917 /* GLV_REPC not supported */ 2918 /* GLV_RMPC not supported */ 2919 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 2920 &oes->rx_unknown_protocol, 2921 &nes->rx_unknown_protocol); 2922 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 2923 vsi->offset_loaded, &oes->tx_bytes, 2924 &nes->tx_bytes); 2925 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 2926 vsi->offset_loaded, &oes->tx_unicast, 2927 &nes->tx_unicast); 2928 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 2929 vsi->offset_loaded, &oes->tx_multicast, 2930 &nes->tx_multicast); 2931 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 2932 vsi->offset_loaded, &oes->tx_broadcast, 2933 &nes->tx_broadcast); 2934 /* GLV_TDPC not supported */ 2935 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 2936 &oes->tx_errors, &nes->tx_errors); 2937 vsi->offset_loaded = true; 2938 2939 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 2940 vsi->vsi_id); 2941 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 2942 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 2943 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 2944 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 2945 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 2946 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 2947 nes->rx_unknown_protocol); 2948 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 2949 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 2950 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 2951 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 2952 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 2953 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 2954 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 2955 vsi->vsi_id); 2956 } 2957 2958 static void 2959 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 2960 { 2961 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 2962 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 2963 2964 /* Get statistics of struct ice_eth_stats */ 2965 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 2966 GLPRT_GORCL(hw->port_info->lport), 2967 pf->offset_loaded, &os->eth.rx_bytes, 2968 &ns->eth.rx_bytes); 2969 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 2970 GLPRT_UPRCL(hw->port_info->lport), 2971 pf->offset_loaded, &os->eth.rx_unicast, 2972 &ns->eth.rx_unicast); 2973 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 2974 GLPRT_MPRCL(hw->port_info->lport), 2975 pf->offset_loaded, &os->eth.rx_multicast, 2976 &ns->eth.rx_multicast); 2977 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 2978 GLPRT_BPRCL(hw->port_info->lport), 2979 pf->offset_loaded, &os->eth.rx_broadcast, 2980 &ns->eth.rx_broadcast); 2981 ice_stat_update_32(hw, PRTRPB_RDPC, 2982 pf->offset_loaded, &os->eth.rx_discards, 2983 &ns->eth.rx_discards); 2984 2985 /* Workaround: CRC size should not be included in byte statistics, 2986 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet. 2987 */ 2988 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 2989 ns->eth.rx_broadcast) * ETHER_CRC_LEN; 2990 2991 /* GLPRT_REPC not supported */ 2992 /* GLPRT_RMPC not supported */ 2993 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 2994 pf->offset_loaded, 2995 &os->eth.rx_unknown_protocol, 2996 &ns->eth.rx_unknown_protocol); 2997 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 2998 GLPRT_GOTCL(hw->port_info->lport), 2999 pf->offset_loaded, &os->eth.tx_bytes, 3000 &ns->eth.tx_bytes); 3001 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 3002 GLPRT_UPTCL(hw->port_info->lport), 3003 pf->offset_loaded, &os->eth.tx_unicast, 3004 &ns->eth.tx_unicast); 3005 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 3006 GLPRT_MPTCL(hw->port_info->lport), 3007 pf->offset_loaded, &os->eth.tx_multicast, 3008 &ns->eth.tx_multicast); 3009 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 3010 GLPRT_BPTCL(hw->port_info->lport), 3011 pf->offset_loaded, &os->eth.tx_broadcast, 3012 &ns->eth.tx_broadcast); 3013 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 3014 ns->eth.tx_broadcast) * ETHER_CRC_LEN; 3015 3016 /* GLPRT_TEPC not supported */ 3017 3018 /* additional port specific stats */ 3019 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 3020 pf->offset_loaded, &os->tx_dropped_link_down, 3021 &ns->tx_dropped_link_down); 3022 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 3023 pf->offset_loaded, &os->crc_errors, 3024 &ns->crc_errors); 3025 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 3026 pf->offset_loaded, &os->illegal_bytes, 3027 &ns->illegal_bytes); 3028 /* GLPRT_ERRBC not supported */ 3029 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 3030 pf->offset_loaded, &os->mac_local_faults, 3031 &ns->mac_local_faults); 3032 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 3033 pf->offset_loaded, &os->mac_remote_faults, 3034 &ns->mac_remote_faults); 3035 3036 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 3037 pf->offset_loaded, &os->rx_len_errors, 3038 &ns->rx_len_errors); 3039 3040 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 3041 pf->offset_loaded, &os->link_xon_rx, 3042 &ns->link_xon_rx); 3043 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 3044 pf->offset_loaded, &os->link_xoff_rx, 3045 &ns->link_xoff_rx); 3046 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 3047 pf->offset_loaded, &os->link_xon_tx, 3048 &ns->link_xon_tx); 3049 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 3050 pf->offset_loaded, &os->link_xoff_tx, 3051 &ns->link_xoff_tx); 3052 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 3053 GLPRT_PRC64L(hw->port_info->lport), 3054 pf->offset_loaded, &os->rx_size_64, 3055 &ns->rx_size_64); 3056 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 3057 GLPRT_PRC127L(hw->port_info->lport), 3058 pf->offset_loaded, &os->rx_size_127, 3059 &ns->rx_size_127); 3060 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 3061 GLPRT_PRC255L(hw->port_info->lport), 3062 pf->offset_loaded, &os->rx_size_255, 3063 &ns->rx_size_255); 3064 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 3065 GLPRT_PRC511L(hw->port_info->lport), 3066 pf->offset_loaded, &os->rx_size_511, 3067 &ns->rx_size_511); 3068 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 3069 GLPRT_PRC1023L(hw->port_info->lport), 3070 pf->offset_loaded, &os->rx_size_1023, 3071 &ns->rx_size_1023); 3072 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 3073 GLPRT_PRC1522L(hw->port_info->lport), 3074 pf->offset_loaded, &os->rx_size_1522, 3075 &ns->rx_size_1522); 3076 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 3077 GLPRT_PRC9522L(hw->port_info->lport), 3078 pf->offset_loaded, &os->rx_size_big, 3079 &ns->rx_size_big); 3080 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 3081 pf->offset_loaded, &os->rx_undersize, 3082 &ns->rx_undersize); 3083 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 3084 pf->offset_loaded, &os->rx_fragments, 3085 &ns->rx_fragments); 3086 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 3087 pf->offset_loaded, &os->rx_oversize, 3088 &ns->rx_oversize); 3089 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 3090 pf->offset_loaded, &os->rx_jabber, 3091 &ns->rx_jabber); 3092 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 3093 GLPRT_PTC64L(hw->port_info->lport), 3094 pf->offset_loaded, &os->tx_size_64, 3095 &ns->tx_size_64); 3096 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 3097 GLPRT_PTC127L(hw->port_info->lport), 3098 pf->offset_loaded, &os->tx_size_127, 3099 &ns->tx_size_127); 3100 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 3101 GLPRT_PTC255L(hw->port_info->lport), 3102 pf->offset_loaded, &os->tx_size_255, 3103 &ns->tx_size_255); 3104 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 3105 GLPRT_PTC511L(hw->port_info->lport), 3106 pf->offset_loaded, &os->tx_size_511, 3107 &ns->tx_size_511); 3108 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 3109 GLPRT_PTC1023L(hw->port_info->lport), 3110 pf->offset_loaded, &os->tx_size_1023, 3111 &ns->tx_size_1023); 3112 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 3113 GLPRT_PTC1522L(hw->port_info->lport), 3114 pf->offset_loaded, &os->tx_size_1522, 3115 &ns->tx_size_1522); 3116 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 3117 GLPRT_PTC9522L(hw->port_info->lport), 3118 pf->offset_loaded, &os->tx_size_big, 3119 &ns->tx_size_big); 3120 3121 /* GLPRT_MSPDC not supported */ 3122 /* GLPRT_XEC not supported */ 3123 3124 pf->offset_loaded = true; 3125 3126 if (pf->main_vsi) 3127 ice_update_vsi_stats(pf->main_vsi); 3128 } 3129 3130 /* Get all statistics of a port */ 3131 static int 3132 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3133 { 3134 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3135 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3136 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 3137 3138 /* call read registers - updates values, now write them to struct */ 3139 ice_read_stats_registers(pf, hw); 3140 3141 stats->ipackets = ns->eth.rx_unicast + 3142 ns->eth.rx_multicast + 3143 ns->eth.rx_broadcast - 3144 ns->eth.rx_discards - 3145 pf->main_vsi->eth_stats.rx_discards; 3146 stats->opackets = ns->eth.tx_unicast + 3147 ns->eth.tx_multicast + 3148 ns->eth.tx_broadcast; 3149 stats->ibytes = ns->eth.rx_bytes; 3150 stats->obytes = ns->eth.tx_bytes; 3151 stats->oerrors = ns->eth.tx_errors + 3152 pf->main_vsi->eth_stats.tx_errors; 3153 3154 /* Rx Errors */ 3155 stats->imissed = ns->eth.rx_discards + 3156 pf->main_vsi->eth_stats.rx_discards; 3157 stats->ierrors = ns->crc_errors + 3158 ns->rx_undersize + 3159 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 3160 3161 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 3162 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 3163 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 3164 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 3165 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 3166 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 3167 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 3168 pf->main_vsi->eth_stats.rx_discards); 3169 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3170 ns->eth.rx_unknown_protocol); 3171 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 3172 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 3173 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 3174 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 3175 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 3176 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 3177 pf->main_vsi->eth_stats.tx_discards); 3178 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 3179 3180 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 3181 ns->tx_dropped_link_down); 3182 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 3183 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 3184 ns->illegal_bytes); 3185 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 3186 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 3187 ns->mac_local_faults); 3188 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 3189 ns->mac_remote_faults); 3190 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 3191 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 3192 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 3193 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 3194 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 3195 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 3196 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 3197 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 3198 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 3199 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 3200 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 3201 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 3202 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 3203 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 3204 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 3205 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 3206 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 3207 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 3208 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 3209 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 3210 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 3211 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 3212 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 3213 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 3214 return 0; 3215 } 3216 3217 /* Reset the statistics */ 3218 static void 3219 ice_stats_reset(struct rte_eth_dev *dev) 3220 { 3221 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3222 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3223 3224 /* Mark PF and VSI stats to update the offset, aka "reset" */ 3225 pf->offset_loaded = false; 3226 if (pf->main_vsi) 3227 pf->main_vsi->offset_loaded = false; 3228 3229 /* read the stats, reading current register values into offset */ 3230 ice_read_stats_registers(pf, hw); 3231 } 3232 3233 static uint32_t 3234 ice_xstats_calc_num(void) 3235 { 3236 uint32_t num; 3237 3238 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 3239 3240 return num; 3241 } 3242 3243 static int 3244 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3245 unsigned int n) 3246 { 3247 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3248 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3249 unsigned int i; 3250 unsigned int count; 3251 struct ice_hw_port_stats *hw_stats = &pf->stats; 3252 3253 count = ice_xstats_calc_num(); 3254 if (n < count) 3255 return count; 3256 3257 ice_read_stats_registers(pf, hw); 3258 3259 if (!xstats) 3260 return 0; 3261 3262 count = 0; 3263 3264 /* Get stats from ice_eth_stats struct */ 3265 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 3266 xstats[count].value = 3267 *(uint64_t *)((char *)&hw_stats->eth + 3268 ice_stats_strings[i].offset); 3269 xstats[count].id = count; 3270 count++; 3271 } 3272 3273 /* Get individiual stats from ice_hw_port struct */ 3274 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 3275 xstats[count].value = 3276 *(uint64_t *)((char *)hw_stats + 3277 ice_hw_port_strings[i].offset); 3278 xstats[count].id = count; 3279 count++; 3280 } 3281 3282 return count; 3283 } 3284 3285 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3286 struct rte_eth_xstat_name *xstats_names, 3287 __rte_unused unsigned int limit) 3288 { 3289 unsigned int count = 0; 3290 unsigned int i; 3291 3292 if (!xstats_names) 3293 return ice_xstats_calc_num(); 3294 3295 /* Note: limit checked in rte_eth_xstats_names() */ 3296 3297 /* Get stats from ice_eth_stats struct */ 3298 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 3299 snprintf(xstats_names[count].name, 3300 sizeof(xstats_names[count].name), 3301 "%s", ice_stats_strings[i].name); 3302 count++; 3303 } 3304 3305 /* Get individiual stats from ice_hw_port struct */ 3306 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 3307 snprintf(xstats_names[count].name, 3308 sizeof(xstats_names[count].name), 3309 "%s", ice_hw_port_strings[i].name); 3310 count++; 3311 } 3312 3313 return count; 3314 } 3315 3316 static int 3317 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3318 struct rte_pci_device *pci_dev) 3319 { 3320 return rte_eth_dev_pci_generic_probe(pci_dev, 3321 sizeof(struct ice_adapter), 3322 ice_dev_init); 3323 } 3324 3325 static int 3326 ice_pci_remove(struct rte_pci_device *pci_dev) 3327 { 3328 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 3329 } 3330 3331 static struct rte_pci_driver rte_ice_pmd = { 3332 .id_table = pci_id_ice_map, 3333 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 3334 RTE_PCI_DRV_IOVA_AS_VA, 3335 .probe = ice_pci_probe, 3336 .remove = ice_pci_remove, 3337 }; 3338 3339 /** 3340 * Driver initialization routine. 3341 * Invoked once at EAL init time. 3342 * Register itself as the [Poll Mode] Driver of PCI devices. 3343 */ 3344 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 3345 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 3346 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 3347 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 3348 ICE_MAX_QP_NUM "=<int>"); 3349 3350 RTE_INIT(ice_init_log) 3351 { 3352 ice_logtype_init = rte_log_register("pmd.net.ice.init"); 3353 if (ice_logtype_init >= 0) 3354 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE); 3355 ice_logtype_driver = rte_log_register("pmd.net.ice.driver"); 3356 if (ice_logtype_driver >= 0) 3357 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE); 3358 } 3359