1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include <rte_tailq.h> 14 15 #include "eal_firmware.h" 16 17 #include "base/ice_sched.h" 18 #include "base/ice_flow.h" 19 #include "base/ice_dcb.h" 20 #include "base/ice_common.h" 21 22 #include "rte_pmd_ice.h" 23 #include "ice_ethdev.h" 24 #include "ice_rxtx.h" 25 #include "ice_generic_flow.h" 26 27 /* devargs */ 28 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" 29 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" 30 #define ICE_PROTO_XTR_ARG "proto_xtr" 31 #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" 32 33 static const char * const ice_valid_args[] = { 34 ICE_SAFE_MODE_SUPPORT_ARG, 35 ICE_PIPELINE_MODE_SUPPORT_ARG, 36 ICE_PROTO_XTR_ARG, 37 ICE_HW_DEBUG_MASK_ARG, 38 NULL 39 }; 40 41 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = { 42 .name = "intel_pmd_dynfield_proto_xtr_metadata", 43 .size = sizeof(uint32_t), 44 .align = __alignof__(uint32_t), 45 .flags = 0, 46 }; 47 48 struct proto_xtr_ol_flag { 49 const struct rte_mbuf_dynflag param; 50 uint64_t *ol_flag; 51 bool required; 52 }; 53 54 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX]; 55 56 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = { 57 [PROTO_XTR_VLAN] = { 58 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" }, 59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask }, 60 [PROTO_XTR_IPV4] = { 61 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" }, 62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask }, 63 [PROTO_XTR_IPV6] = { 64 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" }, 65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask }, 66 [PROTO_XTR_IPV6_FLOW] = { 67 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" }, 68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask }, 69 [PROTO_XTR_TCP] = { 70 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" }, 71 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask }, 72 [PROTO_XTR_IP_OFFSET] = { 73 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" }, 74 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask }, 75 }; 76 77 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package" 78 #define ICE_COMMS_PKG_NAME "ICE COMMS Package" 79 #define ICE_MAX_RES_DESC_NUM 1024 80 81 static int ice_dev_configure(struct rte_eth_dev *dev); 82 static int ice_dev_start(struct rte_eth_dev *dev); 83 static int ice_dev_stop(struct rte_eth_dev *dev); 84 static int ice_dev_close(struct rte_eth_dev *dev); 85 static int ice_dev_reset(struct rte_eth_dev *dev); 86 static int ice_dev_info_get(struct rte_eth_dev *dev, 87 struct rte_eth_dev_info *dev_info); 88 static int ice_link_update(struct rte_eth_dev *dev, 89 int wait_to_complete); 90 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 91 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 92 93 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 94 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 95 static int ice_rss_reta_update(struct rte_eth_dev *dev, 96 struct rte_eth_rss_reta_entry64 *reta_conf, 97 uint16_t reta_size); 98 static int ice_rss_reta_query(struct rte_eth_dev *dev, 99 struct rte_eth_rss_reta_entry64 *reta_conf, 100 uint16_t reta_size); 101 static int ice_rss_hash_update(struct rte_eth_dev *dev, 102 struct rte_eth_rss_conf *rss_conf); 103 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 104 struct rte_eth_rss_conf *rss_conf); 105 static int ice_promisc_enable(struct rte_eth_dev *dev); 106 static int ice_promisc_disable(struct rte_eth_dev *dev); 107 static int ice_allmulti_enable(struct rte_eth_dev *dev); 108 static int ice_allmulti_disable(struct rte_eth_dev *dev); 109 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 110 uint16_t vlan_id, 111 int on); 112 static int ice_macaddr_set(struct rte_eth_dev *dev, 113 struct rte_ether_addr *mac_addr); 114 static int ice_macaddr_add(struct rte_eth_dev *dev, 115 struct rte_ether_addr *mac_addr, 116 __rte_unused uint32_t index, 117 uint32_t pool); 118 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 119 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 120 uint16_t queue_id); 121 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 122 uint16_t queue_id); 123 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 124 size_t fw_size); 125 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 126 uint16_t pvid, int on); 127 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 128 static int ice_get_eeprom(struct rte_eth_dev *dev, 129 struct rte_dev_eeprom_info *eeprom); 130 static int ice_stats_get(struct rte_eth_dev *dev, 131 struct rte_eth_stats *stats); 132 static int ice_stats_reset(struct rte_eth_dev *dev); 133 static int ice_xstats_get(struct rte_eth_dev *dev, 134 struct rte_eth_xstat *xstats, unsigned int n); 135 static int ice_xstats_get_names(struct rte_eth_dev *dev, 136 struct rte_eth_xstat_name *xstats_names, 137 unsigned int limit); 138 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev, 139 const struct rte_flow_ops **ops); 140 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 141 struct rte_eth_udp_tunnel *udp_tunnel); 142 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 143 struct rte_eth_udp_tunnel *udp_tunnel); 144 145 static const struct rte_pci_id pci_id_ice_map[] = { 146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) }, 147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) }, 148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) }, 149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) }, 150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) }, 151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) }, 155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) }, 156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) }, 157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) }, 158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) }, 159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) }, 160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) }, 161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) }, 162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) }, 163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) }, 164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) }, 165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) }, 166 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) }, 167 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) }, 168 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) }, 169 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) }, 170 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) }, 171 { .vendor_id = 0, /* sentinel */ }, 172 }; 173 174 static const struct eth_dev_ops ice_eth_dev_ops = { 175 .dev_configure = ice_dev_configure, 176 .dev_start = ice_dev_start, 177 .dev_stop = ice_dev_stop, 178 .dev_close = ice_dev_close, 179 .dev_reset = ice_dev_reset, 180 .dev_set_link_up = ice_dev_set_link_up, 181 .dev_set_link_down = ice_dev_set_link_down, 182 .rx_queue_start = ice_rx_queue_start, 183 .rx_queue_stop = ice_rx_queue_stop, 184 .tx_queue_start = ice_tx_queue_start, 185 .tx_queue_stop = ice_tx_queue_stop, 186 .rx_queue_setup = ice_rx_queue_setup, 187 .rx_queue_release = ice_rx_queue_release, 188 .tx_queue_setup = ice_tx_queue_setup, 189 .tx_queue_release = ice_tx_queue_release, 190 .dev_infos_get = ice_dev_info_get, 191 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 192 .link_update = ice_link_update, 193 .mtu_set = ice_mtu_set, 194 .mac_addr_set = ice_macaddr_set, 195 .mac_addr_add = ice_macaddr_add, 196 .mac_addr_remove = ice_macaddr_remove, 197 .vlan_filter_set = ice_vlan_filter_set, 198 .vlan_offload_set = ice_vlan_offload_set, 199 .reta_update = ice_rss_reta_update, 200 .reta_query = ice_rss_reta_query, 201 .rss_hash_update = ice_rss_hash_update, 202 .rss_hash_conf_get = ice_rss_hash_conf_get, 203 .promiscuous_enable = ice_promisc_enable, 204 .promiscuous_disable = ice_promisc_disable, 205 .allmulticast_enable = ice_allmulti_enable, 206 .allmulticast_disable = ice_allmulti_disable, 207 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 208 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 209 .fw_version_get = ice_fw_version_get, 210 .vlan_pvid_set = ice_vlan_pvid_set, 211 .rxq_info_get = ice_rxq_info_get, 212 .txq_info_get = ice_txq_info_get, 213 .rx_burst_mode_get = ice_rx_burst_mode_get, 214 .tx_burst_mode_get = ice_tx_burst_mode_get, 215 .get_eeprom_length = ice_get_eeprom_length, 216 .get_eeprom = ice_get_eeprom, 217 .stats_get = ice_stats_get, 218 .stats_reset = ice_stats_reset, 219 .xstats_get = ice_xstats_get, 220 .xstats_get_names = ice_xstats_get_names, 221 .xstats_reset = ice_stats_reset, 222 .flow_ops_get = ice_dev_flow_ops_get, 223 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, 224 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, 225 .tx_done_cleanup = ice_tx_done_cleanup, 226 .get_monitor_addr = ice_get_monitor_addr, 227 }; 228 229 /* store statistics names and its offset in stats structure */ 230 struct ice_xstats_name_off { 231 char name[RTE_ETH_XSTATS_NAME_SIZE]; 232 unsigned int offset; 233 }; 234 235 static const struct ice_xstats_name_off ice_stats_strings[] = { 236 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 237 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 238 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 239 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 240 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 241 rx_unknown_protocol)}, 242 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 243 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 244 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 245 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 246 }; 247 248 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 249 sizeof(ice_stats_strings[0])) 250 251 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 252 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 253 tx_dropped_link_down)}, 254 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 255 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 256 illegal_bytes)}, 257 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 258 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 259 mac_local_faults)}, 260 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 261 mac_remote_faults)}, 262 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 263 rx_len_errors)}, 264 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 265 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 266 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 267 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 268 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 269 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 270 rx_size_127)}, 271 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 272 rx_size_255)}, 273 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 274 rx_size_511)}, 275 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 276 rx_size_1023)}, 277 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 278 rx_size_1522)}, 279 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 280 rx_size_big)}, 281 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 282 rx_undersize)}, 283 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 284 rx_oversize)}, 285 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 286 mac_short_pkt_dropped)}, 287 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 288 rx_fragments)}, 289 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 290 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 291 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 292 tx_size_127)}, 293 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 294 tx_size_255)}, 295 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 296 tx_size_511)}, 297 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 298 tx_size_1023)}, 299 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 300 tx_size_1522)}, 301 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 302 tx_size_big)}, 303 }; 304 305 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 306 sizeof(ice_hw_port_strings[0])) 307 308 static void 309 ice_init_controlq_parameter(struct ice_hw *hw) 310 { 311 /* fields for adminq */ 312 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 313 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 314 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 315 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 316 317 /* fields for mailboxq, DPDK used as PF host */ 318 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 319 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 320 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 321 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 322 } 323 324 static int 325 lookup_proto_xtr_type(const char *xtr_name) 326 { 327 static struct { 328 const char *name; 329 enum proto_xtr_type type; 330 } xtr_type_map[] = { 331 { "vlan", PROTO_XTR_VLAN }, 332 { "ipv4", PROTO_XTR_IPV4 }, 333 { "ipv6", PROTO_XTR_IPV6 }, 334 { "ipv6_flow", PROTO_XTR_IPV6_FLOW }, 335 { "tcp", PROTO_XTR_TCP }, 336 { "ip_offset", PROTO_XTR_IP_OFFSET }, 337 }; 338 uint32_t i; 339 340 for (i = 0; i < RTE_DIM(xtr_type_map); i++) { 341 if (strcmp(xtr_name, xtr_type_map[i].name) == 0) 342 return xtr_type_map[i].type; 343 } 344 345 return -1; 346 } 347 348 /* 349 * Parse elem, the elem could be single number/range or '(' ')' group 350 * 1) A single number elem, it's just a simple digit. e.g. 9 351 * 2) A single range elem, two digits with a '-' between. e.g. 2-6 352 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6) 353 * Within group elem, '-' used for a range separator; 354 * ',' used for a single number. 355 */ 356 static int 357 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs) 358 { 359 const char *str = input; 360 char *end = NULL; 361 uint32_t min, max; 362 uint32_t idx; 363 364 while (isblank(*str)) 365 str++; 366 367 if (!isdigit(*str) && *str != '(') 368 return -1; 369 370 /* process single number or single range of number */ 371 if (*str != '(') { 372 errno = 0; 373 idx = strtoul(str, &end, 10); 374 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 375 return -1; 376 377 while (isblank(*end)) 378 end++; 379 380 min = idx; 381 max = idx; 382 383 /* process single <number>-<number> */ 384 if (*end == '-') { 385 end++; 386 while (isblank(*end)) 387 end++; 388 if (!isdigit(*end)) 389 return -1; 390 391 errno = 0; 392 idx = strtoul(end, &end, 10); 393 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 394 return -1; 395 396 max = idx; 397 while (isblank(*end)) 398 end++; 399 } 400 401 if (*end != ':') 402 return -1; 403 404 for (idx = RTE_MIN(min, max); 405 idx <= RTE_MAX(min, max); idx++) 406 devargs->proto_xtr[idx] = xtr_type; 407 408 return 0; 409 } 410 411 /* process set within bracket */ 412 str++; 413 while (isblank(*str)) 414 str++; 415 if (*str == '\0') 416 return -1; 417 418 min = ICE_MAX_QUEUE_NUM; 419 do { 420 /* go ahead to the first digit */ 421 while (isblank(*str)) 422 str++; 423 if (!isdigit(*str)) 424 return -1; 425 426 /* get the digit value */ 427 errno = 0; 428 idx = strtoul(str, &end, 10); 429 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 430 return -1; 431 432 /* go ahead to separator '-',',' and ')' */ 433 while (isblank(*end)) 434 end++; 435 if (*end == '-') { 436 if (min == ICE_MAX_QUEUE_NUM) 437 min = idx; 438 else /* avoid continuous '-' */ 439 return -1; 440 } else if (*end == ',' || *end == ')') { 441 max = idx; 442 if (min == ICE_MAX_QUEUE_NUM) 443 min = idx; 444 445 for (idx = RTE_MIN(min, max); 446 idx <= RTE_MAX(min, max); idx++) 447 devargs->proto_xtr[idx] = xtr_type; 448 449 min = ICE_MAX_QUEUE_NUM; 450 } else { 451 return -1; 452 } 453 454 str = end + 1; 455 } while (*end != ')' && *end != '\0'); 456 457 return 0; 458 } 459 460 static int 461 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs) 462 { 463 const char *queue_start; 464 uint32_t idx; 465 int xtr_type; 466 char xtr_name[32]; 467 468 while (isblank(*queues)) 469 queues++; 470 471 if (*queues != '[') { 472 xtr_type = lookup_proto_xtr_type(queues); 473 if (xtr_type < 0) 474 return -1; 475 476 devargs->proto_xtr_dflt = xtr_type; 477 478 return 0; 479 } 480 481 queues++; 482 do { 483 while (isblank(*queues)) 484 queues++; 485 if (*queues == '\0') 486 return -1; 487 488 queue_start = queues; 489 490 /* go across a complete bracket */ 491 if (*queue_start == '(') { 492 queues += strcspn(queues, ")"); 493 if (*queues != ')') 494 return -1; 495 } 496 497 /* scan the separator ':' */ 498 queues += strcspn(queues, ":"); 499 if (*queues++ != ':') 500 return -1; 501 while (isblank(*queues)) 502 queues++; 503 504 for (idx = 0; ; idx++) { 505 if (isblank(queues[idx]) || 506 queues[idx] == ',' || 507 queues[idx] == ']' || 508 queues[idx] == '\0') 509 break; 510 511 if (idx > sizeof(xtr_name) - 2) 512 return -1; 513 514 xtr_name[idx] = queues[idx]; 515 } 516 xtr_name[idx] = '\0'; 517 xtr_type = lookup_proto_xtr_type(xtr_name); 518 if (xtr_type < 0) 519 return -1; 520 521 queues += idx; 522 523 while (isblank(*queues) || *queues == ',' || *queues == ']') 524 queues++; 525 526 if (parse_queue_set(queue_start, xtr_type, devargs) < 0) 527 return -1; 528 } while (*queues != '\0'); 529 530 return 0; 531 } 532 533 static int 534 handle_proto_xtr_arg(__rte_unused const char *key, const char *value, 535 void *extra_args) 536 { 537 struct ice_devargs *devargs = extra_args; 538 539 if (value == NULL || extra_args == NULL) 540 return -EINVAL; 541 542 if (parse_queue_proto_xtr(value, devargs) < 0) { 543 PMD_DRV_LOG(ERR, 544 "The protocol extraction parameter is wrong : '%s'", 545 value); 546 return -1; 547 } 548 549 return 0; 550 } 551 552 static void 553 ice_check_proto_xtr_support(struct ice_hw *hw) 554 { 555 #define FLX_REG(val, fld, idx) \ 556 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ 557 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) 558 static struct { 559 uint32_t rxdid; 560 uint8_t opcode; 561 uint8_t protid_0; 562 uint8_t protid_1; 563 } xtr_sets[] = { 564 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN, 565 ICE_RX_OPC_EXTRACT, 566 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O}, 567 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4, 568 ICE_RX_OPC_EXTRACT, 569 ICE_PROT_IPV4_OF_OR_S, 570 ICE_PROT_IPV4_OF_OR_S }, 571 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6, 572 ICE_RX_OPC_EXTRACT, 573 ICE_PROT_IPV6_OF_OR_S, 574 ICE_PROT_IPV6_OF_OR_S }, 575 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW, 576 ICE_RX_OPC_EXTRACT, 577 ICE_PROT_IPV6_OF_OR_S, 578 ICE_PROT_IPV6_OF_OR_S }, 579 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP, 580 ICE_RX_OPC_EXTRACT, 581 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, 582 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET, 583 ICE_RX_OPC_PROTID, 584 ICE_PROT_IPV4_OF_OR_S, 585 ICE_PROT_IPV6_OF_OR_S }, 586 }; 587 uint32_t i; 588 589 for (i = 0; i < RTE_DIM(xtr_sets); i++) { 590 uint32_t rxdid = xtr_sets[i].rxdid; 591 uint32_t v; 592 593 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) { 594 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid)); 595 596 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 && 597 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode) 598 ice_proto_xtr_hw_support[i] = true; 599 } 600 601 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) { 602 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid)); 603 604 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 && 605 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode) 606 ice_proto_xtr_hw_support[i] = true; 607 } 608 } 609 } 610 611 static int 612 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 613 uint32_t num) 614 { 615 struct pool_entry *entry; 616 617 if (!pool || !num) 618 return -EINVAL; 619 620 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 621 if (!entry) { 622 PMD_INIT_LOG(ERR, 623 "Failed to allocate memory for resource pool"); 624 return -ENOMEM; 625 } 626 627 /* queue heap initialize */ 628 pool->num_free = num; 629 pool->num_alloc = 0; 630 pool->base = base; 631 LIST_INIT(&pool->alloc_list); 632 LIST_INIT(&pool->free_list); 633 634 /* Initialize element */ 635 entry->base = 0; 636 entry->len = num; 637 638 LIST_INSERT_HEAD(&pool->free_list, entry, next); 639 return 0; 640 } 641 642 static int 643 ice_res_pool_alloc(struct ice_res_pool_info *pool, 644 uint16_t num) 645 { 646 struct pool_entry *entry, *valid_entry; 647 648 if (!pool || !num) { 649 PMD_INIT_LOG(ERR, "Invalid parameter"); 650 return -EINVAL; 651 } 652 653 if (pool->num_free < num) { 654 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 655 num, pool->num_free); 656 return -ENOMEM; 657 } 658 659 valid_entry = NULL; 660 /* Lookup in free list and find most fit one */ 661 LIST_FOREACH(entry, &pool->free_list, next) { 662 if (entry->len >= num) { 663 /* Find best one */ 664 if (entry->len == num) { 665 valid_entry = entry; 666 break; 667 } 668 if (!valid_entry || 669 valid_entry->len > entry->len) 670 valid_entry = entry; 671 } 672 } 673 674 /* Not find one to satisfy the request, return */ 675 if (!valid_entry) { 676 PMD_INIT_LOG(ERR, "No valid entry found"); 677 return -ENOMEM; 678 } 679 /** 680 * The entry have equal queue number as requested, 681 * remove it from alloc_list. 682 */ 683 if (valid_entry->len == num) { 684 LIST_REMOVE(valid_entry, next); 685 } else { 686 /** 687 * The entry have more numbers than requested, 688 * create a new entry for alloc_list and minus its 689 * queue base and number in free_list. 690 */ 691 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 692 if (!entry) { 693 PMD_INIT_LOG(ERR, 694 "Failed to allocate memory for " 695 "resource pool"); 696 return -ENOMEM; 697 } 698 entry->base = valid_entry->base; 699 entry->len = num; 700 valid_entry->base += num; 701 valid_entry->len -= num; 702 valid_entry = entry; 703 } 704 705 /* Insert it into alloc list, not sorted */ 706 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 707 708 pool->num_free -= valid_entry->len; 709 pool->num_alloc += valid_entry->len; 710 711 return valid_entry->base + pool->base; 712 } 713 714 static void 715 ice_res_pool_destroy(struct ice_res_pool_info *pool) 716 { 717 struct pool_entry *entry, *next_entry; 718 719 if (!pool) 720 return; 721 722 for (entry = LIST_FIRST(&pool->alloc_list); 723 entry && (next_entry = LIST_NEXT(entry, next), 1); 724 entry = next_entry) { 725 LIST_REMOVE(entry, next); 726 rte_free(entry); 727 } 728 729 for (entry = LIST_FIRST(&pool->free_list); 730 entry && (next_entry = LIST_NEXT(entry, next), 1); 731 entry = next_entry) { 732 LIST_REMOVE(entry, next); 733 rte_free(entry); 734 } 735 736 pool->num_free = 0; 737 pool->num_alloc = 0; 738 pool->base = 0; 739 LIST_INIT(&pool->alloc_list); 740 LIST_INIT(&pool->free_list); 741 } 742 743 static void 744 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 745 { 746 /* Set VSI LUT selection */ 747 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 748 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 749 /* Set Hash scheme */ 750 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 751 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 752 /* enable TC */ 753 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 754 } 755 756 static enum ice_status 757 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 758 struct ice_aqc_vsi_props *info, 759 uint8_t enabled_tcmap) 760 { 761 uint16_t bsf, qp_idx; 762 763 /* default tc 0 now. Multi-TC supporting need to be done later. 764 * Configure TC and queue mapping parameters, for enabled TC, 765 * allocate qpnum_per_tc queues to this traffic. 766 */ 767 if (enabled_tcmap != 0x01) { 768 PMD_INIT_LOG(ERR, "only TC0 is supported"); 769 return -ENOTSUP; 770 } 771 772 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 773 bsf = rte_bsf32(vsi->nb_qps); 774 /* Adjust the queue number to actual queues that can be applied */ 775 vsi->nb_qps = 0x1 << bsf; 776 777 qp_idx = 0; 778 /* Set tc and queue mapping with VSI */ 779 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 780 ICE_AQ_VSI_TC_Q_OFFSET_S) | 781 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 782 783 /* Associate queue number with VSI */ 784 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 785 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 786 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 787 info->valid_sections |= 788 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 789 /* Set the info.ingress_table and info.egress_table 790 * for UP translate table. Now just set it to 1:1 map by default 791 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 792 */ 793 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 794 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 795 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 796 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 797 return 0; 798 } 799 800 static int 801 ice_init_mac_address(struct rte_eth_dev *dev) 802 { 803 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 804 805 if (!rte_is_unicast_ether_addr 806 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 807 PMD_INIT_LOG(ERR, "Invalid MAC address"); 808 return -EINVAL; 809 } 810 811 rte_ether_addr_copy( 812 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 813 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 814 815 dev->data->mac_addrs = 816 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0); 817 if (!dev->data->mac_addrs) { 818 PMD_INIT_LOG(ERR, 819 "Failed to allocate memory to store mac address"); 820 return -ENOMEM; 821 } 822 /* store it to dev data */ 823 rte_ether_addr_copy( 824 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 825 &dev->data->mac_addrs[0]); 826 return 0; 827 } 828 829 /* Find out specific MAC filter */ 830 static struct ice_mac_filter * 831 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 832 { 833 struct ice_mac_filter *f; 834 835 TAILQ_FOREACH(f, &vsi->mac_list, next) { 836 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 837 return f; 838 } 839 840 return NULL; 841 } 842 843 static int 844 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 845 { 846 struct ice_fltr_list_entry *m_list_itr = NULL; 847 struct ice_mac_filter *f; 848 struct LIST_HEAD_TYPE list_head; 849 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 850 int ret = 0; 851 852 /* If it's added and configured, return */ 853 f = ice_find_mac_filter(vsi, mac_addr); 854 if (f) { 855 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 856 return 0; 857 } 858 859 INIT_LIST_HEAD(&list_head); 860 861 m_list_itr = (struct ice_fltr_list_entry *) 862 ice_malloc(hw, sizeof(*m_list_itr)); 863 if (!m_list_itr) { 864 ret = -ENOMEM; 865 goto DONE; 866 } 867 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 868 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 869 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 870 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 871 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 872 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 873 m_list_itr->fltr_info.vsi_handle = vsi->idx; 874 875 LIST_ADD(&m_list_itr->list_entry, &list_head); 876 877 /* Add the mac */ 878 ret = ice_add_mac(hw, &list_head); 879 if (ret != ICE_SUCCESS) { 880 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 881 ret = -EINVAL; 882 goto DONE; 883 } 884 /* Add the mac addr into mac list */ 885 f = rte_zmalloc(NULL, sizeof(*f), 0); 886 if (!f) { 887 PMD_DRV_LOG(ERR, "failed to allocate memory"); 888 ret = -ENOMEM; 889 goto DONE; 890 } 891 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr); 892 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 893 vsi->mac_num++; 894 895 ret = 0; 896 897 DONE: 898 rte_free(m_list_itr); 899 return ret; 900 } 901 902 static int 903 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 904 { 905 struct ice_fltr_list_entry *m_list_itr = NULL; 906 struct ice_mac_filter *f; 907 struct LIST_HEAD_TYPE list_head; 908 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 909 int ret = 0; 910 911 /* Can't find it, return an error */ 912 f = ice_find_mac_filter(vsi, mac_addr); 913 if (!f) 914 return -EINVAL; 915 916 INIT_LIST_HEAD(&list_head); 917 918 m_list_itr = (struct ice_fltr_list_entry *) 919 ice_malloc(hw, sizeof(*m_list_itr)); 920 if (!m_list_itr) { 921 ret = -ENOMEM; 922 goto DONE; 923 } 924 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 925 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 926 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 927 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 928 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 929 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 930 m_list_itr->fltr_info.vsi_handle = vsi->idx; 931 932 LIST_ADD(&m_list_itr->list_entry, &list_head); 933 934 /* remove the mac filter */ 935 ret = ice_remove_mac(hw, &list_head); 936 if (ret != ICE_SUCCESS) { 937 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 938 ret = -EINVAL; 939 goto DONE; 940 } 941 942 /* Remove the mac addr from mac list */ 943 TAILQ_REMOVE(&vsi->mac_list, f, next); 944 rte_free(f); 945 vsi->mac_num--; 946 947 ret = 0; 948 DONE: 949 rte_free(m_list_itr); 950 return ret; 951 } 952 953 /* Find out specific VLAN filter */ 954 static struct ice_vlan_filter * 955 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) 956 { 957 struct ice_vlan_filter *f; 958 959 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 960 if (vlan->tpid == f->vlan_info.vlan.tpid && 961 vlan->vid == f->vlan_info.vlan.vid) 962 return f; 963 } 964 965 return NULL; 966 } 967 968 static int 969 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) 970 { 971 struct ice_fltr_list_entry *v_list_itr = NULL; 972 struct ice_vlan_filter *f; 973 struct LIST_HEAD_TYPE list_head; 974 struct ice_hw *hw; 975 int ret = 0; 976 977 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID) 978 return -EINVAL; 979 980 hw = ICE_VSI_TO_HW(vsi); 981 982 /* If it's added and configured, return. */ 983 f = ice_find_vlan_filter(vsi, vlan); 984 if (f) { 985 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 986 return 0; 987 } 988 989 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 990 return 0; 991 992 INIT_LIST_HEAD(&list_head); 993 994 v_list_itr = (struct ice_fltr_list_entry *) 995 ice_malloc(hw, sizeof(*v_list_itr)); 996 if (!v_list_itr) { 997 ret = -ENOMEM; 998 goto DONE; 999 } 1000 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid; 1001 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid; 1002 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true; 1003 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1004 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1005 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1006 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1007 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1008 1009 LIST_ADD(&v_list_itr->list_entry, &list_head); 1010 1011 /* Add the vlan */ 1012 ret = ice_add_vlan(hw, &list_head); 1013 if (ret != ICE_SUCCESS) { 1014 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 1015 ret = -EINVAL; 1016 goto DONE; 1017 } 1018 1019 /* Add vlan into vlan list */ 1020 f = rte_zmalloc(NULL, sizeof(*f), 0); 1021 if (!f) { 1022 PMD_DRV_LOG(ERR, "failed to allocate memory"); 1023 ret = -ENOMEM; 1024 goto DONE; 1025 } 1026 f->vlan_info.vlan.tpid = vlan->tpid; 1027 f->vlan_info.vlan.vid = vlan->vid; 1028 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 1029 vsi->vlan_num++; 1030 1031 ret = 0; 1032 1033 DONE: 1034 rte_free(v_list_itr); 1035 return ret; 1036 } 1037 1038 static int 1039 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) 1040 { 1041 struct ice_fltr_list_entry *v_list_itr = NULL; 1042 struct ice_vlan_filter *f; 1043 struct LIST_HEAD_TYPE list_head; 1044 struct ice_hw *hw; 1045 int ret = 0; 1046 1047 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID) 1048 return -EINVAL; 1049 1050 hw = ICE_VSI_TO_HW(vsi); 1051 1052 /* Can't find it, return an error */ 1053 f = ice_find_vlan_filter(vsi, vlan); 1054 if (!f) 1055 return -EINVAL; 1056 1057 INIT_LIST_HEAD(&list_head); 1058 1059 v_list_itr = (struct ice_fltr_list_entry *) 1060 ice_malloc(hw, sizeof(*v_list_itr)); 1061 if (!v_list_itr) { 1062 ret = -ENOMEM; 1063 goto DONE; 1064 } 1065 1066 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid; 1067 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid; 1068 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true; 1069 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1070 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1071 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1072 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1073 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1074 1075 LIST_ADD(&v_list_itr->list_entry, &list_head); 1076 1077 /* remove the vlan filter */ 1078 ret = ice_remove_vlan(hw, &list_head); 1079 if (ret != ICE_SUCCESS) { 1080 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 1081 ret = -EINVAL; 1082 goto DONE; 1083 } 1084 1085 /* Remove the vlan id from vlan list */ 1086 TAILQ_REMOVE(&vsi->vlan_list, f, next); 1087 rte_free(f); 1088 vsi->vlan_num--; 1089 1090 ret = 0; 1091 DONE: 1092 rte_free(v_list_itr); 1093 return ret; 1094 } 1095 1096 static int 1097 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 1098 { 1099 struct ice_mac_filter *m_f; 1100 struct ice_vlan_filter *v_f; 1101 void *temp; 1102 int ret = 0; 1103 1104 if (!vsi || !vsi->mac_num) 1105 return -EINVAL; 1106 1107 TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) { 1108 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 1109 if (ret != ICE_SUCCESS) { 1110 ret = -EINVAL; 1111 goto DONE; 1112 } 1113 } 1114 1115 if (vsi->vlan_num == 0) 1116 return 0; 1117 1118 TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) { 1119 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan); 1120 if (ret != ICE_SUCCESS) { 1121 ret = -EINVAL; 1122 goto DONE; 1123 } 1124 } 1125 1126 DONE: 1127 return ret; 1128 } 1129 1130 /* Enable IRQ0 */ 1131 static void 1132 ice_pf_enable_irq0(struct ice_hw *hw) 1133 { 1134 /* reset the registers */ 1135 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 1136 ICE_READ_REG(hw, PFINT_OICR); 1137 1138 #ifdef ICE_LSE_SPT 1139 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 1140 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 1141 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 1142 1143 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 1144 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 1145 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 1146 PFINT_OICR_CTL_ITR_INDX_M) | 1147 PFINT_OICR_CTL_CAUSE_ENA_M); 1148 1149 ICE_WRITE_REG(hw, PFINT_FW_CTL, 1150 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 1151 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 1152 PFINT_FW_CTL_ITR_INDX_M) | 1153 PFINT_FW_CTL_CAUSE_ENA_M); 1154 #else 1155 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 1156 #endif 1157 1158 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1159 GLINT_DYN_CTL_INTENA_M | 1160 GLINT_DYN_CTL_CLEARPBA_M | 1161 GLINT_DYN_CTL_ITR_INDX_M); 1162 1163 ice_flush(hw); 1164 } 1165 1166 /* Disable IRQ0 */ 1167 static void 1168 ice_pf_disable_irq0(struct ice_hw *hw) 1169 { 1170 /* Disable all interrupt types */ 1171 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1172 ice_flush(hw); 1173 } 1174 1175 #ifdef ICE_LSE_SPT 1176 static void 1177 ice_handle_aq_msg(struct rte_eth_dev *dev) 1178 { 1179 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1180 struct ice_ctl_q_info *cq = &hw->adminq; 1181 struct ice_rq_event_info event; 1182 uint16_t pending, opcode; 1183 int ret; 1184 1185 event.buf_len = ICE_AQ_MAX_BUF_LEN; 1186 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 1187 if (!event.msg_buf) { 1188 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 1189 return; 1190 } 1191 1192 pending = 1; 1193 while (pending) { 1194 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 1195 1196 if (ret != ICE_SUCCESS) { 1197 PMD_DRV_LOG(INFO, 1198 "Failed to read msg from AdminQ, " 1199 "adminq_err: %u", 1200 hw->adminq.sq_last_status); 1201 break; 1202 } 1203 opcode = rte_le_to_cpu_16(event.desc.opcode); 1204 1205 switch (opcode) { 1206 case ice_aqc_opc_get_link_status: 1207 ret = ice_link_update(dev, 0); 1208 if (!ret) 1209 rte_eth_dev_callback_process 1210 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1211 break; 1212 default: 1213 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1214 opcode); 1215 break; 1216 } 1217 } 1218 rte_free(event.msg_buf); 1219 } 1220 #endif 1221 1222 /** 1223 * Interrupt handler triggered by NIC for handling 1224 * specific interrupt. 1225 * 1226 * @param handle 1227 * Pointer to interrupt handle. 1228 * @param param 1229 * The address of parameter (struct rte_eth_dev *) regsitered before. 1230 * 1231 * @return 1232 * void 1233 */ 1234 static void 1235 ice_interrupt_handler(void *param) 1236 { 1237 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1238 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1239 uint32_t oicr; 1240 uint32_t reg; 1241 uint8_t pf_num; 1242 uint8_t event; 1243 uint16_t queue; 1244 int ret; 1245 #ifdef ICE_LSE_SPT 1246 uint32_t int_fw_ctl; 1247 #endif 1248 1249 /* Disable interrupt */ 1250 ice_pf_disable_irq0(hw); 1251 1252 /* read out interrupt causes */ 1253 oicr = ICE_READ_REG(hw, PFINT_OICR); 1254 #ifdef ICE_LSE_SPT 1255 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1256 #endif 1257 1258 /* No interrupt event indicated */ 1259 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1260 PMD_DRV_LOG(INFO, "No interrupt event"); 1261 goto done; 1262 } 1263 1264 #ifdef ICE_LSE_SPT 1265 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1266 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1267 ice_handle_aq_msg(dev); 1268 } 1269 #else 1270 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1271 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1272 ret = ice_link_update(dev, 0); 1273 if (!ret) 1274 rte_eth_dev_callback_process 1275 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1276 } 1277 #endif 1278 1279 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1280 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1281 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1282 if (reg & GL_MDET_TX_PQM_VALID_M) { 1283 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1284 GL_MDET_TX_PQM_PF_NUM_S; 1285 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1286 GL_MDET_TX_PQM_MAL_TYPE_S; 1287 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1288 GL_MDET_TX_PQM_QNUM_S; 1289 1290 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1291 "%d by PQM on TX queue %d PF# %d", 1292 event, queue, pf_num); 1293 } 1294 1295 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1296 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1297 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1298 GL_MDET_TX_TCLAN_PF_NUM_S; 1299 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1300 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1301 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1302 GL_MDET_TX_TCLAN_QNUM_S; 1303 1304 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1305 "%d by TCLAN on TX queue %d PF# %d", 1306 event, queue, pf_num); 1307 } 1308 } 1309 done: 1310 /* Enable interrupt */ 1311 ice_pf_enable_irq0(hw); 1312 rte_intr_ack(dev->intr_handle); 1313 } 1314 1315 static void 1316 ice_init_proto_xtr(struct rte_eth_dev *dev) 1317 { 1318 struct ice_adapter *ad = 1319 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1320 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1321 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1322 const struct proto_xtr_ol_flag *ol_flag; 1323 bool proto_xtr_enable = false; 1324 int offset; 1325 uint16_t i; 1326 1327 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0); 1328 if (unlikely(pf->proto_xtr == NULL)) { 1329 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table"); 1330 return; 1331 } 1332 1333 for (i = 0; i < pf->lan_nb_qps; i++) { 1334 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ? 1335 ad->devargs.proto_xtr[i] : 1336 ad->devargs.proto_xtr_dflt; 1337 1338 if (pf->proto_xtr[i] != PROTO_XTR_NONE) { 1339 uint8_t type = pf->proto_xtr[i]; 1340 1341 ice_proto_xtr_ol_flag_params[type].required = true; 1342 proto_xtr_enable = true; 1343 } 1344 } 1345 1346 if (likely(!proto_xtr_enable)) 1347 return; 1348 1349 ice_check_proto_xtr_support(hw); 1350 1351 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param); 1352 if (unlikely(offset == -1)) { 1353 PMD_DRV_LOG(ERR, 1354 "Protocol extraction metadata is disabled in mbuf with error %d", 1355 -rte_errno); 1356 return; 1357 } 1358 1359 PMD_DRV_LOG(DEBUG, 1360 "Protocol extraction metadata offset in mbuf is : %d", 1361 offset); 1362 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset; 1363 1364 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) { 1365 ol_flag = &ice_proto_xtr_ol_flag_params[i]; 1366 1367 if (!ol_flag->required) 1368 continue; 1369 1370 if (!ice_proto_xtr_hw_support[i]) { 1371 PMD_DRV_LOG(ERR, 1372 "Protocol extraction type %u is not supported in hardware", 1373 i); 1374 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1375 break; 1376 } 1377 1378 offset = rte_mbuf_dynflag_register(&ol_flag->param); 1379 if (unlikely(offset == -1)) { 1380 PMD_DRV_LOG(ERR, 1381 "Protocol extraction offload '%s' failed to register with error %d", 1382 ol_flag->param.name, -rte_errno); 1383 1384 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1385 break; 1386 } 1387 1388 PMD_DRV_LOG(DEBUG, 1389 "Protocol extraction offload '%s' offset in mbuf is : %d", 1390 ol_flag->param.name, offset); 1391 *ol_flag->ol_flag = 1ULL << offset; 1392 } 1393 } 1394 1395 /* Initialize SW parameters of PF */ 1396 static int 1397 ice_pf_sw_init(struct rte_eth_dev *dev) 1398 { 1399 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1400 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1401 1402 pf->lan_nb_qp_max = 1403 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1404 hw->func_caps.common_cap.num_rxq); 1405 1406 pf->lan_nb_qps = pf->lan_nb_qp_max; 1407 1408 ice_init_proto_xtr(dev); 1409 1410 if (hw->func_caps.fd_fltr_guar > 0 || 1411 hw->func_caps.fd_fltr_best_effort > 0) { 1412 pf->flags |= ICE_FLAG_FDIR; 1413 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR; 1414 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps; 1415 } else { 1416 pf->fdir_nb_qps = 0; 1417 } 1418 pf->fdir_qp_offset = 0; 1419 1420 return 0; 1421 } 1422 1423 struct ice_vsi * 1424 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1425 { 1426 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1427 struct ice_vsi *vsi = NULL; 1428 struct ice_vsi_ctx vsi_ctx; 1429 int ret; 1430 struct rte_ether_addr broadcast = { 1431 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1432 struct rte_ether_addr mac_addr; 1433 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1434 uint8_t tc_bitmap = 0x1; 1435 uint16_t cfg; 1436 1437 /* hw->num_lports = 1 in NIC mode */ 1438 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1439 if (!vsi) 1440 return NULL; 1441 1442 vsi->idx = pf->next_vsi_idx; 1443 pf->next_vsi_idx++; 1444 vsi->type = type; 1445 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1446 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1447 vsi->vlan_anti_spoof_on = 0; 1448 vsi->vlan_filter_on = 1; 1449 TAILQ_INIT(&vsi->mac_list); 1450 TAILQ_INIT(&vsi->vlan_list); 1451 1452 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ 1453 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1454 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : 1455 hw->func_caps.common_cap.rss_table_size; 1456 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1457 1458 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1459 switch (type) { 1460 case ICE_VSI_PF: 1461 vsi->nb_qps = pf->lan_nb_qps; 1462 vsi->base_queue = 1; 1463 ice_vsi_config_default_rss(&vsi_ctx.info); 1464 vsi_ctx.alloc_from_pool = true; 1465 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1466 /* switch_id is queried by get_switch_config aq, which is done 1467 * by ice_init_hw 1468 */ 1469 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1470 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1471 /* Allow all untagged or tagged packets */ 1472 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; 1473 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; 1474 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1475 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1476 if (ice_is_dvm_ena(hw)) { 1477 vsi_ctx.info.outer_vlan_flags = 1478 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL << 1479 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) & 1480 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M; 1481 vsi_ctx.info.outer_vlan_flags |= 1482 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 << 1483 ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 1484 ICE_AQ_VSI_OUTER_TAG_TYPE_M; 1485 } 1486 1487 /* FDIR */ 1488 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID | 1489 ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1490 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1491 cfg = ICE_AQ_VSI_FD_ENABLE; 1492 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1493 vsi_ctx.info.max_fd_fltr_dedicated = 1494 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar); 1495 vsi_ctx.info.max_fd_fltr_shared = 1496 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); 1497 1498 /* Enable VLAN/UP trip */ 1499 ret = ice_vsi_config_tc_queue_mapping(vsi, 1500 &vsi_ctx.info, 1501 ICE_DEFAULT_TCMAP); 1502 if (ret) { 1503 PMD_INIT_LOG(ERR, 1504 "tc queue mapping with vsi failed, " 1505 "err = %d", 1506 ret); 1507 goto fail_mem; 1508 } 1509 1510 break; 1511 case ICE_VSI_CTRL: 1512 vsi->nb_qps = pf->fdir_nb_qps; 1513 vsi->base_queue = ICE_FDIR_QUEUE_ID; 1514 vsi_ctx.alloc_from_pool = true; 1515 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1516 1517 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1518 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1519 cfg = ICE_AQ_VSI_FD_PROG_ENABLE; 1520 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1521 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1522 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1523 ret = ice_vsi_config_tc_queue_mapping(vsi, 1524 &vsi_ctx.info, 1525 ICE_DEFAULT_TCMAP); 1526 if (ret) { 1527 PMD_INIT_LOG(ERR, 1528 "tc queue mapping with vsi failed, " 1529 "err = %d", 1530 ret); 1531 goto fail_mem; 1532 } 1533 break; 1534 default: 1535 /* for other types of VSI */ 1536 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1537 goto fail_mem; 1538 } 1539 1540 /* VF has MSIX interrupt in VF range, don't allocate here */ 1541 if (type == ICE_VSI_PF) { 1542 ret = ice_res_pool_alloc(&pf->msix_pool, 1543 RTE_MIN(vsi->nb_qps, 1544 RTE_MAX_RXTX_INTR_VEC_ID)); 1545 if (ret < 0) { 1546 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1547 vsi->vsi_id, ret); 1548 } 1549 vsi->msix_intr = ret; 1550 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1551 } else if (type == ICE_VSI_CTRL) { 1552 ret = ice_res_pool_alloc(&pf->msix_pool, 1); 1553 if (ret < 0) { 1554 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", 1555 vsi->vsi_id, ret); 1556 } 1557 vsi->msix_intr = ret; 1558 vsi->nb_msix = 1; 1559 } else { 1560 vsi->msix_intr = 0; 1561 vsi->nb_msix = 0; 1562 } 1563 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1564 if (ret != ICE_SUCCESS) { 1565 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1566 goto fail_mem; 1567 } 1568 /* store vsi information is SW structure */ 1569 vsi->vsi_id = vsi_ctx.vsi_num; 1570 vsi->info = vsi_ctx.info; 1571 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1572 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1573 1574 if (type == ICE_VSI_PF) { 1575 /* MAC configuration */ 1576 rte_ether_addr_copy((struct rte_ether_addr *) 1577 hw->port_info->mac.perm_addr, 1578 &pf->dev_addr); 1579 1580 rte_ether_addr_copy(&pf->dev_addr, &mac_addr); 1581 ret = ice_add_mac_filter(vsi, &mac_addr); 1582 if (ret != ICE_SUCCESS) 1583 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1584 1585 rte_ether_addr_copy(&broadcast, &mac_addr); 1586 ret = ice_add_mac_filter(vsi, &mac_addr); 1587 if (ret != ICE_SUCCESS) 1588 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1589 } 1590 1591 /* At the beginning, only TC0. */ 1592 /* What we need here is the maximam number of the TX queues. 1593 * Currently vsi->nb_qps means it. 1594 * Correct it if any change. 1595 */ 1596 max_txqs[0] = vsi->nb_qps; 1597 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1598 tc_bitmap, max_txqs); 1599 if (ret != ICE_SUCCESS) 1600 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1601 1602 return vsi; 1603 fail_mem: 1604 rte_free(vsi); 1605 pf->next_vsi_idx--; 1606 return NULL; 1607 } 1608 1609 static int 1610 ice_send_driver_ver(struct ice_hw *hw) 1611 { 1612 struct ice_driver_ver dv; 1613 1614 /* we don't have driver version use 0 for dummy */ 1615 dv.major_ver = 0; 1616 dv.minor_ver = 0; 1617 dv.build_ver = 0; 1618 dv.subbuild_ver = 0; 1619 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1620 1621 return ice_aq_send_driver_ver(hw, &dv, NULL); 1622 } 1623 1624 static int 1625 ice_pf_setup(struct ice_pf *pf) 1626 { 1627 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1628 struct ice_vsi *vsi; 1629 uint16_t unused; 1630 1631 /* Clear all stats counters */ 1632 pf->offset_loaded = false; 1633 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1634 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1635 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1636 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1637 1638 /* force guaranteed filter pool for PF */ 1639 ice_alloc_fd_guar_item(hw, &unused, 1640 hw->func_caps.fd_fltr_guar); 1641 /* force shared filter pool for PF */ 1642 ice_alloc_fd_shrd_item(hw, &unused, 1643 hw->func_caps.fd_fltr_best_effort); 1644 1645 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1646 if (!vsi) { 1647 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1648 return -EINVAL; 1649 } 1650 1651 pf->main_vsi = vsi; 1652 1653 return 0; 1654 } 1655 1656 static enum ice_pkg_type 1657 ice_load_pkg_type(struct ice_hw *hw) 1658 { 1659 enum ice_pkg_type package_type; 1660 1661 /* store the activated package type (OS default or Comms) */ 1662 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME, 1663 ICE_PKG_NAME_SIZE)) 1664 package_type = ICE_PKG_TYPE_OS_DEFAULT; 1665 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, 1666 ICE_PKG_NAME_SIZE)) 1667 package_type = ICE_PKG_TYPE_COMMS; 1668 else 1669 package_type = ICE_PKG_TYPE_UNKNOWN; 1670 1671 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)", 1672 hw->active_pkg_ver.major, hw->active_pkg_ver.minor, 1673 hw->active_pkg_ver.update, hw->active_pkg_ver.draft, 1674 hw->active_pkg_name, 1675 ice_is_dvm_ena(hw) ? "double" : "single"); 1676 1677 return package_type; 1678 } 1679 1680 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn) 1681 { 1682 struct ice_hw *hw = &adapter->hw; 1683 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE]; 1684 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; 1685 void *buf; 1686 size_t bufsz; 1687 int err; 1688 1689 if (!use_dsn) 1690 goto no_dsn; 1691 1692 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); 1693 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, 1694 "ice-%016" PRIx64 ".pkg", dsn); 1695 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, 1696 ICE_MAX_PKG_FILENAME_SIZE); 1697 strcat(pkg_file, opt_ddp_filename); 1698 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) 1699 goto load_fw; 1700 1701 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, 1702 ICE_MAX_PKG_FILENAME_SIZE); 1703 strcat(pkg_file, opt_ddp_filename); 1704 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) 1705 goto load_fw; 1706 1707 no_dsn: 1708 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); 1709 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) 1710 goto load_fw; 1711 1712 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); 1713 if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) { 1714 PMD_INIT_LOG(ERR, "failed to search file path\n"); 1715 return -1; 1716 } 1717 1718 load_fw: 1719 PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file); 1720 1721 err = ice_copy_and_init_pkg(hw, buf, bufsz); 1722 if (err) { 1723 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1724 goto out; 1725 } 1726 1727 /* store the loaded pkg type info */ 1728 adapter->active_pkg_type = ice_load_pkg_type(hw); 1729 1730 out: 1731 free(buf); 1732 return err; 1733 } 1734 1735 static void 1736 ice_base_queue_get(struct ice_pf *pf) 1737 { 1738 uint32_t reg; 1739 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1740 1741 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); 1742 if (reg & PFLAN_RX_QALLOC_VALID_M) { 1743 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; 1744 } else { 1745 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" 1746 " index"); 1747 } 1748 } 1749 1750 static int 1751 parse_bool(const char *key, const char *value, void *args) 1752 { 1753 int *i = (int *)args; 1754 char *end; 1755 int num; 1756 1757 num = strtoul(value, &end, 10); 1758 1759 if (num != 0 && num != 1) { 1760 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 1761 "value must be 0 or 1", 1762 value, key); 1763 return -1; 1764 } 1765 1766 *i = num; 1767 return 0; 1768 } 1769 1770 static int 1771 parse_u64(const char *key, const char *value, void *args) 1772 { 1773 u64 *num = (u64 *)args; 1774 u64 tmp; 1775 1776 errno = 0; 1777 tmp = strtoull(value, NULL, 16); 1778 if (errno) { 1779 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64", 1780 key, value); 1781 return -1; 1782 } 1783 1784 *num = tmp; 1785 1786 return 0; 1787 } 1788 1789 static int ice_parse_devargs(struct rte_eth_dev *dev) 1790 { 1791 struct ice_adapter *ad = 1792 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1793 struct rte_devargs *devargs = dev->device->devargs; 1794 struct rte_kvargs *kvlist; 1795 int ret; 1796 1797 if (devargs == NULL) 1798 return 0; 1799 1800 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args); 1801 if (kvlist == NULL) { 1802 PMD_INIT_LOG(ERR, "Invalid kvargs key\n"); 1803 return -EINVAL; 1804 } 1805 1806 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE; 1807 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE, 1808 sizeof(ad->devargs.proto_xtr)); 1809 1810 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG, 1811 &handle_proto_xtr_arg, &ad->devargs); 1812 if (ret) 1813 goto bail; 1814 1815 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, 1816 &parse_bool, &ad->devargs.safe_mode_support); 1817 if (ret) 1818 goto bail; 1819 1820 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, 1821 &parse_bool, &ad->devargs.pipe_mode_support); 1822 if (ret) 1823 goto bail; 1824 1825 ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG, 1826 &parse_u64, &ad->hw.debug_mask); 1827 if (ret) 1828 goto bail; 1829 1830 bail: 1831 rte_kvargs_free(kvlist); 1832 return ret; 1833 } 1834 1835 /* Forward LLDP packets to default VSI by set switch rules */ 1836 static int 1837 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on) 1838 { 1839 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1840 struct ice_fltr_list_entry *s_list_itr = NULL; 1841 struct LIST_HEAD_TYPE list_head; 1842 int ret = 0; 1843 1844 INIT_LIST_HEAD(&list_head); 1845 1846 s_list_itr = (struct ice_fltr_list_entry *) 1847 ice_malloc(hw, sizeof(*s_list_itr)); 1848 if (!s_list_itr) 1849 return -ENOMEM; 1850 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE; 1851 s_list_itr->fltr_info.vsi_handle = vsi->idx; 1852 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype = 1853 RTE_ETHER_TYPE_LLDP; 1854 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1855 s_list_itr->fltr_info.flag = ICE_FLTR_RX; 1856 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT; 1857 LIST_ADD(&s_list_itr->list_entry, &list_head); 1858 if (on) 1859 ret = ice_add_eth_mac(hw, &list_head); 1860 else 1861 ret = ice_remove_eth_mac(hw, &list_head); 1862 1863 rte_free(s_list_itr); 1864 return ret; 1865 } 1866 1867 static enum ice_status 1868 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, 1869 uint16_t num, uint16_t desc_id, 1870 uint16_t *prof_buf, uint16_t *num_prof) 1871 { 1872 struct ice_aqc_res_elem *resp_buf; 1873 int ret; 1874 uint16_t buf_len; 1875 bool res_shared = 1; 1876 struct ice_aq_desc aq_desc; 1877 struct ice_sq_cd *cd = NULL; 1878 struct ice_aqc_get_allocd_res_desc *cmd = 1879 &aq_desc.params.get_res_desc; 1880 1881 buf_len = sizeof(*resp_buf) * num; 1882 resp_buf = ice_malloc(hw, buf_len); 1883 if (!resp_buf) 1884 return -ENOMEM; 1885 1886 ice_fill_dflt_direct_cmd_desc(&aq_desc, 1887 ice_aqc_opc_get_allocd_res_desc); 1888 1889 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) & 1890 ICE_AQC_RES_TYPE_M) | (res_shared ? 1891 ICE_AQC_RES_TYPE_FLAG_SHARED : 0)); 1892 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id); 1893 1894 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd); 1895 if (!ret) 1896 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc); 1897 else 1898 goto exit; 1899 1900 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) * 1901 (*num_prof), ICE_NONDMA_TO_NONDMA); 1902 1903 exit: 1904 rte_free(resp_buf); 1905 return ret; 1906 } 1907 static int 1908 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type) 1909 { 1910 int ret; 1911 uint16_t prof_id; 1912 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM]; 1913 uint16_t first_desc = 1; 1914 uint16_t num_prof = 0; 1915 1916 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM, 1917 first_desc, prof_buf, &num_prof); 1918 if (ret) { 1919 PMD_INIT_LOG(ERR, "Failed to get fxp resource"); 1920 return ret; 1921 } 1922 1923 for (prof_id = 0; prof_id < num_prof; prof_id++) { 1924 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]); 1925 if (ret) { 1926 PMD_INIT_LOG(ERR, "Failed to free fxp resource"); 1927 return ret; 1928 } 1929 } 1930 return 0; 1931 } 1932 1933 static int 1934 ice_reset_fxp_resource(struct ice_hw *hw) 1935 { 1936 int ret; 1937 1938 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID); 1939 if (ret) { 1940 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource"); 1941 return ret; 1942 } 1943 1944 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID); 1945 if (ret) { 1946 PMD_INIT_LOG(ERR, "Failed to clearup rss resource"); 1947 return ret; 1948 } 1949 1950 return 0; 1951 } 1952 1953 static void 1954 ice_rss_ctx_init(struct ice_pf *pf) 1955 { 1956 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx)); 1957 } 1958 1959 static uint64_t 1960 ice_get_supported_rxdid(struct ice_hw *hw) 1961 { 1962 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */ 1963 uint32_t regval; 1964 int i; 1965 1966 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1); 1967 1968 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) { 1969 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0)); 1970 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) 1971 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) 1972 supported_rxdid |= BIT(i); 1973 } 1974 return supported_rxdid; 1975 } 1976 1977 static int 1978 ice_dev_init(struct rte_eth_dev *dev) 1979 { 1980 struct rte_pci_device *pci_dev; 1981 struct rte_intr_handle *intr_handle; 1982 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1983 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1984 struct ice_adapter *ad = 1985 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1986 struct ice_vsi *vsi; 1987 int ret; 1988 #ifndef RTE_EXEC_ENV_WINDOWS 1989 off_t pos; 1990 uint32_t dsn_low, dsn_high; 1991 uint64_t dsn; 1992 bool use_dsn; 1993 #endif 1994 1995 dev->dev_ops = &ice_eth_dev_ops; 1996 dev->rx_queue_count = ice_rx_queue_count; 1997 dev->rx_descriptor_status = ice_rx_descriptor_status; 1998 dev->tx_descriptor_status = ice_tx_descriptor_status; 1999 dev->rx_pkt_burst = ice_recv_pkts; 2000 dev->tx_pkt_burst = ice_xmit_pkts; 2001 dev->tx_pkt_prepare = ice_prep_pkts; 2002 2003 /* for secondary processes, we don't initialise any further as primary 2004 * has already done this work. 2005 */ 2006 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2007 ice_set_rx_function(dev); 2008 ice_set_tx_function(dev); 2009 return 0; 2010 } 2011 2012 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2013 2014 ice_set_default_ptype_table(dev); 2015 pci_dev = RTE_DEV_TO_PCI(dev->device); 2016 intr_handle = &pci_dev->intr_handle; 2017 2018 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2019 pf->dev_data = dev->data; 2020 hw->back = pf->adapter; 2021 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 2022 hw->vendor_id = pci_dev->id.vendor_id; 2023 hw->device_id = pci_dev->id.device_id; 2024 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2025 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 2026 hw->bus.device = pci_dev->addr.devid; 2027 hw->bus.func = pci_dev->addr.function; 2028 2029 ret = ice_parse_devargs(dev); 2030 if (ret) { 2031 PMD_INIT_LOG(ERR, "Failed to parse devargs"); 2032 return -EINVAL; 2033 } 2034 2035 ice_init_controlq_parameter(hw); 2036 2037 ret = ice_init_hw(hw); 2038 if (ret) { 2039 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 2040 return -EINVAL; 2041 } 2042 2043 #ifndef RTE_EXEC_ENV_WINDOWS 2044 use_dsn = false; 2045 dsn = 0; 2046 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN); 2047 if (pos) { 2048 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 || 2049 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) { 2050 PMD_INIT_LOG(ERR, "Failed to read pci config space\n"); 2051 } else { 2052 use_dsn = true; 2053 dsn = (uint64_t)dsn_high << 32 | dsn_low; 2054 } 2055 } else { 2056 PMD_INIT_LOG(ERR, "Failed to read device serial number\n"); 2057 } 2058 2059 ret = ice_load_pkg(pf->adapter, use_dsn, dsn); 2060 if (ret == 0) { 2061 ret = ice_init_hw_tbls(hw); 2062 if (ret) { 2063 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret); 2064 rte_free(hw->pkg_copy); 2065 } 2066 } 2067 2068 if (ret) { 2069 if (ad->devargs.safe_mode_support == 0) { 2070 PMD_INIT_LOG(ERR, "Failed to load the DDP package," 2071 "Use safe-mode-support=1 to enter Safe Mode"); 2072 return ret; 2073 } 2074 2075 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 2076 "Entering Safe Mode"); 2077 ad->is_safe_mode = 1; 2078 } 2079 #endif 2080 2081 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 2082 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 2083 hw->api_maj_ver, hw->api_min_ver); 2084 2085 ice_pf_sw_init(dev); 2086 ret = ice_init_mac_address(dev); 2087 if (ret) { 2088 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 2089 goto err_init_mac; 2090 } 2091 2092 ret = ice_res_pool_init(&pf->msix_pool, 1, 2093 hw->func_caps.common_cap.num_msix_vectors - 1); 2094 if (ret) { 2095 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 2096 goto err_msix_pool_init; 2097 } 2098 2099 ret = ice_pf_setup(pf); 2100 if (ret) { 2101 PMD_INIT_LOG(ERR, "Failed to setup PF"); 2102 goto err_pf_setup; 2103 } 2104 2105 ret = ice_send_driver_ver(hw); 2106 if (ret) { 2107 PMD_INIT_LOG(ERR, "Failed to send driver version"); 2108 goto err_pf_setup; 2109 } 2110 2111 vsi = pf->main_vsi; 2112 2113 ret = ice_aq_stop_lldp(hw, true, false, NULL); 2114 if (ret != ICE_SUCCESS) 2115 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 2116 ret = ice_init_dcb(hw, true); 2117 if (ret != ICE_SUCCESS) 2118 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n"); 2119 /* Forward LLDP packets to default VSI */ 2120 ret = ice_vsi_config_sw_lldp(vsi, true); 2121 if (ret != ICE_SUCCESS) 2122 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n"); 2123 /* register callback func to eal lib */ 2124 rte_intr_callback_register(intr_handle, 2125 ice_interrupt_handler, dev); 2126 2127 ice_pf_enable_irq0(hw); 2128 2129 /* enable uio intr after callback register */ 2130 rte_intr_enable(intr_handle); 2131 2132 /* get base queue pairs index in the device */ 2133 ice_base_queue_get(pf); 2134 2135 /* Initialize RSS context for gtpu_eh */ 2136 ice_rss_ctx_init(pf); 2137 2138 if (!ad->is_safe_mode) { 2139 ret = ice_flow_init(ad); 2140 if (ret) { 2141 PMD_INIT_LOG(ERR, "Failed to initialize flow"); 2142 return ret; 2143 } 2144 } 2145 2146 ret = ice_reset_fxp_resource(hw); 2147 if (ret) { 2148 PMD_INIT_LOG(ERR, "Failed to reset fxp resource"); 2149 return ret; 2150 } 2151 2152 pf->supported_rxdid = ice_get_supported_rxdid(hw); 2153 2154 return 0; 2155 2156 err_pf_setup: 2157 ice_res_pool_destroy(&pf->msix_pool); 2158 err_msix_pool_init: 2159 rte_free(dev->data->mac_addrs); 2160 dev->data->mac_addrs = NULL; 2161 err_init_mac: 2162 ice_sched_cleanup_all(hw); 2163 rte_free(hw->port_info); 2164 ice_shutdown_all_ctrlq(hw); 2165 rte_free(pf->proto_xtr); 2166 2167 return ret; 2168 } 2169 2170 int 2171 ice_release_vsi(struct ice_vsi *vsi) 2172 { 2173 struct ice_hw *hw; 2174 struct ice_vsi_ctx vsi_ctx; 2175 enum ice_status ret; 2176 int error = 0; 2177 2178 if (!vsi) 2179 return error; 2180 2181 hw = ICE_VSI_TO_HW(vsi); 2182 2183 ice_remove_all_mac_vlan_filters(vsi); 2184 2185 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 2186 2187 vsi_ctx.vsi_num = vsi->vsi_id; 2188 vsi_ctx.info = vsi->info; 2189 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 2190 if (ret != ICE_SUCCESS) { 2191 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 2192 error = -1; 2193 } 2194 2195 rte_free(vsi->rss_lut); 2196 rte_free(vsi->rss_key); 2197 rte_free(vsi); 2198 return error; 2199 } 2200 2201 void 2202 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 2203 { 2204 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; 2205 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2207 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2208 uint16_t msix_intr, i; 2209 2210 /* disable interrupt and also clear all the exist config */ 2211 for (i = 0; i < vsi->nb_qps; i++) { 2212 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2213 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2214 rte_wmb(); 2215 } 2216 2217 if (rte_intr_allow_others(intr_handle)) 2218 /* vfio-pci */ 2219 for (i = 0; i < vsi->nb_msix; i++) { 2220 msix_intr = vsi->msix_intr + i; 2221 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2222 GLINT_DYN_CTL_WB_ON_ITR_M); 2223 } 2224 else 2225 /* igb_uio */ 2226 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 2227 } 2228 2229 static int 2230 ice_dev_stop(struct rte_eth_dev *dev) 2231 { 2232 struct rte_eth_dev_data *data = dev->data; 2233 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2234 struct ice_vsi *main_vsi = pf->main_vsi; 2235 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2236 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2237 uint16_t i; 2238 2239 /* avoid stopping again */ 2240 if (pf->adapter_stopped) 2241 return 0; 2242 2243 /* stop and clear all Rx queues */ 2244 for (i = 0; i < data->nb_rx_queues; i++) 2245 ice_rx_queue_stop(dev, i); 2246 2247 /* stop and clear all Tx queues */ 2248 for (i = 0; i < data->nb_tx_queues; i++) 2249 ice_tx_queue_stop(dev, i); 2250 2251 /* disable all queue interrupts */ 2252 ice_vsi_disable_queues_intr(main_vsi); 2253 2254 if (pf->init_link_up) 2255 ice_dev_set_link_up(dev); 2256 else 2257 ice_dev_set_link_down(dev); 2258 2259 /* Clean datapath event and queue/vec mapping */ 2260 rte_intr_efd_disable(intr_handle); 2261 if (intr_handle->intr_vec) { 2262 rte_free(intr_handle->intr_vec); 2263 intr_handle->intr_vec = NULL; 2264 } 2265 2266 pf->adapter_stopped = true; 2267 dev->data->dev_started = 0; 2268 2269 return 0; 2270 } 2271 2272 static int 2273 ice_dev_close(struct rte_eth_dev *dev) 2274 { 2275 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2276 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2277 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2278 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2279 struct ice_adapter *ad = 2280 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2281 int ret; 2282 2283 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2284 return 0; 2285 2286 /* Since stop will make link down, then the link event will be 2287 * triggered, disable the irq firstly to avoid the port_infoe etc 2288 * resources deallocation causing the interrupt service thread 2289 * crash. 2290 */ 2291 ice_pf_disable_irq0(hw); 2292 2293 ret = ice_dev_stop(dev); 2294 2295 if (!ad->is_safe_mode) 2296 ice_flow_uninit(ad); 2297 2298 /* release all queue resource */ 2299 ice_free_queues(dev); 2300 2301 ice_res_pool_destroy(&pf->msix_pool); 2302 ice_release_vsi(pf->main_vsi); 2303 ice_sched_cleanup_all(hw); 2304 ice_free_hw_tbls(hw); 2305 rte_free(hw->port_info); 2306 hw->port_info = NULL; 2307 ice_shutdown_all_ctrlq(hw); 2308 rte_free(pf->proto_xtr); 2309 pf->proto_xtr = NULL; 2310 2311 /* disable uio intr before callback unregister */ 2312 rte_intr_disable(intr_handle); 2313 2314 /* unregister callback func from eal lib */ 2315 rte_intr_callback_unregister(intr_handle, 2316 ice_interrupt_handler, dev); 2317 2318 return ret; 2319 } 2320 2321 static int 2322 ice_dev_uninit(struct rte_eth_dev *dev) 2323 { 2324 ice_dev_close(dev); 2325 2326 return 0; 2327 } 2328 2329 static bool 2330 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg) 2331 { 2332 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false; 2333 } 2334 2335 static void 2336 hash_cfg_reset(struct ice_rss_hash_cfg *cfg) 2337 { 2338 cfg->hash_flds = 0; 2339 cfg->addl_hdrs = 0; 2340 cfg->symm = 0; 2341 cfg->hdr_type = ICE_RSS_OUTER_HEADERS; 2342 } 2343 2344 static int 2345 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2346 { 2347 enum ice_status status = ICE_SUCCESS; 2348 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2349 struct ice_vsi *vsi = pf->main_vsi; 2350 2351 if (!is_hash_cfg_valid(cfg)) 2352 return -ENOENT; 2353 2354 status = ice_rem_rss_cfg(hw, vsi->idx, cfg); 2355 if (status && status != ICE_ERR_DOES_NOT_EXIST) { 2356 PMD_DRV_LOG(ERR, 2357 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n", 2358 vsi->idx, status); 2359 return -EBUSY; 2360 } 2361 2362 return 0; 2363 } 2364 2365 static int 2366 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2367 { 2368 enum ice_status status = ICE_SUCCESS; 2369 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2370 struct ice_vsi *vsi = pf->main_vsi; 2371 2372 if (!is_hash_cfg_valid(cfg)) 2373 return -ENOENT; 2374 2375 status = ice_add_rss_cfg(hw, vsi->idx, cfg); 2376 if (status) { 2377 PMD_DRV_LOG(ERR, 2378 "ice_add_rss_cfg failed for VSI:%d, error:%d\n", 2379 vsi->idx, status); 2380 return -EBUSY; 2381 } 2382 2383 return 0; 2384 } 2385 2386 static int 2387 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2388 { 2389 int ret; 2390 2391 ret = ice_hash_moveout(pf, cfg); 2392 if (ret && (ret != -ENOENT)) 2393 return ret; 2394 2395 hash_cfg_reset(cfg); 2396 2397 return 0; 2398 } 2399 2400 static int 2401 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2402 u8 ctx_idx) 2403 { 2404 int ret; 2405 2406 switch (ctx_idx) { 2407 case ICE_HASH_GTPU_CTX_EH_IP: 2408 ret = ice_hash_remove(pf, 2409 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2410 if (ret && (ret != -ENOENT)) 2411 return ret; 2412 2413 ret = ice_hash_remove(pf, 2414 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2415 if (ret && (ret != -ENOENT)) 2416 return ret; 2417 2418 ret = ice_hash_remove(pf, 2419 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2420 if (ret && (ret != -ENOENT)) 2421 return ret; 2422 2423 ret = ice_hash_remove(pf, 2424 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2425 if (ret && (ret != -ENOENT)) 2426 return ret; 2427 2428 ret = ice_hash_remove(pf, 2429 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2430 if (ret && (ret != -ENOENT)) 2431 return ret; 2432 2433 ret = ice_hash_remove(pf, 2434 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2435 if (ret && (ret != -ENOENT)) 2436 return ret; 2437 2438 ret = ice_hash_remove(pf, 2439 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2440 if (ret && (ret != -ENOENT)) 2441 return ret; 2442 2443 ret = ice_hash_remove(pf, 2444 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2445 if (ret && (ret != -ENOENT)) 2446 return ret; 2447 2448 break; 2449 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 2450 ret = ice_hash_remove(pf, 2451 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2452 if (ret && (ret != -ENOENT)) 2453 return ret; 2454 2455 ret = ice_hash_remove(pf, 2456 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2457 if (ret && (ret != -ENOENT)) 2458 return ret; 2459 2460 ret = ice_hash_moveout(pf, 2461 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2462 if (ret && (ret != -ENOENT)) 2463 return ret; 2464 2465 ret = ice_hash_moveout(pf, 2466 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2467 if (ret && (ret != -ENOENT)) 2468 return ret; 2469 2470 ret = ice_hash_moveout(pf, 2471 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2472 if (ret && (ret != -ENOENT)) 2473 return ret; 2474 2475 ret = ice_hash_moveout(pf, 2476 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2477 if (ret && (ret != -ENOENT)) 2478 return ret; 2479 2480 break; 2481 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 2482 ret = ice_hash_remove(pf, 2483 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2484 if (ret && (ret != -ENOENT)) 2485 return ret; 2486 2487 ret = ice_hash_remove(pf, 2488 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2489 if (ret && (ret != -ENOENT)) 2490 return ret; 2491 2492 ret = ice_hash_moveout(pf, 2493 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2494 if (ret && (ret != -ENOENT)) 2495 return ret; 2496 2497 ret = ice_hash_moveout(pf, 2498 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2499 if (ret && (ret != -ENOENT)) 2500 return ret; 2501 2502 ret = ice_hash_moveout(pf, 2503 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2504 if (ret && (ret != -ENOENT)) 2505 return ret; 2506 2507 ret = ice_hash_moveout(pf, 2508 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2509 if (ret && (ret != -ENOENT)) 2510 return ret; 2511 2512 break; 2513 case ICE_HASH_GTPU_CTX_UP_IP: 2514 ret = ice_hash_remove(pf, 2515 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2516 if (ret && (ret != -ENOENT)) 2517 return ret; 2518 2519 ret = ice_hash_remove(pf, 2520 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2521 if (ret && (ret != -ENOENT)) 2522 return ret; 2523 2524 ret = ice_hash_moveout(pf, 2525 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2526 if (ret && (ret != -ENOENT)) 2527 return ret; 2528 2529 ret = ice_hash_moveout(pf, 2530 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2531 if (ret && (ret != -ENOENT)) 2532 return ret; 2533 2534 ret = ice_hash_moveout(pf, 2535 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2536 if (ret && (ret != -ENOENT)) 2537 return ret; 2538 2539 break; 2540 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 2541 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 2542 ret = ice_hash_moveout(pf, 2543 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2544 if (ret && (ret != -ENOENT)) 2545 return ret; 2546 2547 ret = ice_hash_moveout(pf, 2548 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2549 if (ret && (ret != -ENOENT)) 2550 return ret; 2551 2552 ret = ice_hash_moveout(pf, 2553 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2554 if (ret && (ret != -ENOENT)) 2555 return ret; 2556 2557 break; 2558 case ICE_HASH_GTPU_CTX_DW_IP: 2559 ret = ice_hash_remove(pf, 2560 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2561 if (ret && (ret != -ENOENT)) 2562 return ret; 2563 2564 ret = ice_hash_remove(pf, 2565 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2566 if (ret && (ret != -ENOENT)) 2567 return ret; 2568 2569 ret = ice_hash_moveout(pf, 2570 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2571 if (ret && (ret != -ENOENT)) 2572 return ret; 2573 2574 ret = ice_hash_moveout(pf, 2575 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2576 if (ret && (ret != -ENOENT)) 2577 return ret; 2578 2579 ret = ice_hash_moveout(pf, 2580 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2581 if (ret && (ret != -ENOENT)) 2582 return ret; 2583 2584 break; 2585 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 2586 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 2587 ret = ice_hash_moveout(pf, 2588 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2589 if (ret && (ret != -ENOENT)) 2590 return ret; 2591 2592 ret = ice_hash_moveout(pf, 2593 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2594 if (ret && (ret != -ENOENT)) 2595 return ret; 2596 2597 ret = ice_hash_moveout(pf, 2598 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2599 if (ret && (ret != -ENOENT)) 2600 return ret; 2601 2602 break; 2603 default: 2604 break; 2605 } 2606 2607 return 0; 2608 } 2609 2610 static u8 calc_gtpu_ctx_idx(uint32_t hdr) 2611 { 2612 u8 eh_idx, ip_idx; 2613 2614 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) 2615 eh_idx = 0; 2616 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP) 2617 eh_idx = 1; 2618 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN) 2619 eh_idx = 2; 2620 else 2621 return ICE_HASH_GTPU_CTX_MAX; 2622 2623 ip_idx = 0; 2624 if (hdr & ICE_FLOW_SEG_HDR_UDP) 2625 ip_idx = 1; 2626 else if (hdr & ICE_FLOW_SEG_HDR_TCP) 2627 ip_idx = 2; 2628 2629 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)) 2630 return eh_idx * 3 + ip_idx; 2631 else 2632 return ICE_HASH_GTPU_CTX_MAX; 2633 } 2634 2635 static int 2636 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr) 2637 { 2638 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2639 2640 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2641 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4, 2642 gtpu_ctx_idx); 2643 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2644 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6, 2645 gtpu_ctx_idx); 2646 2647 return 0; 2648 } 2649 2650 static int 2651 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2652 u8 ctx_idx, struct ice_rss_hash_cfg *cfg) 2653 { 2654 int ret; 2655 2656 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX) 2657 ctx->ctx[ctx_idx] = *cfg; 2658 2659 switch (ctx_idx) { 2660 case ICE_HASH_GTPU_CTX_EH_IP: 2661 break; 2662 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 2663 ret = ice_hash_moveback(pf, 2664 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2665 if (ret && (ret != -ENOENT)) 2666 return ret; 2667 2668 ret = ice_hash_moveback(pf, 2669 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2670 if (ret && (ret != -ENOENT)) 2671 return ret; 2672 2673 ret = ice_hash_moveback(pf, 2674 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2675 if (ret && (ret != -ENOENT)) 2676 return ret; 2677 2678 ret = ice_hash_moveback(pf, 2679 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2680 if (ret && (ret != -ENOENT)) 2681 return ret; 2682 2683 break; 2684 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 2685 ret = ice_hash_moveback(pf, 2686 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2687 if (ret && (ret != -ENOENT)) 2688 return ret; 2689 2690 ret = ice_hash_moveback(pf, 2691 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2692 if (ret && (ret != -ENOENT)) 2693 return ret; 2694 2695 ret = ice_hash_moveback(pf, 2696 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2697 if (ret && (ret != -ENOENT)) 2698 return ret; 2699 2700 ret = ice_hash_moveback(pf, 2701 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2702 if (ret && (ret != -ENOENT)) 2703 return ret; 2704 2705 break; 2706 case ICE_HASH_GTPU_CTX_UP_IP: 2707 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 2708 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 2709 case ICE_HASH_GTPU_CTX_DW_IP: 2710 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 2711 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 2712 ret = ice_hash_moveback(pf, 2713 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2714 if (ret && (ret != -ENOENT)) 2715 return ret; 2716 2717 ret = ice_hash_moveback(pf, 2718 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2719 if (ret && (ret != -ENOENT)) 2720 return ret; 2721 2722 ret = ice_hash_moveback(pf, 2723 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2724 if (ret && (ret != -ENOENT)) 2725 return ret; 2726 2727 break; 2728 default: 2729 break; 2730 } 2731 2732 return 0; 2733 } 2734 2735 static int 2736 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2737 { 2738 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs); 2739 2740 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4) 2741 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4, 2742 gtpu_ctx_idx, cfg); 2743 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6) 2744 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6, 2745 gtpu_ctx_idx, cfg); 2746 2747 return 0; 2748 } 2749 2750 static void 2751 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr) 2752 { 2753 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2754 2755 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX) 2756 return; 2757 2758 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2759 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]); 2760 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2761 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]); 2762 } 2763 2764 int 2765 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 2766 struct ice_rss_hash_cfg *cfg) 2767 { 2768 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2769 int ret; 2770 2771 ret = ice_rem_rss_cfg(hw, vsi_id, cfg); 2772 if (ret && ret != ICE_ERR_DOES_NOT_EXIST) 2773 PMD_DRV_LOG(ERR, "remove rss cfg failed\n"); 2774 2775 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs); 2776 2777 return 0; 2778 } 2779 2780 int 2781 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 2782 struct ice_rss_hash_cfg *cfg) 2783 { 2784 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2785 int ret; 2786 2787 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs); 2788 if (ret) 2789 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n"); 2790 2791 ret = ice_add_rss_cfg(hw, vsi_id, cfg); 2792 if (ret) 2793 PMD_DRV_LOG(ERR, "add rss cfg failed\n"); 2794 2795 ret = ice_add_rss_cfg_post(pf, cfg); 2796 if (ret) 2797 PMD_DRV_LOG(ERR, "add rss cfg post failed\n"); 2798 2799 return 0; 2800 } 2801 2802 static void 2803 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf) 2804 { 2805 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2806 struct ice_vsi *vsi = pf->main_vsi; 2807 struct ice_rss_hash_cfg cfg; 2808 int ret; 2809 2810 #define ICE_RSS_HF_ALL ( \ 2811 ETH_RSS_IPV4 | \ 2812 ETH_RSS_IPV6 | \ 2813 ETH_RSS_NONFRAG_IPV4_UDP | \ 2814 ETH_RSS_NONFRAG_IPV6_UDP | \ 2815 ETH_RSS_NONFRAG_IPV4_TCP | \ 2816 ETH_RSS_NONFRAG_IPV6_TCP | \ 2817 ETH_RSS_NONFRAG_IPV4_SCTP | \ 2818 ETH_RSS_NONFRAG_IPV6_SCTP | \ 2819 ETH_RSS_FRAG_IPV4 | \ 2820 ETH_RSS_FRAG_IPV6) 2821 2822 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx); 2823 if (ret) 2824 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d", 2825 __func__, ret); 2826 2827 cfg.symm = 0; 2828 cfg.hdr_type = ICE_RSS_OUTER_HEADERS; 2829 /* Configure RSS for IPv4 with src/dst addr as input set */ 2830 if (rss_hf & ETH_RSS_IPV4) { 2831 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 2832 cfg.hash_flds = ICE_FLOW_HASH_IPV4; 2833 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2834 if (ret) 2835 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", 2836 __func__, ret); 2837 } 2838 2839 /* Configure RSS for IPv6 with src/dst addr as input set */ 2840 if (rss_hf & ETH_RSS_IPV6) { 2841 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 2842 cfg.hash_flds = ICE_FLOW_HASH_IPV6; 2843 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2844 if (ret) 2845 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", 2846 __func__, ret); 2847 } 2848 2849 /* Configure RSS for udp4 with src/dst addr and port as input set */ 2850 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 2851 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 | 2852 ICE_FLOW_SEG_HDR_IPV_OTHER; 2853 cfg.hash_flds = ICE_HASH_UDP_IPV4; 2854 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2855 if (ret) 2856 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", 2857 __func__, ret); 2858 } 2859 2860 /* Configure RSS for udp6 with src/dst addr and port as input set */ 2861 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 2862 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 | 2863 ICE_FLOW_SEG_HDR_IPV_OTHER; 2864 cfg.hash_flds = ICE_HASH_UDP_IPV6; 2865 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2866 if (ret) 2867 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", 2868 __func__, ret); 2869 } 2870 2871 /* Configure RSS for tcp4 with src/dst addr and port as input set */ 2872 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 2873 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 | 2874 ICE_FLOW_SEG_HDR_IPV_OTHER; 2875 cfg.hash_flds = ICE_HASH_TCP_IPV4; 2876 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2877 if (ret) 2878 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", 2879 __func__, ret); 2880 } 2881 2882 /* Configure RSS for tcp6 with src/dst addr and port as input set */ 2883 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 2884 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 | 2885 ICE_FLOW_SEG_HDR_IPV_OTHER; 2886 cfg.hash_flds = ICE_HASH_TCP_IPV6; 2887 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2888 if (ret) 2889 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", 2890 __func__, ret); 2891 } 2892 2893 /* Configure RSS for sctp4 with src/dst addr and port as input set */ 2894 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) { 2895 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 | 2896 ICE_FLOW_SEG_HDR_IPV_OTHER; 2897 cfg.hash_flds = ICE_HASH_SCTP_IPV4; 2898 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2899 if (ret) 2900 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 2901 __func__, ret); 2902 } 2903 2904 /* Configure RSS for sctp6 with src/dst addr and port as input set */ 2905 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) { 2906 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 | 2907 ICE_FLOW_SEG_HDR_IPV_OTHER; 2908 cfg.hash_flds = ICE_HASH_SCTP_IPV6; 2909 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2910 if (ret) 2911 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 2912 __func__, ret); 2913 } 2914 2915 if (rss_hf & ETH_RSS_IPV4) { 2916 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 | 2917 ICE_FLOW_SEG_HDR_IPV_OTHER; 2918 cfg.hash_flds = ICE_FLOW_HASH_IPV4; 2919 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2920 if (ret) 2921 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d", 2922 __func__, ret); 2923 } 2924 2925 if (rss_hf & ETH_RSS_IPV6) { 2926 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 | 2927 ICE_FLOW_SEG_HDR_IPV_OTHER; 2928 cfg.hash_flds = ICE_FLOW_HASH_IPV6; 2929 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2930 if (ret) 2931 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d", 2932 __func__, ret); 2933 } 2934 2935 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 2936 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP | 2937 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 2938 cfg.hash_flds = ICE_HASH_UDP_IPV4; 2939 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2940 if (ret) 2941 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d", 2942 __func__, ret); 2943 } 2944 2945 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 2946 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP | 2947 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 2948 cfg.hash_flds = ICE_HASH_UDP_IPV6; 2949 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2950 if (ret) 2951 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d", 2952 __func__, ret); 2953 } 2954 2955 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 2956 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP | 2957 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 2958 cfg.hash_flds = ICE_HASH_TCP_IPV4; 2959 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2960 if (ret) 2961 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d", 2962 __func__, ret); 2963 } 2964 2965 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 2966 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP | 2967 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 2968 cfg.hash_flds = ICE_HASH_TCP_IPV6; 2969 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2970 if (ret) 2971 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d", 2972 __func__, ret); 2973 } 2974 2975 if (rss_hf & ETH_RSS_FRAG_IPV4) { 2976 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_FRAG; 2977 cfg.hash_flds = ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_ID); 2978 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2979 if (ret) 2980 PMD_DRV_LOG(ERR, "%s IPV4_FRAG rss flow fail %d", 2981 __func__, ret); 2982 } 2983 2984 if (rss_hf & ETH_RSS_FRAG_IPV6) { 2985 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_FRAG; 2986 cfg.hash_flds = ICE_FLOW_HASH_IPV6 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_ID); 2987 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2988 if (ret) 2989 PMD_DRV_LOG(ERR, "%s IPV6_FRAG rss flow fail %d", 2990 __func__, ret); 2991 } 2992 2993 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL; 2994 } 2995 2996 static void 2997 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size) 2998 { 2999 static struct ice_aqc_get_set_rss_keys default_key; 3000 static bool default_key_done; 3001 uint8_t *key = (uint8_t *)&default_key; 3002 size_t i; 3003 3004 if (rss_key_size > sizeof(default_key)) { 3005 PMD_DRV_LOG(WARNING, 3006 "requested size %u is larger than default %zu, " 3007 "only %zu bytes are gotten for key\n", 3008 rss_key_size, sizeof(default_key), 3009 sizeof(default_key)); 3010 } 3011 3012 if (!default_key_done) { 3013 /* Calculate the default hash key */ 3014 for (i = 0; i < sizeof(default_key); i++) 3015 key[i] = (uint8_t)rte_rand(); 3016 default_key_done = true; 3017 } 3018 rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key))); 3019 } 3020 3021 static int ice_init_rss(struct ice_pf *pf) 3022 { 3023 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3024 struct ice_vsi *vsi = pf->main_vsi; 3025 struct rte_eth_dev_data *dev_data = pf->dev_data; 3026 struct ice_aq_get_set_rss_lut_params lut_params; 3027 struct rte_eth_rss_conf *rss_conf; 3028 struct ice_aqc_get_set_rss_keys key; 3029 uint16_t i, nb_q; 3030 int ret = 0; 3031 bool is_safe_mode = pf->adapter->is_safe_mode; 3032 uint32_t reg; 3033 3034 rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf; 3035 nb_q = dev_data->nb_rx_queues; 3036 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 3037 vsi->rss_lut_size = pf->hash_lut_size; 3038 3039 if (nb_q == 0) { 3040 PMD_DRV_LOG(WARNING, 3041 "RSS is not supported as rx queues number is zero\n"); 3042 return 0; 3043 } 3044 3045 if (is_safe_mode) { 3046 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 3047 return 0; 3048 } 3049 3050 if (!vsi->rss_key) { 3051 vsi->rss_key = rte_zmalloc(NULL, 3052 vsi->rss_key_size, 0); 3053 if (vsi->rss_key == NULL) { 3054 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3055 return -ENOMEM; 3056 } 3057 } 3058 if (!vsi->rss_lut) { 3059 vsi->rss_lut = rte_zmalloc(NULL, 3060 vsi->rss_lut_size, 0); 3061 if (vsi->rss_lut == NULL) { 3062 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3063 rte_free(vsi->rss_key); 3064 vsi->rss_key = NULL; 3065 return -ENOMEM; 3066 } 3067 } 3068 /* configure RSS key */ 3069 if (!rss_conf->rss_key) 3070 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size); 3071 else 3072 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 3073 RTE_MIN(rss_conf->rss_key_len, 3074 vsi->rss_key_size)); 3075 3076 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 3077 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 3078 if (ret) 3079 goto out; 3080 3081 /* init RSS LUT table */ 3082 for (i = 0; i < vsi->rss_lut_size; i++) 3083 vsi->rss_lut[i] = i % nb_q; 3084 3085 lut_params.vsi_handle = vsi->idx; 3086 lut_params.lut_size = vsi->rss_lut_size; 3087 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 3088 lut_params.lut = vsi->rss_lut; 3089 lut_params.global_lut_id = 0; 3090 ret = ice_aq_set_rss_lut(hw, &lut_params); 3091 if (ret) 3092 goto out; 3093 3094 /* Enable registers for symmetric_toeplitz function. */ 3095 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id)); 3096 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) | 3097 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S); 3098 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg); 3099 3100 /* RSS hash configuration */ 3101 ice_rss_hash_set(pf, rss_conf->rss_hf); 3102 3103 return 0; 3104 out: 3105 rte_free(vsi->rss_key); 3106 vsi->rss_key = NULL; 3107 rte_free(vsi->rss_lut); 3108 vsi->rss_lut = NULL; 3109 return -EINVAL; 3110 } 3111 3112 static int 3113 ice_dev_configure(struct rte_eth_dev *dev) 3114 { 3115 struct ice_adapter *ad = 3116 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 3117 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3118 int ret; 3119 3120 /* Initialize to TRUE. If any of Rx queues doesn't meet the 3121 * bulk allocation or vector Rx preconditions we will reset it. 3122 */ 3123 ad->rx_bulk_alloc_allowed = true; 3124 ad->tx_simple_allowed = true; 3125 3126 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 3127 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 3128 3129 if (dev->data->nb_rx_queues) { 3130 ret = ice_init_rss(pf); 3131 if (ret) { 3132 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 3133 return ret; 3134 } 3135 } 3136 3137 return 0; 3138 } 3139 3140 static void 3141 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 3142 int base_queue, int nb_queue) 3143 { 3144 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3145 uint32_t val, val_tx; 3146 int i; 3147 3148 for (i = 0; i < nb_queue; i++) { 3149 /*do actual bind*/ 3150 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 3151 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 3152 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 3153 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 3154 3155 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 3156 base_queue + i, msix_vect); 3157 /* set ITR0 value */ 3158 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); 3159 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 3160 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 3161 } 3162 } 3163 3164 void 3165 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 3166 { 3167 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; 3168 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3169 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3170 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3171 uint16_t msix_vect = vsi->msix_intr; 3172 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 3173 uint16_t queue_idx = 0; 3174 int record = 0; 3175 int i; 3176 3177 /* clear Rx/Tx queue interrupt */ 3178 for (i = 0; i < vsi->nb_used_qps; i++) { 3179 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 3180 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 3181 } 3182 3183 /* PF bind interrupt */ 3184 if (rte_intr_dp_is_en(intr_handle)) { 3185 queue_idx = 0; 3186 record = 1; 3187 } 3188 3189 for (i = 0; i < vsi->nb_used_qps; i++) { 3190 if (nb_msix <= 1) { 3191 if (!rte_intr_allow_others(intr_handle)) 3192 msix_vect = ICE_MISC_VEC_ID; 3193 3194 /* uio mapping all queue to one msix_vect */ 3195 __vsi_queues_bind_intr(vsi, msix_vect, 3196 vsi->base_queue + i, 3197 vsi->nb_used_qps - i); 3198 3199 for (; !!record && i < vsi->nb_used_qps; i++) 3200 intr_handle->intr_vec[queue_idx + i] = 3201 msix_vect; 3202 break; 3203 } 3204 3205 /* vfio 1:1 queue/msix_vect mapping */ 3206 __vsi_queues_bind_intr(vsi, msix_vect, 3207 vsi->base_queue + i, 1); 3208 3209 if (!!record) 3210 intr_handle->intr_vec[queue_idx + i] = msix_vect; 3211 3212 msix_vect++; 3213 nb_msix--; 3214 } 3215 } 3216 3217 void 3218 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 3219 { 3220 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; 3221 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3222 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3223 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3224 uint16_t msix_intr, i; 3225 3226 if (rte_intr_allow_others(intr_handle)) 3227 for (i = 0; i < vsi->nb_used_qps; i++) { 3228 msix_intr = vsi->msix_intr + i; 3229 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 3230 GLINT_DYN_CTL_INTENA_M | 3231 GLINT_DYN_CTL_CLEARPBA_M | 3232 GLINT_DYN_CTL_ITR_INDX_M | 3233 GLINT_DYN_CTL_WB_ON_ITR_M); 3234 } 3235 else 3236 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 3237 GLINT_DYN_CTL_INTENA_M | 3238 GLINT_DYN_CTL_CLEARPBA_M | 3239 GLINT_DYN_CTL_ITR_INDX_M | 3240 GLINT_DYN_CTL_WB_ON_ITR_M); 3241 } 3242 3243 static int 3244 ice_rxq_intr_setup(struct rte_eth_dev *dev) 3245 { 3246 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3247 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3248 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3249 struct ice_vsi *vsi = pf->main_vsi; 3250 uint32_t intr_vector = 0; 3251 3252 rte_intr_disable(intr_handle); 3253 3254 /* check and configure queue intr-vector mapping */ 3255 if ((rte_intr_cap_multiple(intr_handle) || 3256 !RTE_ETH_DEV_SRIOV(dev).active) && 3257 dev->data->dev_conf.intr_conf.rxq != 0) { 3258 intr_vector = dev->data->nb_rx_queues; 3259 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 3260 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 3261 ICE_MAX_INTR_QUEUE_NUM); 3262 return -ENOTSUP; 3263 } 3264 if (rte_intr_efd_enable(intr_handle, intr_vector)) 3265 return -1; 3266 } 3267 3268 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 3269 intr_handle->intr_vec = 3270 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 3271 0); 3272 if (!intr_handle->intr_vec) { 3273 PMD_DRV_LOG(ERR, 3274 "Failed to allocate %d rx_queues intr_vec", 3275 dev->data->nb_rx_queues); 3276 return -ENOMEM; 3277 } 3278 } 3279 3280 /* Map queues with MSIX interrupt */ 3281 vsi->nb_used_qps = dev->data->nb_rx_queues; 3282 ice_vsi_queues_bind_intr(vsi); 3283 3284 /* Enable interrupts for all the queues */ 3285 ice_vsi_enable_queues_intr(vsi); 3286 3287 rte_intr_enable(intr_handle); 3288 3289 return 0; 3290 } 3291 3292 static void 3293 ice_get_init_link_status(struct rte_eth_dev *dev) 3294 { 3295 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3296 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3297 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3298 struct ice_link_status link_status; 3299 int ret; 3300 3301 ret = ice_aq_get_link_info(hw->port_info, enable_lse, 3302 &link_status, NULL); 3303 if (ret != ICE_SUCCESS) { 3304 PMD_DRV_LOG(ERR, "Failed to get link info"); 3305 pf->init_link_up = false; 3306 return; 3307 } 3308 3309 if (link_status.link_info & ICE_AQ_LINK_UP) 3310 pf->init_link_up = true; 3311 } 3312 3313 static int 3314 ice_dev_start(struct rte_eth_dev *dev) 3315 { 3316 struct rte_eth_dev_data *data = dev->data; 3317 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3318 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3319 struct ice_vsi *vsi = pf->main_vsi; 3320 uint16_t nb_rxq = 0; 3321 uint16_t nb_txq, i; 3322 uint16_t max_frame_size; 3323 int mask, ret; 3324 3325 /* program Tx queues' context in hardware */ 3326 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 3327 ret = ice_tx_queue_start(dev, nb_txq); 3328 if (ret) { 3329 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 3330 goto tx_err; 3331 } 3332 } 3333 3334 /* program Rx queues' context in hardware*/ 3335 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 3336 ret = ice_rx_queue_start(dev, nb_rxq); 3337 if (ret) { 3338 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 3339 goto rx_err; 3340 } 3341 } 3342 3343 ice_set_rx_function(dev); 3344 ice_set_tx_function(dev); 3345 3346 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 3347 ETH_VLAN_EXTEND_MASK; 3348 ret = ice_vlan_offload_set(dev, mask); 3349 if (ret) { 3350 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 3351 goto rx_err; 3352 } 3353 3354 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 3355 if (ice_rxq_intr_setup(dev)) 3356 return -EIO; 3357 3358 /* Enable receiving broadcast packets and transmitting packets */ 3359 ret = ice_set_vsi_promisc(hw, vsi->idx, 3360 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 3361 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 3362 0); 3363 if (ret != ICE_SUCCESS) 3364 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 3365 3366 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 3367 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 3368 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 3369 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 3370 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 3371 ICE_AQ_LINK_EVENT_AN_COMPLETED | 3372 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 3373 NULL); 3374 if (ret != ICE_SUCCESS) 3375 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 3376 3377 ice_get_init_link_status(dev); 3378 3379 ice_dev_set_link_up(dev); 3380 3381 /* Call get_link_info aq commond to enable/disable LSE */ 3382 ice_link_update(dev, 0); 3383 3384 pf->adapter_stopped = false; 3385 3386 /* Set the max frame size to default value*/ 3387 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ? 3388 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len : 3389 ICE_FRAME_SIZE_MAX; 3390 3391 /* Set the max frame size to HW*/ 3392 ice_aq_set_mac_cfg(hw, max_frame_size, NULL); 3393 3394 return 0; 3395 3396 /* stop the started queues if failed to start all queues */ 3397 rx_err: 3398 for (i = 0; i < nb_rxq; i++) 3399 ice_rx_queue_stop(dev, i); 3400 tx_err: 3401 for (i = 0; i < nb_txq; i++) 3402 ice_tx_queue_stop(dev, i); 3403 3404 return -EIO; 3405 } 3406 3407 static int 3408 ice_dev_reset(struct rte_eth_dev *dev) 3409 { 3410 int ret; 3411 3412 if (dev->data->sriov.active) 3413 return -ENOTSUP; 3414 3415 ret = ice_dev_uninit(dev); 3416 if (ret) { 3417 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 3418 return -ENXIO; 3419 } 3420 3421 ret = ice_dev_init(dev); 3422 if (ret) { 3423 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 3424 return -ENXIO; 3425 } 3426 3427 return 0; 3428 } 3429 3430 static int 3431 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3432 { 3433 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3434 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3435 struct ice_vsi *vsi = pf->main_vsi; 3436 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 3437 bool is_safe_mode = pf->adapter->is_safe_mode; 3438 u64 phy_type_low; 3439 u64 phy_type_high; 3440 3441 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 3442 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 3443 dev_info->max_rx_queues = vsi->nb_qps; 3444 dev_info->max_tx_queues = vsi->nb_qps; 3445 dev_info->max_mac_addrs = vsi->max_macaddrs; 3446 dev_info->max_vfs = pci_dev->max_vfs; 3447 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 3448 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3449 3450 dev_info->rx_offload_capa = 3451 DEV_RX_OFFLOAD_VLAN_STRIP | 3452 DEV_RX_OFFLOAD_JUMBO_FRAME | 3453 DEV_RX_OFFLOAD_KEEP_CRC | 3454 DEV_RX_OFFLOAD_SCATTER | 3455 DEV_RX_OFFLOAD_VLAN_FILTER; 3456 dev_info->tx_offload_capa = 3457 DEV_TX_OFFLOAD_VLAN_INSERT | 3458 DEV_TX_OFFLOAD_TCP_TSO | 3459 DEV_TX_OFFLOAD_MULTI_SEGS | 3460 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3461 dev_info->flow_type_rss_offloads = 0; 3462 3463 if (!is_safe_mode) { 3464 dev_info->rx_offload_capa |= 3465 DEV_RX_OFFLOAD_IPV4_CKSUM | 3466 DEV_RX_OFFLOAD_UDP_CKSUM | 3467 DEV_RX_OFFLOAD_TCP_CKSUM | 3468 DEV_RX_OFFLOAD_QINQ_STRIP | 3469 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3470 DEV_RX_OFFLOAD_VLAN_EXTEND | 3471 DEV_RX_OFFLOAD_RSS_HASH; 3472 dev_info->tx_offload_capa |= 3473 DEV_TX_OFFLOAD_QINQ_INSERT | 3474 DEV_TX_OFFLOAD_IPV4_CKSUM | 3475 DEV_TX_OFFLOAD_UDP_CKSUM | 3476 DEV_TX_OFFLOAD_TCP_CKSUM | 3477 DEV_TX_OFFLOAD_SCTP_CKSUM | 3478 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3479 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 3480 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 3481 } 3482 3483 dev_info->rx_queue_offload_capa = 0; 3484 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3485 3486 dev_info->reta_size = pf->hash_lut_size; 3487 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 3488 3489 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3490 .rx_thresh = { 3491 .pthresh = ICE_DEFAULT_RX_PTHRESH, 3492 .hthresh = ICE_DEFAULT_RX_HTHRESH, 3493 .wthresh = ICE_DEFAULT_RX_WTHRESH, 3494 }, 3495 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 3496 .rx_drop_en = 0, 3497 .offloads = 0, 3498 }; 3499 3500 dev_info->default_txconf = (struct rte_eth_txconf) { 3501 .tx_thresh = { 3502 .pthresh = ICE_DEFAULT_TX_PTHRESH, 3503 .hthresh = ICE_DEFAULT_TX_HTHRESH, 3504 .wthresh = ICE_DEFAULT_TX_WTHRESH, 3505 }, 3506 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 3507 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 3508 .offloads = 0, 3509 }; 3510 3511 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3512 .nb_max = ICE_MAX_RING_DESC, 3513 .nb_min = ICE_MIN_RING_DESC, 3514 .nb_align = ICE_ALIGN_RING_DESC, 3515 }; 3516 3517 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3518 .nb_max = ICE_MAX_RING_DESC, 3519 .nb_min = ICE_MIN_RING_DESC, 3520 .nb_align = ICE_ALIGN_RING_DESC, 3521 }; 3522 3523 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3524 ETH_LINK_SPEED_100M | 3525 ETH_LINK_SPEED_1G | 3526 ETH_LINK_SPEED_2_5G | 3527 ETH_LINK_SPEED_5G | 3528 ETH_LINK_SPEED_10G | 3529 ETH_LINK_SPEED_20G | 3530 ETH_LINK_SPEED_25G; 3531 3532 phy_type_low = hw->port_info->phy.phy_type_low; 3533 phy_type_high = hw->port_info->phy.phy_type_high; 3534 3535 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 3536 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 3537 3538 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 3539 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 3540 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 3541 3542 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 3543 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 3544 3545 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 3546 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 3547 dev_info->default_rxportconf.nb_queues = 1; 3548 dev_info->default_txportconf.nb_queues = 1; 3549 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 3550 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 3551 3552 return 0; 3553 } 3554 3555 static inline int 3556 ice_atomic_read_link_status(struct rte_eth_dev *dev, 3557 struct rte_eth_link *link) 3558 { 3559 struct rte_eth_link *dst = link; 3560 struct rte_eth_link *src = &dev->data->dev_link; 3561 3562 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3563 *(uint64_t *)src) == 0) 3564 return -1; 3565 3566 return 0; 3567 } 3568 3569 static inline int 3570 ice_atomic_write_link_status(struct rte_eth_dev *dev, 3571 struct rte_eth_link *link) 3572 { 3573 struct rte_eth_link *dst = &dev->data->dev_link; 3574 struct rte_eth_link *src = link; 3575 3576 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3577 *(uint64_t *)src) == 0) 3578 return -1; 3579 3580 return 0; 3581 } 3582 3583 static int 3584 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 3585 { 3586 #define CHECK_INTERVAL 100 /* 100ms */ 3587 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 3588 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3589 struct ice_link_status link_status; 3590 struct rte_eth_link link, old; 3591 int status; 3592 unsigned int rep_cnt = MAX_REPEAT_TIME; 3593 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3594 3595 memset(&link, 0, sizeof(link)); 3596 memset(&old, 0, sizeof(old)); 3597 memset(&link_status, 0, sizeof(link_status)); 3598 ice_atomic_read_link_status(dev, &old); 3599 3600 do { 3601 /* Get link status information from hardware */ 3602 status = ice_aq_get_link_info(hw->port_info, enable_lse, 3603 &link_status, NULL); 3604 if (status != ICE_SUCCESS) { 3605 link.link_speed = ETH_SPEED_NUM_100M; 3606 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3607 PMD_DRV_LOG(ERR, "Failed to get link info"); 3608 goto out; 3609 } 3610 3611 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 3612 if (!wait_to_complete || link.link_status) 3613 break; 3614 3615 rte_delay_ms(CHECK_INTERVAL); 3616 } while (--rep_cnt); 3617 3618 if (!link.link_status) 3619 goto out; 3620 3621 /* Full-duplex operation at all supported speeds */ 3622 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3623 3624 /* Parse the link status */ 3625 switch (link_status.link_speed) { 3626 case ICE_AQ_LINK_SPEED_10MB: 3627 link.link_speed = ETH_SPEED_NUM_10M; 3628 break; 3629 case ICE_AQ_LINK_SPEED_100MB: 3630 link.link_speed = ETH_SPEED_NUM_100M; 3631 break; 3632 case ICE_AQ_LINK_SPEED_1000MB: 3633 link.link_speed = ETH_SPEED_NUM_1G; 3634 break; 3635 case ICE_AQ_LINK_SPEED_2500MB: 3636 link.link_speed = ETH_SPEED_NUM_2_5G; 3637 break; 3638 case ICE_AQ_LINK_SPEED_5GB: 3639 link.link_speed = ETH_SPEED_NUM_5G; 3640 break; 3641 case ICE_AQ_LINK_SPEED_10GB: 3642 link.link_speed = ETH_SPEED_NUM_10G; 3643 break; 3644 case ICE_AQ_LINK_SPEED_20GB: 3645 link.link_speed = ETH_SPEED_NUM_20G; 3646 break; 3647 case ICE_AQ_LINK_SPEED_25GB: 3648 link.link_speed = ETH_SPEED_NUM_25G; 3649 break; 3650 case ICE_AQ_LINK_SPEED_40GB: 3651 link.link_speed = ETH_SPEED_NUM_40G; 3652 break; 3653 case ICE_AQ_LINK_SPEED_50GB: 3654 link.link_speed = ETH_SPEED_NUM_50G; 3655 break; 3656 case ICE_AQ_LINK_SPEED_100GB: 3657 link.link_speed = ETH_SPEED_NUM_100G; 3658 break; 3659 case ICE_AQ_LINK_SPEED_UNKNOWN: 3660 PMD_DRV_LOG(ERR, "Unknown link speed"); 3661 link.link_speed = ETH_SPEED_NUM_UNKNOWN; 3662 break; 3663 default: 3664 PMD_DRV_LOG(ERR, "None link speed"); 3665 link.link_speed = ETH_SPEED_NUM_NONE; 3666 break; 3667 } 3668 3669 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 3670 ETH_LINK_SPEED_FIXED); 3671 3672 out: 3673 ice_atomic_write_link_status(dev, &link); 3674 if (link.link_status == old.link_status) 3675 return -1; 3676 3677 return 0; 3678 } 3679 3680 /* Force the physical link state by getting the current PHY capabilities from 3681 * hardware and setting the PHY config based on the determined capabilities. If 3682 * link changes, link event will be triggered because both the Enable Automatic 3683 * Link Update and LESM Enable bits are set when setting the PHY capabilities. 3684 */ 3685 static enum ice_status 3686 ice_force_phys_link_state(struct ice_hw *hw, bool link_up) 3687 { 3688 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3689 struct ice_aqc_get_phy_caps_data *pcaps; 3690 struct ice_port_info *pi; 3691 enum ice_status status; 3692 3693 if (!hw || !hw->port_info) 3694 return ICE_ERR_PARAM; 3695 3696 pi = hw->port_info; 3697 3698 pcaps = (struct ice_aqc_get_phy_caps_data *) 3699 ice_malloc(hw, sizeof(*pcaps)); 3700 if (!pcaps) 3701 return ICE_ERR_NO_MEMORY; 3702 3703 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3704 pcaps, NULL); 3705 if (status) 3706 goto out; 3707 3708 /* No change in link */ 3709 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) && 3710 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) 3711 goto out; 3712 3713 cfg.phy_type_low = pcaps->phy_type_low; 3714 cfg.phy_type_high = pcaps->phy_type_high; 3715 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3716 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an; 3717 cfg.eee_cap = pcaps->eee_cap; 3718 cfg.eeer_value = pcaps->eeer_value; 3719 cfg.link_fec_opt = pcaps->link_fec_options; 3720 if (link_up) 3721 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 3722 else 3723 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 3724 3725 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3726 3727 out: 3728 ice_free(hw, pcaps); 3729 return status; 3730 } 3731 3732 static int 3733 ice_dev_set_link_up(struct rte_eth_dev *dev) 3734 { 3735 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3736 3737 return ice_force_phys_link_state(hw, true); 3738 } 3739 3740 static int 3741 ice_dev_set_link_down(struct rte_eth_dev *dev) 3742 { 3743 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3744 3745 return ice_force_phys_link_state(hw, false); 3746 } 3747 3748 static int 3749 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3750 { 3751 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3752 struct rte_eth_dev_data *dev_data = pf->dev_data; 3753 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 3754 3755 /* check if mtu is within the allowed range */ 3756 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 3757 return -EINVAL; 3758 3759 /* mtu setting is forbidden if port is start */ 3760 if (dev_data->dev_started) { 3761 PMD_DRV_LOG(ERR, 3762 "port %d must be stopped before configuration", 3763 dev_data->port_id); 3764 return -EBUSY; 3765 } 3766 3767 if (frame_size > ICE_ETH_MAX_LEN) 3768 dev_data->dev_conf.rxmode.offloads |= 3769 DEV_RX_OFFLOAD_JUMBO_FRAME; 3770 else 3771 dev_data->dev_conf.rxmode.offloads &= 3772 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 3773 3774 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3775 3776 return 0; 3777 } 3778 3779 static int ice_macaddr_set(struct rte_eth_dev *dev, 3780 struct rte_ether_addr *mac_addr) 3781 { 3782 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3783 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3784 struct ice_vsi *vsi = pf->main_vsi; 3785 struct ice_mac_filter *f; 3786 uint8_t flags = 0; 3787 int ret; 3788 3789 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 3790 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 3791 return -EINVAL; 3792 } 3793 3794 TAILQ_FOREACH(f, &vsi->mac_list, next) { 3795 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 3796 break; 3797 } 3798 3799 if (!f) { 3800 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 3801 return -EIO; 3802 } 3803 3804 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 3805 if (ret != ICE_SUCCESS) { 3806 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 3807 return -EIO; 3808 } 3809 ret = ice_add_mac_filter(vsi, mac_addr); 3810 if (ret != ICE_SUCCESS) { 3811 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 3812 return -EIO; 3813 } 3814 rte_ether_addr_copy(mac_addr, &pf->dev_addr); 3815 3816 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 3817 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 3818 if (ret != ICE_SUCCESS) 3819 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 3820 3821 return 0; 3822 } 3823 3824 /* Add a MAC address, and update filters */ 3825 static int 3826 ice_macaddr_add(struct rte_eth_dev *dev, 3827 struct rte_ether_addr *mac_addr, 3828 __rte_unused uint32_t index, 3829 __rte_unused uint32_t pool) 3830 { 3831 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3832 struct ice_vsi *vsi = pf->main_vsi; 3833 int ret; 3834 3835 ret = ice_add_mac_filter(vsi, mac_addr); 3836 if (ret != ICE_SUCCESS) { 3837 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 3838 return -EINVAL; 3839 } 3840 3841 return ICE_SUCCESS; 3842 } 3843 3844 /* Remove a MAC address, and update filters */ 3845 static void 3846 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 3847 { 3848 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3849 struct ice_vsi *vsi = pf->main_vsi; 3850 struct rte_eth_dev_data *data = dev->data; 3851 struct rte_ether_addr *macaddr; 3852 int ret; 3853 3854 macaddr = &data->mac_addrs[index]; 3855 ret = ice_remove_mac_filter(vsi, macaddr); 3856 if (ret) { 3857 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 3858 return; 3859 } 3860 } 3861 3862 static int 3863 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3864 { 3865 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3866 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id); 3867 struct ice_vsi *vsi = pf->main_vsi; 3868 int ret; 3869 3870 PMD_INIT_FUNC_TRACE(); 3871 3872 /** 3873 * Vlan 0 is the generic filter for untagged packets 3874 * and can't be removed or added by user. 3875 */ 3876 if (vlan_id == 0) 3877 return 0; 3878 3879 if (on) { 3880 ret = ice_add_vlan_filter(vsi, &vlan); 3881 if (ret < 0) { 3882 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 3883 return -EINVAL; 3884 } 3885 } else { 3886 ret = ice_remove_vlan_filter(vsi, &vlan); 3887 if (ret < 0) { 3888 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 3889 return -EINVAL; 3890 } 3891 } 3892 3893 return 0; 3894 } 3895 3896 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are 3897 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8) 3898 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via 3899 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID. 3900 * 3901 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic 3902 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged 3903 * traffic in SVM, since the VLAN TPID isn't part of filtering. 3904 * 3905 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be 3906 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is 3907 * part of filtering. 3908 */ 3909 static int 3910 ice_vsi_add_vlan_zero(struct ice_vsi *vsi) 3911 { 3912 struct ice_vlan vlan; 3913 int err; 3914 3915 vlan = ICE_VLAN(0, 0); 3916 err = ice_add_vlan_filter(vsi, &vlan); 3917 if (err) { 3918 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0"); 3919 return err; 3920 } 3921 3922 /* in SVM both VLAN 0 filters are identical */ 3923 if (!ice_is_dvm_ena(&vsi->adapter->hw)) 3924 return 0; 3925 3926 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0); 3927 err = ice_add_vlan_filter(vsi, &vlan); 3928 if (err) { 3929 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode"); 3930 return err; 3931 } 3932 3933 return 0; 3934 } 3935 3936 /* 3937 * Delete the VLAN 0 filters in the same manner that they were added in 3938 * ice_vsi_add_vlan_zero. 3939 */ 3940 static int 3941 ice_vsi_del_vlan_zero(struct ice_vsi *vsi) 3942 { 3943 struct ice_vlan vlan; 3944 int err; 3945 3946 vlan = ICE_VLAN(0, 0); 3947 err = ice_remove_vlan_filter(vsi, &vlan); 3948 if (err) { 3949 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0"); 3950 return err; 3951 } 3952 3953 /* in SVM both VLAN 0 filters are identical */ 3954 if (!ice_is_dvm_ena(&vsi->adapter->hw)) 3955 return 0; 3956 3957 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0); 3958 err = ice_remove_vlan_filter(vsi, &vlan); 3959 if (err) { 3960 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode"); 3961 return err; 3962 } 3963 3964 return 0; 3965 } 3966 3967 /* Configure vlan filter on or off */ 3968 static int 3969 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 3970 { 3971 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3972 struct ice_vsi_ctx ctxt; 3973 uint8_t sw_flags2; 3974 int ret = 0; 3975 3976 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 3977 3978 if (on) 3979 vsi->info.sw_flags2 |= sw_flags2; 3980 else 3981 vsi->info.sw_flags2 &= ~sw_flags2; 3982 3983 vsi->info.sw_id = hw->port_info->sw_id; 3984 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 3985 ctxt.info.valid_sections = 3986 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 3987 ICE_AQ_VSI_PROP_SECURITY_VALID); 3988 ctxt.vsi_num = vsi->vsi_id; 3989 3990 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 3991 if (ret) { 3992 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 3993 on ? "enable" : "disable"); 3994 return -EINVAL; 3995 } else { 3996 vsi->info.valid_sections |= 3997 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 3998 ICE_AQ_VSI_PROP_SECURITY_VALID); 3999 } 4000 4001 /* consist with other drivers, allow untagged packet when vlan filter on */ 4002 if (on) 4003 ret = ice_vsi_add_vlan_zero(vsi); 4004 else 4005 ret = ice_vsi_del_vlan_zero(vsi); 4006 4007 return 0; 4008 } 4009 4010 /* Manage VLAN stripping for the VSI for Rx */ 4011 static int 4012 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena) 4013 { 4014 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4015 struct ice_vsi_ctx ctxt; 4016 enum ice_status status; 4017 int err = 0; 4018 4019 /* do not allow modifying VLAN stripping when a port VLAN is configured 4020 * on this VSI 4021 */ 4022 if (vsi->info.port_based_inner_vlan) 4023 return 0; 4024 4025 memset(&ctxt, 0, sizeof(ctxt)); 4026 4027 if (ena) 4028 /* Strip VLAN tag from Rx packet and put it in the desc */ 4029 ctxt.info.inner_vlan_flags = 4030 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH; 4031 else 4032 /* Disable stripping. Leave tag in packet */ 4033 ctxt.info.inner_vlan_flags = 4034 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; 4035 4036 /* Allow all packets untagged/tagged */ 4037 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; 4038 4039 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4040 4041 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4042 if (status) { 4043 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping", 4044 ena ? "enable" : "disable"); 4045 err = -EIO; 4046 } else { 4047 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags; 4048 } 4049 4050 return err; 4051 } 4052 4053 static int 4054 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi) 4055 { 4056 return ice_vsi_manage_vlan_stripping(vsi, true); 4057 } 4058 4059 static int 4060 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi) 4061 { 4062 return ice_vsi_manage_vlan_stripping(vsi, false); 4063 } 4064 4065 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi) 4066 { 4067 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4068 struct ice_vsi_ctx ctxt; 4069 enum ice_status status; 4070 int err = 0; 4071 4072 /* do not allow modifying VLAN stripping when a port VLAN is configured 4073 * on this VSI 4074 */ 4075 if (vsi->info.port_based_outer_vlan) 4076 return 0; 4077 4078 memset(&ctxt, 0, sizeof(ctxt)); 4079 4080 ctxt.info.valid_sections = 4081 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 4082 /* clear current outer VLAN strip settings */ 4083 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags & 4084 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M); 4085 ctxt.info.outer_vlan_flags |= 4086 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH << 4087 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) | 4088 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 << 4089 ICE_AQ_VSI_OUTER_TAG_TYPE_S); 4090 4091 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4092 if (status) { 4093 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping"); 4094 err = -EIO; 4095 } else { 4096 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; 4097 } 4098 4099 return err; 4100 } 4101 4102 static int 4103 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi) 4104 { 4105 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4106 struct ice_vsi_ctx ctxt; 4107 enum ice_status status; 4108 int err = 0; 4109 4110 if (vsi->info.port_based_outer_vlan) 4111 return 0; 4112 4113 memset(&ctxt, 0, sizeof(ctxt)); 4114 4115 ctxt.info.valid_sections = 4116 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 4117 /* clear current outer VLAN strip settings */ 4118 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags & 4119 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M; 4120 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING << 4121 ICE_AQ_VSI_OUTER_VLAN_EMODE_S; 4122 4123 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4124 if (status) { 4125 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping"); 4126 err = -EIO; 4127 } else { 4128 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; 4129 } 4130 4131 return err; 4132 } 4133 4134 static int 4135 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena) 4136 { 4137 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4138 int ret; 4139 4140 if (ice_is_dvm_ena(hw)) { 4141 if (ena) 4142 ret = ice_vsi_ena_outer_stripping(vsi); 4143 else 4144 ret = ice_vsi_dis_outer_stripping(vsi); 4145 } else { 4146 if (ena) 4147 ret = ice_vsi_ena_inner_stripping(vsi); 4148 else 4149 ret = ice_vsi_dis_inner_stripping(vsi); 4150 } 4151 4152 return ret; 4153 } 4154 4155 static int 4156 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 4157 { 4158 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4159 struct ice_vsi *vsi = pf->main_vsi; 4160 struct rte_eth_rxmode *rxmode; 4161 4162 rxmode = &dev->data->dev_conf.rxmode; 4163 if (mask & ETH_VLAN_FILTER_MASK) { 4164 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 4165 ice_vsi_config_vlan_filter(vsi, true); 4166 else 4167 ice_vsi_config_vlan_filter(vsi, false); 4168 } 4169 4170 if (mask & ETH_VLAN_STRIP_MASK) { 4171 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 4172 ice_vsi_config_vlan_stripping(vsi, true); 4173 else 4174 ice_vsi_config_vlan_stripping(vsi, false); 4175 } 4176 4177 return 0; 4178 } 4179 4180 static int 4181 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4182 { 4183 struct ice_aq_get_set_rss_lut_params lut_params; 4184 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 4185 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4186 int ret; 4187 4188 if (!lut) 4189 return -EINVAL; 4190 4191 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 4192 lut_params.vsi_handle = vsi->idx; 4193 lut_params.lut_size = lut_size; 4194 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 4195 lut_params.lut = lut; 4196 lut_params.global_lut_id = 0; 4197 ret = ice_aq_get_rss_lut(hw, &lut_params); 4198 if (ret) { 4199 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 4200 return -EINVAL; 4201 } 4202 } else { 4203 uint64_t *lut_dw = (uint64_t *)lut; 4204 uint16_t i, lut_size_dw = lut_size / 4; 4205 4206 for (i = 0; i < lut_size_dw; i++) 4207 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 4208 } 4209 4210 return 0; 4211 } 4212 4213 static int 4214 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4215 { 4216 struct ice_aq_get_set_rss_lut_params lut_params; 4217 struct ice_pf *pf; 4218 struct ice_hw *hw; 4219 int ret; 4220 4221 if (!vsi || !lut) 4222 return -EINVAL; 4223 4224 pf = ICE_VSI_TO_PF(vsi); 4225 hw = ICE_VSI_TO_HW(vsi); 4226 4227 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 4228 lut_params.vsi_handle = vsi->idx; 4229 lut_params.lut_size = lut_size; 4230 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 4231 lut_params.lut = lut; 4232 lut_params.global_lut_id = 0; 4233 ret = ice_aq_set_rss_lut(hw, &lut_params); 4234 if (ret) { 4235 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 4236 return -EINVAL; 4237 } 4238 } else { 4239 uint64_t *lut_dw = (uint64_t *)lut; 4240 uint16_t i, lut_size_dw = lut_size / 4; 4241 4242 for (i = 0; i < lut_size_dw; i++) 4243 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 4244 4245 ice_flush(hw); 4246 } 4247 4248 return 0; 4249 } 4250 4251 static int 4252 ice_rss_reta_update(struct rte_eth_dev *dev, 4253 struct rte_eth_rss_reta_entry64 *reta_conf, 4254 uint16_t reta_size) 4255 { 4256 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4257 uint16_t i, lut_size = pf->hash_lut_size; 4258 uint16_t idx, shift; 4259 uint8_t *lut; 4260 int ret; 4261 4262 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 4263 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 4264 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 4265 PMD_DRV_LOG(ERR, 4266 "The size of hash lookup table configured (%d)" 4267 "doesn't match the number hardware can " 4268 "supported (128, 512, 2048)", 4269 reta_size); 4270 return -EINVAL; 4271 } 4272 4273 /* It MUST use the current LUT size to get the RSS lookup table, 4274 * otherwise if will fail with -100 error code. 4275 */ 4276 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 4277 if (!lut) { 4278 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4279 return -ENOMEM; 4280 } 4281 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 4282 if (ret) 4283 goto out; 4284 4285 for (i = 0; i < reta_size; i++) { 4286 idx = i / RTE_RETA_GROUP_SIZE; 4287 shift = i % RTE_RETA_GROUP_SIZE; 4288 if (reta_conf[idx].mask & (1ULL << shift)) 4289 lut[i] = reta_conf[idx].reta[shift]; 4290 } 4291 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 4292 if (ret == 0 && lut_size != reta_size) { 4293 PMD_DRV_LOG(INFO, 4294 "The size of hash lookup table is changed from (%d) to (%d)", 4295 lut_size, reta_size); 4296 pf->hash_lut_size = reta_size; 4297 } 4298 4299 out: 4300 rte_free(lut); 4301 4302 return ret; 4303 } 4304 4305 static int 4306 ice_rss_reta_query(struct rte_eth_dev *dev, 4307 struct rte_eth_rss_reta_entry64 *reta_conf, 4308 uint16_t reta_size) 4309 { 4310 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4311 uint16_t i, lut_size = pf->hash_lut_size; 4312 uint16_t idx, shift; 4313 uint8_t *lut; 4314 int ret; 4315 4316 if (reta_size != lut_size) { 4317 PMD_DRV_LOG(ERR, 4318 "The size of hash lookup table configured (%d)" 4319 "doesn't match the number hardware can " 4320 "supported (%d)", 4321 reta_size, lut_size); 4322 return -EINVAL; 4323 } 4324 4325 lut = rte_zmalloc(NULL, reta_size, 0); 4326 if (!lut) { 4327 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4328 return -ENOMEM; 4329 } 4330 4331 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 4332 if (ret) 4333 goto out; 4334 4335 for (i = 0; i < reta_size; i++) { 4336 idx = i / RTE_RETA_GROUP_SIZE; 4337 shift = i % RTE_RETA_GROUP_SIZE; 4338 if (reta_conf[idx].mask & (1ULL << shift)) 4339 reta_conf[idx].reta[shift] = lut[i]; 4340 } 4341 4342 out: 4343 rte_free(lut); 4344 4345 return ret; 4346 } 4347 4348 static int 4349 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 4350 { 4351 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4352 int ret = 0; 4353 4354 if (!key || key_len == 0) { 4355 PMD_DRV_LOG(DEBUG, "No key to be configured"); 4356 return 0; 4357 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 4358 sizeof(uint32_t)) { 4359 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 4360 return -EINVAL; 4361 } 4362 4363 struct ice_aqc_get_set_rss_keys *key_dw = 4364 (struct ice_aqc_get_set_rss_keys *)key; 4365 4366 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 4367 if (ret) { 4368 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 4369 ret = -EINVAL; 4370 } 4371 4372 return ret; 4373 } 4374 4375 static int 4376 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 4377 { 4378 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4379 int ret; 4380 4381 if (!key || !key_len) 4382 return -EINVAL; 4383 4384 ret = ice_aq_get_rss_key 4385 (hw, vsi->idx, 4386 (struct ice_aqc_get_set_rss_keys *)key); 4387 if (ret) { 4388 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 4389 return -EINVAL; 4390 } 4391 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 4392 4393 return 0; 4394 } 4395 4396 static int 4397 ice_rss_hash_update(struct rte_eth_dev *dev, 4398 struct rte_eth_rss_conf *rss_conf) 4399 { 4400 enum ice_status status = ICE_SUCCESS; 4401 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4402 struct ice_vsi *vsi = pf->main_vsi; 4403 4404 /* set hash key */ 4405 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 4406 if (status) 4407 return status; 4408 4409 if (rss_conf->rss_hf == 0) { 4410 pf->rss_hf = 0; 4411 return 0; 4412 } 4413 4414 /* RSS hash configuration */ 4415 ice_rss_hash_set(pf, rss_conf->rss_hf); 4416 4417 return 0; 4418 } 4419 4420 static int 4421 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 4422 struct rte_eth_rss_conf *rss_conf) 4423 { 4424 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4425 struct ice_vsi *vsi = pf->main_vsi; 4426 4427 ice_get_rss_key(vsi, rss_conf->rss_key, 4428 &rss_conf->rss_key_len); 4429 4430 rss_conf->rss_hf = pf->rss_hf; 4431 return 0; 4432 } 4433 4434 static int 4435 ice_promisc_enable(struct rte_eth_dev *dev) 4436 { 4437 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4438 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4439 struct ice_vsi *vsi = pf->main_vsi; 4440 enum ice_status status; 4441 uint8_t pmask; 4442 int ret = 0; 4443 4444 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 4445 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4446 4447 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4448 switch (status) { 4449 case ICE_ERR_ALREADY_EXISTS: 4450 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 4451 case ICE_SUCCESS: 4452 break; 4453 default: 4454 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 4455 ret = -EAGAIN; 4456 } 4457 4458 return ret; 4459 } 4460 4461 static int 4462 ice_promisc_disable(struct rte_eth_dev *dev) 4463 { 4464 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4465 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4466 struct ice_vsi *vsi = pf->main_vsi; 4467 enum ice_status status; 4468 uint8_t pmask; 4469 int ret = 0; 4470 4471 if (dev->data->all_multicast == 1) 4472 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX; 4473 else 4474 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 4475 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4476 4477 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 4478 if (status != ICE_SUCCESS) { 4479 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 4480 ret = -EAGAIN; 4481 } 4482 4483 return ret; 4484 } 4485 4486 static int 4487 ice_allmulti_enable(struct rte_eth_dev *dev) 4488 { 4489 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4490 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4491 struct ice_vsi *vsi = pf->main_vsi; 4492 enum ice_status status; 4493 uint8_t pmask; 4494 int ret = 0; 4495 4496 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4497 4498 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4499 4500 switch (status) { 4501 case ICE_ERR_ALREADY_EXISTS: 4502 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled"); 4503 case ICE_SUCCESS: 4504 break; 4505 default: 4506 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 4507 ret = -EAGAIN; 4508 } 4509 4510 return ret; 4511 } 4512 4513 static int 4514 ice_allmulti_disable(struct rte_eth_dev *dev) 4515 { 4516 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4517 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4518 struct ice_vsi *vsi = pf->main_vsi; 4519 enum ice_status status; 4520 uint8_t pmask; 4521 int ret = 0; 4522 4523 if (dev->data->promiscuous == 1) 4524 return 0; /* must remain in all_multicast mode */ 4525 4526 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4527 4528 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 4529 if (status != ICE_SUCCESS) { 4530 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 4531 ret = -EAGAIN; 4532 } 4533 4534 return ret; 4535 } 4536 4537 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 4538 uint16_t queue_id) 4539 { 4540 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 4541 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4542 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4543 uint32_t val; 4544 uint16_t msix_intr; 4545 4546 msix_intr = intr_handle->intr_vec[queue_id]; 4547 4548 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 4549 GLINT_DYN_CTL_ITR_INDX_M; 4550 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 4551 4552 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 4553 rte_intr_ack(&pci_dev->intr_handle); 4554 4555 return 0; 4556 } 4557 4558 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 4559 uint16_t queue_id) 4560 { 4561 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 4562 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4563 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4564 uint16_t msix_intr; 4565 4566 msix_intr = intr_handle->intr_vec[queue_id]; 4567 4568 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 4569 4570 return 0; 4571 } 4572 4573 static int 4574 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 4575 { 4576 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4577 u8 ver, patch; 4578 u16 build; 4579 int ret; 4580 4581 ver = hw->flash.orom.major; 4582 patch = hw->flash.orom.patch; 4583 build = hw->flash.orom.build; 4584 4585 ret = snprintf(fw_version, fw_size, 4586 "%x.%02x 0x%08x %d.%d.%d", 4587 hw->flash.nvm.major, 4588 hw->flash.nvm.minor, 4589 hw->flash.nvm.eetrack, 4590 ver, build, patch); 4591 if (ret < 0) 4592 return -EINVAL; 4593 4594 /* add the size of '\0' */ 4595 ret += 1; 4596 if (fw_size < (size_t)ret) 4597 return ret; 4598 else 4599 return 0; 4600 } 4601 4602 static int 4603 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 4604 { 4605 struct ice_hw *hw; 4606 struct ice_vsi_ctx ctxt; 4607 uint8_t vlan_flags = 0; 4608 int ret; 4609 4610 if (!vsi || !info) { 4611 PMD_DRV_LOG(ERR, "invalid parameters"); 4612 return -EINVAL; 4613 } 4614 4615 if (info->on) { 4616 vsi->info.port_based_inner_vlan = info->config.pvid; 4617 /** 4618 * If insert pvid is enabled, only tagged pkts are 4619 * allowed to be sent out. 4620 */ 4621 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | 4622 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; 4623 } else { 4624 vsi->info.port_based_inner_vlan = 0; 4625 if (info->config.reject.tagged == 0) 4626 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED; 4627 4628 if (info->config.reject.untagged == 0) 4629 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; 4630 } 4631 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | 4632 ICE_AQ_VSI_INNER_VLAN_EMODE_M); 4633 vsi->info.inner_vlan_flags |= vlan_flags; 4634 memset(&ctxt, 0, sizeof(ctxt)); 4635 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4636 ctxt.info.valid_sections = 4637 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4638 ctxt.vsi_num = vsi->vsi_id; 4639 4640 hw = ICE_VSI_TO_HW(vsi); 4641 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4642 if (ret != ICE_SUCCESS) { 4643 PMD_DRV_LOG(ERR, 4644 "update VSI for VLAN insert failed, err %d", 4645 ret); 4646 return -EINVAL; 4647 } 4648 4649 vsi->info.valid_sections |= 4650 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4651 4652 return ret; 4653 } 4654 4655 static int 4656 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 4657 { 4658 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4659 struct ice_vsi *vsi = pf->main_vsi; 4660 struct rte_eth_dev_data *data = pf->dev_data; 4661 struct ice_vsi_vlan_pvid_info info; 4662 int ret; 4663 4664 memset(&info, 0, sizeof(info)); 4665 info.on = on; 4666 if (info.on) { 4667 info.config.pvid = pvid; 4668 } else { 4669 info.config.reject.tagged = 4670 data->dev_conf.txmode.hw_vlan_reject_tagged; 4671 info.config.reject.untagged = 4672 data->dev_conf.txmode.hw_vlan_reject_untagged; 4673 } 4674 4675 ret = ice_vsi_vlan_pvid_set(vsi, &info); 4676 if (ret < 0) { 4677 PMD_DRV_LOG(ERR, "Failed to set pvid."); 4678 return -EINVAL; 4679 } 4680 4681 return 0; 4682 } 4683 4684 static int 4685 ice_get_eeprom_length(struct rte_eth_dev *dev) 4686 { 4687 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4688 4689 return hw->flash.flash_size; 4690 } 4691 4692 static int 4693 ice_get_eeprom(struct rte_eth_dev *dev, 4694 struct rte_dev_eeprom_info *eeprom) 4695 { 4696 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4697 enum ice_status status = ICE_SUCCESS; 4698 uint8_t *data = eeprom->data; 4699 4700 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4701 4702 status = ice_acquire_nvm(hw, ICE_RES_READ); 4703 if (status) { 4704 PMD_DRV_LOG(ERR, "acquire nvm failed."); 4705 return -EIO; 4706 } 4707 4708 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length, 4709 data, false); 4710 4711 ice_release_nvm(hw); 4712 4713 if (status) { 4714 PMD_DRV_LOG(ERR, "EEPROM read failed."); 4715 return -EIO; 4716 } 4717 4718 return 0; 4719 } 4720 4721 static void 4722 ice_stat_update_32(struct ice_hw *hw, 4723 uint32_t reg, 4724 bool offset_loaded, 4725 uint64_t *offset, 4726 uint64_t *stat) 4727 { 4728 uint64_t new_data; 4729 4730 new_data = (uint64_t)ICE_READ_REG(hw, reg); 4731 if (!offset_loaded) 4732 *offset = new_data; 4733 4734 if (new_data >= *offset) 4735 *stat = (uint64_t)(new_data - *offset); 4736 else 4737 *stat = (uint64_t)((new_data + 4738 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 4739 - *offset); 4740 } 4741 4742 static void 4743 ice_stat_update_40(struct ice_hw *hw, 4744 uint32_t hireg, 4745 uint32_t loreg, 4746 bool offset_loaded, 4747 uint64_t *offset, 4748 uint64_t *stat) 4749 { 4750 uint64_t new_data; 4751 4752 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 4753 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 4754 ICE_32_BIT_WIDTH; 4755 4756 if (!offset_loaded) 4757 *offset = new_data; 4758 4759 if (new_data >= *offset) 4760 *stat = new_data - *offset; 4761 else 4762 *stat = (uint64_t)((new_data + 4763 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 4764 *offset); 4765 4766 *stat &= ICE_40_BIT_MASK; 4767 } 4768 4769 /* Get all the statistics of a VSI */ 4770 static void 4771 ice_update_vsi_stats(struct ice_vsi *vsi) 4772 { 4773 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 4774 struct ice_eth_stats *nes = &vsi->eth_stats; 4775 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4776 int idx = rte_le_to_cpu_16(vsi->vsi_id); 4777 4778 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 4779 vsi->offset_loaded, &oes->rx_bytes, 4780 &nes->rx_bytes); 4781 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 4782 vsi->offset_loaded, &oes->rx_unicast, 4783 &nes->rx_unicast); 4784 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 4785 vsi->offset_loaded, &oes->rx_multicast, 4786 &nes->rx_multicast); 4787 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 4788 vsi->offset_loaded, &oes->rx_broadcast, 4789 &nes->rx_broadcast); 4790 /* enlarge the limitation when rx_bytes overflowed */ 4791 if (vsi->offset_loaded) { 4792 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes) 4793 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4794 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes); 4795 } 4796 vsi->old_rx_bytes = nes->rx_bytes; 4797 /* exclude CRC bytes */ 4798 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 4799 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 4800 4801 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 4802 &oes->rx_discards, &nes->rx_discards); 4803 /* GLV_REPC not supported */ 4804 /* GLV_RMPC not supported */ 4805 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 4806 &oes->rx_unknown_protocol, 4807 &nes->rx_unknown_protocol); 4808 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 4809 vsi->offset_loaded, &oes->tx_bytes, 4810 &nes->tx_bytes); 4811 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 4812 vsi->offset_loaded, &oes->tx_unicast, 4813 &nes->tx_unicast); 4814 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 4815 vsi->offset_loaded, &oes->tx_multicast, 4816 &nes->tx_multicast); 4817 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 4818 vsi->offset_loaded, &oes->tx_broadcast, 4819 &nes->tx_broadcast); 4820 /* GLV_TDPC not supported */ 4821 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 4822 &oes->tx_errors, &nes->tx_errors); 4823 /* enlarge the limitation when tx_bytes overflowed */ 4824 if (vsi->offset_loaded) { 4825 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes) 4826 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4827 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes); 4828 } 4829 vsi->old_tx_bytes = nes->tx_bytes; 4830 vsi->offset_loaded = true; 4831 4832 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 4833 vsi->vsi_id); 4834 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 4835 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 4836 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 4837 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 4838 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 4839 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 4840 nes->rx_unknown_protocol); 4841 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 4842 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 4843 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 4844 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 4845 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 4846 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 4847 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 4848 vsi->vsi_id); 4849 } 4850 4851 static void 4852 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 4853 { 4854 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 4855 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 4856 4857 /* Get statistics of struct ice_eth_stats */ 4858 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 4859 GLPRT_GORCL(hw->port_info->lport), 4860 pf->offset_loaded, &os->eth.rx_bytes, 4861 &ns->eth.rx_bytes); 4862 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 4863 GLPRT_UPRCL(hw->port_info->lport), 4864 pf->offset_loaded, &os->eth.rx_unicast, 4865 &ns->eth.rx_unicast); 4866 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 4867 GLPRT_MPRCL(hw->port_info->lport), 4868 pf->offset_loaded, &os->eth.rx_multicast, 4869 &ns->eth.rx_multicast); 4870 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 4871 GLPRT_BPRCL(hw->port_info->lport), 4872 pf->offset_loaded, &os->eth.rx_broadcast, 4873 &ns->eth.rx_broadcast); 4874 ice_stat_update_32(hw, PRTRPB_RDPC, 4875 pf->offset_loaded, &os->eth.rx_discards, 4876 &ns->eth.rx_discards); 4877 /* enlarge the limitation when rx_bytes overflowed */ 4878 if (pf->offset_loaded) { 4879 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes) 4880 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4881 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes); 4882 } 4883 pf->old_rx_bytes = ns->eth.rx_bytes; 4884 4885 /* Workaround: CRC size should not be included in byte statistics, 4886 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 4887 * packet. 4888 */ 4889 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 4890 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 4891 4892 /* GLPRT_REPC not supported */ 4893 /* GLPRT_RMPC not supported */ 4894 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 4895 pf->offset_loaded, 4896 &os->eth.rx_unknown_protocol, 4897 &ns->eth.rx_unknown_protocol); 4898 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 4899 GLPRT_GOTCL(hw->port_info->lport), 4900 pf->offset_loaded, &os->eth.tx_bytes, 4901 &ns->eth.tx_bytes); 4902 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 4903 GLPRT_UPTCL(hw->port_info->lport), 4904 pf->offset_loaded, &os->eth.tx_unicast, 4905 &ns->eth.tx_unicast); 4906 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 4907 GLPRT_MPTCL(hw->port_info->lport), 4908 pf->offset_loaded, &os->eth.tx_multicast, 4909 &ns->eth.tx_multicast); 4910 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 4911 GLPRT_BPTCL(hw->port_info->lport), 4912 pf->offset_loaded, &os->eth.tx_broadcast, 4913 &ns->eth.tx_broadcast); 4914 /* enlarge the limitation when tx_bytes overflowed */ 4915 if (pf->offset_loaded) { 4916 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes) 4917 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4918 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes); 4919 } 4920 pf->old_tx_bytes = ns->eth.tx_bytes; 4921 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 4922 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 4923 4924 /* GLPRT_TEPC not supported */ 4925 4926 /* additional port specific stats */ 4927 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 4928 pf->offset_loaded, &os->tx_dropped_link_down, 4929 &ns->tx_dropped_link_down); 4930 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 4931 pf->offset_loaded, &os->crc_errors, 4932 &ns->crc_errors); 4933 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 4934 pf->offset_loaded, &os->illegal_bytes, 4935 &ns->illegal_bytes); 4936 /* GLPRT_ERRBC not supported */ 4937 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 4938 pf->offset_loaded, &os->mac_local_faults, 4939 &ns->mac_local_faults); 4940 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 4941 pf->offset_loaded, &os->mac_remote_faults, 4942 &ns->mac_remote_faults); 4943 4944 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 4945 pf->offset_loaded, &os->rx_len_errors, 4946 &ns->rx_len_errors); 4947 4948 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 4949 pf->offset_loaded, &os->link_xon_rx, 4950 &ns->link_xon_rx); 4951 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 4952 pf->offset_loaded, &os->link_xoff_rx, 4953 &ns->link_xoff_rx); 4954 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 4955 pf->offset_loaded, &os->link_xon_tx, 4956 &ns->link_xon_tx); 4957 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 4958 pf->offset_loaded, &os->link_xoff_tx, 4959 &ns->link_xoff_tx); 4960 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 4961 GLPRT_PRC64L(hw->port_info->lport), 4962 pf->offset_loaded, &os->rx_size_64, 4963 &ns->rx_size_64); 4964 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 4965 GLPRT_PRC127L(hw->port_info->lport), 4966 pf->offset_loaded, &os->rx_size_127, 4967 &ns->rx_size_127); 4968 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 4969 GLPRT_PRC255L(hw->port_info->lport), 4970 pf->offset_loaded, &os->rx_size_255, 4971 &ns->rx_size_255); 4972 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 4973 GLPRT_PRC511L(hw->port_info->lport), 4974 pf->offset_loaded, &os->rx_size_511, 4975 &ns->rx_size_511); 4976 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 4977 GLPRT_PRC1023L(hw->port_info->lport), 4978 pf->offset_loaded, &os->rx_size_1023, 4979 &ns->rx_size_1023); 4980 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 4981 GLPRT_PRC1522L(hw->port_info->lport), 4982 pf->offset_loaded, &os->rx_size_1522, 4983 &ns->rx_size_1522); 4984 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 4985 GLPRT_PRC9522L(hw->port_info->lport), 4986 pf->offset_loaded, &os->rx_size_big, 4987 &ns->rx_size_big); 4988 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 4989 pf->offset_loaded, &os->rx_undersize, 4990 &ns->rx_undersize); 4991 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 4992 pf->offset_loaded, &os->rx_fragments, 4993 &ns->rx_fragments); 4994 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 4995 pf->offset_loaded, &os->rx_oversize, 4996 &ns->rx_oversize); 4997 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 4998 pf->offset_loaded, &os->rx_jabber, 4999 &ns->rx_jabber); 5000 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 5001 GLPRT_PTC64L(hw->port_info->lport), 5002 pf->offset_loaded, &os->tx_size_64, 5003 &ns->tx_size_64); 5004 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 5005 GLPRT_PTC127L(hw->port_info->lport), 5006 pf->offset_loaded, &os->tx_size_127, 5007 &ns->tx_size_127); 5008 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 5009 GLPRT_PTC255L(hw->port_info->lport), 5010 pf->offset_loaded, &os->tx_size_255, 5011 &ns->tx_size_255); 5012 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 5013 GLPRT_PTC511L(hw->port_info->lport), 5014 pf->offset_loaded, &os->tx_size_511, 5015 &ns->tx_size_511); 5016 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 5017 GLPRT_PTC1023L(hw->port_info->lport), 5018 pf->offset_loaded, &os->tx_size_1023, 5019 &ns->tx_size_1023); 5020 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 5021 GLPRT_PTC1522L(hw->port_info->lport), 5022 pf->offset_loaded, &os->tx_size_1522, 5023 &ns->tx_size_1522); 5024 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 5025 GLPRT_PTC9522L(hw->port_info->lport), 5026 pf->offset_loaded, &os->tx_size_big, 5027 &ns->tx_size_big); 5028 5029 /* GLPRT_MSPDC not supported */ 5030 /* GLPRT_XEC not supported */ 5031 5032 pf->offset_loaded = true; 5033 5034 if (pf->main_vsi) 5035 ice_update_vsi_stats(pf->main_vsi); 5036 } 5037 5038 /* Get all statistics of a port */ 5039 static int 5040 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 5041 { 5042 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5043 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5044 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 5045 5046 /* call read registers - updates values, now write them to struct */ 5047 ice_read_stats_registers(pf, hw); 5048 5049 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 5050 pf->main_vsi->eth_stats.rx_multicast + 5051 pf->main_vsi->eth_stats.rx_broadcast - 5052 pf->main_vsi->eth_stats.rx_discards; 5053 stats->opackets = ns->eth.tx_unicast + 5054 ns->eth.tx_multicast + 5055 ns->eth.tx_broadcast; 5056 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 5057 stats->obytes = ns->eth.tx_bytes; 5058 stats->oerrors = ns->eth.tx_errors + 5059 pf->main_vsi->eth_stats.tx_errors; 5060 5061 /* Rx Errors */ 5062 stats->imissed = ns->eth.rx_discards + 5063 pf->main_vsi->eth_stats.rx_discards; 5064 stats->ierrors = ns->crc_errors + 5065 ns->rx_undersize + 5066 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 5067 5068 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 5069 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 5070 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 5071 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 5072 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 5073 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 5074 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 5075 pf->main_vsi->eth_stats.rx_discards); 5076 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 5077 ns->eth.rx_unknown_protocol); 5078 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 5079 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 5080 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 5081 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 5082 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 5083 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 5084 pf->main_vsi->eth_stats.tx_discards); 5085 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 5086 5087 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 5088 ns->tx_dropped_link_down); 5089 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 5090 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 5091 ns->illegal_bytes); 5092 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 5093 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 5094 ns->mac_local_faults); 5095 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 5096 ns->mac_remote_faults); 5097 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 5098 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 5099 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 5100 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 5101 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 5102 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 5103 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 5104 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 5105 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 5106 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 5107 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 5108 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 5109 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 5110 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 5111 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 5112 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 5113 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 5114 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 5115 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 5116 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 5117 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 5118 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 5119 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 5120 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 5121 return 0; 5122 } 5123 5124 /* Reset the statistics */ 5125 static int 5126 ice_stats_reset(struct rte_eth_dev *dev) 5127 { 5128 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5129 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5130 5131 /* Mark PF and VSI stats to update the offset, aka "reset" */ 5132 pf->offset_loaded = false; 5133 if (pf->main_vsi) 5134 pf->main_vsi->offset_loaded = false; 5135 5136 /* read the stats, reading current register values into offset */ 5137 ice_read_stats_registers(pf, hw); 5138 5139 return 0; 5140 } 5141 5142 static uint32_t 5143 ice_xstats_calc_num(void) 5144 { 5145 uint32_t num; 5146 5147 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 5148 5149 return num; 5150 } 5151 5152 static int 5153 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 5154 unsigned int n) 5155 { 5156 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5157 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5158 unsigned int i; 5159 unsigned int count; 5160 struct ice_hw_port_stats *hw_stats = &pf->stats; 5161 5162 count = ice_xstats_calc_num(); 5163 if (n < count) 5164 return count; 5165 5166 ice_read_stats_registers(pf, hw); 5167 5168 if (!xstats) 5169 return 0; 5170 5171 count = 0; 5172 5173 /* Get stats from ice_eth_stats struct */ 5174 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 5175 xstats[count].value = 5176 *(uint64_t *)((char *)&hw_stats->eth + 5177 ice_stats_strings[i].offset); 5178 xstats[count].id = count; 5179 count++; 5180 } 5181 5182 /* Get individiual stats from ice_hw_port struct */ 5183 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 5184 xstats[count].value = 5185 *(uint64_t *)((char *)hw_stats + 5186 ice_hw_port_strings[i].offset); 5187 xstats[count].id = count; 5188 count++; 5189 } 5190 5191 return count; 5192 } 5193 5194 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 5195 struct rte_eth_xstat_name *xstats_names, 5196 __rte_unused unsigned int limit) 5197 { 5198 unsigned int count = 0; 5199 unsigned int i; 5200 5201 if (!xstats_names) 5202 return ice_xstats_calc_num(); 5203 5204 /* Note: limit checked in rte_eth_xstats_names() */ 5205 5206 /* Get stats from ice_eth_stats struct */ 5207 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 5208 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 5209 sizeof(xstats_names[count].name)); 5210 count++; 5211 } 5212 5213 /* Get individiual stats from ice_hw_port struct */ 5214 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 5215 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 5216 sizeof(xstats_names[count].name)); 5217 count++; 5218 } 5219 5220 return count; 5221 } 5222 5223 static int 5224 ice_dev_flow_ops_get(struct rte_eth_dev *dev, 5225 const struct rte_flow_ops **ops) 5226 { 5227 if (!dev) 5228 return -EINVAL; 5229 5230 *ops = &ice_flow_ops; 5231 return 0; 5232 } 5233 5234 /* Add UDP tunneling port */ 5235 static int 5236 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 5237 struct rte_eth_udp_tunnel *udp_tunnel) 5238 { 5239 int ret = 0; 5240 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5241 5242 if (udp_tunnel == NULL) 5243 return -EINVAL; 5244 5245 switch (udp_tunnel->prot_type) { 5246 case RTE_TUNNEL_TYPE_VXLAN: 5247 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); 5248 break; 5249 default: 5250 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5251 ret = -EINVAL; 5252 break; 5253 } 5254 5255 return ret; 5256 } 5257 5258 /* Delete UDP tunneling port */ 5259 static int 5260 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 5261 struct rte_eth_udp_tunnel *udp_tunnel) 5262 { 5263 int ret = 0; 5264 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5265 5266 if (udp_tunnel == NULL) 5267 return -EINVAL; 5268 5269 switch (udp_tunnel->prot_type) { 5270 case RTE_TUNNEL_TYPE_VXLAN: 5271 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); 5272 break; 5273 default: 5274 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5275 ret = -EINVAL; 5276 break; 5277 } 5278 5279 return ret; 5280 } 5281 5282 static int 5283 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5284 struct rte_pci_device *pci_dev) 5285 { 5286 return rte_eth_dev_pci_generic_probe(pci_dev, 5287 sizeof(struct ice_adapter), 5288 ice_dev_init); 5289 } 5290 5291 static int 5292 ice_pci_remove(struct rte_pci_device *pci_dev) 5293 { 5294 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 5295 } 5296 5297 static struct rte_pci_driver rte_ice_pmd = { 5298 .id_table = pci_id_ice_map, 5299 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 5300 .probe = ice_pci_probe, 5301 .remove = ice_pci_remove, 5302 }; 5303 5304 /** 5305 * Driver initialization routine. 5306 * Invoked once at EAL init time. 5307 * Register itself as the [Poll Mode] Driver of PCI devices. 5308 */ 5309 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 5310 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 5311 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 5312 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 5313 ICE_HW_DEBUG_MASK_ARG "=0xXXX" 5314 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>" 5315 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" 5316 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"); 5317 5318 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE); 5319 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE); 5320 #ifdef RTE_ETHDEV_DEBUG_RX 5321 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG); 5322 #endif 5323 #ifdef RTE_ETHDEV_DEBUG_TX 5324 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG); 5325 #endif 5326