1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <rte_ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include "base/ice_sched.h" 14 #include "base/ice_flow.h" 15 #include "base/ice_dcb.h" 16 #include "base/ice_common.h" 17 18 #include "rte_pmd_ice.h" 19 #include "ice_ethdev.h" 20 #include "ice_rxtx.h" 21 #include "ice_generic_flow.h" 22 23 /* devargs */ 24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" 25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" 26 #define ICE_PROTO_XTR_ARG "proto_xtr" 27 28 static const char * const ice_valid_args[] = { 29 ICE_SAFE_MODE_SUPPORT_ARG, 30 ICE_PIPELINE_MODE_SUPPORT_ARG, 31 ICE_PROTO_XTR_ARG, 32 NULL 33 }; 34 35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = { 36 .name = "ice_dynfield_proto_xtr_metadata", 37 .size = sizeof(uint32_t), 38 .align = __alignof__(uint32_t), 39 .flags = 0, 40 }; 41 42 struct proto_xtr_ol_flag { 43 const struct rte_mbuf_dynflag param; 44 uint64_t *ol_flag; 45 bool required; 46 }; 47 48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX]; 49 50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = { 51 [PROTO_XTR_VLAN] = { 52 .param = { .name = "ice_dynflag_proto_xtr_vlan" }, 53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask }, 54 [PROTO_XTR_IPV4] = { 55 .param = { .name = "ice_dynflag_proto_xtr_ipv4" }, 56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask }, 57 [PROTO_XTR_IPV6] = { 58 .param = { .name = "ice_dynflag_proto_xtr_ipv6" }, 59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask }, 60 [PROTO_XTR_IPV6_FLOW] = { 61 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" }, 62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask }, 63 [PROTO_XTR_TCP] = { 64 .param = { .name = "ice_dynflag_proto_xtr_tcp" }, 65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask }, 66 [PROTO_XTR_IP_OFFSET] = { 67 .param = { .name = "ice_dynflag_proto_xtr_ip_offset" }, 68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask }, 69 }; 70 71 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 72 73 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package" 74 #define ICE_COMMS_PKG_NAME "ICE COMMS Package" 75 #define ICE_MAX_RES_DESC_NUM 1024 76 77 static int ice_dev_configure(struct rte_eth_dev *dev); 78 static int ice_dev_start(struct rte_eth_dev *dev); 79 static int ice_dev_stop(struct rte_eth_dev *dev); 80 static int ice_dev_close(struct rte_eth_dev *dev); 81 static int ice_dev_reset(struct rte_eth_dev *dev); 82 static int ice_dev_info_get(struct rte_eth_dev *dev, 83 struct rte_eth_dev_info *dev_info); 84 static int ice_link_update(struct rte_eth_dev *dev, 85 int wait_to_complete); 86 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 87 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 88 89 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 90 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 91 static int ice_rss_reta_update(struct rte_eth_dev *dev, 92 struct rte_eth_rss_reta_entry64 *reta_conf, 93 uint16_t reta_size); 94 static int ice_rss_reta_query(struct rte_eth_dev *dev, 95 struct rte_eth_rss_reta_entry64 *reta_conf, 96 uint16_t reta_size); 97 static int ice_rss_hash_update(struct rte_eth_dev *dev, 98 struct rte_eth_rss_conf *rss_conf); 99 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 100 struct rte_eth_rss_conf *rss_conf); 101 static int ice_promisc_enable(struct rte_eth_dev *dev); 102 static int ice_promisc_disable(struct rte_eth_dev *dev); 103 static int ice_allmulti_enable(struct rte_eth_dev *dev); 104 static int ice_allmulti_disable(struct rte_eth_dev *dev); 105 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 106 uint16_t vlan_id, 107 int on); 108 static int ice_macaddr_set(struct rte_eth_dev *dev, 109 struct rte_ether_addr *mac_addr); 110 static int ice_macaddr_add(struct rte_eth_dev *dev, 111 struct rte_ether_addr *mac_addr, 112 __rte_unused uint32_t index, 113 uint32_t pool); 114 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 115 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 116 uint16_t queue_id); 117 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 118 uint16_t queue_id); 119 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 120 size_t fw_size); 121 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 122 uint16_t pvid, int on); 123 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 124 static int ice_get_eeprom(struct rte_eth_dev *dev, 125 struct rte_dev_eeprom_info *eeprom); 126 static int ice_stats_get(struct rte_eth_dev *dev, 127 struct rte_eth_stats *stats); 128 static int ice_stats_reset(struct rte_eth_dev *dev); 129 static int ice_xstats_get(struct rte_eth_dev *dev, 130 struct rte_eth_xstat *xstats, unsigned int n); 131 static int ice_xstats_get_names(struct rte_eth_dev *dev, 132 struct rte_eth_xstat_name *xstats_names, 133 unsigned int limit); 134 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, 135 enum rte_filter_type filter_type, 136 enum rte_filter_op filter_op, 137 void *arg); 138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 139 struct rte_eth_udp_tunnel *udp_tunnel); 140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 141 struct rte_eth_udp_tunnel *udp_tunnel); 142 143 static const struct rte_pci_id pci_id_ice_map[] = { 144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) }, 145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) }, 146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) }, 147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) }, 148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) }, 149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) }, 153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) }, 154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) }, 155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) }, 156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) }, 157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) }, 158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) }, 159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) }, 160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) }, 161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) }, 162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) }, 163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) }, 164 { .vendor_id = 0, /* sentinel */ }, 165 }; 166 167 static const struct eth_dev_ops ice_eth_dev_ops = { 168 .dev_configure = ice_dev_configure, 169 .dev_start = ice_dev_start, 170 .dev_stop = ice_dev_stop, 171 .dev_close = ice_dev_close, 172 .dev_reset = ice_dev_reset, 173 .dev_set_link_up = ice_dev_set_link_up, 174 .dev_set_link_down = ice_dev_set_link_down, 175 .rx_queue_start = ice_rx_queue_start, 176 .rx_queue_stop = ice_rx_queue_stop, 177 .tx_queue_start = ice_tx_queue_start, 178 .tx_queue_stop = ice_tx_queue_stop, 179 .rx_queue_setup = ice_rx_queue_setup, 180 .rx_queue_release = ice_rx_queue_release, 181 .tx_queue_setup = ice_tx_queue_setup, 182 .tx_queue_release = ice_tx_queue_release, 183 .dev_infos_get = ice_dev_info_get, 184 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 185 .link_update = ice_link_update, 186 .mtu_set = ice_mtu_set, 187 .mac_addr_set = ice_macaddr_set, 188 .mac_addr_add = ice_macaddr_add, 189 .mac_addr_remove = ice_macaddr_remove, 190 .vlan_filter_set = ice_vlan_filter_set, 191 .vlan_offload_set = ice_vlan_offload_set, 192 .reta_update = ice_rss_reta_update, 193 .reta_query = ice_rss_reta_query, 194 .rss_hash_update = ice_rss_hash_update, 195 .rss_hash_conf_get = ice_rss_hash_conf_get, 196 .promiscuous_enable = ice_promisc_enable, 197 .promiscuous_disable = ice_promisc_disable, 198 .allmulticast_enable = ice_allmulti_enable, 199 .allmulticast_disable = ice_allmulti_disable, 200 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 201 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 202 .fw_version_get = ice_fw_version_get, 203 .vlan_pvid_set = ice_vlan_pvid_set, 204 .rxq_info_get = ice_rxq_info_get, 205 .txq_info_get = ice_txq_info_get, 206 .rx_burst_mode_get = ice_rx_burst_mode_get, 207 .tx_burst_mode_get = ice_tx_burst_mode_get, 208 .get_eeprom_length = ice_get_eeprom_length, 209 .get_eeprom = ice_get_eeprom, 210 .stats_get = ice_stats_get, 211 .stats_reset = ice_stats_reset, 212 .xstats_get = ice_xstats_get, 213 .xstats_get_names = ice_xstats_get_names, 214 .xstats_reset = ice_stats_reset, 215 .filter_ctrl = ice_dev_filter_ctrl, 216 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, 217 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, 218 .tx_done_cleanup = ice_tx_done_cleanup, 219 }; 220 221 /* store statistics names and its offset in stats structure */ 222 struct ice_xstats_name_off { 223 char name[RTE_ETH_XSTATS_NAME_SIZE]; 224 unsigned int offset; 225 }; 226 227 static const struct ice_xstats_name_off ice_stats_strings[] = { 228 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 229 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 230 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 231 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 232 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 233 rx_unknown_protocol)}, 234 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 235 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 236 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 237 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 238 }; 239 240 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 241 sizeof(ice_stats_strings[0])) 242 243 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 244 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 245 tx_dropped_link_down)}, 246 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 247 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 248 illegal_bytes)}, 249 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 250 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 251 mac_local_faults)}, 252 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 253 mac_remote_faults)}, 254 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 255 rx_len_errors)}, 256 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 257 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 258 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 259 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 260 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 261 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 262 rx_size_127)}, 263 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 264 rx_size_255)}, 265 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 266 rx_size_511)}, 267 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 268 rx_size_1023)}, 269 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 270 rx_size_1522)}, 271 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 272 rx_size_big)}, 273 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 274 rx_undersize)}, 275 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 276 rx_oversize)}, 277 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 278 mac_short_pkt_dropped)}, 279 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 280 rx_fragments)}, 281 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 282 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 283 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 284 tx_size_127)}, 285 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 286 tx_size_255)}, 287 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 288 tx_size_511)}, 289 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 290 tx_size_1023)}, 291 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 292 tx_size_1522)}, 293 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 294 tx_size_big)}, 295 }; 296 297 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 298 sizeof(ice_hw_port_strings[0])) 299 300 static void 301 ice_init_controlq_parameter(struct ice_hw *hw) 302 { 303 /* fields for adminq */ 304 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 305 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 306 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 307 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 308 309 /* fields for mailboxq, DPDK used as PF host */ 310 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 311 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 312 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 313 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 314 } 315 316 static int 317 lookup_proto_xtr_type(const char *xtr_name) 318 { 319 static struct { 320 const char *name; 321 enum proto_xtr_type type; 322 } xtr_type_map[] = { 323 { "vlan", PROTO_XTR_VLAN }, 324 { "ipv4", PROTO_XTR_IPV4 }, 325 { "ipv6", PROTO_XTR_IPV6 }, 326 { "ipv6_flow", PROTO_XTR_IPV6_FLOW }, 327 { "tcp", PROTO_XTR_TCP }, 328 { "ip_offset", PROTO_XTR_IP_OFFSET }, 329 }; 330 uint32_t i; 331 332 for (i = 0; i < RTE_DIM(xtr_type_map); i++) { 333 if (strcmp(xtr_name, xtr_type_map[i].name) == 0) 334 return xtr_type_map[i].type; 335 } 336 337 return -1; 338 } 339 340 /* 341 * Parse elem, the elem could be single number/range or '(' ')' group 342 * 1) A single number elem, it's just a simple digit. e.g. 9 343 * 2) A single range elem, two digits with a '-' between. e.g. 2-6 344 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6) 345 * Within group elem, '-' used for a range separator; 346 * ',' used for a single number. 347 */ 348 static int 349 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs) 350 { 351 const char *str = input; 352 char *end = NULL; 353 uint32_t min, max; 354 uint32_t idx; 355 356 while (isblank(*str)) 357 str++; 358 359 if (!isdigit(*str) && *str != '(') 360 return -1; 361 362 /* process single number or single range of number */ 363 if (*str != '(') { 364 errno = 0; 365 idx = strtoul(str, &end, 10); 366 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 367 return -1; 368 369 while (isblank(*end)) 370 end++; 371 372 min = idx; 373 max = idx; 374 375 /* process single <number>-<number> */ 376 if (*end == '-') { 377 end++; 378 while (isblank(*end)) 379 end++; 380 if (!isdigit(*end)) 381 return -1; 382 383 errno = 0; 384 idx = strtoul(end, &end, 10); 385 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 386 return -1; 387 388 max = idx; 389 while (isblank(*end)) 390 end++; 391 } 392 393 if (*end != ':') 394 return -1; 395 396 for (idx = RTE_MIN(min, max); 397 idx <= RTE_MAX(min, max); idx++) 398 devargs->proto_xtr[idx] = xtr_type; 399 400 return 0; 401 } 402 403 /* process set within bracket */ 404 str++; 405 while (isblank(*str)) 406 str++; 407 if (*str == '\0') 408 return -1; 409 410 min = ICE_MAX_QUEUE_NUM; 411 do { 412 /* go ahead to the first digit */ 413 while (isblank(*str)) 414 str++; 415 if (!isdigit(*str)) 416 return -1; 417 418 /* get the digit value */ 419 errno = 0; 420 idx = strtoul(str, &end, 10); 421 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 422 return -1; 423 424 /* go ahead to separator '-',',' and ')' */ 425 while (isblank(*end)) 426 end++; 427 if (*end == '-') { 428 if (min == ICE_MAX_QUEUE_NUM) 429 min = idx; 430 else /* avoid continuous '-' */ 431 return -1; 432 } else if (*end == ',' || *end == ')') { 433 max = idx; 434 if (min == ICE_MAX_QUEUE_NUM) 435 min = idx; 436 437 for (idx = RTE_MIN(min, max); 438 idx <= RTE_MAX(min, max); idx++) 439 devargs->proto_xtr[idx] = xtr_type; 440 441 min = ICE_MAX_QUEUE_NUM; 442 } else { 443 return -1; 444 } 445 446 str = end + 1; 447 } while (*end != ')' && *end != '\0'); 448 449 return 0; 450 } 451 452 static int 453 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs) 454 { 455 const char *queue_start; 456 uint32_t idx; 457 int xtr_type; 458 char xtr_name[32]; 459 460 while (isblank(*queues)) 461 queues++; 462 463 if (*queues != '[') { 464 xtr_type = lookup_proto_xtr_type(queues); 465 if (xtr_type < 0) 466 return -1; 467 468 devargs->proto_xtr_dflt = xtr_type; 469 470 return 0; 471 } 472 473 queues++; 474 do { 475 while (isblank(*queues)) 476 queues++; 477 if (*queues == '\0') 478 return -1; 479 480 queue_start = queues; 481 482 /* go across a complete bracket */ 483 if (*queue_start == '(') { 484 queues += strcspn(queues, ")"); 485 if (*queues != ')') 486 return -1; 487 } 488 489 /* scan the separator ':' */ 490 queues += strcspn(queues, ":"); 491 if (*queues++ != ':') 492 return -1; 493 while (isblank(*queues)) 494 queues++; 495 496 for (idx = 0; ; idx++) { 497 if (isblank(queues[idx]) || 498 queues[idx] == ',' || 499 queues[idx] == ']' || 500 queues[idx] == '\0') 501 break; 502 503 if (idx > sizeof(xtr_name) - 2) 504 return -1; 505 506 xtr_name[idx] = queues[idx]; 507 } 508 xtr_name[idx] = '\0'; 509 xtr_type = lookup_proto_xtr_type(xtr_name); 510 if (xtr_type < 0) 511 return -1; 512 513 queues += idx; 514 515 while (isblank(*queues) || *queues == ',' || *queues == ']') 516 queues++; 517 518 if (parse_queue_set(queue_start, xtr_type, devargs) < 0) 519 return -1; 520 } while (*queues != '\0'); 521 522 return 0; 523 } 524 525 static int 526 handle_proto_xtr_arg(__rte_unused const char *key, const char *value, 527 void *extra_args) 528 { 529 struct ice_devargs *devargs = extra_args; 530 531 if (value == NULL || extra_args == NULL) 532 return -EINVAL; 533 534 if (parse_queue_proto_xtr(value, devargs) < 0) { 535 PMD_DRV_LOG(ERR, 536 "The protocol extraction parameter is wrong : '%s'", 537 value); 538 return -1; 539 } 540 541 return 0; 542 } 543 544 static void 545 ice_check_proto_xtr_support(struct ice_hw *hw) 546 { 547 #define FLX_REG(val, fld, idx) \ 548 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ 549 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) 550 static struct { 551 uint32_t rxdid; 552 uint8_t opcode; 553 uint8_t protid_0; 554 uint8_t protid_1; 555 } xtr_sets[] = { 556 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN, 557 ICE_RX_OPC_EXTRACT, 558 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O}, 559 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4, 560 ICE_RX_OPC_EXTRACT, 561 ICE_PROT_IPV4_OF_OR_S, 562 ICE_PROT_IPV4_OF_OR_S }, 563 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6, 564 ICE_RX_OPC_EXTRACT, 565 ICE_PROT_IPV6_OF_OR_S, 566 ICE_PROT_IPV6_OF_OR_S }, 567 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW, 568 ICE_RX_OPC_EXTRACT, 569 ICE_PROT_IPV6_OF_OR_S, 570 ICE_PROT_IPV6_OF_OR_S }, 571 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP, 572 ICE_RX_OPC_EXTRACT, 573 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, 574 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET, 575 ICE_RX_OPC_PROTID, 576 ICE_PROT_IPV4_OF_OR_S, 577 ICE_PROT_IPV6_OF_OR_S }, 578 }; 579 uint32_t i; 580 581 for (i = 0; i < RTE_DIM(xtr_sets); i++) { 582 uint32_t rxdid = xtr_sets[i].rxdid; 583 uint32_t v; 584 585 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) { 586 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid)); 587 588 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 && 589 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode) 590 ice_proto_xtr_hw_support[i] = true; 591 } 592 593 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) { 594 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid)); 595 596 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 && 597 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode) 598 ice_proto_xtr_hw_support[i] = true; 599 } 600 } 601 } 602 603 static int 604 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 605 uint32_t num) 606 { 607 struct pool_entry *entry; 608 609 if (!pool || !num) 610 return -EINVAL; 611 612 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 613 if (!entry) { 614 PMD_INIT_LOG(ERR, 615 "Failed to allocate memory for resource pool"); 616 return -ENOMEM; 617 } 618 619 /* queue heap initialize */ 620 pool->num_free = num; 621 pool->num_alloc = 0; 622 pool->base = base; 623 LIST_INIT(&pool->alloc_list); 624 LIST_INIT(&pool->free_list); 625 626 /* Initialize element */ 627 entry->base = 0; 628 entry->len = num; 629 630 LIST_INSERT_HEAD(&pool->free_list, entry, next); 631 return 0; 632 } 633 634 static int 635 ice_res_pool_alloc(struct ice_res_pool_info *pool, 636 uint16_t num) 637 { 638 struct pool_entry *entry, *valid_entry; 639 640 if (!pool || !num) { 641 PMD_INIT_LOG(ERR, "Invalid parameter"); 642 return -EINVAL; 643 } 644 645 if (pool->num_free < num) { 646 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 647 num, pool->num_free); 648 return -ENOMEM; 649 } 650 651 valid_entry = NULL; 652 /* Lookup in free list and find most fit one */ 653 LIST_FOREACH(entry, &pool->free_list, next) { 654 if (entry->len >= num) { 655 /* Find best one */ 656 if (entry->len == num) { 657 valid_entry = entry; 658 break; 659 } 660 if (!valid_entry || 661 valid_entry->len > entry->len) 662 valid_entry = entry; 663 } 664 } 665 666 /* Not find one to satisfy the request, return */ 667 if (!valid_entry) { 668 PMD_INIT_LOG(ERR, "No valid entry found"); 669 return -ENOMEM; 670 } 671 /** 672 * The entry have equal queue number as requested, 673 * remove it from alloc_list. 674 */ 675 if (valid_entry->len == num) { 676 LIST_REMOVE(valid_entry, next); 677 } else { 678 /** 679 * The entry have more numbers than requested, 680 * create a new entry for alloc_list and minus its 681 * queue base and number in free_list. 682 */ 683 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 684 if (!entry) { 685 PMD_INIT_LOG(ERR, 686 "Failed to allocate memory for " 687 "resource pool"); 688 return -ENOMEM; 689 } 690 entry->base = valid_entry->base; 691 entry->len = num; 692 valid_entry->base += num; 693 valid_entry->len -= num; 694 valid_entry = entry; 695 } 696 697 /* Insert it into alloc list, not sorted */ 698 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 699 700 pool->num_free -= valid_entry->len; 701 pool->num_alloc += valid_entry->len; 702 703 return valid_entry->base + pool->base; 704 } 705 706 static void 707 ice_res_pool_destroy(struct ice_res_pool_info *pool) 708 { 709 struct pool_entry *entry, *next_entry; 710 711 if (!pool) 712 return; 713 714 for (entry = LIST_FIRST(&pool->alloc_list); 715 entry && (next_entry = LIST_NEXT(entry, next), 1); 716 entry = next_entry) { 717 LIST_REMOVE(entry, next); 718 rte_free(entry); 719 } 720 721 for (entry = LIST_FIRST(&pool->free_list); 722 entry && (next_entry = LIST_NEXT(entry, next), 1); 723 entry = next_entry) { 724 LIST_REMOVE(entry, next); 725 rte_free(entry); 726 } 727 728 pool->num_free = 0; 729 pool->num_alloc = 0; 730 pool->base = 0; 731 LIST_INIT(&pool->alloc_list); 732 LIST_INIT(&pool->free_list); 733 } 734 735 static void 736 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 737 { 738 /* Set VSI LUT selection */ 739 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 740 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 741 /* Set Hash scheme */ 742 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 743 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 744 /* enable TC */ 745 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 746 } 747 748 static enum ice_status 749 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 750 struct ice_aqc_vsi_props *info, 751 uint8_t enabled_tcmap) 752 { 753 uint16_t bsf, qp_idx; 754 755 /* default tc 0 now. Multi-TC supporting need to be done later. 756 * Configure TC and queue mapping parameters, for enabled TC, 757 * allocate qpnum_per_tc queues to this traffic. 758 */ 759 if (enabled_tcmap != 0x01) { 760 PMD_INIT_LOG(ERR, "only TC0 is supported"); 761 return -ENOTSUP; 762 } 763 764 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 765 bsf = rte_bsf32(vsi->nb_qps); 766 /* Adjust the queue number to actual queues that can be applied */ 767 vsi->nb_qps = 0x1 << bsf; 768 769 qp_idx = 0; 770 /* Set tc and queue mapping with VSI */ 771 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 772 ICE_AQ_VSI_TC_Q_OFFSET_S) | 773 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 774 775 /* Associate queue number with VSI */ 776 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 777 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 778 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 779 info->valid_sections |= 780 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 781 /* Set the info.ingress_table and info.egress_table 782 * for UP translate table. Now just set it to 1:1 map by default 783 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 784 */ 785 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 786 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 787 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 788 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 789 return 0; 790 } 791 792 static int 793 ice_init_mac_address(struct rte_eth_dev *dev) 794 { 795 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 796 797 if (!rte_is_unicast_ether_addr 798 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 799 PMD_INIT_LOG(ERR, "Invalid MAC address"); 800 return -EINVAL; 801 } 802 803 rte_ether_addr_copy( 804 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 805 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 806 807 dev->data->mac_addrs = 808 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0); 809 if (!dev->data->mac_addrs) { 810 PMD_INIT_LOG(ERR, 811 "Failed to allocate memory to store mac address"); 812 return -ENOMEM; 813 } 814 /* store it to dev data */ 815 rte_ether_addr_copy( 816 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 817 &dev->data->mac_addrs[0]); 818 return 0; 819 } 820 821 /* Find out specific MAC filter */ 822 static struct ice_mac_filter * 823 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 824 { 825 struct ice_mac_filter *f; 826 827 TAILQ_FOREACH(f, &vsi->mac_list, next) { 828 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 829 return f; 830 } 831 832 return NULL; 833 } 834 835 static int 836 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 837 { 838 struct ice_fltr_list_entry *m_list_itr = NULL; 839 struct ice_mac_filter *f; 840 struct LIST_HEAD_TYPE list_head; 841 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 842 int ret = 0; 843 844 /* If it's added and configured, return */ 845 f = ice_find_mac_filter(vsi, mac_addr); 846 if (f) { 847 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 848 return 0; 849 } 850 851 INIT_LIST_HEAD(&list_head); 852 853 m_list_itr = (struct ice_fltr_list_entry *) 854 ice_malloc(hw, sizeof(*m_list_itr)); 855 if (!m_list_itr) { 856 ret = -ENOMEM; 857 goto DONE; 858 } 859 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 860 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 861 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 862 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 863 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 864 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 865 m_list_itr->fltr_info.vsi_handle = vsi->idx; 866 867 LIST_ADD(&m_list_itr->list_entry, &list_head); 868 869 /* Add the mac */ 870 ret = ice_add_mac(hw, &list_head); 871 if (ret != ICE_SUCCESS) { 872 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 873 ret = -EINVAL; 874 goto DONE; 875 } 876 /* Add the mac addr into mac list */ 877 f = rte_zmalloc(NULL, sizeof(*f), 0); 878 if (!f) { 879 PMD_DRV_LOG(ERR, "failed to allocate memory"); 880 ret = -ENOMEM; 881 goto DONE; 882 } 883 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr); 884 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 885 vsi->mac_num++; 886 887 ret = 0; 888 889 DONE: 890 rte_free(m_list_itr); 891 return ret; 892 } 893 894 static int 895 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 896 { 897 struct ice_fltr_list_entry *m_list_itr = NULL; 898 struct ice_mac_filter *f; 899 struct LIST_HEAD_TYPE list_head; 900 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 901 int ret = 0; 902 903 /* Can't find it, return an error */ 904 f = ice_find_mac_filter(vsi, mac_addr); 905 if (!f) 906 return -EINVAL; 907 908 INIT_LIST_HEAD(&list_head); 909 910 m_list_itr = (struct ice_fltr_list_entry *) 911 ice_malloc(hw, sizeof(*m_list_itr)); 912 if (!m_list_itr) { 913 ret = -ENOMEM; 914 goto DONE; 915 } 916 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 917 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 918 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 919 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 920 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 921 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 922 m_list_itr->fltr_info.vsi_handle = vsi->idx; 923 924 LIST_ADD(&m_list_itr->list_entry, &list_head); 925 926 /* remove the mac filter */ 927 ret = ice_remove_mac(hw, &list_head); 928 if (ret != ICE_SUCCESS) { 929 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 930 ret = -EINVAL; 931 goto DONE; 932 } 933 934 /* Remove the mac addr from mac list */ 935 TAILQ_REMOVE(&vsi->mac_list, f, next); 936 rte_free(f); 937 vsi->mac_num--; 938 939 ret = 0; 940 DONE: 941 rte_free(m_list_itr); 942 return ret; 943 } 944 945 /* Find out specific VLAN filter */ 946 static struct ice_vlan_filter * 947 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 948 { 949 struct ice_vlan_filter *f; 950 951 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 952 if (vlan_id == f->vlan_info.vlan_id) 953 return f; 954 } 955 956 return NULL; 957 } 958 959 static int 960 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 961 { 962 struct ice_fltr_list_entry *v_list_itr = NULL; 963 struct ice_vlan_filter *f; 964 struct LIST_HEAD_TYPE list_head; 965 struct ice_hw *hw; 966 int ret = 0; 967 968 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID) 969 return -EINVAL; 970 971 hw = ICE_VSI_TO_HW(vsi); 972 973 /* If it's added and configured, return. */ 974 f = ice_find_vlan_filter(vsi, vlan_id); 975 if (f) { 976 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 977 return 0; 978 } 979 980 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 981 return 0; 982 983 INIT_LIST_HEAD(&list_head); 984 985 v_list_itr = (struct ice_fltr_list_entry *) 986 ice_malloc(hw, sizeof(*v_list_itr)); 987 if (!v_list_itr) { 988 ret = -ENOMEM; 989 goto DONE; 990 } 991 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 992 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 993 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 994 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 995 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 996 v_list_itr->fltr_info.vsi_handle = vsi->idx; 997 998 LIST_ADD(&v_list_itr->list_entry, &list_head); 999 1000 /* Add the vlan */ 1001 ret = ice_add_vlan(hw, &list_head); 1002 if (ret != ICE_SUCCESS) { 1003 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 1004 ret = -EINVAL; 1005 goto DONE; 1006 } 1007 1008 /* Add vlan into vlan list */ 1009 f = rte_zmalloc(NULL, sizeof(*f), 0); 1010 if (!f) { 1011 PMD_DRV_LOG(ERR, "failed to allocate memory"); 1012 ret = -ENOMEM; 1013 goto DONE; 1014 } 1015 f->vlan_info.vlan_id = vlan_id; 1016 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 1017 vsi->vlan_num++; 1018 1019 ret = 0; 1020 1021 DONE: 1022 rte_free(v_list_itr); 1023 return ret; 1024 } 1025 1026 static int 1027 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 1028 { 1029 struct ice_fltr_list_entry *v_list_itr = NULL; 1030 struct ice_vlan_filter *f; 1031 struct LIST_HEAD_TYPE list_head; 1032 struct ice_hw *hw; 1033 int ret = 0; 1034 1035 /** 1036 * Vlan 0 is the generic filter for untagged packets 1037 * and can't be removed. 1038 */ 1039 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID) 1040 return -EINVAL; 1041 1042 hw = ICE_VSI_TO_HW(vsi); 1043 1044 /* Can't find it, return an error */ 1045 f = ice_find_vlan_filter(vsi, vlan_id); 1046 if (!f) 1047 return -EINVAL; 1048 1049 INIT_LIST_HEAD(&list_head); 1050 1051 v_list_itr = (struct ice_fltr_list_entry *) 1052 ice_malloc(hw, sizeof(*v_list_itr)); 1053 if (!v_list_itr) { 1054 ret = -ENOMEM; 1055 goto DONE; 1056 } 1057 1058 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 1059 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1060 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1061 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1062 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1063 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1064 1065 LIST_ADD(&v_list_itr->list_entry, &list_head); 1066 1067 /* remove the vlan filter */ 1068 ret = ice_remove_vlan(hw, &list_head); 1069 if (ret != ICE_SUCCESS) { 1070 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 1071 ret = -EINVAL; 1072 goto DONE; 1073 } 1074 1075 /* Remove the vlan id from vlan list */ 1076 TAILQ_REMOVE(&vsi->vlan_list, f, next); 1077 rte_free(f); 1078 vsi->vlan_num--; 1079 1080 ret = 0; 1081 DONE: 1082 rte_free(v_list_itr); 1083 return ret; 1084 } 1085 1086 static int 1087 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 1088 { 1089 struct ice_mac_filter *m_f; 1090 struct ice_vlan_filter *v_f; 1091 int ret = 0; 1092 1093 if (!vsi || !vsi->mac_num) 1094 return -EINVAL; 1095 1096 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 1097 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 1098 if (ret != ICE_SUCCESS) { 1099 ret = -EINVAL; 1100 goto DONE; 1101 } 1102 } 1103 1104 if (vsi->vlan_num == 0) 1105 return 0; 1106 1107 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 1108 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 1109 if (ret != ICE_SUCCESS) { 1110 ret = -EINVAL; 1111 goto DONE; 1112 } 1113 } 1114 1115 DONE: 1116 return ret; 1117 } 1118 1119 static int 1120 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 1121 { 1122 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1123 struct ice_vsi_ctx ctxt; 1124 uint8_t qinq_flags; 1125 int ret = 0; 1126 1127 /* Check if it has been already on or off */ 1128 if (vsi->info.valid_sections & 1129 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1130 if (on) { 1131 if ((vsi->info.outer_tag_flags & 1132 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == 1133 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) 1134 return 0; /* already on */ 1135 } else { 1136 if (!(vsi->info.outer_tag_flags & 1137 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) 1138 return 0; /* already off */ 1139 } 1140 } 1141 1142 if (on) 1143 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; 1144 else 1145 qinq_flags = 0; 1146 /* clear global insertion and use per packet insertion */ 1147 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); 1148 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); 1149 vsi->info.outer_tag_flags |= qinq_flags; 1150 /* use default vlan type 0x8100 */ 1151 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1152 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1153 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1154 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1155 ctxt.info.valid_sections = 1156 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1157 ctxt.vsi_num = vsi->vsi_id; 1158 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1159 if (ret) { 1160 PMD_DRV_LOG(INFO, 1161 "Update VSI failed to %s qinq stripping", 1162 on ? "enable" : "disable"); 1163 return -EINVAL; 1164 } 1165 1166 vsi->info.valid_sections |= 1167 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1168 1169 return ret; 1170 } 1171 1172 static int 1173 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 1174 { 1175 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1176 struct ice_vsi_ctx ctxt; 1177 uint8_t qinq_flags; 1178 int ret = 0; 1179 1180 /* Check if it has been already on or off */ 1181 if (vsi->info.valid_sections & 1182 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1183 if (on) { 1184 if ((vsi->info.outer_tag_flags & 1185 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 1186 ICE_AQ_VSI_OUTER_TAG_COPY) 1187 return 0; /* already on */ 1188 } else { 1189 if ((vsi->info.outer_tag_flags & 1190 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 1191 ICE_AQ_VSI_OUTER_TAG_NOTHING) 1192 return 0; /* already off */ 1193 } 1194 } 1195 1196 if (on) 1197 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; 1198 else 1199 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; 1200 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); 1201 vsi->info.outer_tag_flags |= qinq_flags; 1202 /* use default vlan type 0x8100 */ 1203 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1204 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1205 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1206 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1207 ctxt.info.valid_sections = 1208 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1209 ctxt.vsi_num = vsi->vsi_id; 1210 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1211 if (ret) { 1212 PMD_DRV_LOG(INFO, 1213 "Update VSI failed to %s qinq stripping", 1214 on ? "enable" : "disable"); 1215 return -EINVAL; 1216 } 1217 1218 vsi->info.valid_sections |= 1219 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1220 1221 return ret; 1222 } 1223 1224 static int 1225 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 1226 { 1227 int ret; 1228 1229 ret = ice_vsi_config_qinq_stripping(vsi, on); 1230 if (ret) 1231 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 1232 1233 ret = ice_vsi_config_qinq_insertion(vsi, on); 1234 if (ret) 1235 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 1236 1237 return ret; 1238 } 1239 1240 /* Enable IRQ0 */ 1241 static void 1242 ice_pf_enable_irq0(struct ice_hw *hw) 1243 { 1244 /* reset the registers */ 1245 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 1246 ICE_READ_REG(hw, PFINT_OICR); 1247 1248 #ifdef ICE_LSE_SPT 1249 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 1250 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 1251 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 1252 1253 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 1254 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 1255 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 1256 PFINT_OICR_CTL_ITR_INDX_M) | 1257 PFINT_OICR_CTL_CAUSE_ENA_M); 1258 1259 ICE_WRITE_REG(hw, PFINT_FW_CTL, 1260 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 1261 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 1262 PFINT_FW_CTL_ITR_INDX_M) | 1263 PFINT_FW_CTL_CAUSE_ENA_M); 1264 #else 1265 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 1266 #endif 1267 1268 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1269 GLINT_DYN_CTL_INTENA_M | 1270 GLINT_DYN_CTL_CLEARPBA_M | 1271 GLINT_DYN_CTL_ITR_INDX_M); 1272 1273 ice_flush(hw); 1274 } 1275 1276 /* Disable IRQ0 */ 1277 static void 1278 ice_pf_disable_irq0(struct ice_hw *hw) 1279 { 1280 /* Disable all interrupt types */ 1281 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1282 ice_flush(hw); 1283 } 1284 1285 #ifdef ICE_LSE_SPT 1286 static void 1287 ice_handle_aq_msg(struct rte_eth_dev *dev) 1288 { 1289 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1290 struct ice_ctl_q_info *cq = &hw->adminq; 1291 struct ice_rq_event_info event; 1292 uint16_t pending, opcode; 1293 int ret; 1294 1295 event.buf_len = ICE_AQ_MAX_BUF_LEN; 1296 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 1297 if (!event.msg_buf) { 1298 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 1299 return; 1300 } 1301 1302 pending = 1; 1303 while (pending) { 1304 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 1305 1306 if (ret != ICE_SUCCESS) { 1307 PMD_DRV_LOG(INFO, 1308 "Failed to read msg from AdminQ, " 1309 "adminq_err: %u", 1310 hw->adminq.sq_last_status); 1311 break; 1312 } 1313 opcode = rte_le_to_cpu_16(event.desc.opcode); 1314 1315 switch (opcode) { 1316 case ice_aqc_opc_get_link_status: 1317 ret = ice_link_update(dev, 0); 1318 if (!ret) 1319 rte_eth_dev_callback_process 1320 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1321 break; 1322 default: 1323 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1324 opcode); 1325 break; 1326 } 1327 } 1328 rte_free(event.msg_buf); 1329 } 1330 #endif 1331 1332 /** 1333 * Interrupt handler triggered by NIC for handling 1334 * specific interrupt. 1335 * 1336 * @param handle 1337 * Pointer to interrupt handle. 1338 * @param param 1339 * The address of parameter (struct rte_eth_dev *) regsitered before. 1340 * 1341 * @return 1342 * void 1343 */ 1344 static void 1345 ice_interrupt_handler(void *param) 1346 { 1347 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1348 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1349 uint32_t oicr; 1350 uint32_t reg; 1351 uint8_t pf_num; 1352 uint8_t event; 1353 uint16_t queue; 1354 int ret; 1355 #ifdef ICE_LSE_SPT 1356 uint32_t int_fw_ctl; 1357 #endif 1358 1359 /* Disable interrupt */ 1360 ice_pf_disable_irq0(hw); 1361 1362 /* read out interrupt causes */ 1363 oicr = ICE_READ_REG(hw, PFINT_OICR); 1364 #ifdef ICE_LSE_SPT 1365 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1366 #endif 1367 1368 /* No interrupt event indicated */ 1369 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1370 PMD_DRV_LOG(INFO, "No interrupt event"); 1371 goto done; 1372 } 1373 1374 #ifdef ICE_LSE_SPT 1375 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1376 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1377 ice_handle_aq_msg(dev); 1378 } 1379 #else 1380 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1381 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1382 ret = ice_link_update(dev, 0); 1383 if (!ret) 1384 rte_eth_dev_callback_process 1385 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1386 } 1387 #endif 1388 1389 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1390 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1391 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1392 if (reg & GL_MDET_TX_PQM_VALID_M) { 1393 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1394 GL_MDET_TX_PQM_PF_NUM_S; 1395 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1396 GL_MDET_TX_PQM_MAL_TYPE_S; 1397 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1398 GL_MDET_TX_PQM_QNUM_S; 1399 1400 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1401 "%d by PQM on TX queue %d PF# %d", 1402 event, queue, pf_num); 1403 } 1404 1405 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1406 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1407 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1408 GL_MDET_TX_TCLAN_PF_NUM_S; 1409 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1410 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1411 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1412 GL_MDET_TX_TCLAN_QNUM_S; 1413 1414 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1415 "%d by TCLAN on TX queue %d PF# %d", 1416 event, queue, pf_num); 1417 } 1418 } 1419 done: 1420 /* Enable interrupt */ 1421 ice_pf_enable_irq0(hw); 1422 rte_intr_ack(dev->intr_handle); 1423 } 1424 1425 static void 1426 ice_init_proto_xtr(struct rte_eth_dev *dev) 1427 { 1428 struct ice_adapter *ad = 1429 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1430 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1431 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1432 const struct proto_xtr_ol_flag *ol_flag; 1433 bool proto_xtr_enable = false; 1434 int offset; 1435 uint16_t i; 1436 1437 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0); 1438 if (unlikely(pf->proto_xtr == NULL)) { 1439 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table"); 1440 return; 1441 } 1442 1443 for (i = 0; i < pf->lan_nb_qps; i++) { 1444 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ? 1445 ad->devargs.proto_xtr[i] : 1446 ad->devargs.proto_xtr_dflt; 1447 1448 if (pf->proto_xtr[i] != PROTO_XTR_NONE) { 1449 uint8_t type = pf->proto_xtr[i]; 1450 1451 ice_proto_xtr_ol_flag_params[type].required = true; 1452 proto_xtr_enable = true; 1453 } 1454 } 1455 1456 if (likely(!proto_xtr_enable)) 1457 return; 1458 1459 ice_check_proto_xtr_support(hw); 1460 1461 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param); 1462 if (unlikely(offset == -1)) { 1463 PMD_DRV_LOG(ERR, 1464 "Protocol extraction metadata is disabled in mbuf with error %d", 1465 -rte_errno); 1466 return; 1467 } 1468 1469 PMD_DRV_LOG(DEBUG, 1470 "Protocol extraction metadata offset in mbuf is : %d", 1471 offset); 1472 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset; 1473 1474 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) { 1475 ol_flag = &ice_proto_xtr_ol_flag_params[i]; 1476 1477 if (!ol_flag->required) 1478 continue; 1479 1480 if (!ice_proto_xtr_hw_support[i]) { 1481 PMD_DRV_LOG(ERR, 1482 "Protocol extraction type %u is not supported in hardware", 1483 i); 1484 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1485 break; 1486 } 1487 1488 offset = rte_mbuf_dynflag_register(&ol_flag->param); 1489 if (unlikely(offset == -1)) { 1490 PMD_DRV_LOG(ERR, 1491 "Protocol extraction offload '%s' failed to register with error %d", 1492 ol_flag->param.name, -rte_errno); 1493 1494 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1495 break; 1496 } 1497 1498 PMD_DRV_LOG(DEBUG, 1499 "Protocol extraction offload '%s' offset in mbuf is : %d", 1500 ol_flag->param.name, offset); 1501 *ol_flag->ol_flag = 1ULL << offset; 1502 } 1503 } 1504 1505 /* Initialize SW parameters of PF */ 1506 static int 1507 ice_pf_sw_init(struct rte_eth_dev *dev) 1508 { 1509 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1510 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1511 1512 pf->lan_nb_qp_max = 1513 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1514 hw->func_caps.common_cap.num_rxq); 1515 1516 pf->lan_nb_qps = pf->lan_nb_qp_max; 1517 1518 ice_init_proto_xtr(dev); 1519 1520 if (hw->func_caps.fd_fltr_guar > 0 || 1521 hw->func_caps.fd_fltr_best_effort > 0) { 1522 pf->flags |= ICE_FLAG_FDIR; 1523 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR; 1524 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps; 1525 } else { 1526 pf->fdir_nb_qps = 0; 1527 } 1528 pf->fdir_qp_offset = 0; 1529 1530 return 0; 1531 } 1532 1533 struct ice_vsi * 1534 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1535 { 1536 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1537 struct ice_vsi *vsi = NULL; 1538 struct ice_vsi_ctx vsi_ctx; 1539 int ret; 1540 struct rte_ether_addr broadcast = { 1541 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1542 struct rte_ether_addr mac_addr; 1543 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1544 uint8_t tc_bitmap = 0x1; 1545 uint16_t cfg; 1546 1547 /* hw->num_lports = 1 in NIC mode */ 1548 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1549 if (!vsi) 1550 return NULL; 1551 1552 vsi->idx = pf->next_vsi_idx; 1553 pf->next_vsi_idx++; 1554 vsi->type = type; 1555 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1556 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1557 vsi->vlan_anti_spoof_on = 0; 1558 vsi->vlan_filter_on = 1; 1559 TAILQ_INIT(&vsi->mac_list); 1560 TAILQ_INIT(&vsi->vlan_list); 1561 1562 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ 1563 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1564 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : 1565 hw->func_caps.common_cap.rss_table_size; 1566 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1567 1568 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1569 switch (type) { 1570 case ICE_VSI_PF: 1571 vsi->nb_qps = pf->lan_nb_qps; 1572 vsi->base_queue = 1; 1573 ice_vsi_config_default_rss(&vsi_ctx.info); 1574 vsi_ctx.alloc_from_pool = true; 1575 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1576 /* switch_id is queried by get_switch_config aq, which is done 1577 * by ice_init_hw 1578 */ 1579 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1580 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1581 /* Allow all untagged or tagged packets */ 1582 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; 1583 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; 1584 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1585 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1586 1587 /* FDIR */ 1588 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID | 1589 ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1590 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1591 cfg = ICE_AQ_VSI_FD_ENABLE; 1592 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1593 vsi_ctx.info.max_fd_fltr_dedicated = 1594 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar); 1595 vsi_ctx.info.max_fd_fltr_shared = 1596 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); 1597 1598 /* Enable VLAN/UP trip */ 1599 ret = ice_vsi_config_tc_queue_mapping(vsi, 1600 &vsi_ctx.info, 1601 ICE_DEFAULT_TCMAP); 1602 if (ret) { 1603 PMD_INIT_LOG(ERR, 1604 "tc queue mapping with vsi failed, " 1605 "err = %d", 1606 ret); 1607 goto fail_mem; 1608 } 1609 1610 break; 1611 case ICE_VSI_CTRL: 1612 vsi->nb_qps = pf->fdir_nb_qps; 1613 vsi->base_queue = ICE_FDIR_QUEUE_ID; 1614 vsi_ctx.alloc_from_pool = true; 1615 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1616 1617 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1618 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1619 cfg = ICE_AQ_VSI_FD_PROG_ENABLE; 1620 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1621 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1622 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1623 ret = ice_vsi_config_tc_queue_mapping(vsi, 1624 &vsi_ctx.info, 1625 ICE_DEFAULT_TCMAP); 1626 if (ret) { 1627 PMD_INIT_LOG(ERR, 1628 "tc queue mapping with vsi failed, " 1629 "err = %d", 1630 ret); 1631 goto fail_mem; 1632 } 1633 break; 1634 default: 1635 /* for other types of VSI */ 1636 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1637 goto fail_mem; 1638 } 1639 1640 /* VF has MSIX interrupt in VF range, don't allocate here */ 1641 if (type == ICE_VSI_PF) { 1642 ret = ice_res_pool_alloc(&pf->msix_pool, 1643 RTE_MIN(vsi->nb_qps, 1644 RTE_MAX_RXTX_INTR_VEC_ID)); 1645 if (ret < 0) { 1646 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1647 vsi->vsi_id, ret); 1648 } 1649 vsi->msix_intr = ret; 1650 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1651 } else if (type == ICE_VSI_CTRL) { 1652 ret = ice_res_pool_alloc(&pf->msix_pool, 1); 1653 if (ret < 0) { 1654 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", 1655 vsi->vsi_id, ret); 1656 } 1657 vsi->msix_intr = ret; 1658 vsi->nb_msix = 1; 1659 } else { 1660 vsi->msix_intr = 0; 1661 vsi->nb_msix = 0; 1662 } 1663 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1664 if (ret != ICE_SUCCESS) { 1665 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1666 goto fail_mem; 1667 } 1668 /* store vsi information is SW structure */ 1669 vsi->vsi_id = vsi_ctx.vsi_num; 1670 vsi->info = vsi_ctx.info; 1671 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1672 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1673 1674 if (type == ICE_VSI_PF) { 1675 /* MAC configuration */ 1676 rte_ether_addr_copy((struct rte_ether_addr *) 1677 hw->port_info->mac.perm_addr, 1678 &pf->dev_addr); 1679 1680 rte_ether_addr_copy(&pf->dev_addr, &mac_addr); 1681 ret = ice_add_mac_filter(vsi, &mac_addr); 1682 if (ret != ICE_SUCCESS) 1683 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1684 1685 rte_ether_addr_copy(&broadcast, &mac_addr); 1686 ret = ice_add_mac_filter(vsi, &mac_addr); 1687 if (ret != ICE_SUCCESS) 1688 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1689 } 1690 1691 /* At the beginning, only TC0. */ 1692 /* What we need here is the maximam number of the TX queues. 1693 * Currently vsi->nb_qps means it. 1694 * Correct it if any change. 1695 */ 1696 max_txqs[0] = vsi->nb_qps; 1697 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1698 tc_bitmap, max_txqs); 1699 if (ret != ICE_SUCCESS) 1700 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1701 1702 return vsi; 1703 fail_mem: 1704 rte_free(vsi); 1705 pf->next_vsi_idx--; 1706 return NULL; 1707 } 1708 1709 static int 1710 ice_send_driver_ver(struct ice_hw *hw) 1711 { 1712 struct ice_driver_ver dv; 1713 1714 /* we don't have driver version use 0 for dummy */ 1715 dv.major_ver = 0; 1716 dv.minor_ver = 0; 1717 dv.build_ver = 0; 1718 dv.subbuild_ver = 0; 1719 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1720 1721 return ice_aq_send_driver_ver(hw, &dv, NULL); 1722 } 1723 1724 static int 1725 ice_pf_setup(struct ice_pf *pf) 1726 { 1727 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1728 struct ice_vsi *vsi; 1729 uint16_t unused; 1730 1731 /* Clear all stats counters */ 1732 pf->offset_loaded = false; 1733 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1734 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1735 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1736 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1737 1738 /* force guaranteed filter pool for PF */ 1739 ice_alloc_fd_guar_item(hw, &unused, 1740 hw->func_caps.fd_fltr_guar); 1741 /* force shared filter pool for PF */ 1742 ice_alloc_fd_shrd_item(hw, &unused, 1743 hw->func_caps.fd_fltr_best_effort); 1744 1745 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1746 if (!vsi) { 1747 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1748 return -EINVAL; 1749 } 1750 1751 pf->main_vsi = vsi; 1752 1753 return 0; 1754 } 1755 1756 /* 1757 * Extract device serial number from PCIe Configuration Space and 1758 * determine the pkg file path according to the DSN. 1759 */ 1760 static int 1761 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file) 1762 { 1763 off_t pos; 1764 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; 1765 uint32_t dsn_low, dsn_high; 1766 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); 1767 1768 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN); 1769 1770 if (pos) { 1771 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4); 1772 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8); 1773 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, 1774 "ice-%08x%08x.pkg", dsn_high, dsn_low); 1775 } else { 1776 PMD_INIT_LOG(ERR, "Failed to read device serial number\n"); 1777 goto fail_dsn; 1778 } 1779 1780 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, 1781 ICE_MAX_PKG_FILENAME_SIZE); 1782 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1783 return 0; 1784 1785 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, 1786 ICE_MAX_PKG_FILENAME_SIZE); 1787 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1788 return 0; 1789 1790 fail_dsn: 1791 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); 1792 if (!access(pkg_file, 0)) 1793 return 0; 1794 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); 1795 return 0; 1796 } 1797 1798 enum ice_pkg_type 1799 ice_load_pkg_type(struct ice_hw *hw) 1800 { 1801 enum ice_pkg_type package_type; 1802 1803 /* store the activated package type (OS default or Comms) */ 1804 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME, 1805 ICE_PKG_NAME_SIZE)) 1806 package_type = ICE_PKG_TYPE_OS_DEFAULT; 1807 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, 1808 ICE_PKG_NAME_SIZE)) 1809 package_type = ICE_PKG_TYPE_COMMS; 1810 else 1811 package_type = ICE_PKG_TYPE_UNKNOWN; 1812 1813 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s", 1814 hw->active_pkg_ver.major, hw->active_pkg_ver.minor, 1815 hw->active_pkg_ver.update, hw->active_pkg_ver.draft, 1816 hw->active_pkg_name); 1817 1818 return package_type; 1819 } 1820 1821 static int ice_load_pkg(struct rte_eth_dev *dev) 1822 { 1823 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1824 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE]; 1825 int err; 1826 uint8_t *buf; 1827 int buf_len; 1828 FILE *file; 1829 struct stat fstat; 1830 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1831 struct ice_adapter *ad = 1832 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1833 1834 ice_pkg_file_search_path(pci_dev, pkg_file); 1835 1836 file = fopen(pkg_file, "rb"); 1837 if (!file) { 1838 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); 1839 return -1; 1840 } 1841 1842 err = stat(pkg_file, &fstat); 1843 if (err) { 1844 PMD_INIT_LOG(ERR, "failed to get file stats\n"); 1845 fclose(file); 1846 return err; 1847 } 1848 1849 buf_len = fstat.st_size; 1850 buf = rte_malloc(NULL, buf_len, 0); 1851 1852 if (!buf) { 1853 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", 1854 buf_len); 1855 fclose(file); 1856 return -1; 1857 } 1858 1859 err = fread(buf, buf_len, 1, file); 1860 if (err != 1) { 1861 PMD_INIT_LOG(ERR, "failed to read package data\n"); 1862 fclose(file); 1863 err = -1; 1864 goto fail_exit; 1865 } 1866 1867 fclose(file); 1868 1869 err = ice_copy_and_init_pkg(hw, buf, buf_len); 1870 if (err) { 1871 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1872 goto fail_exit; 1873 } 1874 1875 /* store the loaded pkg type info */ 1876 ad->active_pkg_type = ice_load_pkg_type(hw); 1877 1878 err = ice_init_hw_tbls(hw); 1879 if (err) { 1880 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); 1881 goto fail_init_tbls; 1882 } 1883 1884 return 0; 1885 1886 fail_init_tbls: 1887 rte_free(hw->pkg_copy); 1888 fail_exit: 1889 rte_free(buf); 1890 return err; 1891 } 1892 1893 static void 1894 ice_base_queue_get(struct ice_pf *pf) 1895 { 1896 uint32_t reg; 1897 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1898 1899 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); 1900 if (reg & PFLAN_RX_QALLOC_VALID_M) { 1901 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; 1902 } else { 1903 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" 1904 " index"); 1905 } 1906 } 1907 1908 static int 1909 parse_bool(const char *key, const char *value, void *args) 1910 { 1911 int *i = (int *)args; 1912 char *end; 1913 int num; 1914 1915 num = strtoul(value, &end, 10); 1916 1917 if (num != 0 && num != 1) { 1918 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 1919 "value must be 0 or 1", 1920 value, key); 1921 return -1; 1922 } 1923 1924 *i = num; 1925 return 0; 1926 } 1927 1928 static int ice_parse_devargs(struct rte_eth_dev *dev) 1929 { 1930 struct ice_adapter *ad = 1931 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1932 struct rte_devargs *devargs = dev->device->devargs; 1933 struct rte_kvargs *kvlist; 1934 int ret; 1935 1936 if (devargs == NULL) 1937 return 0; 1938 1939 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args); 1940 if (kvlist == NULL) { 1941 PMD_INIT_LOG(ERR, "Invalid kvargs key\n"); 1942 return -EINVAL; 1943 } 1944 1945 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE; 1946 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE, 1947 sizeof(ad->devargs.proto_xtr)); 1948 1949 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG, 1950 &handle_proto_xtr_arg, &ad->devargs); 1951 if (ret) 1952 goto bail; 1953 1954 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, 1955 &parse_bool, &ad->devargs.safe_mode_support); 1956 if (ret) 1957 goto bail; 1958 1959 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, 1960 &parse_bool, &ad->devargs.pipe_mode_support); 1961 if (ret) 1962 goto bail; 1963 1964 bail: 1965 rte_kvargs_free(kvlist); 1966 return ret; 1967 } 1968 1969 /* Forward LLDP packets to default VSI by set switch rules */ 1970 static int 1971 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on) 1972 { 1973 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1974 struct ice_fltr_list_entry *s_list_itr = NULL; 1975 struct LIST_HEAD_TYPE list_head; 1976 int ret = 0; 1977 1978 INIT_LIST_HEAD(&list_head); 1979 1980 s_list_itr = (struct ice_fltr_list_entry *) 1981 ice_malloc(hw, sizeof(*s_list_itr)); 1982 if (!s_list_itr) 1983 return -ENOMEM; 1984 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE; 1985 s_list_itr->fltr_info.vsi_handle = vsi->idx; 1986 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype = 1987 RTE_ETHER_TYPE_LLDP; 1988 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1989 s_list_itr->fltr_info.flag = ICE_FLTR_RX; 1990 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT; 1991 LIST_ADD(&s_list_itr->list_entry, &list_head); 1992 if (on) 1993 ret = ice_add_eth_mac(hw, &list_head); 1994 else 1995 ret = ice_remove_eth_mac(hw, &list_head); 1996 1997 rte_free(s_list_itr); 1998 return ret; 1999 } 2000 2001 static enum ice_status 2002 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, 2003 uint16_t num, uint16_t desc_id, 2004 uint16_t *prof_buf, uint16_t *num_prof) 2005 { 2006 struct ice_aqc_res_elem *resp_buf; 2007 int ret; 2008 uint16_t buf_len; 2009 bool res_shared = 1; 2010 struct ice_aq_desc aq_desc; 2011 struct ice_sq_cd *cd = NULL; 2012 struct ice_aqc_get_allocd_res_desc *cmd = 2013 &aq_desc.params.get_res_desc; 2014 2015 buf_len = sizeof(*resp_buf) * num; 2016 resp_buf = ice_malloc(hw, buf_len); 2017 if (!resp_buf) 2018 return -ENOMEM; 2019 2020 ice_fill_dflt_direct_cmd_desc(&aq_desc, 2021 ice_aqc_opc_get_allocd_res_desc); 2022 2023 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) & 2024 ICE_AQC_RES_TYPE_M) | (res_shared ? 2025 ICE_AQC_RES_TYPE_FLAG_SHARED : 0)); 2026 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id); 2027 2028 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd); 2029 if (!ret) 2030 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc); 2031 else 2032 goto exit; 2033 2034 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) * 2035 (*num_prof), ICE_NONDMA_TO_NONDMA); 2036 2037 exit: 2038 rte_free(resp_buf); 2039 return ret; 2040 } 2041 static int 2042 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type) 2043 { 2044 int ret; 2045 uint16_t prof_id; 2046 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM]; 2047 uint16_t first_desc = 1; 2048 uint16_t num_prof = 0; 2049 2050 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM, 2051 first_desc, prof_buf, &num_prof); 2052 if (ret) { 2053 PMD_INIT_LOG(ERR, "Failed to get fxp resource"); 2054 return ret; 2055 } 2056 2057 for (prof_id = 0; prof_id < num_prof; prof_id++) { 2058 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]); 2059 if (ret) { 2060 PMD_INIT_LOG(ERR, "Failed to free fxp resource"); 2061 return ret; 2062 } 2063 } 2064 return 0; 2065 } 2066 2067 static int 2068 ice_reset_fxp_resource(struct ice_hw *hw) 2069 { 2070 int ret; 2071 2072 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID); 2073 if (ret) { 2074 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource"); 2075 return ret; 2076 } 2077 2078 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID); 2079 if (ret) { 2080 PMD_INIT_LOG(ERR, "Failed to clearup rss resource"); 2081 return ret; 2082 } 2083 2084 return 0; 2085 } 2086 2087 static void 2088 ice_rss_ctx_init(struct ice_pf *pf) 2089 { 2090 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx)); 2091 } 2092 2093 static uint64_t 2094 ice_get_supported_rxdid(struct ice_hw *hw) 2095 { 2096 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */ 2097 uint32_t regval; 2098 int i; 2099 2100 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1); 2101 2102 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) { 2103 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0)); 2104 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) 2105 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) 2106 supported_rxdid |= BIT(i); 2107 } 2108 return supported_rxdid; 2109 } 2110 2111 static int 2112 ice_dev_init(struct rte_eth_dev *dev) 2113 { 2114 struct rte_pci_device *pci_dev; 2115 struct rte_intr_handle *intr_handle; 2116 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2117 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2118 struct ice_adapter *ad = 2119 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2120 struct ice_vsi *vsi; 2121 int ret; 2122 2123 dev->dev_ops = &ice_eth_dev_ops; 2124 dev->rx_queue_count = ice_rx_queue_count; 2125 dev->rx_descriptor_status = ice_rx_descriptor_status; 2126 dev->tx_descriptor_status = ice_tx_descriptor_status; 2127 dev->rx_pkt_burst = ice_recv_pkts; 2128 dev->tx_pkt_burst = ice_xmit_pkts; 2129 dev->tx_pkt_prepare = ice_prep_pkts; 2130 2131 /* for secondary processes, we don't initialise any further as primary 2132 * has already done this work. 2133 */ 2134 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2135 ice_set_rx_function(dev); 2136 ice_set_tx_function(dev); 2137 return 0; 2138 } 2139 2140 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2141 2142 ice_set_default_ptype_table(dev); 2143 pci_dev = RTE_DEV_TO_PCI(dev->device); 2144 intr_handle = &pci_dev->intr_handle; 2145 2146 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2147 pf->adapter->eth_dev = dev; 2148 pf->dev_data = dev->data; 2149 hw->back = pf->adapter; 2150 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 2151 hw->vendor_id = pci_dev->id.vendor_id; 2152 hw->device_id = pci_dev->id.device_id; 2153 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2154 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 2155 hw->bus.device = pci_dev->addr.devid; 2156 hw->bus.func = pci_dev->addr.function; 2157 2158 ret = ice_parse_devargs(dev); 2159 if (ret) { 2160 PMD_INIT_LOG(ERR, "Failed to parse devargs"); 2161 return -EINVAL; 2162 } 2163 2164 ice_init_controlq_parameter(hw); 2165 2166 ret = ice_init_hw(hw); 2167 if (ret) { 2168 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 2169 return -EINVAL; 2170 } 2171 2172 ret = ice_load_pkg(dev); 2173 if (ret) { 2174 if (ad->devargs.safe_mode_support == 0) { 2175 PMD_INIT_LOG(ERR, "Failed to load the DDP package," 2176 "Use safe-mode-support=1 to enter Safe Mode"); 2177 return ret; 2178 } 2179 2180 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 2181 "Entering Safe Mode"); 2182 ad->is_safe_mode = 1; 2183 } 2184 2185 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 2186 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 2187 hw->api_maj_ver, hw->api_min_ver); 2188 2189 ice_pf_sw_init(dev); 2190 ret = ice_init_mac_address(dev); 2191 if (ret) { 2192 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 2193 goto err_init_mac; 2194 } 2195 2196 ret = ice_res_pool_init(&pf->msix_pool, 1, 2197 hw->func_caps.common_cap.num_msix_vectors - 1); 2198 if (ret) { 2199 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 2200 goto err_msix_pool_init; 2201 } 2202 2203 ret = ice_pf_setup(pf); 2204 if (ret) { 2205 PMD_INIT_LOG(ERR, "Failed to setup PF"); 2206 goto err_pf_setup; 2207 } 2208 2209 ret = ice_send_driver_ver(hw); 2210 if (ret) { 2211 PMD_INIT_LOG(ERR, "Failed to send driver version"); 2212 goto err_pf_setup; 2213 } 2214 2215 vsi = pf->main_vsi; 2216 2217 /* Disable double vlan by default */ 2218 ice_vsi_config_double_vlan(vsi, false); 2219 2220 ret = ice_aq_stop_lldp(hw, true, false, NULL); 2221 if (ret != ICE_SUCCESS) 2222 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 2223 ret = ice_init_dcb(hw, true); 2224 if (ret != ICE_SUCCESS) 2225 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n"); 2226 /* Forward LLDP packets to default VSI */ 2227 ret = ice_vsi_config_sw_lldp(vsi, true); 2228 if (ret != ICE_SUCCESS) 2229 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n"); 2230 /* register callback func to eal lib */ 2231 rte_intr_callback_register(intr_handle, 2232 ice_interrupt_handler, dev); 2233 2234 ice_pf_enable_irq0(hw); 2235 2236 /* enable uio intr after callback register */ 2237 rte_intr_enable(intr_handle); 2238 2239 /* get base queue pairs index in the device */ 2240 ice_base_queue_get(pf); 2241 2242 /* Initialize RSS context for gtpu_eh */ 2243 ice_rss_ctx_init(pf); 2244 2245 if (!ad->is_safe_mode) { 2246 ret = ice_flow_init(ad); 2247 if (ret) { 2248 PMD_INIT_LOG(ERR, "Failed to initialize flow"); 2249 return ret; 2250 } 2251 } 2252 2253 ret = ice_reset_fxp_resource(hw); 2254 if (ret) { 2255 PMD_INIT_LOG(ERR, "Failed to reset fxp resource"); 2256 return ret; 2257 } 2258 2259 pf->supported_rxdid = ice_get_supported_rxdid(hw); 2260 2261 return 0; 2262 2263 err_pf_setup: 2264 ice_res_pool_destroy(&pf->msix_pool); 2265 err_msix_pool_init: 2266 rte_free(dev->data->mac_addrs); 2267 dev->data->mac_addrs = NULL; 2268 err_init_mac: 2269 ice_sched_cleanup_all(hw); 2270 rte_free(hw->port_info); 2271 ice_shutdown_all_ctrlq(hw); 2272 rte_free(pf->proto_xtr); 2273 2274 return ret; 2275 } 2276 2277 int 2278 ice_release_vsi(struct ice_vsi *vsi) 2279 { 2280 struct ice_hw *hw; 2281 struct ice_vsi_ctx vsi_ctx; 2282 enum ice_status ret; 2283 int error = 0; 2284 2285 if (!vsi) 2286 return error; 2287 2288 hw = ICE_VSI_TO_HW(vsi); 2289 2290 ice_remove_all_mac_vlan_filters(vsi); 2291 2292 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 2293 2294 vsi_ctx.vsi_num = vsi->vsi_id; 2295 vsi_ctx.info = vsi->info; 2296 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 2297 if (ret != ICE_SUCCESS) { 2298 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 2299 error = -1; 2300 } 2301 2302 rte_free(vsi->rss_lut); 2303 rte_free(vsi->rss_key); 2304 rte_free(vsi); 2305 return error; 2306 } 2307 2308 void 2309 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 2310 { 2311 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2312 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2313 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2314 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2315 uint16_t msix_intr, i; 2316 2317 /* disable interrupt and also clear all the exist config */ 2318 for (i = 0; i < vsi->nb_qps; i++) { 2319 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2320 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2321 rte_wmb(); 2322 } 2323 2324 if (rte_intr_allow_others(intr_handle)) 2325 /* vfio-pci */ 2326 for (i = 0; i < vsi->nb_msix; i++) { 2327 msix_intr = vsi->msix_intr + i; 2328 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2329 GLINT_DYN_CTL_WB_ON_ITR_M); 2330 } 2331 else 2332 /* igb_uio */ 2333 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 2334 } 2335 2336 static int 2337 ice_dev_stop(struct rte_eth_dev *dev) 2338 { 2339 struct rte_eth_dev_data *data = dev->data; 2340 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2341 struct ice_vsi *main_vsi = pf->main_vsi; 2342 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2343 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2344 uint16_t i; 2345 2346 /* avoid stopping again */ 2347 if (pf->adapter_stopped) 2348 return 0; 2349 2350 /* stop and clear all Rx queues */ 2351 for (i = 0; i < data->nb_rx_queues; i++) 2352 ice_rx_queue_stop(dev, i); 2353 2354 /* stop and clear all Tx queues */ 2355 for (i = 0; i < data->nb_tx_queues; i++) 2356 ice_tx_queue_stop(dev, i); 2357 2358 /* disable all queue interrupts */ 2359 ice_vsi_disable_queues_intr(main_vsi); 2360 2361 if (pf->init_link_up) 2362 ice_dev_set_link_up(dev); 2363 else 2364 ice_dev_set_link_down(dev); 2365 2366 /* Clean datapath event and queue/vec mapping */ 2367 rte_intr_efd_disable(intr_handle); 2368 if (intr_handle->intr_vec) { 2369 rte_free(intr_handle->intr_vec); 2370 intr_handle->intr_vec = NULL; 2371 } 2372 2373 pf->adapter_stopped = true; 2374 dev->data->dev_started = 0; 2375 2376 return 0; 2377 } 2378 2379 static int 2380 ice_dev_close(struct rte_eth_dev *dev) 2381 { 2382 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2383 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2384 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2385 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2386 struct ice_adapter *ad = 2387 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2388 int ret; 2389 2390 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2391 return 0; 2392 2393 /* Since stop will make link down, then the link event will be 2394 * triggered, disable the irq firstly to avoid the port_infoe etc 2395 * resources deallocation causing the interrupt service thread 2396 * crash. 2397 */ 2398 ice_pf_disable_irq0(hw); 2399 2400 ret = ice_dev_stop(dev); 2401 2402 if (!ad->is_safe_mode) 2403 ice_flow_uninit(ad); 2404 2405 /* release all queue resource */ 2406 ice_free_queues(dev); 2407 2408 ice_res_pool_destroy(&pf->msix_pool); 2409 ice_release_vsi(pf->main_vsi); 2410 ice_sched_cleanup_all(hw); 2411 ice_free_hw_tbls(hw); 2412 rte_free(hw->port_info); 2413 hw->port_info = NULL; 2414 ice_shutdown_all_ctrlq(hw); 2415 rte_free(pf->proto_xtr); 2416 pf->proto_xtr = NULL; 2417 2418 /* disable uio intr before callback unregister */ 2419 rte_intr_disable(intr_handle); 2420 2421 /* unregister callback func from eal lib */ 2422 rte_intr_callback_unregister(intr_handle, 2423 ice_interrupt_handler, dev); 2424 2425 return ret; 2426 } 2427 2428 static int 2429 ice_dev_uninit(struct rte_eth_dev *dev) 2430 { 2431 ice_dev_close(dev); 2432 2433 return 0; 2434 } 2435 2436 static bool 2437 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg) 2438 { 2439 return ((cfg->hash_func >= ICE_RSS_HASH_TOEPLITZ && 2440 cfg->hash_func <= ICE_RSS_HASH_JHASH) && 2441 (cfg->hash_flds != 0 && cfg->addl_hdrs != 0)) ? 2442 true : false; 2443 } 2444 2445 static void 2446 hash_cfg_reset(struct ice_rss_hash_cfg *cfg) 2447 { 2448 cfg->hash_flds = 0; 2449 cfg->addl_hdrs = 0; 2450 cfg->hash_func = 0; 2451 } 2452 2453 static int 2454 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2455 { 2456 enum ice_status status = ICE_SUCCESS; 2457 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2458 struct ice_vsi *vsi = pf->main_vsi; 2459 2460 if (!is_hash_cfg_valid(cfg)) 2461 return -ENOENT; 2462 2463 status = ice_rem_rss_cfg(hw, vsi->idx, cfg->hash_flds, 2464 cfg->addl_hdrs); 2465 if (status && status != ICE_ERR_DOES_NOT_EXIST) { 2466 PMD_DRV_LOG(ERR, 2467 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n", 2468 vsi->idx, status); 2469 return -EBUSY; 2470 } 2471 2472 return 0; 2473 } 2474 2475 static int 2476 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2477 { 2478 enum ice_status status = ICE_SUCCESS; 2479 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2480 struct ice_vsi *vsi = pf->main_vsi; 2481 bool symm; 2482 2483 if (!is_hash_cfg_valid(cfg)) 2484 return -ENOENT; 2485 2486 symm = (cfg->hash_func == ICE_RSS_HASH_TOEPLITZ_SYMMETRIC) ? 2487 true : false; 2488 2489 status = ice_add_rss_cfg(hw, vsi->idx, cfg->hash_flds, 2490 cfg->addl_hdrs, symm); 2491 if (status) { 2492 PMD_DRV_LOG(ERR, 2493 "ice_add_rss_cfg failed for VSI:%d, error:%d\n", 2494 vsi->idx, status); 2495 return -EBUSY; 2496 } 2497 2498 return 0; 2499 } 2500 2501 static int 2502 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2503 { 2504 int ret; 2505 2506 ret = ice_hash_moveout(pf, cfg); 2507 if (ret && (ret != -ENOENT)) 2508 return ret; 2509 2510 hash_cfg_reset(cfg); 2511 2512 return 0; 2513 } 2514 2515 static int 2516 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2517 u8 ctx_idx) 2518 { 2519 int ret; 2520 2521 switch (ctx_idx) { 2522 case ICE_HASH_GTPU_CTX_EH_IP: 2523 ret = ice_hash_remove(pf, 2524 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2525 if (ret && (ret != -ENOENT)) 2526 return ret; 2527 2528 ret = ice_hash_remove(pf, 2529 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2530 if (ret && (ret != -ENOENT)) 2531 return ret; 2532 2533 ret = ice_hash_remove(pf, 2534 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2535 if (ret && (ret != -ENOENT)) 2536 return ret; 2537 2538 ret = ice_hash_remove(pf, 2539 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2540 if (ret && (ret != -ENOENT)) 2541 return ret; 2542 2543 ret = ice_hash_remove(pf, 2544 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2545 if (ret && (ret != -ENOENT)) 2546 return ret; 2547 2548 ret = ice_hash_remove(pf, 2549 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2550 if (ret && (ret != -ENOENT)) 2551 return ret; 2552 2553 ret = ice_hash_remove(pf, 2554 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2555 if (ret && (ret != -ENOENT)) 2556 return ret; 2557 2558 ret = ice_hash_remove(pf, 2559 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2560 if (ret && (ret != -ENOENT)) 2561 return ret; 2562 2563 break; 2564 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 2565 ret = ice_hash_remove(pf, 2566 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2567 if (ret && (ret != -ENOENT)) 2568 return ret; 2569 2570 ret = ice_hash_remove(pf, 2571 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2572 if (ret && (ret != -ENOENT)) 2573 return ret; 2574 2575 ret = ice_hash_moveout(pf, 2576 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2577 if (ret && (ret != -ENOENT)) 2578 return ret; 2579 2580 ret = ice_hash_moveout(pf, 2581 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2582 if (ret && (ret != -ENOENT)) 2583 return ret; 2584 2585 ret = ice_hash_moveout(pf, 2586 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2587 if (ret && (ret != -ENOENT)) 2588 return ret; 2589 2590 ret = ice_hash_moveout(pf, 2591 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2592 if (ret && (ret != -ENOENT)) 2593 return ret; 2594 2595 break; 2596 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 2597 ret = ice_hash_remove(pf, 2598 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2599 if (ret && (ret != -ENOENT)) 2600 return ret; 2601 2602 ret = ice_hash_remove(pf, 2603 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2604 if (ret && (ret != -ENOENT)) 2605 return ret; 2606 2607 ret = ice_hash_moveout(pf, 2608 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2609 if (ret && (ret != -ENOENT)) 2610 return ret; 2611 2612 ret = ice_hash_moveout(pf, 2613 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2614 if (ret && (ret != -ENOENT)) 2615 return ret; 2616 2617 ret = ice_hash_moveout(pf, 2618 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2619 if (ret && (ret != -ENOENT)) 2620 return ret; 2621 2622 ret = ice_hash_moveout(pf, 2623 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2624 if (ret && (ret != -ENOENT)) 2625 return ret; 2626 2627 break; 2628 case ICE_HASH_GTPU_CTX_UP_IP: 2629 ret = ice_hash_remove(pf, 2630 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2631 if (ret && (ret != -ENOENT)) 2632 return ret; 2633 2634 ret = ice_hash_remove(pf, 2635 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2636 if (ret && (ret != -ENOENT)) 2637 return ret; 2638 2639 ret = ice_hash_moveout(pf, 2640 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2641 if (ret && (ret != -ENOENT)) 2642 return ret; 2643 2644 ret = ice_hash_moveout(pf, 2645 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2646 if (ret && (ret != -ENOENT)) 2647 return ret; 2648 2649 ret = ice_hash_moveout(pf, 2650 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2651 if (ret && (ret != -ENOENT)) 2652 return ret; 2653 2654 break; 2655 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 2656 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 2657 ret = ice_hash_moveout(pf, 2658 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2659 if (ret && (ret != -ENOENT)) 2660 return ret; 2661 2662 ret = ice_hash_moveout(pf, 2663 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2664 if (ret && (ret != -ENOENT)) 2665 return ret; 2666 2667 ret = ice_hash_moveout(pf, 2668 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2669 if (ret && (ret != -ENOENT)) 2670 return ret; 2671 2672 break; 2673 case ICE_HASH_GTPU_CTX_DW_IP: 2674 ret = ice_hash_remove(pf, 2675 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2676 if (ret && (ret != -ENOENT)) 2677 return ret; 2678 2679 ret = ice_hash_remove(pf, 2680 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2681 if (ret && (ret != -ENOENT)) 2682 return ret; 2683 2684 ret = ice_hash_moveout(pf, 2685 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2686 if (ret && (ret != -ENOENT)) 2687 return ret; 2688 2689 ret = ice_hash_moveout(pf, 2690 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2691 if (ret && (ret != -ENOENT)) 2692 return ret; 2693 2694 ret = ice_hash_moveout(pf, 2695 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2696 if (ret && (ret != -ENOENT)) 2697 return ret; 2698 2699 break; 2700 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 2701 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 2702 ret = ice_hash_moveout(pf, 2703 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2704 if (ret && (ret != -ENOENT)) 2705 return ret; 2706 2707 ret = ice_hash_moveout(pf, 2708 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2709 if (ret && (ret != -ENOENT)) 2710 return ret; 2711 2712 ret = ice_hash_moveout(pf, 2713 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2714 if (ret && (ret != -ENOENT)) 2715 return ret; 2716 2717 break; 2718 default: 2719 break; 2720 } 2721 2722 return 0; 2723 } 2724 2725 static u8 calc_gtpu_ctx_idx(uint32_t hdr) 2726 { 2727 u8 eh_idx, ip_idx; 2728 2729 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) 2730 eh_idx = 0; 2731 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP) 2732 eh_idx = 1; 2733 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN) 2734 eh_idx = 2; 2735 else 2736 return ICE_HASH_GTPU_CTX_MAX; 2737 2738 ip_idx = 0; 2739 if (hdr & ICE_FLOW_SEG_HDR_UDP) 2740 ip_idx = 1; 2741 else if (hdr & ICE_FLOW_SEG_HDR_TCP) 2742 ip_idx = 2; 2743 2744 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)) 2745 return eh_idx * 3 + ip_idx; 2746 else 2747 return ICE_HASH_GTPU_CTX_MAX; 2748 } 2749 2750 static int 2751 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr) 2752 { 2753 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2754 2755 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2756 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4, 2757 gtpu_ctx_idx); 2758 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2759 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6, 2760 gtpu_ctx_idx); 2761 2762 return 0; 2763 } 2764 2765 static int 2766 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2767 u32 hdr, u64 fld, bool symm, u8 ctx_idx) 2768 { 2769 int ret; 2770 2771 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX) { 2772 ctx->ctx[ctx_idx].addl_hdrs = hdr; 2773 ctx->ctx[ctx_idx].hash_flds = fld; 2774 ctx->ctx[ctx_idx].hash_func = symm; 2775 } 2776 2777 switch (ctx_idx) { 2778 case ICE_HASH_GTPU_CTX_EH_IP: 2779 break; 2780 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 2781 ret = ice_hash_moveback(pf, 2782 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2783 if (ret && (ret != -ENOENT)) 2784 return ret; 2785 2786 ret = ice_hash_moveback(pf, 2787 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2788 if (ret && (ret != -ENOENT)) 2789 return ret; 2790 2791 ret = ice_hash_moveback(pf, 2792 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2793 if (ret && (ret != -ENOENT)) 2794 return ret; 2795 2796 ret = ice_hash_moveback(pf, 2797 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2798 if (ret && (ret != -ENOENT)) 2799 return ret; 2800 2801 break; 2802 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 2803 ret = ice_hash_moveback(pf, 2804 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2805 if (ret && (ret != -ENOENT)) 2806 return ret; 2807 2808 ret = ice_hash_moveback(pf, 2809 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2810 if (ret && (ret != -ENOENT)) 2811 return ret; 2812 2813 ret = ice_hash_moveback(pf, 2814 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2815 if (ret && (ret != -ENOENT)) 2816 return ret; 2817 2818 ret = ice_hash_moveback(pf, 2819 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2820 if (ret && (ret != -ENOENT)) 2821 return ret; 2822 2823 break; 2824 case ICE_HASH_GTPU_CTX_UP_IP: 2825 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 2826 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 2827 case ICE_HASH_GTPU_CTX_DW_IP: 2828 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 2829 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 2830 ret = ice_hash_moveback(pf, 2831 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2832 if (ret && (ret != -ENOENT)) 2833 return ret; 2834 2835 ret = ice_hash_moveback(pf, 2836 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2837 if (ret && (ret != -ENOENT)) 2838 return ret; 2839 2840 ret = ice_hash_moveback(pf, 2841 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2842 if (ret && (ret != -ENOENT)) 2843 return ret; 2844 2845 break; 2846 default: 2847 break; 2848 } 2849 2850 return 0; 2851 } 2852 2853 static int 2854 ice_add_rss_cfg_post(struct ice_pf *pf, uint32_t hdr, uint64_t fld, bool symm) 2855 { 2856 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2857 2858 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2859 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4, hdr, 2860 fld, symm, gtpu_ctx_idx); 2861 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2862 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6, hdr, 2863 fld, symm, gtpu_ctx_idx); 2864 2865 return 0; 2866 } 2867 2868 static void 2869 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr) 2870 { 2871 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2872 2873 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX) 2874 return; 2875 2876 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2877 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]); 2878 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2879 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]); 2880 } 2881 2882 int 2883 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 2884 uint64_t fld, uint32_t hdr) 2885 { 2886 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2887 int ret; 2888 2889 ret = ice_rem_rss_cfg(hw, vsi_id, fld, hdr); 2890 if (ret && ret != ICE_ERR_DOES_NOT_EXIST) 2891 PMD_DRV_LOG(ERR, "remove rss cfg failed\n"); 2892 2893 ice_rem_rss_cfg_post(pf, hdr); 2894 2895 return 0; 2896 } 2897 2898 int 2899 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 2900 uint64_t fld, uint32_t hdr, bool symm) 2901 { 2902 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2903 int ret; 2904 2905 ret = ice_add_rss_cfg_pre(pf, hdr); 2906 if (ret) 2907 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n"); 2908 2909 ret = ice_add_rss_cfg(hw, vsi_id, fld, hdr, symm); 2910 if (ret) 2911 PMD_DRV_LOG(ERR, "add rss cfg failed\n"); 2912 2913 ret = ice_add_rss_cfg_post(pf, hdr, fld, symm); 2914 if (ret) 2915 PMD_DRV_LOG(ERR, "add rss cfg post failed\n"); 2916 2917 return 0; 2918 } 2919 2920 static void 2921 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf) 2922 { 2923 struct ice_vsi *vsi = pf->main_vsi; 2924 int ret; 2925 2926 /* Configure RSS for IPv4 with src/dst addr as input set */ 2927 if (rss_hf & ETH_RSS_IPV4) { 2928 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 2929 ICE_FLOW_SEG_HDR_IPV4 | 2930 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2931 if (ret) 2932 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", 2933 __func__, ret); 2934 } 2935 2936 /* Configure RSS for IPv6 with src/dst addr as input set */ 2937 if (rss_hf & ETH_RSS_IPV6) { 2938 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 2939 ICE_FLOW_SEG_HDR_IPV6 | 2940 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2941 if (ret) 2942 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", 2943 __func__, ret); 2944 } 2945 2946 /* Configure RSS for udp4 with src/dst addr and port as input set */ 2947 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 2948 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4, 2949 ICE_FLOW_SEG_HDR_UDP | 2950 ICE_FLOW_SEG_HDR_IPV4 | 2951 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2952 if (ret) 2953 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", 2954 __func__, ret); 2955 } 2956 2957 /* Configure RSS for udp6 with src/dst addr and port as input set */ 2958 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 2959 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6, 2960 ICE_FLOW_SEG_HDR_UDP | 2961 ICE_FLOW_SEG_HDR_IPV6 | 2962 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2963 if (ret) 2964 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", 2965 __func__, ret); 2966 } 2967 2968 /* Configure RSS for tcp4 with src/dst addr and port as input set */ 2969 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 2970 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4, 2971 ICE_FLOW_SEG_HDR_TCP | 2972 ICE_FLOW_SEG_HDR_IPV4 | 2973 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2974 if (ret) 2975 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", 2976 __func__, ret); 2977 } 2978 2979 /* Configure RSS for tcp6 with src/dst addr and port as input set */ 2980 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 2981 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6, 2982 ICE_FLOW_SEG_HDR_TCP | 2983 ICE_FLOW_SEG_HDR_IPV6 | 2984 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2985 if (ret) 2986 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", 2987 __func__, ret); 2988 } 2989 2990 /* Configure RSS for sctp4 with src/dst addr and port as input set */ 2991 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) { 2992 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 2993 ICE_FLOW_SEG_HDR_SCTP | 2994 ICE_FLOW_SEG_HDR_IPV4 | 2995 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 2996 if (ret) 2997 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 2998 __func__, ret); 2999 } 3000 3001 /* Configure RSS for sctp6 with src/dst addr and port as input set */ 3002 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) { 3003 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 3004 ICE_FLOW_SEG_HDR_SCTP | 3005 ICE_FLOW_SEG_HDR_IPV6 | 3006 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3007 if (ret) 3008 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 3009 __func__, ret); 3010 } 3011 3012 if (rss_hf & ETH_RSS_IPV4) { 3013 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 3014 ICE_FLOW_SEG_HDR_GTPU_IP | 3015 ICE_FLOW_SEG_HDR_IPV4 | 3016 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3017 if (ret) 3018 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d", 3019 __func__, ret); 3020 3021 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 3022 ICE_FLOW_SEG_HDR_GTPU_EH | 3023 ICE_FLOW_SEG_HDR_IPV4 | 3024 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3025 if (ret) 3026 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d", 3027 __func__, ret); 3028 3029 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4, 3030 ICE_FLOW_SEG_HDR_PPPOE | 3031 ICE_FLOW_SEG_HDR_IPV4 | 3032 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3033 if (ret) 3034 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d", 3035 __func__, ret); 3036 } 3037 3038 if (rss_hf & ETH_RSS_IPV6) { 3039 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 3040 ICE_FLOW_SEG_HDR_GTPU_IP | 3041 ICE_FLOW_SEG_HDR_IPV6 | 3042 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3043 if (ret) 3044 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d", 3045 __func__, ret); 3046 3047 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 3048 ICE_FLOW_SEG_HDR_GTPU_EH | 3049 ICE_FLOW_SEG_HDR_IPV6 | 3050 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3051 if (ret) 3052 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d", 3053 __func__, ret); 3054 3055 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6, 3056 ICE_FLOW_SEG_HDR_PPPOE | 3057 ICE_FLOW_SEG_HDR_IPV6 | 3058 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3059 if (ret) 3060 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d", 3061 __func__, ret); 3062 } 3063 3064 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 3065 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4, 3066 ICE_FLOW_SEG_HDR_GTPU_IP | 3067 ICE_FLOW_SEG_HDR_UDP | 3068 ICE_FLOW_SEG_HDR_IPV4 | 3069 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3070 if (ret) 3071 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d", 3072 __func__, ret); 3073 3074 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4, 3075 ICE_FLOW_SEG_HDR_GTPU_EH | 3076 ICE_FLOW_SEG_HDR_UDP | 3077 ICE_FLOW_SEG_HDR_IPV4 | 3078 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3079 if (ret) 3080 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d", 3081 __func__, ret); 3082 3083 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4, 3084 ICE_FLOW_SEG_HDR_PPPOE | 3085 ICE_FLOW_SEG_HDR_UDP | 3086 ICE_FLOW_SEG_HDR_IPV4 | 3087 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3088 if (ret) 3089 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d", 3090 __func__, ret); 3091 } 3092 3093 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 3094 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6, 3095 ICE_FLOW_SEG_HDR_GTPU_IP | 3096 ICE_FLOW_SEG_HDR_UDP | 3097 ICE_FLOW_SEG_HDR_IPV6 | 3098 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3099 if (ret) 3100 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d", 3101 __func__, ret); 3102 3103 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6, 3104 ICE_FLOW_SEG_HDR_GTPU_EH | 3105 ICE_FLOW_SEG_HDR_UDP | 3106 ICE_FLOW_SEG_HDR_IPV6 | 3107 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3108 if (ret) 3109 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d", 3110 __func__, ret); 3111 3112 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6, 3113 ICE_FLOW_SEG_HDR_PPPOE | 3114 ICE_FLOW_SEG_HDR_UDP | 3115 ICE_FLOW_SEG_HDR_IPV6 | 3116 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3117 if (ret) 3118 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d", 3119 __func__, ret); 3120 } 3121 3122 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 3123 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4, 3124 ICE_FLOW_SEG_HDR_GTPU_IP | 3125 ICE_FLOW_SEG_HDR_TCP | 3126 ICE_FLOW_SEG_HDR_IPV4 | 3127 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3128 if (ret) 3129 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d", 3130 __func__, ret); 3131 3132 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4, 3133 ICE_FLOW_SEG_HDR_GTPU_EH | 3134 ICE_FLOW_SEG_HDR_TCP | 3135 ICE_FLOW_SEG_HDR_IPV4 | 3136 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3137 if (ret) 3138 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d", 3139 __func__, ret); 3140 3141 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4, 3142 ICE_FLOW_SEG_HDR_PPPOE | 3143 ICE_FLOW_SEG_HDR_TCP | 3144 ICE_FLOW_SEG_HDR_IPV4 | 3145 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3146 if (ret) 3147 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d", 3148 __func__, ret); 3149 } 3150 3151 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 3152 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6, 3153 ICE_FLOW_SEG_HDR_GTPU_IP | 3154 ICE_FLOW_SEG_HDR_TCP | 3155 ICE_FLOW_SEG_HDR_IPV6 | 3156 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3157 if (ret) 3158 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d", 3159 __func__, ret); 3160 3161 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6, 3162 ICE_FLOW_SEG_HDR_GTPU_EH | 3163 ICE_FLOW_SEG_HDR_TCP | 3164 ICE_FLOW_SEG_HDR_IPV6 | 3165 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3166 if (ret) 3167 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d", 3168 __func__, ret); 3169 3170 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6, 3171 ICE_FLOW_SEG_HDR_PPPOE | 3172 ICE_FLOW_SEG_HDR_TCP | 3173 ICE_FLOW_SEG_HDR_IPV6 | 3174 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3175 if (ret) 3176 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d", 3177 __func__, ret); 3178 } 3179 3180 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) { 3181 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4, 3182 ICE_FLOW_SEG_HDR_GTPU_IP | 3183 ICE_FLOW_SEG_HDR_SCTP | 3184 ICE_FLOW_SEG_HDR_IPV4 | 3185 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3186 if (ret) 3187 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d", 3188 __func__, ret); 3189 3190 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4, 3191 ICE_FLOW_SEG_HDR_GTPU_EH | 3192 ICE_FLOW_SEG_HDR_SCTP | 3193 ICE_FLOW_SEG_HDR_IPV4 | 3194 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3195 if (ret) 3196 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d", 3197 __func__, ret); 3198 } 3199 3200 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) { 3201 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6, 3202 ICE_FLOW_SEG_HDR_GTPU_IP | 3203 ICE_FLOW_SEG_HDR_SCTP | 3204 ICE_FLOW_SEG_HDR_IPV6 | 3205 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3206 if (ret) 3207 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d", 3208 __func__, ret); 3209 3210 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6, 3211 ICE_FLOW_SEG_HDR_GTPU_EH | 3212 ICE_FLOW_SEG_HDR_SCTP | 3213 ICE_FLOW_SEG_HDR_IPV6 | 3214 ICE_FLOW_SEG_HDR_IPV_OTHER, 0); 3215 if (ret) 3216 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d", 3217 __func__, ret); 3218 } 3219 } 3220 3221 static int ice_init_rss(struct ice_pf *pf) 3222 { 3223 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3224 struct ice_vsi *vsi = pf->main_vsi; 3225 struct rte_eth_dev *dev = pf->adapter->eth_dev; 3226 struct rte_eth_rss_conf *rss_conf; 3227 struct ice_aqc_get_set_rss_keys key; 3228 uint16_t i, nb_q; 3229 int ret = 0; 3230 bool is_safe_mode = pf->adapter->is_safe_mode; 3231 uint32_t reg; 3232 3233 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 3234 nb_q = dev->data->nb_rx_queues; 3235 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 3236 vsi->rss_lut_size = pf->hash_lut_size; 3237 3238 if (is_safe_mode) { 3239 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 3240 return 0; 3241 } 3242 3243 if (!vsi->rss_key) { 3244 vsi->rss_key = rte_zmalloc(NULL, 3245 vsi->rss_key_size, 0); 3246 if (vsi->rss_key == NULL) { 3247 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3248 return -ENOMEM; 3249 } 3250 } 3251 if (!vsi->rss_lut) { 3252 vsi->rss_lut = rte_zmalloc(NULL, 3253 vsi->rss_lut_size, 0); 3254 if (vsi->rss_lut == NULL) { 3255 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3256 rte_free(vsi->rss_key); 3257 vsi->rss_key = NULL; 3258 return -ENOMEM; 3259 } 3260 } 3261 /* configure RSS key */ 3262 if (!rss_conf->rss_key) { 3263 /* Calculate the default hash key */ 3264 for (i = 0; i <= vsi->rss_key_size; i++) 3265 vsi->rss_key[i] = (uint8_t)rte_rand(); 3266 } else { 3267 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 3268 RTE_MIN(rss_conf->rss_key_len, 3269 vsi->rss_key_size)); 3270 } 3271 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 3272 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 3273 if (ret) 3274 goto out; 3275 3276 /* init RSS LUT table */ 3277 for (i = 0; i < vsi->rss_lut_size; i++) 3278 vsi->rss_lut[i] = i % nb_q; 3279 3280 ret = ice_aq_set_rss_lut(hw, vsi->idx, 3281 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, 3282 vsi->rss_lut, vsi->rss_lut_size); 3283 if (ret) 3284 goto out; 3285 3286 /* Enable registers for symmetric_toeplitz function. */ 3287 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id)); 3288 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) | 3289 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S); 3290 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg); 3291 3292 /* RSS hash configuration */ 3293 ice_rss_hash_set(pf, rss_conf->rss_hf); 3294 3295 return 0; 3296 out: 3297 rte_free(vsi->rss_key); 3298 vsi->rss_key = NULL; 3299 rte_free(vsi->rss_lut); 3300 vsi->rss_lut = NULL; 3301 return -EINVAL; 3302 } 3303 3304 static int 3305 ice_dev_configure(struct rte_eth_dev *dev) 3306 { 3307 struct ice_adapter *ad = 3308 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 3309 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3310 int ret; 3311 3312 /* Initialize to TRUE. If any of Rx queues doesn't meet the 3313 * bulk allocation or vector Rx preconditions we will reset it. 3314 */ 3315 ad->rx_bulk_alloc_allowed = true; 3316 ad->tx_simple_allowed = true; 3317 3318 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 3319 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 3320 3321 ret = ice_init_rss(pf); 3322 if (ret) { 3323 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 3324 return ret; 3325 } 3326 3327 return 0; 3328 } 3329 3330 static void 3331 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 3332 int base_queue, int nb_queue) 3333 { 3334 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3335 uint32_t val, val_tx; 3336 int i; 3337 3338 for (i = 0; i < nb_queue; i++) { 3339 /*do actual bind*/ 3340 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 3341 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 3342 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 3343 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 3344 3345 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 3346 base_queue + i, msix_vect); 3347 /* set ITR0 value */ 3348 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); 3349 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 3350 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 3351 } 3352 } 3353 3354 void 3355 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 3356 { 3357 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 3358 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3359 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3360 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3361 uint16_t msix_vect = vsi->msix_intr; 3362 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 3363 uint16_t queue_idx = 0; 3364 int record = 0; 3365 int i; 3366 3367 /* clear Rx/Tx queue interrupt */ 3368 for (i = 0; i < vsi->nb_used_qps; i++) { 3369 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 3370 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 3371 } 3372 3373 /* PF bind interrupt */ 3374 if (rte_intr_dp_is_en(intr_handle)) { 3375 queue_idx = 0; 3376 record = 1; 3377 } 3378 3379 for (i = 0; i < vsi->nb_used_qps; i++) { 3380 if (nb_msix <= 1) { 3381 if (!rte_intr_allow_others(intr_handle)) 3382 msix_vect = ICE_MISC_VEC_ID; 3383 3384 /* uio mapping all queue to one msix_vect */ 3385 __vsi_queues_bind_intr(vsi, msix_vect, 3386 vsi->base_queue + i, 3387 vsi->nb_used_qps - i); 3388 3389 for (; !!record && i < vsi->nb_used_qps; i++) 3390 intr_handle->intr_vec[queue_idx + i] = 3391 msix_vect; 3392 break; 3393 } 3394 3395 /* vfio 1:1 queue/msix_vect mapping */ 3396 __vsi_queues_bind_intr(vsi, msix_vect, 3397 vsi->base_queue + i, 1); 3398 3399 if (!!record) 3400 intr_handle->intr_vec[queue_idx + i] = msix_vect; 3401 3402 msix_vect++; 3403 nb_msix--; 3404 } 3405 } 3406 3407 void 3408 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 3409 { 3410 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 3411 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3412 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3413 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3414 uint16_t msix_intr, i; 3415 3416 if (rte_intr_allow_others(intr_handle)) 3417 for (i = 0; i < vsi->nb_used_qps; i++) { 3418 msix_intr = vsi->msix_intr + i; 3419 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 3420 GLINT_DYN_CTL_INTENA_M | 3421 GLINT_DYN_CTL_CLEARPBA_M | 3422 GLINT_DYN_CTL_ITR_INDX_M | 3423 GLINT_DYN_CTL_WB_ON_ITR_M); 3424 } 3425 else 3426 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 3427 GLINT_DYN_CTL_INTENA_M | 3428 GLINT_DYN_CTL_CLEARPBA_M | 3429 GLINT_DYN_CTL_ITR_INDX_M | 3430 GLINT_DYN_CTL_WB_ON_ITR_M); 3431 } 3432 3433 static int 3434 ice_rxq_intr_setup(struct rte_eth_dev *dev) 3435 { 3436 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3437 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3438 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3439 struct ice_vsi *vsi = pf->main_vsi; 3440 uint32_t intr_vector = 0; 3441 3442 rte_intr_disable(intr_handle); 3443 3444 /* check and configure queue intr-vector mapping */ 3445 if ((rte_intr_cap_multiple(intr_handle) || 3446 !RTE_ETH_DEV_SRIOV(dev).active) && 3447 dev->data->dev_conf.intr_conf.rxq != 0) { 3448 intr_vector = dev->data->nb_rx_queues; 3449 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 3450 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 3451 ICE_MAX_INTR_QUEUE_NUM); 3452 return -ENOTSUP; 3453 } 3454 if (rte_intr_efd_enable(intr_handle, intr_vector)) 3455 return -1; 3456 } 3457 3458 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 3459 intr_handle->intr_vec = 3460 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 3461 0); 3462 if (!intr_handle->intr_vec) { 3463 PMD_DRV_LOG(ERR, 3464 "Failed to allocate %d rx_queues intr_vec", 3465 dev->data->nb_rx_queues); 3466 return -ENOMEM; 3467 } 3468 } 3469 3470 /* Map queues with MSIX interrupt */ 3471 vsi->nb_used_qps = dev->data->nb_rx_queues; 3472 ice_vsi_queues_bind_intr(vsi); 3473 3474 /* Enable interrupts for all the queues */ 3475 ice_vsi_enable_queues_intr(vsi); 3476 3477 rte_intr_enable(intr_handle); 3478 3479 return 0; 3480 } 3481 3482 static void 3483 ice_get_init_link_status(struct rte_eth_dev *dev) 3484 { 3485 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3486 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3487 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3488 struct ice_link_status link_status; 3489 int ret; 3490 3491 ret = ice_aq_get_link_info(hw->port_info, enable_lse, 3492 &link_status, NULL); 3493 if (ret != ICE_SUCCESS) { 3494 PMD_DRV_LOG(ERR, "Failed to get link info"); 3495 pf->init_link_up = false; 3496 return; 3497 } 3498 3499 if (link_status.link_info & ICE_AQ_LINK_UP) 3500 pf->init_link_up = true; 3501 } 3502 3503 static int 3504 ice_dev_start(struct rte_eth_dev *dev) 3505 { 3506 struct rte_eth_dev_data *data = dev->data; 3507 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3508 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3509 struct ice_vsi *vsi = pf->main_vsi; 3510 uint16_t nb_rxq = 0; 3511 uint16_t nb_txq, i; 3512 uint16_t max_frame_size; 3513 int mask, ret; 3514 3515 /* program Tx queues' context in hardware */ 3516 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 3517 ret = ice_tx_queue_start(dev, nb_txq); 3518 if (ret) { 3519 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 3520 goto tx_err; 3521 } 3522 } 3523 3524 /* program Rx queues' context in hardware*/ 3525 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 3526 ret = ice_rx_queue_start(dev, nb_rxq); 3527 if (ret) { 3528 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 3529 goto rx_err; 3530 } 3531 } 3532 3533 ice_set_rx_function(dev); 3534 ice_set_tx_function(dev); 3535 3536 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 3537 ETH_VLAN_EXTEND_MASK; 3538 ret = ice_vlan_offload_set(dev, mask); 3539 if (ret) { 3540 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 3541 goto rx_err; 3542 } 3543 3544 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 3545 if (ice_rxq_intr_setup(dev)) 3546 return -EIO; 3547 3548 /* Enable receiving broadcast packets and transmitting packets */ 3549 ret = ice_set_vsi_promisc(hw, vsi->idx, 3550 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 3551 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 3552 0); 3553 if (ret != ICE_SUCCESS) 3554 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 3555 3556 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 3557 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 3558 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 3559 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 3560 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 3561 ICE_AQ_LINK_EVENT_AN_COMPLETED | 3562 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 3563 NULL); 3564 if (ret != ICE_SUCCESS) 3565 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 3566 3567 ice_get_init_link_status(dev); 3568 3569 ice_dev_set_link_up(dev); 3570 3571 /* Call get_link_info aq commond to enable/disable LSE */ 3572 ice_link_update(dev, 0); 3573 3574 pf->adapter_stopped = false; 3575 3576 /* Set the max frame size to default value*/ 3577 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ? 3578 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len : 3579 ICE_FRAME_SIZE_MAX; 3580 3581 /* Set the max frame size to HW*/ 3582 ice_aq_set_mac_cfg(hw, max_frame_size, NULL); 3583 3584 return 0; 3585 3586 /* stop the started queues if failed to start all queues */ 3587 rx_err: 3588 for (i = 0; i < nb_rxq; i++) 3589 ice_rx_queue_stop(dev, i); 3590 tx_err: 3591 for (i = 0; i < nb_txq; i++) 3592 ice_tx_queue_stop(dev, i); 3593 3594 return -EIO; 3595 } 3596 3597 static int 3598 ice_dev_reset(struct rte_eth_dev *dev) 3599 { 3600 int ret; 3601 3602 if (dev->data->sriov.active) 3603 return -ENOTSUP; 3604 3605 ret = ice_dev_uninit(dev); 3606 if (ret) { 3607 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 3608 return -ENXIO; 3609 } 3610 3611 ret = ice_dev_init(dev); 3612 if (ret) { 3613 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 3614 return -ENXIO; 3615 } 3616 3617 return 0; 3618 } 3619 3620 static int 3621 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3622 { 3623 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3624 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3625 struct ice_vsi *vsi = pf->main_vsi; 3626 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 3627 bool is_safe_mode = pf->adapter->is_safe_mode; 3628 u64 phy_type_low; 3629 u64 phy_type_high; 3630 3631 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 3632 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 3633 dev_info->max_rx_queues = vsi->nb_qps; 3634 dev_info->max_tx_queues = vsi->nb_qps; 3635 dev_info->max_mac_addrs = vsi->max_macaddrs; 3636 dev_info->max_vfs = pci_dev->max_vfs; 3637 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 3638 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3639 3640 dev_info->rx_offload_capa = 3641 DEV_RX_OFFLOAD_VLAN_STRIP | 3642 DEV_RX_OFFLOAD_JUMBO_FRAME | 3643 DEV_RX_OFFLOAD_KEEP_CRC | 3644 DEV_RX_OFFLOAD_SCATTER | 3645 DEV_RX_OFFLOAD_VLAN_FILTER; 3646 dev_info->tx_offload_capa = 3647 DEV_TX_OFFLOAD_VLAN_INSERT | 3648 DEV_TX_OFFLOAD_TCP_TSO | 3649 DEV_TX_OFFLOAD_MULTI_SEGS | 3650 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3651 dev_info->flow_type_rss_offloads = 0; 3652 3653 if (!is_safe_mode) { 3654 dev_info->rx_offload_capa |= 3655 DEV_RX_OFFLOAD_IPV4_CKSUM | 3656 DEV_RX_OFFLOAD_UDP_CKSUM | 3657 DEV_RX_OFFLOAD_TCP_CKSUM | 3658 DEV_RX_OFFLOAD_QINQ_STRIP | 3659 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3660 DEV_RX_OFFLOAD_VLAN_EXTEND | 3661 DEV_RX_OFFLOAD_RSS_HASH; 3662 dev_info->tx_offload_capa |= 3663 DEV_TX_OFFLOAD_QINQ_INSERT | 3664 DEV_TX_OFFLOAD_IPV4_CKSUM | 3665 DEV_TX_OFFLOAD_UDP_CKSUM | 3666 DEV_TX_OFFLOAD_TCP_CKSUM | 3667 DEV_TX_OFFLOAD_SCTP_CKSUM | 3668 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3669 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 3670 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 3671 } 3672 3673 dev_info->rx_queue_offload_capa = 0; 3674 dev_info->tx_queue_offload_capa = 0; 3675 3676 dev_info->reta_size = pf->hash_lut_size; 3677 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 3678 3679 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3680 .rx_thresh = { 3681 .pthresh = ICE_DEFAULT_RX_PTHRESH, 3682 .hthresh = ICE_DEFAULT_RX_HTHRESH, 3683 .wthresh = ICE_DEFAULT_RX_WTHRESH, 3684 }, 3685 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 3686 .rx_drop_en = 0, 3687 .offloads = 0, 3688 }; 3689 3690 dev_info->default_txconf = (struct rte_eth_txconf) { 3691 .tx_thresh = { 3692 .pthresh = ICE_DEFAULT_TX_PTHRESH, 3693 .hthresh = ICE_DEFAULT_TX_HTHRESH, 3694 .wthresh = ICE_DEFAULT_TX_WTHRESH, 3695 }, 3696 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 3697 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 3698 .offloads = 0, 3699 }; 3700 3701 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3702 .nb_max = ICE_MAX_RING_DESC, 3703 .nb_min = ICE_MIN_RING_DESC, 3704 .nb_align = ICE_ALIGN_RING_DESC, 3705 }; 3706 3707 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3708 .nb_max = ICE_MAX_RING_DESC, 3709 .nb_min = ICE_MIN_RING_DESC, 3710 .nb_align = ICE_ALIGN_RING_DESC, 3711 }; 3712 3713 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3714 ETH_LINK_SPEED_100M | 3715 ETH_LINK_SPEED_1G | 3716 ETH_LINK_SPEED_2_5G | 3717 ETH_LINK_SPEED_5G | 3718 ETH_LINK_SPEED_10G | 3719 ETH_LINK_SPEED_20G | 3720 ETH_LINK_SPEED_25G; 3721 3722 phy_type_low = hw->port_info->phy.phy_type_low; 3723 phy_type_high = hw->port_info->phy.phy_type_high; 3724 3725 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 3726 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 3727 3728 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 3729 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 3730 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 3731 3732 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 3733 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 3734 3735 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 3736 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 3737 dev_info->default_rxportconf.nb_queues = 1; 3738 dev_info->default_txportconf.nb_queues = 1; 3739 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 3740 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 3741 3742 return 0; 3743 } 3744 3745 static inline int 3746 ice_atomic_read_link_status(struct rte_eth_dev *dev, 3747 struct rte_eth_link *link) 3748 { 3749 struct rte_eth_link *dst = link; 3750 struct rte_eth_link *src = &dev->data->dev_link; 3751 3752 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3753 *(uint64_t *)src) == 0) 3754 return -1; 3755 3756 return 0; 3757 } 3758 3759 static inline int 3760 ice_atomic_write_link_status(struct rte_eth_dev *dev, 3761 struct rte_eth_link *link) 3762 { 3763 struct rte_eth_link *dst = &dev->data->dev_link; 3764 struct rte_eth_link *src = link; 3765 3766 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3767 *(uint64_t *)src) == 0) 3768 return -1; 3769 3770 return 0; 3771 } 3772 3773 static int 3774 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 3775 { 3776 #define CHECK_INTERVAL 100 /* 100ms */ 3777 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 3778 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3779 struct ice_link_status link_status; 3780 struct rte_eth_link link, old; 3781 int status; 3782 unsigned int rep_cnt = MAX_REPEAT_TIME; 3783 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3784 3785 memset(&link, 0, sizeof(link)); 3786 memset(&old, 0, sizeof(old)); 3787 memset(&link_status, 0, sizeof(link_status)); 3788 ice_atomic_read_link_status(dev, &old); 3789 3790 do { 3791 /* Get link status information from hardware */ 3792 status = ice_aq_get_link_info(hw->port_info, enable_lse, 3793 &link_status, NULL); 3794 if (status != ICE_SUCCESS) { 3795 link.link_speed = ETH_SPEED_NUM_100M; 3796 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3797 PMD_DRV_LOG(ERR, "Failed to get link info"); 3798 goto out; 3799 } 3800 3801 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 3802 if (!wait_to_complete || link.link_status) 3803 break; 3804 3805 rte_delay_ms(CHECK_INTERVAL); 3806 } while (--rep_cnt); 3807 3808 if (!link.link_status) 3809 goto out; 3810 3811 /* Full-duplex operation at all supported speeds */ 3812 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3813 3814 /* Parse the link status */ 3815 switch (link_status.link_speed) { 3816 case ICE_AQ_LINK_SPEED_10MB: 3817 link.link_speed = ETH_SPEED_NUM_10M; 3818 break; 3819 case ICE_AQ_LINK_SPEED_100MB: 3820 link.link_speed = ETH_SPEED_NUM_100M; 3821 break; 3822 case ICE_AQ_LINK_SPEED_1000MB: 3823 link.link_speed = ETH_SPEED_NUM_1G; 3824 break; 3825 case ICE_AQ_LINK_SPEED_2500MB: 3826 link.link_speed = ETH_SPEED_NUM_2_5G; 3827 break; 3828 case ICE_AQ_LINK_SPEED_5GB: 3829 link.link_speed = ETH_SPEED_NUM_5G; 3830 break; 3831 case ICE_AQ_LINK_SPEED_10GB: 3832 link.link_speed = ETH_SPEED_NUM_10G; 3833 break; 3834 case ICE_AQ_LINK_SPEED_20GB: 3835 link.link_speed = ETH_SPEED_NUM_20G; 3836 break; 3837 case ICE_AQ_LINK_SPEED_25GB: 3838 link.link_speed = ETH_SPEED_NUM_25G; 3839 break; 3840 case ICE_AQ_LINK_SPEED_40GB: 3841 link.link_speed = ETH_SPEED_NUM_40G; 3842 break; 3843 case ICE_AQ_LINK_SPEED_50GB: 3844 link.link_speed = ETH_SPEED_NUM_50G; 3845 break; 3846 case ICE_AQ_LINK_SPEED_100GB: 3847 link.link_speed = ETH_SPEED_NUM_100G; 3848 break; 3849 case ICE_AQ_LINK_SPEED_UNKNOWN: 3850 PMD_DRV_LOG(ERR, "Unknown link speed"); 3851 link.link_speed = ETH_SPEED_NUM_UNKNOWN; 3852 break; 3853 default: 3854 PMD_DRV_LOG(ERR, "None link speed"); 3855 link.link_speed = ETH_SPEED_NUM_NONE; 3856 break; 3857 } 3858 3859 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 3860 ETH_LINK_SPEED_FIXED); 3861 3862 out: 3863 ice_atomic_write_link_status(dev, &link); 3864 if (link.link_status == old.link_status) 3865 return -1; 3866 3867 return 0; 3868 } 3869 3870 /* Force the physical link state by getting the current PHY capabilities from 3871 * hardware and setting the PHY config based on the determined capabilities. If 3872 * link changes, link event will be triggered because both the Enable Automatic 3873 * Link Update and LESM Enable bits are set when setting the PHY capabilities. 3874 */ 3875 static enum ice_status 3876 ice_force_phys_link_state(struct ice_hw *hw, bool link_up) 3877 { 3878 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3879 struct ice_aqc_get_phy_caps_data *pcaps; 3880 struct ice_port_info *pi; 3881 enum ice_status status; 3882 3883 if (!hw || !hw->port_info) 3884 return ICE_ERR_PARAM; 3885 3886 pi = hw->port_info; 3887 3888 pcaps = (struct ice_aqc_get_phy_caps_data *) 3889 ice_malloc(hw, sizeof(*pcaps)); 3890 if (!pcaps) 3891 return ICE_ERR_NO_MEMORY; 3892 3893 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 3894 NULL); 3895 if (status) 3896 goto out; 3897 3898 /* No change in link */ 3899 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) && 3900 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) 3901 goto out; 3902 3903 cfg.phy_type_low = pcaps->phy_type_low; 3904 cfg.phy_type_high = pcaps->phy_type_high; 3905 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3906 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an; 3907 cfg.eee_cap = pcaps->eee_cap; 3908 cfg.eeer_value = pcaps->eeer_value; 3909 cfg.link_fec_opt = pcaps->link_fec_options; 3910 if (link_up) 3911 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 3912 else 3913 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 3914 3915 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3916 3917 out: 3918 ice_free(hw, pcaps); 3919 return status; 3920 } 3921 3922 static int 3923 ice_dev_set_link_up(struct rte_eth_dev *dev) 3924 { 3925 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3926 3927 return ice_force_phys_link_state(hw, true); 3928 } 3929 3930 static int 3931 ice_dev_set_link_down(struct rte_eth_dev *dev) 3932 { 3933 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3934 3935 return ice_force_phys_link_state(hw, false); 3936 } 3937 3938 static int 3939 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3940 { 3941 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3942 struct rte_eth_dev_data *dev_data = pf->dev_data; 3943 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 3944 3945 /* check if mtu is within the allowed range */ 3946 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 3947 return -EINVAL; 3948 3949 /* mtu setting is forbidden if port is start */ 3950 if (dev_data->dev_started) { 3951 PMD_DRV_LOG(ERR, 3952 "port %d must be stopped before configuration", 3953 dev_data->port_id); 3954 return -EBUSY; 3955 } 3956 3957 if (frame_size > RTE_ETHER_MAX_LEN) 3958 dev_data->dev_conf.rxmode.offloads |= 3959 DEV_RX_OFFLOAD_JUMBO_FRAME; 3960 else 3961 dev_data->dev_conf.rxmode.offloads &= 3962 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 3963 3964 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3965 3966 return 0; 3967 } 3968 3969 static int ice_macaddr_set(struct rte_eth_dev *dev, 3970 struct rte_ether_addr *mac_addr) 3971 { 3972 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3973 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3974 struct ice_vsi *vsi = pf->main_vsi; 3975 struct ice_mac_filter *f; 3976 uint8_t flags = 0; 3977 int ret; 3978 3979 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 3980 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 3981 return -EINVAL; 3982 } 3983 3984 TAILQ_FOREACH(f, &vsi->mac_list, next) { 3985 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 3986 break; 3987 } 3988 3989 if (!f) { 3990 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 3991 return -EIO; 3992 } 3993 3994 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 3995 if (ret != ICE_SUCCESS) { 3996 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 3997 return -EIO; 3998 } 3999 ret = ice_add_mac_filter(vsi, mac_addr); 4000 if (ret != ICE_SUCCESS) { 4001 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 4002 return -EIO; 4003 } 4004 rte_ether_addr_copy(mac_addr, &pf->dev_addr); 4005 4006 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 4007 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 4008 if (ret != ICE_SUCCESS) 4009 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 4010 4011 return 0; 4012 } 4013 4014 /* Add a MAC address, and update filters */ 4015 static int 4016 ice_macaddr_add(struct rte_eth_dev *dev, 4017 struct rte_ether_addr *mac_addr, 4018 __rte_unused uint32_t index, 4019 __rte_unused uint32_t pool) 4020 { 4021 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4022 struct ice_vsi *vsi = pf->main_vsi; 4023 int ret; 4024 4025 ret = ice_add_mac_filter(vsi, mac_addr); 4026 if (ret != ICE_SUCCESS) { 4027 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 4028 return -EINVAL; 4029 } 4030 4031 return ICE_SUCCESS; 4032 } 4033 4034 /* Remove a MAC address, and update filters */ 4035 static void 4036 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 4037 { 4038 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4039 struct ice_vsi *vsi = pf->main_vsi; 4040 struct rte_eth_dev_data *data = dev->data; 4041 struct rte_ether_addr *macaddr; 4042 int ret; 4043 4044 macaddr = &data->mac_addrs[index]; 4045 ret = ice_remove_mac_filter(vsi, macaddr); 4046 if (ret) { 4047 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 4048 return; 4049 } 4050 } 4051 4052 static int 4053 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 4054 { 4055 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4056 struct ice_vsi *vsi = pf->main_vsi; 4057 int ret; 4058 4059 PMD_INIT_FUNC_TRACE(); 4060 4061 if (on) { 4062 ret = ice_add_vlan_filter(vsi, vlan_id); 4063 if (ret < 0) { 4064 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 4065 return -EINVAL; 4066 } 4067 } else { 4068 ret = ice_remove_vlan_filter(vsi, vlan_id); 4069 if (ret < 0) { 4070 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 4071 return -EINVAL; 4072 } 4073 } 4074 4075 return 0; 4076 } 4077 4078 /* Configure vlan filter on or off */ 4079 static int 4080 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 4081 { 4082 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4083 struct ice_vsi_ctx ctxt; 4084 uint8_t sec_flags, sw_flags2; 4085 int ret = 0; 4086 4087 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 4088 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 4089 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 4090 4091 if (on) { 4092 vsi->info.sec_flags |= sec_flags; 4093 vsi->info.sw_flags2 |= sw_flags2; 4094 } else { 4095 vsi->info.sec_flags &= ~sec_flags; 4096 vsi->info.sw_flags2 &= ~sw_flags2; 4097 } 4098 vsi->info.sw_id = hw->port_info->sw_id; 4099 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4100 ctxt.info.valid_sections = 4101 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 4102 ICE_AQ_VSI_PROP_SECURITY_VALID); 4103 ctxt.vsi_num = vsi->vsi_id; 4104 4105 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4106 if (ret) { 4107 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 4108 on ? "enable" : "disable"); 4109 return -EINVAL; 4110 } else { 4111 vsi->info.valid_sections |= 4112 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 4113 ICE_AQ_VSI_PROP_SECURITY_VALID); 4114 } 4115 4116 /* consist with other drivers, allow untagged packet when vlan filter on */ 4117 if (on) 4118 ret = ice_add_vlan_filter(vsi, 0); 4119 else 4120 ret = ice_remove_vlan_filter(vsi, 0); 4121 4122 return 0; 4123 } 4124 4125 static int 4126 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 4127 { 4128 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4129 struct ice_vsi_ctx ctxt; 4130 uint8_t vlan_flags; 4131 int ret = 0; 4132 4133 /* Check if it has been already on or off */ 4134 if (vsi->info.valid_sections & 4135 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 4136 if (on) { 4137 if ((vsi->info.vlan_flags & 4138 ICE_AQ_VSI_VLAN_EMOD_M) == 4139 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) 4140 return 0; /* already on */ 4141 } else { 4142 if ((vsi->info.vlan_flags & 4143 ICE_AQ_VSI_VLAN_EMOD_M) == 4144 ICE_AQ_VSI_VLAN_EMOD_NOTHING) 4145 return 0; /* already off */ 4146 } 4147 } 4148 4149 if (on) 4150 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; 4151 else 4152 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; 4153 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); 4154 vsi->info.vlan_flags |= vlan_flags; 4155 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4156 ctxt.info.valid_sections = 4157 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4158 ctxt.vsi_num = vsi->vsi_id; 4159 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4160 if (ret) { 4161 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 4162 on ? "enable" : "disable"); 4163 return -EINVAL; 4164 } 4165 4166 vsi->info.valid_sections |= 4167 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4168 4169 return ret; 4170 } 4171 4172 static int 4173 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 4174 { 4175 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4176 struct ice_vsi *vsi = pf->main_vsi; 4177 struct rte_eth_rxmode *rxmode; 4178 4179 rxmode = &dev->data->dev_conf.rxmode; 4180 if (mask & ETH_VLAN_FILTER_MASK) { 4181 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 4182 ice_vsi_config_vlan_filter(vsi, true); 4183 else 4184 ice_vsi_config_vlan_filter(vsi, false); 4185 } 4186 4187 if (mask & ETH_VLAN_STRIP_MASK) { 4188 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 4189 ice_vsi_config_vlan_stripping(vsi, true); 4190 else 4191 ice_vsi_config_vlan_stripping(vsi, false); 4192 } 4193 4194 if (mask & ETH_VLAN_EXTEND_MASK) { 4195 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 4196 ice_vsi_config_double_vlan(vsi, true); 4197 else 4198 ice_vsi_config_double_vlan(vsi, false); 4199 } 4200 4201 return 0; 4202 } 4203 4204 static int 4205 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4206 { 4207 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 4208 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4209 int ret; 4210 4211 if (!lut) 4212 return -EINVAL; 4213 4214 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 4215 ret = ice_aq_get_rss_lut(hw, vsi->idx, 4216 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); 4217 if (ret) { 4218 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 4219 return -EINVAL; 4220 } 4221 } else { 4222 uint64_t *lut_dw = (uint64_t *)lut; 4223 uint16_t i, lut_size_dw = lut_size / 4; 4224 4225 for (i = 0; i < lut_size_dw; i++) 4226 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 4227 } 4228 4229 return 0; 4230 } 4231 4232 static int 4233 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4234 { 4235 struct ice_pf *pf; 4236 struct ice_hw *hw; 4237 int ret; 4238 4239 if (!vsi || !lut) 4240 return -EINVAL; 4241 4242 pf = ICE_VSI_TO_PF(vsi); 4243 hw = ICE_VSI_TO_HW(vsi); 4244 4245 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 4246 ret = ice_aq_set_rss_lut(hw, vsi->idx, 4247 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); 4248 if (ret) { 4249 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 4250 return -EINVAL; 4251 } 4252 } else { 4253 uint64_t *lut_dw = (uint64_t *)lut; 4254 uint16_t i, lut_size_dw = lut_size / 4; 4255 4256 for (i = 0; i < lut_size_dw; i++) 4257 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 4258 4259 ice_flush(hw); 4260 } 4261 4262 return 0; 4263 } 4264 4265 static int 4266 ice_rss_reta_update(struct rte_eth_dev *dev, 4267 struct rte_eth_rss_reta_entry64 *reta_conf, 4268 uint16_t reta_size) 4269 { 4270 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4271 uint16_t i, lut_size = pf->hash_lut_size; 4272 uint16_t idx, shift; 4273 uint8_t *lut; 4274 int ret; 4275 4276 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 4277 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 4278 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 4279 PMD_DRV_LOG(ERR, 4280 "The size of hash lookup table configured (%d)" 4281 "doesn't match the number hardware can " 4282 "supported (128, 512, 2048)", 4283 reta_size); 4284 return -EINVAL; 4285 } 4286 4287 /* It MUST use the current LUT size to get the RSS lookup table, 4288 * otherwise if will fail with -100 error code. 4289 */ 4290 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 4291 if (!lut) { 4292 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4293 return -ENOMEM; 4294 } 4295 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 4296 if (ret) 4297 goto out; 4298 4299 for (i = 0; i < reta_size; i++) { 4300 idx = i / RTE_RETA_GROUP_SIZE; 4301 shift = i % RTE_RETA_GROUP_SIZE; 4302 if (reta_conf[idx].mask & (1ULL << shift)) 4303 lut[i] = reta_conf[idx].reta[shift]; 4304 } 4305 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 4306 if (ret == 0 && lut_size != reta_size) { 4307 PMD_DRV_LOG(INFO, 4308 "The size of hash lookup table is changed from (%d) to (%d)", 4309 lut_size, reta_size); 4310 pf->hash_lut_size = reta_size; 4311 } 4312 4313 out: 4314 rte_free(lut); 4315 4316 return ret; 4317 } 4318 4319 static int 4320 ice_rss_reta_query(struct rte_eth_dev *dev, 4321 struct rte_eth_rss_reta_entry64 *reta_conf, 4322 uint16_t reta_size) 4323 { 4324 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4325 uint16_t i, lut_size = pf->hash_lut_size; 4326 uint16_t idx, shift; 4327 uint8_t *lut; 4328 int ret; 4329 4330 if (reta_size != lut_size) { 4331 PMD_DRV_LOG(ERR, 4332 "The size of hash lookup table configured (%d)" 4333 "doesn't match the number hardware can " 4334 "supported (%d)", 4335 reta_size, lut_size); 4336 return -EINVAL; 4337 } 4338 4339 lut = rte_zmalloc(NULL, reta_size, 0); 4340 if (!lut) { 4341 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4342 return -ENOMEM; 4343 } 4344 4345 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 4346 if (ret) 4347 goto out; 4348 4349 for (i = 0; i < reta_size; i++) { 4350 idx = i / RTE_RETA_GROUP_SIZE; 4351 shift = i % RTE_RETA_GROUP_SIZE; 4352 if (reta_conf[idx].mask & (1ULL << shift)) 4353 reta_conf[idx].reta[shift] = lut[i]; 4354 } 4355 4356 out: 4357 rte_free(lut); 4358 4359 return ret; 4360 } 4361 4362 static int 4363 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 4364 { 4365 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4366 int ret = 0; 4367 4368 if (!key || key_len == 0) { 4369 PMD_DRV_LOG(DEBUG, "No key to be configured"); 4370 return 0; 4371 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 4372 sizeof(uint32_t)) { 4373 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 4374 return -EINVAL; 4375 } 4376 4377 struct ice_aqc_get_set_rss_keys *key_dw = 4378 (struct ice_aqc_get_set_rss_keys *)key; 4379 4380 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 4381 if (ret) { 4382 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 4383 ret = -EINVAL; 4384 } 4385 4386 return ret; 4387 } 4388 4389 static int 4390 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 4391 { 4392 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4393 int ret; 4394 4395 if (!key || !key_len) 4396 return -EINVAL; 4397 4398 ret = ice_aq_get_rss_key 4399 (hw, vsi->idx, 4400 (struct ice_aqc_get_set_rss_keys *)key); 4401 if (ret) { 4402 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 4403 return -EINVAL; 4404 } 4405 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 4406 4407 return 0; 4408 } 4409 4410 static int 4411 ice_rss_hash_update(struct rte_eth_dev *dev, 4412 struct rte_eth_rss_conf *rss_conf) 4413 { 4414 enum ice_status status = ICE_SUCCESS; 4415 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4416 struct ice_vsi *vsi = pf->main_vsi; 4417 4418 /* set hash key */ 4419 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 4420 if (status) 4421 return status; 4422 4423 if (rss_conf->rss_hf == 0) 4424 return 0; 4425 4426 /* RSS hash configuration */ 4427 ice_rss_hash_set(pf, rss_conf->rss_hf); 4428 4429 return 0; 4430 } 4431 4432 static int 4433 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 4434 struct rte_eth_rss_conf *rss_conf) 4435 { 4436 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4437 struct ice_vsi *vsi = pf->main_vsi; 4438 4439 ice_get_rss_key(vsi, rss_conf->rss_key, 4440 &rss_conf->rss_key_len); 4441 4442 /* TODO: default set to 0 as hf config is not supported now */ 4443 rss_conf->rss_hf = 0; 4444 return 0; 4445 } 4446 4447 static int 4448 ice_promisc_enable(struct rte_eth_dev *dev) 4449 { 4450 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4451 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4452 struct ice_vsi *vsi = pf->main_vsi; 4453 enum ice_status status; 4454 uint8_t pmask; 4455 int ret = 0; 4456 4457 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 4458 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4459 4460 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4461 switch (status) { 4462 case ICE_ERR_ALREADY_EXISTS: 4463 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 4464 case ICE_SUCCESS: 4465 break; 4466 default: 4467 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 4468 ret = -EAGAIN; 4469 } 4470 4471 return ret; 4472 } 4473 4474 static int 4475 ice_promisc_disable(struct rte_eth_dev *dev) 4476 { 4477 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4478 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4479 struct ice_vsi *vsi = pf->main_vsi; 4480 enum ice_status status; 4481 uint8_t pmask; 4482 int ret = 0; 4483 4484 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 4485 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4486 4487 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 4488 if (status != ICE_SUCCESS) { 4489 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 4490 ret = -EAGAIN; 4491 } 4492 4493 return ret; 4494 } 4495 4496 static int 4497 ice_allmulti_enable(struct rte_eth_dev *dev) 4498 { 4499 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4500 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4501 struct ice_vsi *vsi = pf->main_vsi; 4502 enum ice_status status; 4503 uint8_t pmask; 4504 int ret = 0; 4505 4506 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4507 4508 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4509 4510 switch (status) { 4511 case ICE_ERR_ALREADY_EXISTS: 4512 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled"); 4513 case ICE_SUCCESS: 4514 break; 4515 default: 4516 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 4517 ret = -EAGAIN; 4518 } 4519 4520 return ret; 4521 } 4522 4523 static int 4524 ice_allmulti_disable(struct rte_eth_dev *dev) 4525 { 4526 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4527 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4528 struct ice_vsi *vsi = pf->main_vsi; 4529 enum ice_status status; 4530 uint8_t pmask; 4531 int ret = 0; 4532 4533 if (dev->data->promiscuous == 1) 4534 return 0; /* must remain in all_multicast mode */ 4535 4536 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4537 4538 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 4539 if (status != ICE_SUCCESS) { 4540 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 4541 ret = -EAGAIN; 4542 } 4543 4544 return ret; 4545 } 4546 4547 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 4548 uint16_t queue_id) 4549 { 4550 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 4551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4552 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4553 uint32_t val; 4554 uint16_t msix_intr; 4555 4556 msix_intr = intr_handle->intr_vec[queue_id]; 4557 4558 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 4559 GLINT_DYN_CTL_ITR_INDX_M; 4560 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 4561 4562 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 4563 rte_intr_ack(&pci_dev->intr_handle); 4564 4565 return 0; 4566 } 4567 4568 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 4569 uint16_t queue_id) 4570 { 4571 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 4572 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4573 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4574 uint16_t msix_intr; 4575 4576 msix_intr = intr_handle->intr_vec[queue_id]; 4577 4578 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 4579 4580 return 0; 4581 } 4582 4583 static int 4584 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 4585 { 4586 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4587 u8 ver, patch; 4588 u16 build; 4589 int ret; 4590 4591 ver = hw->flash.orom.major; 4592 patch = hw->flash.orom.patch; 4593 build = hw->flash.orom.build; 4594 4595 ret = snprintf(fw_version, fw_size, 4596 "%x.%02x 0x%08x %d.%d.%d", 4597 hw->flash.nvm.major, 4598 hw->flash.nvm.minor, 4599 hw->flash.nvm.eetrack, 4600 ver, build, patch); 4601 4602 /* add the size of '\0' */ 4603 ret += 1; 4604 if (fw_size < (u32)ret) 4605 return ret; 4606 else 4607 return 0; 4608 } 4609 4610 static int 4611 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 4612 { 4613 struct ice_hw *hw; 4614 struct ice_vsi_ctx ctxt; 4615 uint8_t vlan_flags = 0; 4616 int ret; 4617 4618 if (!vsi || !info) { 4619 PMD_DRV_LOG(ERR, "invalid parameters"); 4620 return -EINVAL; 4621 } 4622 4623 if (info->on) { 4624 vsi->info.pvid = info->config.pvid; 4625 /** 4626 * If insert pvid is enabled, only tagged pkts are 4627 * allowed to be sent out. 4628 */ 4629 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | 4630 ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 4631 } else { 4632 vsi->info.pvid = 0; 4633 if (info->config.reject.tagged == 0) 4634 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; 4635 4636 if (info->config.reject.untagged == 0) 4637 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 4638 } 4639 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | 4640 ICE_AQ_VSI_VLAN_MODE_M); 4641 vsi->info.vlan_flags |= vlan_flags; 4642 memset(&ctxt, 0, sizeof(ctxt)); 4643 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4644 ctxt.info.valid_sections = 4645 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4646 ctxt.vsi_num = vsi->vsi_id; 4647 4648 hw = ICE_VSI_TO_HW(vsi); 4649 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4650 if (ret != ICE_SUCCESS) { 4651 PMD_DRV_LOG(ERR, 4652 "update VSI for VLAN insert failed, err %d", 4653 ret); 4654 return -EINVAL; 4655 } 4656 4657 vsi->info.valid_sections |= 4658 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4659 4660 return ret; 4661 } 4662 4663 static int 4664 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 4665 { 4666 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4667 struct ice_vsi *vsi = pf->main_vsi; 4668 struct rte_eth_dev_data *data = pf->dev_data; 4669 struct ice_vsi_vlan_pvid_info info; 4670 int ret; 4671 4672 memset(&info, 0, sizeof(info)); 4673 info.on = on; 4674 if (info.on) { 4675 info.config.pvid = pvid; 4676 } else { 4677 info.config.reject.tagged = 4678 data->dev_conf.txmode.hw_vlan_reject_tagged; 4679 info.config.reject.untagged = 4680 data->dev_conf.txmode.hw_vlan_reject_untagged; 4681 } 4682 4683 ret = ice_vsi_vlan_pvid_set(vsi, &info); 4684 if (ret < 0) { 4685 PMD_DRV_LOG(ERR, "Failed to set pvid."); 4686 return -EINVAL; 4687 } 4688 4689 return 0; 4690 } 4691 4692 static int 4693 ice_get_eeprom_length(struct rte_eth_dev *dev) 4694 { 4695 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4696 4697 return hw->flash.flash_size; 4698 } 4699 4700 static int 4701 ice_get_eeprom(struct rte_eth_dev *dev, 4702 struct rte_dev_eeprom_info *eeprom) 4703 { 4704 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4705 enum ice_status status = ICE_SUCCESS; 4706 uint8_t *data = eeprom->data; 4707 4708 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4709 4710 status = ice_acquire_nvm(hw, ICE_RES_READ); 4711 if (status) { 4712 PMD_DRV_LOG(ERR, "acquire nvm failed."); 4713 return -EIO; 4714 } 4715 4716 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length, 4717 data, false); 4718 4719 ice_release_nvm(hw); 4720 4721 if (status) { 4722 PMD_DRV_LOG(ERR, "EEPROM read failed."); 4723 return -EIO; 4724 } 4725 4726 return 0; 4727 } 4728 4729 static void 4730 ice_stat_update_32(struct ice_hw *hw, 4731 uint32_t reg, 4732 bool offset_loaded, 4733 uint64_t *offset, 4734 uint64_t *stat) 4735 { 4736 uint64_t new_data; 4737 4738 new_data = (uint64_t)ICE_READ_REG(hw, reg); 4739 if (!offset_loaded) 4740 *offset = new_data; 4741 4742 if (new_data >= *offset) 4743 *stat = (uint64_t)(new_data - *offset); 4744 else 4745 *stat = (uint64_t)((new_data + 4746 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 4747 - *offset); 4748 } 4749 4750 static void 4751 ice_stat_update_40(struct ice_hw *hw, 4752 uint32_t hireg, 4753 uint32_t loreg, 4754 bool offset_loaded, 4755 uint64_t *offset, 4756 uint64_t *stat) 4757 { 4758 uint64_t new_data; 4759 4760 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 4761 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 4762 ICE_32_BIT_WIDTH; 4763 4764 if (!offset_loaded) 4765 *offset = new_data; 4766 4767 if (new_data >= *offset) 4768 *stat = new_data - *offset; 4769 else 4770 *stat = (uint64_t)((new_data + 4771 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 4772 *offset); 4773 4774 *stat &= ICE_40_BIT_MASK; 4775 } 4776 4777 /* Get all the statistics of a VSI */ 4778 static void 4779 ice_update_vsi_stats(struct ice_vsi *vsi) 4780 { 4781 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 4782 struct ice_eth_stats *nes = &vsi->eth_stats; 4783 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4784 int idx = rte_le_to_cpu_16(vsi->vsi_id); 4785 4786 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 4787 vsi->offset_loaded, &oes->rx_bytes, 4788 &nes->rx_bytes); 4789 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 4790 vsi->offset_loaded, &oes->rx_unicast, 4791 &nes->rx_unicast); 4792 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 4793 vsi->offset_loaded, &oes->rx_multicast, 4794 &nes->rx_multicast); 4795 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 4796 vsi->offset_loaded, &oes->rx_broadcast, 4797 &nes->rx_broadcast); 4798 /* enlarge the limitation when rx_bytes overflowed */ 4799 if (vsi->offset_loaded) { 4800 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes) 4801 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4802 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes); 4803 } 4804 vsi->old_rx_bytes = nes->rx_bytes; 4805 /* exclude CRC bytes */ 4806 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 4807 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 4808 4809 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 4810 &oes->rx_discards, &nes->rx_discards); 4811 /* GLV_REPC not supported */ 4812 /* GLV_RMPC not supported */ 4813 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 4814 &oes->rx_unknown_protocol, 4815 &nes->rx_unknown_protocol); 4816 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 4817 vsi->offset_loaded, &oes->tx_bytes, 4818 &nes->tx_bytes); 4819 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 4820 vsi->offset_loaded, &oes->tx_unicast, 4821 &nes->tx_unicast); 4822 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 4823 vsi->offset_loaded, &oes->tx_multicast, 4824 &nes->tx_multicast); 4825 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 4826 vsi->offset_loaded, &oes->tx_broadcast, 4827 &nes->tx_broadcast); 4828 /* GLV_TDPC not supported */ 4829 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 4830 &oes->tx_errors, &nes->tx_errors); 4831 /* enlarge the limitation when tx_bytes overflowed */ 4832 if (vsi->offset_loaded) { 4833 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes) 4834 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4835 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes); 4836 } 4837 vsi->old_tx_bytes = nes->tx_bytes; 4838 vsi->offset_loaded = true; 4839 4840 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 4841 vsi->vsi_id); 4842 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 4843 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 4844 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 4845 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 4846 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 4847 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 4848 nes->rx_unknown_protocol); 4849 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 4850 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 4851 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 4852 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 4853 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 4854 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 4855 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 4856 vsi->vsi_id); 4857 } 4858 4859 static void 4860 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 4861 { 4862 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 4863 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 4864 4865 /* Get statistics of struct ice_eth_stats */ 4866 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 4867 GLPRT_GORCL(hw->port_info->lport), 4868 pf->offset_loaded, &os->eth.rx_bytes, 4869 &ns->eth.rx_bytes); 4870 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 4871 GLPRT_UPRCL(hw->port_info->lport), 4872 pf->offset_loaded, &os->eth.rx_unicast, 4873 &ns->eth.rx_unicast); 4874 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 4875 GLPRT_MPRCL(hw->port_info->lport), 4876 pf->offset_loaded, &os->eth.rx_multicast, 4877 &ns->eth.rx_multicast); 4878 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 4879 GLPRT_BPRCL(hw->port_info->lport), 4880 pf->offset_loaded, &os->eth.rx_broadcast, 4881 &ns->eth.rx_broadcast); 4882 ice_stat_update_32(hw, PRTRPB_RDPC, 4883 pf->offset_loaded, &os->eth.rx_discards, 4884 &ns->eth.rx_discards); 4885 /* enlarge the limitation when rx_bytes overflowed */ 4886 if (pf->offset_loaded) { 4887 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes) 4888 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4889 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes); 4890 } 4891 pf->old_rx_bytes = ns->eth.rx_bytes; 4892 4893 /* Workaround: CRC size should not be included in byte statistics, 4894 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 4895 * packet. 4896 */ 4897 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 4898 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 4899 4900 /* GLPRT_REPC not supported */ 4901 /* GLPRT_RMPC not supported */ 4902 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 4903 pf->offset_loaded, 4904 &os->eth.rx_unknown_protocol, 4905 &ns->eth.rx_unknown_protocol); 4906 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 4907 GLPRT_GOTCL(hw->port_info->lport), 4908 pf->offset_loaded, &os->eth.tx_bytes, 4909 &ns->eth.tx_bytes); 4910 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 4911 GLPRT_UPTCL(hw->port_info->lport), 4912 pf->offset_loaded, &os->eth.tx_unicast, 4913 &ns->eth.tx_unicast); 4914 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 4915 GLPRT_MPTCL(hw->port_info->lport), 4916 pf->offset_loaded, &os->eth.tx_multicast, 4917 &ns->eth.tx_multicast); 4918 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 4919 GLPRT_BPTCL(hw->port_info->lport), 4920 pf->offset_loaded, &os->eth.tx_broadcast, 4921 &ns->eth.tx_broadcast); 4922 /* enlarge the limitation when tx_bytes overflowed */ 4923 if (pf->offset_loaded) { 4924 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes) 4925 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4926 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes); 4927 } 4928 pf->old_tx_bytes = ns->eth.tx_bytes; 4929 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 4930 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 4931 4932 /* GLPRT_TEPC not supported */ 4933 4934 /* additional port specific stats */ 4935 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 4936 pf->offset_loaded, &os->tx_dropped_link_down, 4937 &ns->tx_dropped_link_down); 4938 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 4939 pf->offset_loaded, &os->crc_errors, 4940 &ns->crc_errors); 4941 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 4942 pf->offset_loaded, &os->illegal_bytes, 4943 &ns->illegal_bytes); 4944 /* GLPRT_ERRBC not supported */ 4945 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 4946 pf->offset_loaded, &os->mac_local_faults, 4947 &ns->mac_local_faults); 4948 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 4949 pf->offset_loaded, &os->mac_remote_faults, 4950 &ns->mac_remote_faults); 4951 4952 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 4953 pf->offset_loaded, &os->rx_len_errors, 4954 &ns->rx_len_errors); 4955 4956 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 4957 pf->offset_loaded, &os->link_xon_rx, 4958 &ns->link_xon_rx); 4959 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 4960 pf->offset_loaded, &os->link_xoff_rx, 4961 &ns->link_xoff_rx); 4962 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 4963 pf->offset_loaded, &os->link_xon_tx, 4964 &ns->link_xon_tx); 4965 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 4966 pf->offset_loaded, &os->link_xoff_tx, 4967 &ns->link_xoff_tx); 4968 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 4969 GLPRT_PRC64L(hw->port_info->lport), 4970 pf->offset_loaded, &os->rx_size_64, 4971 &ns->rx_size_64); 4972 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 4973 GLPRT_PRC127L(hw->port_info->lport), 4974 pf->offset_loaded, &os->rx_size_127, 4975 &ns->rx_size_127); 4976 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 4977 GLPRT_PRC255L(hw->port_info->lport), 4978 pf->offset_loaded, &os->rx_size_255, 4979 &ns->rx_size_255); 4980 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 4981 GLPRT_PRC511L(hw->port_info->lport), 4982 pf->offset_loaded, &os->rx_size_511, 4983 &ns->rx_size_511); 4984 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 4985 GLPRT_PRC1023L(hw->port_info->lport), 4986 pf->offset_loaded, &os->rx_size_1023, 4987 &ns->rx_size_1023); 4988 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 4989 GLPRT_PRC1522L(hw->port_info->lport), 4990 pf->offset_loaded, &os->rx_size_1522, 4991 &ns->rx_size_1522); 4992 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 4993 GLPRT_PRC9522L(hw->port_info->lport), 4994 pf->offset_loaded, &os->rx_size_big, 4995 &ns->rx_size_big); 4996 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 4997 pf->offset_loaded, &os->rx_undersize, 4998 &ns->rx_undersize); 4999 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 5000 pf->offset_loaded, &os->rx_fragments, 5001 &ns->rx_fragments); 5002 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 5003 pf->offset_loaded, &os->rx_oversize, 5004 &ns->rx_oversize); 5005 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 5006 pf->offset_loaded, &os->rx_jabber, 5007 &ns->rx_jabber); 5008 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 5009 GLPRT_PTC64L(hw->port_info->lport), 5010 pf->offset_loaded, &os->tx_size_64, 5011 &ns->tx_size_64); 5012 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 5013 GLPRT_PTC127L(hw->port_info->lport), 5014 pf->offset_loaded, &os->tx_size_127, 5015 &ns->tx_size_127); 5016 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 5017 GLPRT_PTC255L(hw->port_info->lport), 5018 pf->offset_loaded, &os->tx_size_255, 5019 &ns->tx_size_255); 5020 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 5021 GLPRT_PTC511L(hw->port_info->lport), 5022 pf->offset_loaded, &os->tx_size_511, 5023 &ns->tx_size_511); 5024 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 5025 GLPRT_PTC1023L(hw->port_info->lport), 5026 pf->offset_loaded, &os->tx_size_1023, 5027 &ns->tx_size_1023); 5028 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 5029 GLPRT_PTC1522L(hw->port_info->lport), 5030 pf->offset_loaded, &os->tx_size_1522, 5031 &ns->tx_size_1522); 5032 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 5033 GLPRT_PTC9522L(hw->port_info->lport), 5034 pf->offset_loaded, &os->tx_size_big, 5035 &ns->tx_size_big); 5036 5037 /* GLPRT_MSPDC not supported */ 5038 /* GLPRT_XEC not supported */ 5039 5040 pf->offset_loaded = true; 5041 5042 if (pf->main_vsi) 5043 ice_update_vsi_stats(pf->main_vsi); 5044 } 5045 5046 /* Get all statistics of a port */ 5047 static int 5048 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 5049 { 5050 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5051 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5052 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 5053 5054 /* call read registers - updates values, now write them to struct */ 5055 ice_read_stats_registers(pf, hw); 5056 5057 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 5058 pf->main_vsi->eth_stats.rx_multicast + 5059 pf->main_vsi->eth_stats.rx_broadcast - 5060 pf->main_vsi->eth_stats.rx_discards; 5061 stats->opackets = ns->eth.tx_unicast + 5062 ns->eth.tx_multicast + 5063 ns->eth.tx_broadcast; 5064 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 5065 stats->obytes = ns->eth.tx_bytes; 5066 stats->oerrors = ns->eth.tx_errors + 5067 pf->main_vsi->eth_stats.tx_errors; 5068 5069 /* Rx Errors */ 5070 stats->imissed = ns->eth.rx_discards + 5071 pf->main_vsi->eth_stats.rx_discards; 5072 stats->ierrors = ns->crc_errors + 5073 ns->rx_undersize + 5074 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 5075 5076 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 5077 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 5078 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 5079 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 5080 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 5081 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 5082 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 5083 pf->main_vsi->eth_stats.rx_discards); 5084 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 5085 ns->eth.rx_unknown_protocol); 5086 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 5087 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 5088 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 5089 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 5090 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 5091 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 5092 pf->main_vsi->eth_stats.tx_discards); 5093 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 5094 5095 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 5096 ns->tx_dropped_link_down); 5097 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 5098 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 5099 ns->illegal_bytes); 5100 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 5101 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 5102 ns->mac_local_faults); 5103 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 5104 ns->mac_remote_faults); 5105 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 5106 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 5107 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 5108 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 5109 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 5110 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 5111 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 5112 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 5113 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 5114 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 5115 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 5116 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 5117 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 5118 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 5119 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 5120 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 5121 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 5122 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 5123 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 5124 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 5125 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 5126 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 5127 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 5128 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 5129 return 0; 5130 } 5131 5132 /* Reset the statistics */ 5133 static int 5134 ice_stats_reset(struct rte_eth_dev *dev) 5135 { 5136 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5137 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5138 5139 /* Mark PF and VSI stats to update the offset, aka "reset" */ 5140 pf->offset_loaded = false; 5141 if (pf->main_vsi) 5142 pf->main_vsi->offset_loaded = false; 5143 5144 /* read the stats, reading current register values into offset */ 5145 ice_read_stats_registers(pf, hw); 5146 5147 return 0; 5148 } 5149 5150 static uint32_t 5151 ice_xstats_calc_num(void) 5152 { 5153 uint32_t num; 5154 5155 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 5156 5157 return num; 5158 } 5159 5160 static int 5161 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 5162 unsigned int n) 5163 { 5164 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5165 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5166 unsigned int i; 5167 unsigned int count; 5168 struct ice_hw_port_stats *hw_stats = &pf->stats; 5169 5170 count = ice_xstats_calc_num(); 5171 if (n < count) 5172 return count; 5173 5174 ice_read_stats_registers(pf, hw); 5175 5176 if (!xstats) 5177 return 0; 5178 5179 count = 0; 5180 5181 /* Get stats from ice_eth_stats struct */ 5182 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 5183 xstats[count].value = 5184 *(uint64_t *)((char *)&hw_stats->eth + 5185 ice_stats_strings[i].offset); 5186 xstats[count].id = count; 5187 count++; 5188 } 5189 5190 /* Get individiual stats from ice_hw_port struct */ 5191 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 5192 xstats[count].value = 5193 *(uint64_t *)((char *)hw_stats + 5194 ice_hw_port_strings[i].offset); 5195 xstats[count].id = count; 5196 count++; 5197 } 5198 5199 return count; 5200 } 5201 5202 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 5203 struct rte_eth_xstat_name *xstats_names, 5204 __rte_unused unsigned int limit) 5205 { 5206 unsigned int count = 0; 5207 unsigned int i; 5208 5209 if (!xstats_names) 5210 return ice_xstats_calc_num(); 5211 5212 /* Note: limit checked in rte_eth_xstats_names() */ 5213 5214 /* Get stats from ice_eth_stats struct */ 5215 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 5216 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 5217 sizeof(xstats_names[count].name)); 5218 count++; 5219 } 5220 5221 /* Get individiual stats from ice_hw_port struct */ 5222 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 5223 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 5224 sizeof(xstats_names[count].name)); 5225 count++; 5226 } 5227 5228 return count; 5229 } 5230 5231 static int 5232 ice_dev_filter_ctrl(struct rte_eth_dev *dev, 5233 enum rte_filter_type filter_type, 5234 enum rte_filter_op filter_op, 5235 void *arg) 5236 { 5237 int ret = 0; 5238 5239 if (!dev) 5240 return -EINVAL; 5241 5242 switch (filter_type) { 5243 case RTE_ETH_FILTER_GENERIC: 5244 if (filter_op != RTE_ETH_FILTER_GET) 5245 return -EINVAL; 5246 *(const void **)arg = &ice_flow_ops; 5247 break; 5248 default: 5249 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 5250 filter_type); 5251 ret = -EINVAL; 5252 break; 5253 } 5254 5255 return ret; 5256 } 5257 5258 /* Add UDP tunneling port */ 5259 static int 5260 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 5261 struct rte_eth_udp_tunnel *udp_tunnel) 5262 { 5263 int ret = 0; 5264 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5265 5266 if (udp_tunnel == NULL) 5267 return -EINVAL; 5268 5269 switch (udp_tunnel->prot_type) { 5270 case RTE_TUNNEL_TYPE_VXLAN: 5271 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); 5272 break; 5273 default: 5274 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5275 ret = -EINVAL; 5276 break; 5277 } 5278 5279 return ret; 5280 } 5281 5282 /* Delete UDP tunneling port */ 5283 static int 5284 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 5285 struct rte_eth_udp_tunnel *udp_tunnel) 5286 { 5287 int ret = 0; 5288 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5289 5290 if (udp_tunnel == NULL) 5291 return -EINVAL; 5292 5293 switch (udp_tunnel->prot_type) { 5294 case RTE_TUNNEL_TYPE_VXLAN: 5295 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); 5296 break; 5297 default: 5298 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5299 ret = -EINVAL; 5300 break; 5301 } 5302 5303 return ret; 5304 } 5305 5306 static int 5307 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5308 struct rte_pci_device *pci_dev) 5309 { 5310 return rte_eth_dev_pci_generic_probe(pci_dev, 5311 sizeof(struct ice_adapter), 5312 ice_dev_init); 5313 } 5314 5315 static int 5316 ice_pci_remove(struct rte_pci_device *pci_dev) 5317 { 5318 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 5319 } 5320 5321 static struct rte_pci_driver rte_ice_pmd = { 5322 .id_table = pci_id_ice_map, 5323 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 5324 .probe = ice_pci_probe, 5325 .remove = ice_pci_remove, 5326 }; 5327 5328 /** 5329 * Driver initialization routine. 5330 * Invoked once at EAL init time. 5331 * Register itself as the [Poll Mode] Driver of PCI devices. 5332 */ 5333 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 5334 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 5335 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 5336 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 5337 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>" 5338 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" 5339 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"); 5340 5341 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE); 5342 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE); 5343 #ifdef RTE_LIBRTE_ICE_DEBUG_RX 5344 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG); 5345 #endif 5346 #ifdef RTE_LIBRTE_ICE_DEBUG_TX 5347 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG); 5348 #endif 5349 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE 5350 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG); 5351 #endif 5352