1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <rte_ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include "base/ice_sched.h" 14 #include "base/ice_flow.h" 15 #include "base/ice_dcb.h" 16 #include "ice_ethdev.h" 17 #include "ice_rxtx.h" 18 19 #define ICE_MAX_QP_NUM "max_queue_pair_num" 20 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 21 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg" 22 23 int ice_logtype_init; 24 int ice_logtype_driver; 25 26 static int ice_dev_configure(struct rte_eth_dev *dev); 27 static int ice_dev_start(struct rte_eth_dev *dev); 28 static void ice_dev_stop(struct rte_eth_dev *dev); 29 static void ice_dev_close(struct rte_eth_dev *dev); 30 static int ice_dev_reset(struct rte_eth_dev *dev); 31 static void ice_dev_info_get(struct rte_eth_dev *dev, 32 struct rte_eth_dev_info *dev_info); 33 static int ice_link_update(struct rte_eth_dev *dev, 34 int wait_to_complete); 35 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 36 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 37 static int ice_vlan_tpid_set(struct rte_eth_dev *dev, 38 enum rte_vlan_type vlan_type, 39 uint16_t tpid); 40 static int ice_rss_reta_update(struct rte_eth_dev *dev, 41 struct rte_eth_rss_reta_entry64 *reta_conf, 42 uint16_t reta_size); 43 static int ice_rss_reta_query(struct rte_eth_dev *dev, 44 struct rte_eth_rss_reta_entry64 *reta_conf, 45 uint16_t reta_size); 46 static int ice_rss_hash_update(struct rte_eth_dev *dev, 47 struct rte_eth_rss_conf *rss_conf); 48 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 49 struct rte_eth_rss_conf *rss_conf); 50 static void ice_promisc_enable(struct rte_eth_dev *dev); 51 static void ice_promisc_disable(struct rte_eth_dev *dev); 52 static void ice_allmulti_enable(struct rte_eth_dev *dev); 53 static void ice_allmulti_disable(struct rte_eth_dev *dev); 54 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 55 uint16_t vlan_id, 56 int on); 57 static int ice_macaddr_set(struct rte_eth_dev *dev, 58 struct ether_addr *mac_addr); 59 static int ice_macaddr_add(struct rte_eth_dev *dev, 60 struct ether_addr *mac_addr, 61 __rte_unused uint32_t index, 62 uint32_t pool); 63 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 64 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 65 uint16_t queue_id); 66 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 67 uint16_t queue_id); 68 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 69 size_t fw_size); 70 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 71 uint16_t pvid, int on); 72 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 73 static int ice_get_eeprom(struct rte_eth_dev *dev, 74 struct rte_dev_eeprom_info *eeprom); 75 static int ice_stats_get(struct rte_eth_dev *dev, 76 struct rte_eth_stats *stats); 77 static void ice_stats_reset(struct rte_eth_dev *dev); 78 static int ice_xstats_get(struct rte_eth_dev *dev, 79 struct rte_eth_xstat *xstats, unsigned int n); 80 static int ice_xstats_get_names(struct rte_eth_dev *dev, 81 struct rte_eth_xstat_name *xstats_names, 82 unsigned int limit); 83 84 static const struct rte_pci_id pci_id_ice_map[] = { 85 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 86 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 87 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 88 { .vendor_id = 0, /* sentinel */ }, 89 }; 90 91 static const struct eth_dev_ops ice_eth_dev_ops = { 92 .dev_configure = ice_dev_configure, 93 .dev_start = ice_dev_start, 94 .dev_stop = ice_dev_stop, 95 .dev_close = ice_dev_close, 96 .dev_reset = ice_dev_reset, 97 .rx_queue_start = ice_rx_queue_start, 98 .rx_queue_stop = ice_rx_queue_stop, 99 .tx_queue_start = ice_tx_queue_start, 100 .tx_queue_stop = ice_tx_queue_stop, 101 .rx_queue_setup = ice_rx_queue_setup, 102 .rx_queue_release = ice_rx_queue_release, 103 .tx_queue_setup = ice_tx_queue_setup, 104 .tx_queue_release = ice_tx_queue_release, 105 .dev_infos_get = ice_dev_info_get, 106 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 107 .link_update = ice_link_update, 108 .mtu_set = ice_mtu_set, 109 .mac_addr_set = ice_macaddr_set, 110 .mac_addr_add = ice_macaddr_add, 111 .mac_addr_remove = ice_macaddr_remove, 112 .vlan_filter_set = ice_vlan_filter_set, 113 .vlan_offload_set = ice_vlan_offload_set, 114 .vlan_tpid_set = ice_vlan_tpid_set, 115 .reta_update = ice_rss_reta_update, 116 .reta_query = ice_rss_reta_query, 117 .rss_hash_update = ice_rss_hash_update, 118 .rss_hash_conf_get = ice_rss_hash_conf_get, 119 .promiscuous_enable = ice_promisc_enable, 120 .promiscuous_disable = ice_promisc_disable, 121 .allmulticast_enable = ice_allmulti_enable, 122 .allmulticast_disable = ice_allmulti_disable, 123 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 124 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 125 .fw_version_get = ice_fw_version_get, 126 .vlan_pvid_set = ice_vlan_pvid_set, 127 .rxq_info_get = ice_rxq_info_get, 128 .txq_info_get = ice_txq_info_get, 129 .get_eeprom_length = ice_get_eeprom_length, 130 .get_eeprom = ice_get_eeprom, 131 .rx_queue_count = ice_rx_queue_count, 132 .rx_descriptor_status = ice_rx_descriptor_status, 133 .tx_descriptor_status = ice_tx_descriptor_status, 134 .stats_get = ice_stats_get, 135 .stats_reset = ice_stats_reset, 136 .xstats_get = ice_xstats_get, 137 .xstats_get_names = ice_xstats_get_names, 138 .xstats_reset = ice_stats_reset, 139 }; 140 141 /* store statistics names and its offset in stats structure */ 142 struct ice_xstats_name_off { 143 char name[RTE_ETH_XSTATS_NAME_SIZE]; 144 unsigned int offset; 145 }; 146 147 static const struct ice_xstats_name_off ice_stats_strings[] = { 148 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 149 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 150 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 151 {"rx_dropped", offsetof(struct ice_eth_stats, rx_discards)}, 152 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 153 rx_unknown_protocol)}, 154 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 155 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 156 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 157 {"tx_dropped", offsetof(struct ice_eth_stats, tx_discards)}, 158 }; 159 160 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 161 sizeof(ice_stats_strings[0])) 162 163 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 164 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 165 tx_dropped_link_down)}, 166 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 167 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 168 illegal_bytes)}, 169 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 170 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 171 mac_local_faults)}, 172 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 173 mac_remote_faults)}, 174 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 175 rx_len_errors)}, 176 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 177 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 178 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 179 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 180 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 181 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 182 rx_size_127)}, 183 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 184 rx_size_255)}, 185 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 186 rx_size_511)}, 187 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 188 rx_size_1023)}, 189 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 190 rx_size_1522)}, 191 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 192 rx_size_big)}, 193 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 194 rx_undersize)}, 195 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 196 rx_oversize)}, 197 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 198 mac_short_pkt_dropped)}, 199 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 200 rx_fragments)}, 201 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 202 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 203 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 204 tx_size_127)}, 205 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 206 tx_size_255)}, 207 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 208 tx_size_511)}, 209 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 210 tx_size_1023)}, 211 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 212 tx_size_1522)}, 213 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 214 tx_size_big)}, 215 }; 216 217 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 218 sizeof(ice_hw_port_strings[0])) 219 220 static void 221 ice_init_controlq_parameter(struct ice_hw *hw) 222 { 223 /* fields for adminq */ 224 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 225 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 226 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 227 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 228 229 /* fields for mailboxq, DPDK used as PF host */ 230 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 231 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 232 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 233 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 234 } 235 236 static int 237 ice_check_qp_num(const char *key, const char *qp_value, 238 __rte_unused void *opaque) 239 { 240 char *end = NULL; 241 int num = 0; 242 243 while (isblank(*qp_value)) 244 qp_value++; 245 246 num = strtoul(qp_value, &end, 10); 247 248 if (!num || (*end == '-') || errno) { 249 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 250 "value must be > 0", 251 qp_value, key); 252 return -1; 253 } 254 255 return num; 256 } 257 258 static int 259 ice_config_max_queue_pair_num(struct rte_devargs *devargs) 260 { 261 struct rte_kvargs *kvlist; 262 const char *queue_num_key = ICE_MAX_QP_NUM; 263 int ret; 264 265 if (!devargs) 266 return 0; 267 268 kvlist = rte_kvargs_parse(devargs->args, NULL); 269 if (!kvlist) 270 return 0; 271 272 if (!rte_kvargs_count(kvlist, queue_num_key)) { 273 rte_kvargs_free(kvlist); 274 return 0; 275 } 276 277 if (rte_kvargs_process(kvlist, queue_num_key, 278 ice_check_qp_num, NULL) < 0) { 279 rte_kvargs_free(kvlist); 280 return 0; 281 } 282 ret = rte_kvargs_process(kvlist, queue_num_key, 283 ice_check_qp_num, NULL); 284 rte_kvargs_free(kvlist); 285 286 return ret; 287 } 288 289 static int 290 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 291 uint32_t num) 292 { 293 struct pool_entry *entry; 294 295 if (!pool || !num) 296 return -EINVAL; 297 298 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 299 if (!entry) { 300 PMD_INIT_LOG(ERR, 301 "Failed to allocate memory for resource pool"); 302 return -ENOMEM; 303 } 304 305 /* queue heap initialize */ 306 pool->num_free = num; 307 pool->num_alloc = 0; 308 pool->base = base; 309 LIST_INIT(&pool->alloc_list); 310 LIST_INIT(&pool->free_list); 311 312 /* Initialize element */ 313 entry->base = 0; 314 entry->len = num; 315 316 LIST_INSERT_HEAD(&pool->free_list, entry, next); 317 return 0; 318 } 319 320 static int 321 ice_res_pool_alloc(struct ice_res_pool_info *pool, 322 uint16_t num) 323 { 324 struct pool_entry *entry, *valid_entry; 325 326 if (!pool || !num) { 327 PMD_INIT_LOG(ERR, "Invalid parameter"); 328 return -EINVAL; 329 } 330 331 if (pool->num_free < num) { 332 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 333 num, pool->num_free); 334 return -ENOMEM; 335 } 336 337 valid_entry = NULL; 338 /* Lookup in free list and find most fit one */ 339 LIST_FOREACH(entry, &pool->free_list, next) { 340 if (entry->len >= num) { 341 /* Find best one */ 342 if (entry->len == num) { 343 valid_entry = entry; 344 break; 345 } 346 if (!valid_entry || 347 valid_entry->len > entry->len) 348 valid_entry = entry; 349 } 350 } 351 352 /* Not find one to satisfy the request, return */ 353 if (!valid_entry) { 354 PMD_INIT_LOG(ERR, "No valid entry found"); 355 return -ENOMEM; 356 } 357 /** 358 * The entry have equal queue number as requested, 359 * remove it from alloc_list. 360 */ 361 if (valid_entry->len == num) { 362 LIST_REMOVE(valid_entry, next); 363 } else { 364 /** 365 * The entry have more numbers than requested, 366 * create a new entry for alloc_list and minus its 367 * queue base and number in free_list. 368 */ 369 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 370 if (!entry) { 371 PMD_INIT_LOG(ERR, 372 "Failed to allocate memory for " 373 "resource pool"); 374 return -ENOMEM; 375 } 376 entry->base = valid_entry->base; 377 entry->len = num; 378 valid_entry->base += num; 379 valid_entry->len -= num; 380 valid_entry = entry; 381 } 382 383 /* Insert it into alloc list, not sorted */ 384 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 385 386 pool->num_free -= valid_entry->len; 387 pool->num_alloc += valid_entry->len; 388 389 return valid_entry->base + pool->base; 390 } 391 392 static void 393 ice_res_pool_destroy(struct ice_res_pool_info *pool) 394 { 395 struct pool_entry *entry, *next_entry; 396 397 if (!pool) 398 return; 399 400 for (entry = LIST_FIRST(&pool->alloc_list); 401 entry && (next_entry = LIST_NEXT(entry, next), 1); 402 entry = next_entry) { 403 LIST_REMOVE(entry, next); 404 rte_free(entry); 405 } 406 407 for (entry = LIST_FIRST(&pool->free_list); 408 entry && (next_entry = LIST_NEXT(entry, next), 1); 409 entry = next_entry) { 410 LIST_REMOVE(entry, next); 411 rte_free(entry); 412 } 413 414 pool->num_free = 0; 415 pool->num_alloc = 0; 416 pool->base = 0; 417 LIST_INIT(&pool->alloc_list); 418 LIST_INIT(&pool->free_list); 419 } 420 421 static void 422 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 423 { 424 /* Set VSI LUT selection */ 425 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 426 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 427 /* Set Hash scheme */ 428 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 429 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 430 /* enable TC */ 431 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 432 } 433 434 static enum ice_status 435 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 436 struct ice_aqc_vsi_props *info, 437 uint8_t enabled_tcmap) 438 { 439 uint16_t bsf, qp_idx; 440 441 /* default tc 0 now. Multi-TC supporting need to be done later. 442 * Configure TC and queue mapping parameters, for enabled TC, 443 * allocate qpnum_per_tc queues to this traffic. 444 */ 445 if (enabled_tcmap != 0x01) { 446 PMD_INIT_LOG(ERR, "only TC0 is supported"); 447 return -ENOTSUP; 448 } 449 450 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 451 bsf = rte_bsf32(vsi->nb_qps); 452 /* Adjust the queue number to actual queues that can be applied */ 453 vsi->nb_qps = 0x1 << bsf; 454 455 qp_idx = 0; 456 /* Set tc and queue mapping with VSI */ 457 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 458 ICE_AQ_VSI_TC_Q_OFFSET_S) | 459 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 460 461 /* Associate queue number with VSI */ 462 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 463 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 464 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 465 info->valid_sections |= 466 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 467 /* Set the info.ingress_table and info.egress_table 468 * for UP translate table. Now just set it to 1:1 map by default 469 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 470 */ 471 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 472 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 473 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 474 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 475 return 0; 476 } 477 478 static int 479 ice_init_mac_address(struct rte_eth_dev *dev) 480 { 481 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 482 483 if (!is_unicast_ether_addr 484 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) { 485 PMD_INIT_LOG(ERR, "Invalid MAC address"); 486 return -EINVAL; 487 } 488 489 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr, 490 (struct ether_addr *)hw->port_info[0].mac.perm_addr); 491 492 dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0); 493 if (!dev->data->mac_addrs) { 494 PMD_INIT_LOG(ERR, 495 "Failed to allocate memory to store mac address"); 496 return -ENOMEM; 497 } 498 /* store it to dev data */ 499 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr, 500 &dev->data->mac_addrs[0]); 501 return 0; 502 } 503 504 /* Find out specific MAC filter */ 505 static struct ice_mac_filter * 506 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr) 507 { 508 struct ice_mac_filter *f; 509 510 TAILQ_FOREACH(f, &vsi->mac_list, next) { 511 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 512 return f; 513 } 514 515 return NULL; 516 } 517 518 static int 519 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr) 520 { 521 struct ice_fltr_list_entry *m_list_itr = NULL; 522 struct ice_mac_filter *f; 523 struct LIST_HEAD_TYPE list_head; 524 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 525 int ret = 0; 526 527 /* If it's added and configured, return */ 528 f = ice_find_mac_filter(vsi, mac_addr); 529 if (f) { 530 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 531 return 0; 532 } 533 534 INIT_LIST_HEAD(&list_head); 535 536 m_list_itr = (struct ice_fltr_list_entry *) 537 ice_malloc(hw, sizeof(*m_list_itr)); 538 if (!m_list_itr) { 539 ret = -ENOMEM; 540 goto DONE; 541 } 542 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 543 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 544 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 545 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 546 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 547 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 548 m_list_itr->fltr_info.vsi_handle = vsi->idx; 549 550 LIST_ADD(&m_list_itr->list_entry, &list_head); 551 552 /* Add the mac */ 553 ret = ice_add_mac(hw, &list_head); 554 if (ret != ICE_SUCCESS) { 555 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 556 ret = -EINVAL; 557 goto DONE; 558 } 559 /* Add the mac addr into mac list */ 560 f = rte_zmalloc(NULL, sizeof(*f), 0); 561 if (!f) { 562 PMD_DRV_LOG(ERR, "failed to allocate memory"); 563 ret = -ENOMEM; 564 goto DONE; 565 } 566 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN); 567 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 568 vsi->mac_num++; 569 570 ret = 0; 571 572 DONE: 573 rte_free(m_list_itr); 574 return ret; 575 } 576 577 static int 578 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr) 579 { 580 struct ice_fltr_list_entry *m_list_itr = NULL; 581 struct ice_mac_filter *f; 582 struct LIST_HEAD_TYPE list_head; 583 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 584 int ret = 0; 585 586 /* Can't find it, return an error */ 587 f = ice_find_mac_filter(vsi, mac_addr); 588 if (!f) 589 return -EINVAL; 590 591 INIT_LIST_HEAD(&list_head); 592 593 m_list_itr = (struct ice_fltr_list_entry *) 594 ice_malloc(hw, sizeof(*m_list_itr)); 595 if (!m_list_itr) { 596 ret = -ENOMEM; 597 goto DONE; 598 } 599 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 600 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 601 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 602 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 603 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 604 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 605 m_list_itr->fltr_info.vsi_handle = vsi->idx; 606 607 LIST_ADD(&m_list_itr->list_entry, &list_head); 608 609 /* remove the mac filter */ 610 ret = ice_remove_mac(hw, &list_head); 611 if (ret != ICE_SUCCESS) { 612 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 613 ret = -EINVAL; 614 goto DONE; 615 } 616 617 /* Remove the mac addr from mac list */ 618 TAILQ_REMOVE(&vsi->mac_list, f, next); 619 rte_free(f); 620 vsi->mac_num--; 621 622 ret = 0; 623 DONE: 624 rte_free(m_list_itr); 625 return ret; 626 } 627 628 /* Find out specific VLAN filter */ 629 static struct ice_vlan_filter * 630 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 631 { 632 struct ice_vlan_filter *f; 633 634 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 635 if (vlan_id == f->vlan_info.vlan_id) 636 return f; 637 } 638 639 return NULL; 640 } 641 642 static int 643 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 644 { 645 struct ice_fltr_list_entry *v_list_itr = NULL; 646 struct ice_vlan_filter *f; 647 struct LIST_HEAD_TYPE list_head; 648 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 649 int ret = 0; 650 651 if (!vsi || vlan_id > ETHER_MAX_VLAN_ID) 652 return -EINVAL; 653 654 /* If it's added and configured, return. */ 655 f = ice_find_vlan_filter(vsi, vlan_id); 656 if (f) { 657 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 658 return 0; 659 } 660 661 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 662 return 0; 663 664 INIT_LIST_HEAD(&list_head); 665 666 v_list_itr = (struct ice_fltr_list_entry *) 667 ice_malloc(hw, sizeof(*v_list_itr)); 668 if (!v_list_itr) { 669 ret = -ENOMEM; 670 goto DONE; 671 } 672 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 673 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 674 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 675 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 676 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 677 v_list_itr->fltr_info.vsi_handle = vsi->idx; 678 679 LIST_ADD(&v_list_itr->list_entry, &list_head); 680 681 /* Add the vlan */ 682 ret = ice_add_vlan(hw, &list_head); 683 if (ret != ICE_SUCCESS) { 684 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 685 ret = -EINVAL; 686 goto DONE; 687 } 688 689 /* Add vlan into vlan list */ 690 f = rte_zmalloc(NULL, sizeof(*f), 0); 691 if (!f) { 692 PMD_DRV_LOG(ERR, "failed to allocate memory"); 693 ret = -ENOMEM; 694 goto DONE; 695 } 696 f->vlan_info.vlan_id = vlan_id; 697 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 698 vsi->vlan_num++; 699 700 ret = 0; 701 702 DONE: 703 rte_free(v_list_itr); 704 return ret; 705 } 706 707 static int 708 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 709 { 710 struct ice_fltr_list_entry *v_list_itr = NULL; 711 struct ice_vlan_filter *f; 712 struct LIST_HEAD_TYPE list_head; 713 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 714 int ret = 0; 715 716 /** 717 * Vlan 0 is the generic filter for untagged packets 718 * and can't be removed. 719 */ 720 if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID) 721 return -EINVAL; 722 723 /* Can't find it, return an error */ 724 f = ice_find_vlan_filter(vsi, vlan_id); 725 if (!f) 726 return -EINVAL; 727 728 INIT_LIST_HEAD(&list_head); 729 730 v_list_itr = (struct ice_fltr_list_entry *) 731 ice_malloc(hw, sizeof(*v_list_itr)); 732 if (!v_list_itr) { 733 ret = -ENOMEM; 734 goto DONE; 735 } 736 737 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 738 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 739 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 740 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 741 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 742 v_list_itr->fltr_info.vsi_handle = vsi->idx; 743 744 LIST_ADD(&v_list_itr->list_entry, &list_head); 745 746 /* remove the vlan filter */ 747 ret = ice_remove_vlan(hw, &list_head); 748 if (ret != ICE_SUCCESS) { 749 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 750 ret = -EINVAL; 751 goto DONE; 752 } 753 754 /* Remove the vlan id from vlan list */ 755 TAILQ_REMOVE(&vsi->vlan_list, f, next); 756 rte_free(f); 757 vsi->vlan_num--; 758 759 ret = 0; 760 DONE: 761 rte_free(v_list_itr); 762 return ret; 763 } 764 765 static int 766 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 767 { 768 struct ice_mac_filter *m_f; 769 struct ice_vlan_filter *v_f; 770 int ret = 0; 771 772 if (!vsi || !vsi->mac_num) 773 return -EINVAL; 774 775 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 776 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 777 if (ret != ICE_SUCCESS) { 778 ret = -EINVAL; 779 goto DONE; 780 } 781 } 782 783 if (vsi->vlan_num == 0) 784 return 0; 785 786 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 787 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 788 if (ret != ICE_SUCCESS) { 789 ret = -EINVAL; 790 goto DONE; 791 } 792 } 793 794 DONE: 795 return ret; 796 } 797 798 static int 799 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 800 { 801 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 802 struct ice_vsi_ctx ctxt; 803 uint8_t qinq_flags; 804 int ret = 0; 805 806 /* Check if it has been already on or off */ 807 if (vsi->info.valid_sections & 808 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 809 if (on) { 810 if ((vsi->info.outer_tag_flags & 811 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == 812 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) 813 return 0; /* already on */ 814 } else { 815 if (!(vsi->info.outer_tag_flags & 816 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) 817 return 0; /* already off */ 818 } 819 } 820 821 if (on) 822 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; 823 else 824 qinq_flags = 0; 825 /* clear global insertion and use per packet insertion */ 826 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); 827 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); 828 vsi->info.outer_tag_flags |= qinq_flags; 829 /* use default vlan type 0x8100 */ 830 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 831 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 832 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 833 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 834 ctxt.info.valid_sections = 835 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 836 ctxt.vsi_num = vsi->vsi_id; 837 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 838 if (ret) { 839 PMD_DRV_LOG(INFO, 840 "Update VSI failed to %s qinq stripping", 841 on ? "enable" : "disable"); 842 return -EINVAL; 843 } 844 845 vsi->info.valid_sections |= 846 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 847 848 return ret; 849 } 850 851 static int 852 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 853 { 854 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 855 struct ice_vsi_ctx ctxt; 856 uint8_t qinq_flags; 857 int ret = 0; 858 859 /* Check if it has been already on or off */ 860 if (vsi->info.valid_sections & 861 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 862 if (on) { 863 if ((vsi->info.outer_tag_flags & 864 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 865 ICE_AQ_VSI_OUTER_TAG_COPY) 866 return 0; /* already on */ 867 } else { 868 if ((vsi->info.outer_tag_flags & 869 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 870 ICE_AQ_VSI_OUTER_TAG_NOTHING) 871 return 0; /* already off */ 872 } 873 } 874 875 if (on) 876 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; 877 else 878 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; 879 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); 880 vsi->info.outer_tag_flags |= qinq_flags; 881 /* use default vlan type 0x8100 */ 882 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 883 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 884 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 885 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 886 ctxt.info.valid_sections = 887 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 888 ctxt.vsi_num = vsi->vsi_id; 889 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 890 if (ret) { 891 PMD_DRV_LOG(INFO, 892 "Update VSI failed to %s qinq stripping", 893 on ? "enable" : "disable"); 894 return -EINVAL; 895 } 896 897 vsi->info.valid_sections |= 898 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 899 900 return ret; 901 } 902 903 static int 904 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 905 { 906 int ret; 907 908 ret = ice_vsi_config_qinq_stripping(vsi, on); 909 if (ret) 910 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 911 912 ret = ice_vsi_config_qinq_insertion(vsi, on); 913 if (ret) 914 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 915 916 return ret; 917 } 918 919 /* Enable IRQ0 */ 920 static void 921 ice_pf_enable_irq0(struct ice_hw *hw) 922 { 923 /* reset the registers */ 924 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 925 ICE_READ_REG(hw, PFINT_OICR); 926 927 #ifdef ICE_LSE_SPT 928 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 929 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 930 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 931 932 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 933 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 934 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 935 PFINT_OICR_CTL_ITR_INDX_M) | 936 PFINT_OICR_CTL_CAUSE_ENA_M); 937 938 ICE_WRITE_REG(hw, PFINT_FW_CTL, 939 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 940 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 941 PFINT_FW_CTL_ITR_INDX_M) | 942 PFINT_FW_CTL_CAUSE_ENA_M); 943 #else 944 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 945 #endif 946 947 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 948 GLINT_DYN_CTL_INTENA_M | 949 GLINT_DYN_CTL_CLEARPBA_M | 950 GLINT_DYN_CTL_ITR_INDX_M); 951 952 ice_flush(hw); 953 } 954 955 /* Disable IRQ0 */ 956 static void 957 ice_pf_disable_irq0(struct ice_hw *hw) 958 { 959 /* Disable all interrupt types */ 960 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 961 ice_flush(hw); 962 } 963 964 #ifdef ICE_LSE_SPT 965 static void 966 ice_handle_aq_msg(struct rte_eth_dev *dev) 967 { 968 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 969 struct ice_ctl_q_info *cq = &hw->adminq; 970 struct ice_rq_event_info event; 971 uint16_t pending, opcode; 972 int ret; 973 974 event.buf_len = ICE_AQ_MAX_BUF_LEN; 975 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 976 if (!event.msg_buf) { 977 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 978 return; 979 } 980 981 pending = 1; 982 while (pending) { 983 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 984 985 if (ret != ICE_SUCCESS) { 986 PMD_DRV_LOG(INFO, 987 "Failed to read msg from AdminQ, " 988 "adminq_err: %u", 989 hw->adminq.sq_last_status); 990 break; 991 } 992 opcode = rte_le_to_cpu_16(event.desc.opcode); 993 994 switch (opcode) { 995 case ice_aqc_opc_get_link_status: 996 ret = ice_link_update(dev, 0); 997 if (!ret) 998 _rte_eth_dev_callback_process 999 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1000 break; 1001 default: 1002 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1003 opcode); 1004 break; 1005 } 1006 } 1007 rte_free(event.msg_buf); 1008 } 1009 #endif 1010 1011 /** 1012 * Interrupt handler triggered by NIC for handling 1013 * specific interrupt. 1014 * 1015 * @param handle 1016 * Pointer to interrupt handle. 1017 * @param param 1018 * The address of parameter (struct rte_eth_dev *) regsitered before. 1019 * 1020 * @return 1021 * void 1022 */ 1023 static void 1024 ice_interrupt_handler(void *param) 1025 { 1026 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1027 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1028 uint32_t oicr; 1029 uint32_t reg; 1030 uint8_t pf_num; 1031 uint8_t event; 1032 uint16_t queue; 1033 #ifdef ICE_LSE_SPT 1034 uint32_t int_fw_ctl; 1035 #endif 1036 1037 /* Disable interrupt */ 1038 ice_pf_disable_irq0(hw); 1039 1040 /* read out interrupt causes */ 1041 oicr = ICE_READ_REG(hw, PFINT_OICR); 1042 #ifdef ICE_LSE_SPT 1043 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1044 #endif 1045 1046 /* No interrupt event indicated */ 1047 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1048 PMD_DRV_LOG(INFO, "No interrupt event"); 1049 goto done; 1050 } 1051 1052 #ifdef ICE_LSE_SPT 1053 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1054 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1055 ice_handle_aq_msg(dev); 1056 } 1057 #else 1058 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1059 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1060 ice_link_update(dev, 0); 1061 } 1062 #endif 1063 1064 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1065 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1066 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1067 if (reg & GL_MDET_TX_PQM_VALID_M) { 1068 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1069 GL_MDET_TX_PQM_PF_NUM_S; 1070 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1071 GL_MDET_TX_PQM_MAL_TYPE_S; 1072 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1073 GL_MDET_TX_PQM_QNUM_S; 1074 1075 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1076 "%d by PQM on TX queue %d PF# %d", 1077 event, queue, pf_num); 1078 } 1079 1080 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1081 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1082 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1083 GL_MDET_TX_TCLAN_PF_NUM_S; 1084 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1085 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1086 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1087 GL_MDET_TX_TCLAN_QNUM_S; 1088 1089 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1090 "%d by TCLAN on TX queue %d PF# %d", 1091 event, queue, pf_num); 1092 } 1093 } 1094 done: 1095 /* Enable interrupt */ 1096 ice_pf_enable_irq0(hw); 1097 rte_intr_enable(dev->intr_handle); 1098 } 1099 1100 /* Initialize SW parameters of PF */ 1101 static int 1102 ice_pf_sw_init(struct rte_eth_dev *dev) 1103 { 1104 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1105 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1106 1107 if (ice_config_max_queue_pair_num(dev->device->devargs) > 0) 1108 pf->lan_nb_qp_max = 1109 ice_config_max_queue_pair_num(dev->device->devargs); 1110 else 1111 pf->lan_nb_qp_max = 1112 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1113 hw->func_caps.common_cap.num_rxq); 1114 1115 pf->lan_nb_qps = pf->lan_nb_qp_max; 1116 1117 return 0; 1118 } 1119 1120 static struct ice_vsi * 1121 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1122 { 1123 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1124 struct ice_vsi *vsi = NULL; 1125 struct ice_vsi_ctx vsi_ctx; 1126 int ret; 1127 struct ether_addr broadcast = { 1128 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1129 struct ether_addr mac_addr; 1130 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1131 uint8_t tc_bitmap = 0x1; 1132 1133 /* hw->num_lports = 1 in NIC mode */ 1134 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1135 if (!vsi) 1136 return NULL; 1137 1138 vsi->idx = pf->next_vsi_idx; 1139 pf->next_vsi_idx++; 1140 vsi->type = type; 1141 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1142 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1143 vsi->vlan_anti_spoof_on = 0; 1144 vsi->vlan_filter_on = 1; 1145 TAILQ_INIT(&vsi->mac_list); 1146 TAILQ_INIT(&vsi->vlan_list); 1147 1148 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1149 /* base_queue in used in queue mapping of VSI add/update command. 1150 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ 1151 * cases in the first stage. Only Main VSI. 1152 */ 1153 vsi->base_queue = 0; 1154 switch (type) { 1155 case ICE_VSI_PF: 1156 vsi->nb_qps = pf->lan_nb_qps; 1157 ice_vsi_config_default_rss(&vsi_ctx.info); 1158 vsi_ctx.alloc_from_pool = true; 1159 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1160 /* switch_id is queried by get_switch_config aq, which is done 1161 * by ice_init_hw 1162 */ 1163 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1164 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1165 /* Allow all untagged or tagged packets */ 1166 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; 1167 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; 1168 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1169 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1170 /* Enable VLAN/UP trip */ 1171 ret = ice_vsi_config_tc_queue_mapping(vsi, 1172 &vsi_ctx.info, 1173 ICE_DEFAULT_TCMAP); 1174 if (ret) { 1175 PMD_INIT_LOG(ERR, 1176 "tc queue mapping with vsi failed, " 1177 "err = %d", 1178 ret); 1179 goto fail_mem; 1180 } 1181 1182 break; 1183 default: 1184 /* for other types of VSI */ 1185 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1186 goto fail_mem; 1187 } 1188 1189 /* VF has MSIX interrupt in VF range, don't allocate here */ 1190 if (type == ICE_VSI_PF) { 1191 ret = ice_res_pool_alloc(&pf->msix_pool, 1192 RTE_MIN(vsi->nb_qps, 1193 RTE_MAX_RXTX_INTR_VEC_ID)); 1194 if (ret < 0) { 1195 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1196 vsi->vsi_id, ret); 1197 } 1198 vsi->msix_intr = ret; 1199 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1200 } else { 1201 vsi->msix_intr = 0; 1202 vsi->nb_msix = 0; 1203 } 1204 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1205 if (ret != ICE_SUCCESS) { 1206 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1207 goto fail_mem; 1208 } 1209 /* store vsi information is SW structure */ 1210 vsi->vsi_id = vsi_ctx.vsi_num; 1211 vsi->info = vsi_ctx.info; 1212 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1213 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1214 1215 /* MAC configuration */ 1216 rte_memcpy(pf->dev_addr.addr_bytes, 1217 hw->port_info->mac.perm_addr, 1218 ETH_ADDR_LEN); 1219 1220 rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN); 1221 ret = ice_add_mac_filter(vsi, &mac_addr); 1222 if (ret != ICE_SUCCESS) 1223 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1224 1225 rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN); 1226 ret = ice_add_mac_filter(vsi, &mac_addr); 1227 if (ret != ICE_SUCCESS) 1228 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1229 1230 /* At the beginning, only TC0. */ 1231 /* What we need here is the maximam number of the TX queues. 1232 * Currently vsi->nb_qps means it. 1233 * Correct it if any change. 1234 */ 1235 max_txqs[0] = vsi->nb_qps; 1236 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1237 tc_bitmap, max_txqs); 1238 if (ret != ICE_SUCCESS) 1239 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1240 1241 return vsi; 1242 fail_mem: 1243 rte_free(vsi); 1244 pf->next_vsi_idx--; 1245 return NULL; 1246 } 1247 1248 static int 1249 ice_send_driver_ver(struct ice_hw *hw) 1250 { 1251 struct ice_driver_ver dv; 1252 1253 /* we don't have driver version use 0 for dummy */ 1254 dv.major_ver = 0; 1255 dv.minor_ver = 0; 1256 dv.build_ver = 0; 1257 dv.subbuild_ver = 0; 1258 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1259 1260 return ice_aq_send_driver_ver(hw, &dv, NULL); 1261 } 1262 1263 static int 1264 ice_pf_setup(struct ice_pf *pf) 1265 { 1266 struct ice_vsi *vsi; 1267 1268 /* Clear all stats counters */ 1269 pf->offset_loaded = FALSE; 1270 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1271 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1272 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1273 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1274 1275 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1276 if (!vsi) { 1277 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1278 return -EINVAL; 1279 } 1280 1281 pf->main_vsi = vsi; 1282 1283 return 0; 1284 } 1285 1286 static int ice_load_pkg(struct rte_eth_dev *dev) 1287 { 1288 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1289 const char *pkg_file = ICE_DFLT_PKG_FILE; 1290 int err; 1291 uint8_t *buf; 1292 int buf_len; 1293 FILE *file; 1294 struct stat fstat; 1295 1296 file = fopen(pkg_file, "rb"); 1297 if (!file) { 1298 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); 1299 return -1; 1300 } 1301 1302 err = stat(pkg_file, &fstat); 1303 if (err) { 1304 PMD_INIT_LOG(ERR, "failed to get file stats\n"); 1305 fclose(file); 1306 return err; 1307 } 1308 1309 buf_len = fstat.st_size; 1310 buf = rte_malloc(NULL, buf_len, 0); 1311 1312 if (!buf) { 1313 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", 1314 buf_len); 1315 fclose(file); 1316 return -1; 1317 } 1318 1319 err = fread(buf, buf_len, 1, file); 1320 if (err != 1) { 1321 PMD_INIT_LOG(ERR, "failed to read package data\n"); 1322 fclose(file); 1323 err = -1; 1324 goto fail_exit; 1325 } 1326 1327 fclose(file); 1328 1329 err = ice_copy_and_init_pkg(hw, buf, buf_len); 1330 if (err) { 1331 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1332 goto fail_exit; 1333 } 1334 err = ice_init_hw_tbls(hw); 1335 if (err) { 1336 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); 1337 goto fail_init_tbls; 1338 } 1339 1340 return 0; 1341 1342 fail_init_tbls: 1343 rte_free(hw->pkg_copy); 1344 fail_exit: 1345 rte_free(buf); 1346 return err; 1347 } 1348 1349 static int 1350 ice_dev_init(struct rte_eth_dev *dev) 1351 { 1352 struct rte_pci_device *pci_dev; 1353 struct rte_intr_handle *intr_handle; 1354 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1355 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1356 struct ice_adapter *ad = 1357 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1358 struct ice_vsi *vsi; 1359 int ret; 1360 1361 dev->dev_ops = &ice_eth_dev_ops; 1362 dev->rx_pkt_burst = ice_recv_pkts; 1363 dev->tx_pkt_burst = ice_xmit_pkts; 1364 dev->tx_pkt_prepare = ice_prep_pkts; 1365 1366 ice_set_default_ptype_table(dev); 1367 pci_dev = RTE_DEV_TO_PCI(dev->device); 1368 intr_handle = &pci_dev->intr_handle; 1369 1370 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1371 pf->adapter->eth_dev = dev; 1372 pf->dev_data = dev->data; 1373 hw->back = pf->adapter; 1374 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 1375 hw->vendor_id = pci_dev->id.vendor_id; 1376 hw->device_id = pci_dev->id.device_id; 1377 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1378 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1379 hw->bus.device = pci_dev->addr.devid; 1380 hw->bus.func = pci_dev->addr.function; 1381 1382 ice_init_controlq_parameter(hw); 1383 1384 ret = ice_init_hw(hw); 1385 if (ret) { 1386 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 1387 return -EINVAL; 1388 } 1389 1390 ret = ice_load_pkg(dev); 1391 if (ret) { 1392 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 1393 "Entering Safe Mode"); 1394 ad->is_safe_mode = 1; 1395 } 1396 1397 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 1398 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 1399 hw->api_maj_ver, hw->api_min_ver); 1400 1401 ice_pf_sw_init(dev); 1402 ret = ice_init_mac_address(dev); 1403 if (ret) { 1404 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 1405 goto err_init_mac; 1406 } 1407 1408 ret = ice_res_pool_init(&pf->msix_pool, 1, 1409 hw->func_caps.common_cap.num_msix_vectors - 1); 1410 if (ret) { 1411 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 1412 goto err_msix_pool_init; 1413 } 1414 1415 ret = ice_pf_setup(pf); 1416 if (ret) { 1417 PMD_INIT_LOG(ERR, "Failed to setup PF"); 1418 goto err_pf_setup; 1419 } 1420 1421 ret = ice_send_driver_ver(hw); 1422 if (ret) { 1423 PMD_INIT_LOG(ERR, "Failed to send driver version"); 1424 goto err_pf_setup; 1425 } 1426 1427 vsi = pf->main_vsi; 1428 1429 /* Disable double vlan by default */ 1430 ice_vsi_config_double_vlan(vsi, FALSE); 1431 1432 ret = ice_aq_stop_lldp(hw, TRUE, NULL); 1433 if (ret != ICE_SUCCESS) 1434 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 1435 1436 /* register callback func to eal lib */ 1437 rte_intr_callback_register(intr_handle, 1438 ice_interrupt_handler, dev); 1439 1440 ice_pf_enable_irq0(hw); 1441 1442 /* enable uio intr after callback register */ 1443 rte_intr_enable(intr_handle); 1444 1445 return 0; 1446 1447 err_pf_setup: 1448 ice_res_pool_destroy(&pf->msix_pool); 1449 err_msix_pool_init: 1450 rte_free(dev->data->mac_addrs); 1451 err_init_mac: 1452 ice_sched_cleanup_all(hw); 1453 rte_free(hw->port_info); 1454 ice_shutdown_all_ctrlq(hw); 1455 1456 return ret; 1457 } 1458 1459 static int 1460 ice_release_vsi(struct ice_vsi *vsi) 1461 { 1462 struct ice_hw *hw; 1463 struct ice_vsi_ctx vsi_ctx; 1464 enum ice_status ret; 1465 1466 if (!vsi) 1467 return 0; 1468 1469 hw = ICE_VSI_TO_HW(vsi); 1470 1471 ice_remove_all_mac_vlan_filters(vsi); 1472 1473 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1474 1475 vsi_ctx.vsi_num = vsi->vsi_id; 1476 vsi_ctx.info = vsi->info; 1477 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 1478 if (ret != ICE_SUCCESS) { 1479 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 1480 rte_free(vsi); 1481 return -1; 1482 } 1483 1484 rte_free(vsi); 1485 return 0; 1486 } 1487 1488 static void 1489 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 1490 { 1491 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1492 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1493 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1494 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1495 uint16_t msix_intr, i; 1496 1497 /* disable interrupt and also clear all the exist config */ 1498 for (i = 0; i < vsi->nb_qps; i++) { 1499 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 1500 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 1501 rte_wmb(); 1502 } 1503 1504 if (rte_intr_allow_others(intr_handle)) 1505 /* vfio-pci */ 1506 for (i = 0; i < vsi->nb_msix; i++) { 1507 msix_intr = vsi->msix_intr + i; 1508 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 1509 GLINT_DYN_CTL_WB_ON_ITR_M); 1510 } 1511 else 1512 /* igb_uio */ 1513 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1514 } 1515 1516 static void 1517 ice_dev_stop(struct rte_eth_dev *dev) 1518 { 1519 struct rte_eth_dev_data *data = dev->data; 1520 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1521 struct ice_vsi *main_vsi = pf->main_vsi; 1522 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1523 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1524 uint16_t i; 1525 1526 /* avoid stopping again */ 1527 if (pf->adapter_stopped) 1528 return; 1529 1530 /* stop and clear all Rx queues */ 1531 for (i = 0; i < data->nb_rx_queues; i++) 1532 ice_rx_queue_stop(dev, i); 1533 1534 /* stop and clear all Tx queues */ 1535 for (i = 0; i < data->nb_tx_queues; i++) 1536 ice_tx_queue_stop(dev, i); 1537 1538 /* disable all queue interrupts */ 1539 ice_vsi_disable_queues_intr(main_vsi); 1540 1541 /* Clear all queues and release mbufs */ 1542 ice_clear_queues(dev); 1543 1544 /* Clean datapath event and queue/vec mapping */ 1545 rte_intr_efd_disable(intr_handle); 1546 if (intr_handle->intr_vec) { 1547 rte_free(intr_handle->intr_vec); 1548 intr_handle->intr_vec = NULL; 1549 } 1550 1551 pf->adapter_stopped = true; 1552 } 1553 1554 static void 1555 ice_dev_close(struct rte_eth_dev *dev) 1556 { 1557 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1558 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1559 1560 ice_dev_stop(dev); 1561 1562 /* release all queue resource */ 1563 ice_free_queues(dev); 1564 1565 ice_res_pool_destroy(&pf->msix_pool); 1566 ice_release_vsi(pf->main_vsi); 1567 ice_sched_cleanup_all(hw); 1568 rte_free(hw->port_info); 1569 ice_shutdown_all_ctrlq(hw); 1570 } 1571 1572 static int 1573 ice_dev_uninit(struct rte_eth_dev *dev) 1574 { 1575 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1576 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1577 1578 ice_dev_close(dev); 1579 1580 dev->dev_ops = NULL; 1581 dev->rx_pkt_burst = NULL; 1582 dev->tx_pkt_burst = NULL; 1583 1584 rte_free(dev->data->mac_addrs); 1585 dev->data->mac_addrs = NULL; 1586 1587 /* disable uio intr before callback unregister */ 1588 rte_intr_disable(intr_handle); 1589 1590 /* register callback func to eal lib */ 1591 rte_intr_callback_unregister(intr_handle, 1592 ice_interrupt_handler, dev); 1593 1594 return 0; 1595 } 1596 1597 static int 1598 ice_dev_configure(__rte_unused struct rte_eth_dev *dev) 1599 { 1600 struct ice_adapter *ad = 1601 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1602 1603 /* Initialize to TRUE. If any of Rx queues doesn't meet the 1604 * bulk allocation or vector Rx preconditions we will reset it. 1605 */ 1606 ad->rx_bulk_alloc_allowed = true; 1607 ad->tx_simple_allowed = true; 1608 1609 return 0; 1610 } 1611 1612 static int ice_init_rss(struct ice_pf *pf) 1613 { 1614 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1615 struct ice_vsi *vsi = pf->main_vsi; 1616 struct rte_eth_dev *dev = pf->adapter->eth_dev; 1617 struct rte_eth_rss_conf *rss_conf; 1618 struct ice_aqc_get_set_rss_keys key; 1619 uint16_t i, nb_q; 1620 int ret = 0; 1621 bool is_safe_mode = pf->adapter->is_safe_mode; 1622 1623 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 1624 nb_q = dev->data->nb_rx_queues; 1625 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 1626 vsi->rss_lut_size = hw->func_caps.common_cap.rss_table_size; 1627 1628 if (is_safe_mode) { 1629 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 1630 return 0; 1631 } 1632 1633 if (!vsi->rss_key) 1634 vsi->rss_key = rte_zmalloc(NULL, 1635 vsi->rss_key_size, 0); 1636 if (!vsi->rss_lut) 1637 vsi->rss_lut = rte_zmalloc(NULL, 1638 vsi->rss_lut_size, 0); 1639 1640 /* configure RSS key */ 1641 if (!rss_conf->rss_key) { 1642 /* Calculate the default hash key */ 1643 for (i = 0; i <= vsi->rss_key_size; i++) 1644 vsi->rss_key[i] = (uint8_t)rte_rand(); 1645 } else { 1646 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 1647 RTE_MIN(rss_conf->rss_key_len, 1648 vsi->rss_key_size)); 1649 } 1650 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 1651 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 1652 if (ret) 1653 return -EINVAL; 1654 1655 /* init RSS LUT table */ 1656 for (i = 0; i < vsi->rss_lut_size; i++) 1657 vsi->rss_lut[i] = i % nb_q; 1658 1659 ret = ice_aq_set_rss_lut(hw, vsi->idx, 1660 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, 1661 vsi->rss_lut, vsi->rss_lut_size); 1662 if (ret) 1663 return -EINVAL; 1664 1665 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */ 1666 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6, 1667 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6); 1668 if (ret) 1669 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret); 1670 1671 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */ 1672 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6, 1673 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6); 1674 if (ret) 1675 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret); 1676 1677 /* configure RSS for sctp6 with input set IPv6 src/dst */ 1678 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 1679 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6); 1680 if (ret) 1681 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 1682 __func__, ret); 1683 1684 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */ 1685 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4, 1686 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4); 1687 if (ret) 1688 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret); 1689 1690 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */ 1691 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4, 1692 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4); 1693 if (ret) 1694 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret); 1695 1696 /* configure RSS for sctp4 with input set IP src/dst */ 1697 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 1698 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4); 1699 if (ret) 1700 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 1701 __func__, ret); 1702 1703 return 0; 1704 } 1705 1706 static void 1707 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 1708 int base_queue, int nb_queue) 1709 { 1710 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1711 uint32_t val, val_tx; 1712 int i; 1713 1714 for (i = 0; i < nb_queue; i++) { 1715 /*do actual bind*/ 1716 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 1717 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 1718 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 1719 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 1720 1721 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 1722 base_queue + i, msix_vect); 1723 /* set ITR0 value */ 1724 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); 1725 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 1726 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 1727 } 1728 } 1729 1730 static void 1731 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 1732 { 1733 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1734 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1735 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1736 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1737 uint16_t msix_vect = vsi->msix_intr; 1738 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 1739 uint16_t queue_idx = 0; 1740 int record = 0; 1741 int i; 1742 1743 /* clear Rx/Tx queue interrupt */ 1744 for (i = 0; i < vsi->nb_used_qps; i++) { 1745 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 1746 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 1747 } 1748 1749 /* PF bind interrupt */ 1750 if (rte_intr_dp_is_en(intr_handle)) { 1751 queue_idx = 0; 1752 record = 1; 1753 } 1754 1755 for (i = 0; i < vsi->nb_used_qps; i++) { 1756 if (nb_msix <= 1) { 1757 if (!rte_intr_allow_others(intr_handle)) 1758 msix_vect = ICE_MISC_VEC_ID; 1759 1760 /* uio mapping all queue to one msix_vect */ 1761 __vsi_queues_bind_intr(vsi, msix_vect, 1762 vsi->base_queue + i, 1763 vsi->nb_used_qps - i); 1764 1765 for (; !!record && i < vsi->nb_used_qps; i++) 1766 intr_handle->intr_vec[queue_idx + i] = 1767 msix_vect; 1768 break; 1769 } 1770 1771 /* vfio 1:1 queue/msix_vect mapping */ 1772 __vsi_queues_bind_intr(vsi, msix_vect, 1773 vsi->base_queue + i, 1); 1774 1775 if (!!record) 1776 intr_handle->intr_vec[queue_idx + i] = msix_vect; 1777 1778 msix_vect++; 1779 nb_msix--; 1780 } 1781 } 1782 1783 static void 1784 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 1785 { 1786 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1787 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1788 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1789 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1790 uint16_t msix_intr, i; 1791 1792 if (rte_intr_allow_others(intr_handle)) 1793 for (i = 0; i < vsi->nb_used_qps; i++) { 1794 msix_intr = vsi->msix_intr + i; 1795 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 1796 GLINT_DYN_CTL_INTENA_M | 1797 GLINT_DYN_CTL_CLEARPBA_M | 1798 GLINT_DYN_CTL_ITR_INDX_M | 1799 GLINT_DYN_CTL_WB_ON_ITR_M); 1800 } 1801 else 1802 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1803 GLINT_DYN_CTL_INTENA_M | 1804 GLINT_DYN_CTL_CLEARPBA_M | 1805 GLINT_DYN_CTL_ITR_INDX_M | 1806 GLINT_DYN_CTL_WB_ON_ITR_M); 1807 } 1808 1809 static int 1810 ice_rxq_intr_setup(struct rte_eth_dev *dev) 1811 { 1812 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1813 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 1814 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1815 struct ice_vsi *vsi = pf->main_vsi; 1816 uint32_t intr_vector = 0; 1817 1818 rte_intr_disable(intr_handle); 1819 1820 /* check and configure queue intr-vector mapping */ 1821 if ((rte_intr_cap_multiple(intr_handle) || 1822 !RTE_ETH_DEV_SRIOV(dev).active) && 1823 dev->data->dev_conf.intr_conf.rxq != 0) { 1824 intr_vector = dev->data->nb_rx_queues; 1825 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 1826 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 1827 ICE_MAX_INTR_QUEUE_NUM); 1828 return -ENOTSUP; 1829 } 1830 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1831 return -1; 1832 } 1833 1834 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1835 intr_handle->intr_vec = 1836 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 1837 0); 1838 if (!intr_handle->intr_vec) { 1839 PMD_DRV_LOG(ERR, 1840 "Failed to allocate %d rx_queues intr_vec", 1841 dev->data->nb_rx_queues); 1842 return -ENOMEM; 1843 } 1844 } 1845 1846 /* Map queues with MSIX interrupt */ 1847 vsi->nb_used_qps = dev->data->nb_rx_queues; 1848 ice_vsi_queues_bind_intr(vsi); 1849 1850 /* Enable interrupts for all the queues */ 1851 ice_vsi_enable_queues_intr(vsi); 1852 1853 rte_intr_enable(intr_handle); 1854 1855 return 0; 1856 } 1857 1858 static int 1859 ice_dev_start(struct rte_eth_dev *dev) 1860 { 1861 struct rte_eth_dev_data *data = dev->data; 1862 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1863 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1864 struct ice_vsi *vsi = pf->main_vsi; 1865 uint16_t nb_rxq = 0; 1866 uint16_t nb_txq, i; 1867 int mask, ret; 1868 1869 /* program Tx queues' context in hardware */ 1870 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 1871 ret = ice_tx_queue_start(dev, nb_txq); 1872 if (ret) { 1873 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 1874 goto tx_err; 1875 } 1876 } 1877 1878 /* program Rx queues' context in hardware*/ 1879 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 1880 ret = ice_rx_queue_start(dev, nb_rxq); 1881 if (ret) { 1882 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 1883 goto rx_err; 1884 } 1885 } 1886 1887 ret = ice_init_rss(pf); 1888 if (ret) { 1889 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 1890 goto rx_err; 1891 } 1892 1893 ice_set_rx_function(dev); 1894 ice_set_tx_function(dev); 1895 1896 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 1897 ETH_VLAN_EXTEND_MASK; 1898 ret = ice_vlan_offload_set(dev, mask); 1899 if (ret) { 1900 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 1901 goto rx_err; 1902 } 1903 1904 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 1905 if (ice_rxq_intr_setup(dev)) 1906 return -EIO; 1907 1908 /* Enable receiving broadcast packets and transmitting packets */ 1909 ret = ice_set_vsi_promisc(hw, vsi->idx, 1910 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 1911 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 1912 0); 1913 if (ret != ICE_SUCCESS) 1914 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 1915 1916 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 1917 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 1918 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 1919 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 1920 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 1921 ICE_AQ_LINK_EVENT_AN_COMPLETED | 1922 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 1923 NULL); 1924 if (ret != ICE_SUCCESS) 1925 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 1926 1927 /* Call get_link_info aq commond to enable/disable LSE */ 1928 ice_link_update(dev, 0); 1929 1930 pf->adapter_stopped = false; 1931 1932 return 0; 1933 1934 /* stop the started queues if failed to start all queues */ 1935 rx_err: 1936 for (i = 0; i < nb_rxq; i++) 1937 ice_rx_queue_stop(dev, i); 1938 tx_err: 1939 for (i = 0; i < nb_txq; i++) 1940 ice_tx_queue_stop(dev, i); 1941 1942 return -EIO; 1943 } 1944 1945 static int 1946 ice_dev_reset(struct rte_eth_dev *dev) 1947 { 1948 int ret; 1949 1950 if (dev->data->sriov.active) 1951 return -ENOTSUP; 1952 1953 ret = ice_dev_uninit(dev); 1954 if (ret) { 1955 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 1956 return -ENXIO; 1957 } 1958 1959 ret = ice_dev_init(dev); 1960 if (ret) { 1961 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 1962 return -ENXIO; 1963 } 1964 1965 return 0; 1966 } 1967 1968 static void 1969 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1970 { 1971 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1972 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1973 struct ice_vsi *vsi = pf->main_vsi; 1974 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1975 bool is_safe_mode = pf->adapter->is_safe_mode; 1976 u64 phy_type_low; 1977 u64 phy_type_high; 1978 1979 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 1980 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 1981 dev_info->max_rx_queues = vsi->nb_qps; 1982 dev_info->max_tx_queues = vsi->nb_qps; 1983 dev_info->max_mac_addrs = vsi->max_macaddrs; 1984 dev_info->max_vfs = pci_dev->max_vfs; 1985 1986 dev_info->rx_offload_capa = 1987 DEV_RX_OFFLOAD_VLAN_STRIP | 1988 DEV_RX_OFFLOAD_JUMBO_FRAME | 1989 DEV_RX_OFFLOAD_KEEP_CRC | 1990 DEV_RX_OFFLOAD_SCATTER | 1991 DEV_RX_OFFLOAD_VLAN_FILTER; 1992 dev_info->tx_offload_capa = 1993 DEV_TX_OFFLOAD_VLAN_INSERT | 1994 DEV_TX_OFFLOAD_TCP_TSO | 1995 DEV_TX_OFFLOAD_MULTI_SEGS | 1996 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 1997 dev_info->flow_type_rss_offloads = 0; 1998 1999 if (!is_safe_mode) { 2000 dev_info->rx_offload_capa |= 2001 DEV_RX_OFFLOAD_IPV4_CKSUM | 2002 DEV_RX_OFFLOAD_UDP_CKSUM | 2003 DEV_RX_OFFLOAD_TCP_CKSUM | 2004 DEV_RX_OFFLOAD_QINQ_STRIP | 2005 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2006 DEV_RX_OFFLOAD_VLAN_EXTEND; 2007 dev_info->tx_offload_capa |= 2008 DEV_TX_OFFLOAD_QINQ_INSERT | 2009 DEV_TX_OFFLOAD_IPV4_CKSUM | 2010 DEV_TX_OFFLOAD_UDP_CKSUM | 2011 DEV_TX_OFFLOAD_TCP_CKSUM | 2012 DEV_TX_OFFLOAD_SCTP_CKSUM | 2013 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 2014 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 2015 } 2016 2017 dev_info->rx_queue_offload_capa = 0; 2018 dev_info->tx_queue_offload_capa = 0; 2019 2020 dev_info->reta_size = hw->func_caps.common_cap.rss_table_size; 2021 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2022 2023 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2024 .rx_thresh = { 2025 .pthresh = ICE_DEFAULT_RX_PTHRESH, 2026 .hthresh = ICE_DEFAULT_RX_HTHRESH, 2027 .wthresh = ICE_DEFAULT_RX_WTHRESH, 2028 }, 2029 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 2030 .rx_drop_en = 0, 2031 .offloads = 0, 2032 }; 2033 2034 dev_info->default_txconf = (struct rte_eth_txconf) { 2035 .tx_thresh = { 2036 .pthresh = ICE_DEFAULT_TX_PTHRESH, 2037 .hthresh = ICE_DEFAULT_TX_HTHRESH, 2038 .wthresh = ICE_DEFAULT_TX_WTHRESH, 2039 }, 2040 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 2041 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 2042 .offloads = 0, 2043 }; 2044 2045 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 2046 .nb_max = ICE_MAX_RING_DESC, 2047 .nb_min = ICE_MIN_RING_DESC, 2048 .nb_align = ICE_ALIGN_RING_DESC, 2049 }; 2050 2051 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 2052 .nb_max = ICE_MAX_RING_DESC, 2053 .nb_min = ICE_MIN_RING_DESC, 2054 .nb_align = ICE_ALIGN_RING_DESC, 2055 }; 2056 2057 dev_info->speed_capa = ETH_LINK_SPEED_10M | 2058 ETH_LINK_SPEED_100M | 2059 ETH_LINK_SPEED_1G | 2060 ETH_LINK_SPEED_2_5G | 2061 ETH_LINK_SPEED_5G | 2062 ETH_LINK_SPEED_10G | 2063 ETH_LINK_SPEED_20G | 2064 ETH_LINK_SPEED_25G; 2065 2066 phy_type_low = hw->port_info->phy.phy_type_low; 2067 phy_type_high = hw->port_info->phy.phy_type_high; 2068 2069 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 2070 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 2071 2072 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 2073 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 2074 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 2075 2076 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 2077 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 2078 2079 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 2080 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 2081 dev_info->default_rxportconf.nb_queues = 1; 2082 dev_info->default_txportconf.nb_queues = 1; 2083 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 2084 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 2085 } 2086 2087 static inline int 2088 ice_atomic_read_link_status(struct rte_eth_dev *dev, 2089 struct rte_eth_link *link) 2090 { 2091 struct rte_eth_link *dst = link; 2092 struct rte_eth_link *src = &dev->data->dev_link; 2093 2094 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 2095 *(uint64_t *)src) == 0) 2096 return -1; 2097 2098 return 0; 2099 } 2100 2101 static inline int 2102 ice_atomic_write_link_status(struct rte_eth_dev *dev, 2103 struct rte_eth_link *link) 2104 { 2105 struct rte_eth_link *dst = &dev->data->dev_link; 2106 struct rte_eth_link *src = link; 2107 2108 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 2109 *(uint64_t *)src) == 0) 2110 return -1; 2111 2112 return 0; 2113 } 2114 2115 static int 2116 ice_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete) 2117 { 2118 #define CHECK_INTERVAL 100 /* 100ms */ 2119 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 2120 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2121 struct ice_link_status link_status; 2122 struct rte_eth_link link, old; 2123 int status; 2124 unsigned int rep_cnt = MAX_REPEAT_TIME; 2125 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2126 2127 memset(&link, 0, sizeof(link)); 2128 memset(&old, 0, sizeof(old)); 2129 memset(&link_status, 0, sizeof(link_status)); 2130 ice_atomic_read_link_status(dev, &old); 2131 2132 do { 2133 /* Get link status information from hardware */ 2134 status = ice_aq_get_link_info(hw->port_info, enable_lse, 2135 &link_status, NULL); 2136 if (status != ICE_SUCCESS) { 2137 link.link_speed = ETH_SPEED_NUM_100M; 2138 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2139 PMD_DRV_LOG(ERR, "Failed to get link info"); 2140 goto out; 2141 } 2142 2143 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 2144 if (!wait_to_complete || link.link_status) 2145 break; 2146 2147 rte_delay_ms(CHECK_INTERVAL); 2148 } while (--rep_cnt); 2149 2150 if (!link.link_status) 2151 goto out; 2152 2153 /* Full-duplex operation at all supported speeds */ 2154 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2155 2156 /* Parse the link status */ 2157 switch (link_status.link_speed) { 2158 case ICE_AQ_LINK_SPEED_10MB: 2159 link.link_speed = ETH_SPEED_NUM_10M; 2160 break; 2161 case ICE_AQ_LINK_SPEED_100MB: 2162 link.link_speed = ETH_SPEED_NUM_100M; 2163 break; 2164 case ICE_AQ_LINK_SPEED_1000MB: 2165 link.link_speed = ETH_SPEED_NUM_1G; 2166 break; 2167 case ICE_AQ_LINK_SPEED_2500MB: 2168 link.link_speed = ETH_SPEED_NUM_2_5G; 2169 break; 2170 case ICE_AQ_LINK_SPEED_5GB: 2171 link.link_speed = ETH_SPEED_NUM_5G; 2172 break; 2173 case ICE_AQ_LINK_SPEED_10GB: 2174 link.link_speed = ETH_SPEED_NUM_10G; 2175 break; 2176 case ICE_AQ_LINK_SPEED_20GB: 2177 link.link_speed = ETH_SPEED_NUM_20G; 2178 break; 2179 case ICE_AQ_LINK_SPEED_25GB: 2180 link.link_speed = ETH_SPEED_NUM_25G; 2181 break; 2182 case ICE_AQ_LINK_SPEED_40GB: 2183 link.link_speed = ETH_SPEED_NUM_40G; 2184 break; 2185 case ICE_AQ_LINK_SPEED_50GB: 2186 link.link_speed = ETH_SPEED_NUM_50G; 2187 break; 2188 case ICE_AQ_LINK_SPEED_100GB: 2189 link.link_speed = ETH_SPEED_NUM_100G; 2190 break; 2191 case ICE_AQ_LINK_SPEED_UNKNOWN: 2192 default: 2193 PMD_DRV_LOG(ERR, "Unknown link speed"); 2194 link.link_speed = ETH_SPEED_NUM_NONE; 2195 break; 2196 } 2197 2198 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2199 ETH_LINK_SPEED_FIXED); 2200 2201 out: 2202 ice_atomic_write_link_status(dev, &link); 2203 if (link.link_status == old.link_status) 2204 return -1; 2205 2206 return 0; 2207 } 2208 2209 static int 2210 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2211 { 2212 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2213 struct rte_eth_dev_data *dev_data = pf->dev_data; 2214 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 2215 2216 /* check if mtu is within the allowed range */ 2217 if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 2218 return -EINVAL; 2219 2220 /* mtu setting is forbidden if port is start */ 2221 if (dev_data->dev_started) { 2222 PMD_DRV_LOG(ERR, 2223 "port %d must be stopped before configuration", 2224 dev_data->port_id); 2225 return -EBUSY; 2226 } 2227 2228 if (frame_size > ETHER_MAX_LEN) 2229 dev_data->dev_conf.rxmode.offloads |= 2230 DEV_RX_OFFLOAD_JUMBO_FRAME; 2231 else 2232 dev_data->dev_conf.rxmode.offloads &= 2233 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2234 2235 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2236 2237 return 0; 2238 } 2239 2240 static int ice_macaddr_set(struct rte_eth_dev *dev, 2241 struct ether_addr *mac_addr) 2242 { 2243 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2244 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2245 struct ice_vsi *vsi = pf->main_vsi; 2246 struct ice_mac_filter *f; 2247 uint8_t flags = 0; 2248 int ret; 2249 2250 if (!is_valid_assigned_ether_addr(mac_addr)) { 2251 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 2252 return -EINVAL; 2253 } 2254 2255 TAILQ_FOREACH(f, &vsi->mac_list, next) { 2256 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 2257 break; 2258 } 2259 2260 if (!f) { 2261 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 2262 return -EIO; 2263 } 2264 2265 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 2266 if (ret != ICE_SUCCESS) { 2267 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 2268 return -EIO; 2269 } 2270 ret = ice_add_mac_filter(vsi, mac_addr); 2271 if (ret != ICE_SUCCESS) { 2272 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 2273 return -EIO; 2274 } 2275 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN); 2276 2277 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 2278 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 2279 if (ret != ICE_SUCCESS) 2280 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 2281 2282 return 0; 2283 } 2284 2285 /* Add a MAC address, and update filters */ 2286 static int 2287 ice_macaddr_add(struct rte_eth_dev *dev, 2288 struct ether_addr *mac_addr, 2289 __rte_unused uint32_t index, 2290 __rte_unused uint32_t pool) 2291 { 2292 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2293 struct ice_vsi *vsi = pf->main_vsi; 2294 int ret; 2295 2296 ret = ice_add_mac_filter(vsi, mac_addr); 2297 if (ret != ICE_SUCCESS) { 2298 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 2299 return -EINVAL; 2300 } 2301 2302 return ICE_SUCCESS; 2303 } 2304 2305 /* Remove a MAC address, and update filters */ 2306 static void 2307 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 2308 { 2309 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2310 struct ice_vsi *vsi = pf->main_vsi; 2311 struct rte_eth_dev_data *data = dev->data; 2312 struct ether_addr *macaddr; 2313 int ret; 2314 2315 macaddr = &data->mac_addrs[index]; 2316 ret = ice_remove_mac_filter(vsi, macaddr); 2317 if (ret) { 2318 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 2319 return; 2320 } 2321 } 2322 2323 static int 2324 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 2325 { 2326 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2327 struct ice_vsi *vsi = pf->main_vsi; 2328 int ret; 2329 2330 PMD_INIT_FUNC_TRACE(); 2331 2332 if (on) { 2333 ret = ice_add_vlan_filter(vsi, vlan_id); 2334 if (ret < 0) { 2335 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 2336 return -EINVAL; 2337 } 2338 } else { 2339 ret = ice_remove_vlan_filter(vsi, vlan_id); 2340 if (ret < 0) { 2341 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 2342 return -EINVAL; 2343 } 2344 } 2345 2346 return 0; 2347 } 2348 2349 /* Configure vlan filter on or off */ 2350 static int 2351 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 2352 { 2353 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2354 struct ice_vsi_ctx ctxt; 2355 uint8_t sec_flags, sw_flags2; 2356 int ret = 0; 2357 2358 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 2359 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 2360 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 2361 2362 if (on) { 2363 vsi->info.sec_flags |= sec_flags; 2364 vsi->info.sw_flags2 |= sw_flags2; 2365 } else { 2366 vsi->info.sec_flags &= ~sec_flags; 2367 vsi->info.sw_flags2 &= ~sw_flags2; 2368 } 2369 vsi->info.sw_id = hw->port_info->sw_id; 2370 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2371 ctxt.info.valid_sections = 2372 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 2373 ICE_AQ_VSI_PROP_SECURITY_VALID); 2374 ctxt.vsi_num = vsi->vsi_id; 2375 2376 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2377 if (ret) { 2378 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 2379 on ? "enable" : "disable"); 2380 return -EINVAL; 2381 } else { 2382 vsi->info.valid_sections |= 2383 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 2384 ICE_AQ_VSI_PROP_SECURITY_VALID); 2385 } 2386 2387 /* consist with other drivers, allow untagged packet when vlan filter on */ 2388 if (on) 2389 ret = ice_add_vlan_filter(vsi, 0); 2390 else 2391 ret = ice_remove_vlan_filter(vsi, 0); 2392 2393 return 0; 2394 } 2395 2396 static int 2397 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 2398 { 2399 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2400 struct ice_vsi_ctx ctxt; 2401 uint8_t vlan_flags; 2402 int ret = 0; 2403 2404 /* Check if it has been already on or off */ 2405 if (vsi->info.valid_sections & 2406 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 2407 if (on) { 2408 if ((vsi->info.vlan_flags & 2409 ICE_AQ_VSI_VLAN_EMOD_M) == 2410 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) 2411 return 0; /* already on */ 2412 } else { 2413 if ((vsi->info.vlan_flags & 2414 ICE_AQ_VSI_VLAN_EMOD_M) == 2415 ICE_AQ_VSI_VLAN_EMOD_NOTHING) 2416 return 0; /* already off */ 2417 } 2418 } 2419 2420 if (on) 2421 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; 2422 else 2423 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; 2424 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); 2425 vsi->info.vlan_flags |= vlan_flags; 2426 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2427 ctxt.info.valid_sections = 2428 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2429 ctxt.vsi_num = vsi->vsi_id; 2430 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2431 if (ret) { 2432 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 2433 on ? "enable" : "disable"); 2434 return -EINVAL; 2435 } 2436 2437 vsi->info.valid_sections |= 2438 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2439 2440 return ret; 2441 } 2442 2443 static int 2444 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2445 { 2446 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2447 struct ice_vsi *vsi = pf->main_vsi; 2448 struct rte_eth_rxmode *rxmode; 2449 2450 rxmode = &dev->data->dev_conf.rxmode; 2451 if (mask & ETH_VLAN_FILTER_MASK) { 2452 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2453 ice_vsi_config_vlan_filter(vsi, TRUE); 2454 else 2455 ice_vsi_config_vlan_filter(vsi, FALSE); 2456 } 2457 2458 if (mask & ETH_VLAN_STRIP_MASK) { 2459 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2460 ice_vsi_config_vlan_stripping(vsi, TRUE); 2461 else 2462 ice_vsi_config_vlan_stripping(vsi, FALSE); 2463 } 2464 2465 if (mask & ETH_VLAN_EXTEND_MASK) { 2466 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2467 ice_vsi_config_double_vlan(vsi, TRUE); 2468 else 2469 ice_vsi_config_double_vlan(vsi, FALSE); 2470 } 2471 2472 return 0; 2473 } 2474 2475 static int 2476 ice_vlan_tpid_set(struct rte_eth_dev *dev, 2477 enum rte_vlan_type vlan_type, 2478 uint16_t tpid) 2479 { 2480 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2481 uint64_t reg_r = 0, reg_w = 0; 2482 uint16_t reg_id = 0; 2483 int ret = 0; 2484 int qinq = dev->data->dev_conf.rxmode.offloads & 2485 DEV_RX_OFFLOAD_VLAN_EXTEND; 2486 2487 switch (vlan_type) { 2488 case ETH_VLAN_TYPE_OUTER: 2489 if (qinq) 2490 reg_id = 3; 2491 else 2492 reg_id = 5; 2493 break; 2494 case ETH_VLAN_TYPE_INNER: 2495 if (qinq) { 2496 reg_id = 5; 2497 } else { 2498 PMD_DRV_LOG(ERR, 2499 "Unsupported vlan type in single vlan."); 2500 return -EINVAL; 2501 } 2502 break; 2503 default: 2504 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type); 2505 return -EINVAL; 2506 } 2507 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id)); 2508 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: " 2509 "0x%08"PRIx64"", reg_id, reg_r); 2510 2511 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M)); 2512 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S); 2513 if (reg_r == reg_w) { 2514 PMD_DRV_LOG(DEBUG, "No need to write"); 2515 return 0; 2516 } 2517 2518 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w); 2519 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to " 2520 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id); 2521 2522 return ret; 2523 } 2524 2525 static int 2526 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2527 { 2528 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 2529 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2530 int ret; 2531 2532 if (!lut) 2533 return -EINVAL; 2534 2535 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 2536 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE, 2537 lut, lut_size); 2538 if (ret) { 2539 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 2540 return -EINVAL; 2541 } 2542 } else { 2543 uint64_t *lut_dw = (uint64_t *)lut; 2544 uint16_t i, lut_size_dw = lut_size / 4; 2545 2546 for (i = 0; i < lut_size_dw; i++) 2547 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 2548 } 2549 2550 return 0; 2551 } 2552 2553 static int 2554 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2555 { 2556 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 2557 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2558 int ret; 2559 2560 if (!vsi || !lut) 2561 return -EINVAL; 2562 2563 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 2564 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE, 2565 lut, lut_size); 2566 if (ret) { 2567 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 2568 return -EINVAL; 2569 } 2570 } else { 2571 uint64_t *lut_dw = (uint64_t *)lut; 2572 uint16_t i, lut_size_dw = lut_size / 4; 2573 2574 for (i = 0; i < lut_size_dw; i++) 2575 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 2576 2577 ice_flush(hw); 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int 2584 ice_rss_reta_update(struct rte_eth_dev *dev, 2585 struct rte_eth_rss_reta_entry64 *reta_conf, 2586 uint16_t reta_size) 2587 { 2588 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2589 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2590 uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size; 2591 uint16_t idx, shift; 2592 uint8_t *lut; 2593 int ret; 2594 2595 if (reta_size != lut_size || 2596 reta_size > ETH_RSS_RETA_SIZE_512) { 2597 PMD_DRV_LOG(ERR, 2598 "The size of hash lookup table configured (%d)" 2599 "doesn't match the number hardware can " 2600 "supported (%d)", 2601 reta_size, lut_size); 2602 return -EINVAL; 2603 } 2604 2605 lut = rte_zmalloc(NULL, reta_size, 0); 2606 if (!lut) { 2607 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2608 return -ENOMEM; 2609 } 2610 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 2611 if (ret) 2612 goto out; 2613 2614 for (i = 0; i < reta_size; i++) { 2615 idx = i / RTE_RETA_GROUP_SIZE; 2616 shift = i % RTE_RETA_GROUP_SIZE; 2617 if (reta_conf[idx].mask & (1ULL << shift)) 2618 lut[i] = reta_conf[idx].reta[shift]; 2619 } 2620 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 2621 2622 out: 2623 rte_free(lut); 2624 2625 return ret; 2626 } 2627 2628 static int 2629 ice_rss_reta_query(struct rte_eth_dev *dev, 2630 struct rte_eth_rss_reta_entry64 *reta_conf, 2631 uint16_t reta_size) 2632 { 2633 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2634 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2635 uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size; 2636 uint16_t idx, shift; 2637 uint8_t *lut; 2638 int ret; 2639 2640 if (reta_size != lut_size || 2641 reta_size > ETH_RSS_RETA_SIZE_512) { 2642 PMD_DRV_LOG(ERR, 2643 "The size of hash lookup table configured (%d)" 2644 "doesn't match the number hardware can " 2645 "supported (%d)", 2646 reta_size, lut_size); 2647 return -EINVAL; 2648 } 2649 2650 lut = rte_zmalloc(NULL, reta_size, 0); 2651 if (!lut) { 2652 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2653 return -ENOMEM; 2654 } 2655 2656 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 2657 if (ret) 2658 goto out; 2659 2660 for (i = 0; i < reta_size; i++) { 2661 idx = i / RTE_RETA_GROUP_SIZE; 2662 shift = i % RTE_RETA_GROUP_SIZE; 2663 if (reta_conf[idx].mask & (1ULL << shift)) 2664 reta_conf[idx].reta[shift] = lut[i]; 2665 } 2666 2667 out: 2668 rte_free(lut); 2669 2670 return ret; 2671 } 2672 2673 static int 2674 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 2675 { 2676 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2677 int ret = 0; 2678 2679 if (!key || key_len == 0) { 2680 PMD_DRV_LOG(DEBUG, "No key to be configured"); 2681 return 0; 2682 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 2683 sizeof(uint32_t)) { 2684 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 2685 return -EINVAL; 2686 } 2687 2688 struct ice_aqc_get_set_rss_keys *key_dw = 2689 (struct ice_aqc_get_set_rss_keys *)key; 2690 2691 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 2692 if (ret) { 2693 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 2694 ret = -EINVAL; 2695 } 2696 2697 return ret; 2698 } 2699 2700 static int 2701 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 2702 { 2703 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2704 int ret; 2705 2706 if (!key || !key_len) 2707 return -EINVAL; 2708 2709 ret = ice_aq_get_rss_key 2710 (hw, vsi->idx, 2711 (struct ice_aqc_get_set_rss_keys *)key); 2712 if (ret) { 2713 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 2714 return -EINVAL; 2715 } 2716 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2717 2718 return 0; 2719 } 2720 2721 static int 2722 ice_rss_hash_update(struct rte_eth_dev *dev, 2723 struct rte_eth_rss_conf *rss_conf) 2724 { 2725 enum ice_status status = ICE_SUCCESS; 2726 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2727 struct ice_vsi *vsi = pf->main_vsi; 2728 2729 /* set hash key */ 2730 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 2731 if (status) 2732 return status; 2733 2734 /* TODO: hash enable config, ice_add_rss_cfg */ 2735 return 0; 2736 } 2737 2738 static int 2739 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 2740 struct rte_eth_rss_conf *rss_conf) 2741 { 2742 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2743 struct ice_vsi *vsi = pf->main_vsi; 2744 2745 ice_get_rss_key(vsi, rss_conf->rss_key, 2746 &rss_conf->rss_key_len); 2747 2748 /* TODO: default set to 0 as hf config is not supported now */ 2749 rss_conf->rss_hf = 0; 2750 return 0; 2751 } 2752 2753 static void 2754 ice_promisc_enable(struct rte_eth_dev *dev) 2755 { 2756 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2757 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2758 struct ice_vsi *vsi = pf->main_vsi; 2759 uint8_t pmask; 2760 uint16_t status; 2761 2762 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 2763 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2764 2765 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 2766 if (status != ICE_SUCCESS) 2767 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 2768 } 2769 2770 static void 2771 ice_promisc_disable(struct rte_eth_dev *dev) 2772 { 2773 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2774 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2775 struct ice_vsi *vsi = pf->main_vsi; 2776 uint16_t status; 2777 uint8_t pmask; 2778 2779 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 2780 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2781 2782 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 2783 if (status != ICE_SUCCESS) 2784 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 2785 } 2786 2787 static void 2788 ice_allmulti_enable(struct rte_eth_dev *dev) 2789 { 2790 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2791 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2792 struct ice_vsi *vsi = pf->main_vsi; 2793 uint8_t pmask; 2794 uint16_t status; 2795 2796 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2797 2798 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 2799 if (status != ICE_SUCCESS) 2800 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 2801 } 2802 2803 static void 2804 ice_allmulti_disable(struct rte_eth_dev *dev) 2805 { 2806 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2807 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2808 struct ice_vsi *vsi = pf->main_vsi; 2809 uint16_t status; 2810 uint8_t pmask; 2811 2812 if (dev->data->promiscuous == 1) 2813 return; /* must remain in all_multicast mode */ 2814 2815 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 2816 2817 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 2818 if (status != ICE_SUCCESS) 2819 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 2820 } 2821 2822 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 2823 uint16_t queue_id) 2824 { 2825 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2826 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2827 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2828 uint32_t val; 2829 uint16_t msix_intr; 2830 2831 msix_intr = intr_handle->intr_vec[queue_id]; 2832 2833 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 2834 GLINT_DYN_CTL_ITR_INDX_M; 2835 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 2836 2837 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 2838 rte_intr_enable(&pci_dev->intr_handle); 2839 2840 return 0; 2841 } 2842 2843 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 2844 uint16_t queue_id) 2845 { 2846 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2847 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2848 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2849 uint16_t msix_intr; 2850 2851 msix_intr = intr_handle->intr_vec[queue_id]; 2852 2853 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 2854 2855 return 0; 2856 } 2857 2858 static int 2859 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2860 { 2861 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2862 u32 full_ver; 2863 u8 ver, patch; 2864 u16 build; 2865 int ret; 2866 2867 full_ver = hw->nvm.oem_ver; 2868 ver = (u8)(full_ver >> 24); 2869 build = (u16)((full_ver >> 8) & 0xffff); 2870 patch = (u8)(full_ver & 0xff); 2871 2872 ret = snprintf(fw_version, fw_size, 2873 "%d.%d%d 0x%08x %d.%d.%d", 2874 ((hw->nvm.ver >> 12) & 0xf), 2875 ((hw->nvm.ver >> 4) & 0xff), 2876 (hw->nvm.ver & 0xf), hw->nvm.eetrack, 2877 ver, build, patch); 2878 2879 /* add the size of '\0' */ 2880 ret += 1; 2881 if (fw_size < (u32)ret) 2882 return ret; 2883 else 2884 return 0; 2885 } 2886 2887 static int 2888 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 2889 { 2890 struct ice_hw *hw; 2891 struct ice_vsi_ctx ctxt; 2892 uint8_t vlan_flags = 0; 2893 int ret; 2894 2895 if (!vsi || !info) { 2896 PMD_DRV_LOG(ERR, "invalid parameters"); 2897 return -EINVAL; 2898 } 2899 2900 if (info->on) { 2901 vsi->info.pvid = info->config.pvid; 2902 /** 2903 * If insert pvid is enabled, only tagged pkts are 2904 * allowed to be sent out. 2905 */ 2906 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | 2907 ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 2908 } else { 2909 vsi->info.pvid = 0; 2910 if (info->config.reject.tagged == 0) 2911 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; 2912 2913 if (info->config.reject.untagged == 0) 2914 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 2915 } 2916 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | 2917 ICE_AQ_VSI_VLAN_MODE_M); 2918 vsi->info.vlan_flags |= vlan_flags; 2919 memset(&ctxt, 0, sizeof(ctxt)); 2920 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 2921 ctxt.info.valid_sections = 2922 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2923 ctxt.vsi_num = vsi->vsi_id; 2924 2925 hw = ICE_VSI_TO_HW(vsi); 2926 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 2927 if (ret != ICE_SUCCESS) { 2928 PMD_DRV_LOG(ERR, 2929 "update VSI for VLAN insert failed, err %d", 2930 ret); 2931 return -EINVAL; 2932 } 2933 2934 vsi->info.valid_sections |= 2935 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 2936 2937 return ret; 2938 } 2939 2940 static int 2941 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 2942 { 2943 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2944 struct ice_vsi *vsi = pf->main_vsi; 2945 struct rte_eth_dev_data *data = pf->dev_data; 2946 struct ice_vsi_vlan_pvid_info info; 2947 int ret; 2948 2949 memset(&info, 0, sizeof(info)); 2950 info.on = on; 2951 if (info.on) { 2952 info.config.pvid = pvid; 2953 } else { 2954 info.config.reject.tagged = 2955 data->dev_conf.txmode.hw_vlan_reject_tagged; 2956 info.config.reject.untagged = 2957 data->dev_conf.txmode.hw_vlan_reject_untagged; 2958 } 2959 2960 ret = ice_vsi_vlan_pvid_set(vsi, &info); 2961 if (ret < 0) { 2962 PMD_DRV_LOG(ERR, "Failed to set pvid."); 2963 return -EINVAL; 2964 } 2965 2966 return 0; 2967 } 2968 2969 static int 2970 ice_get_eeprom_length(struct rte_eth_dev *dev) 2971 { 2972 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2973 2974 /* Convert word count to byte count */ 2975 return hw->nvm.sr_words << 1; 2976 } 2977 2978 static int 2979 ice_get_eeprom(struct rte_eth_dev *dev, 2980 struct rte_dev_eeprom_info *eeprom) 2981 { 2982 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2983 uint16_t *data = eeprom->data; 2984 uint16_t first_word, last_word, nwords; 2985 enum ice_status status = ICE_SUCCESS; 2986 2987 first_word = eeprom->offset >> 1; 2988 last_word = (eeprom->offset + eeprom->length - 1) >> 1; 2989 nwords = last_word - first_word + 1; 2990 2991 if (first_word > hw->nvm.sr_words || 2992 last_word > hw->nvm.sr_words) { 2993 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 2994 return -EINVAL; 2995 } 2996 2997 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 2998 2999 status = ice_read_sr_buf(hw, first_word, &nwords, data); 3000 if (status) { 3001 PMD_DRV_LOG(ERR, "EEPROM read failed."); 3002 eeprom->length = sizeof(uint16_t) * nwords; 3003 return -EIO; 3004 } 3005 3006 return 0; 3007 } 3008 3009 static void 3010 ice_stat_update_32(struct ice_hw *hw, 3011 uint32_t reg, 3012 bool offset_loaded, 3013 uint64_t *offset, 3014 uint64_t *stat) 3015 { 3016 uint64_t new_data; 3017 3018 new_data = (uint64_t)ICE_READ_REG(hw, reg); 3019 if (!offset_loaded) 3020 *offset = new_data; 3021 3022 if (new_data >= *offset) 3023 *stat = (uint64_t)(new_data - *offset); 3024 else 3025 *stat = (uint64_t)((new_data + 3026 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 3027 - *offset); 3028 } 3029 3030 static void 3031 ice_stat_update_40(struct ice_hw *hw, 3032 uint32_t hireg, 3033 uint32_t loreg, 3034 bool offset_loaded, 3035 uint64_t *offset, 3036 uint64_t *stat) 3037 { 3038 uint64_t new_data; 3039 3040 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 3041 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 3042 ICE_32_BIT_WIDTH; 3043 3044 if (!offset_loaded) 3045 *offset = new_data; 3046 3047 if (new_data >= *offset) 3048 *stat = new_data - *offset; 3049 else 3050 *stat = (uint64_t)((new_data + 3051 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 3052 *offset); 3053 3054 *stat &= ICE_40_BIT_MASK; 3055 } 3056 3057 /* Get all the statistics of a VSI */ 3058 static void 3059 ice_update_vsi_stats(struct ice_vsi *vsi) 3060 { 3061 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 3062 struct ice_eth_stats *nes = &vsi->eth_stats; 3063 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3064 int idx = rte_le_to_cpu_16(vsi->vsi_id); 3065 3066 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 3067 vsi->offset_loaded, &oes->rx_bytes, 3068 &nes->rx_bytes); 3069 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 3070 vsi->offset_loaded, &oes->rx_unicast, 3071 &nes->rx_unicast); 3072 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 3073 vsi->offset_loaded, &oes->rx_multicast, 3074 &nes->rx_multicast); 3075 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 3076 vsi->offset_loaded, &oes->rx_broadcast, 3077 &nes->rx_broadcast); 3078 /* exclude CRC bytes */ 3079 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 3080 nes->rx_broadcast) * ETHER_CRC_LEN; 3081 3082 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 3083 &oes->rx_discards, &nes->rx_discards); 3084 /* GLV_REPC not supported */ 3085 /* GLV_RMPC not supported */ 3086 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 3087 &oes->rx_unknown_protocol, 3088 &nes->rx_unknown_protocol); 3089 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 3090 vsi->offset_loaded, &oes->tx_bytes, 3091 &nes->tx_bytes); 3092 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 3093 vsi->offset_loaded, &oes->tx_unicast, 3094 &nes->tx_unicast); 3095 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 3096 vsi->offset_loaded, &oes->tx_multicast, 3097 &nes->tx_multicast); 3098 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 3099 vsi->offset_loaded, &oes->tx_broadcast, 3100 &nes->tx_broadcast); 3101 /* GLV_TDPC not supported */ 3102 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 3103 &oes->tx_errors, &nes->tx_errors); 3104 vsi->offset_loaded = true; 3105 3106 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 3107 vsi->vsi_id); 3108 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 3109 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 3110 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 3111 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 3112 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 3113 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3114 nes->rx_unknown_protocol); 3115 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 3116 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 3117 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 3118 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 3119 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 3120 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 3121 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 3122 vsi->vsi_id); 3123 } 3124 3125 static void 3126 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 3127 { 3128 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 3129 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 3130 3131 /* Get statistics of struct ice_eth_stats */ 3132 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 3133 GLPRT_GORCL(hw->port_info->lport), 3134 pf->offset_loaded, &os->eth.rx_bytes, 3135 &ns->eth.rx_bytes); 3136 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 3137 GLPRT_UPRCL(hw->port_info->lport), 3138 pf->offset_loaded, &os->eth.rx_unicast, 3139 &ns->eth.rx_unicast); 3140 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 3141 GLPRT_MPRCL(hw->port_info->lport), 3142 pf->offset_loaded, &os->eth.rx_multicast, 3143 &ns->eth.rx_multicast); 3144 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 3145 GLPRT_BPRCL(hw->port_info->lport), 3146 pf->offset_loaded, &os->eth.rx_broadcast, 3147 &ns->eth.rx_broadcast); 3148 ice_stat_update_32(hw, PRTRPB_RDPC, 3149 pf->offset_loaded, &os->eth.rx_discards, 3150 &ns->eth.rx_discards); 3151 3152 /* Workaround: CRC size should not be included in byte statistics, 3153 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet. 3154 */ 3155 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 3156 ns->eth.rx_broadcast) * ETHER_CRC_LEN; 3157 3158 /* GLPRT_REPC not supported */ 3159 /* GLPRT_RMPC not supported */ 3160 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 3161 pf->offset_loaded, 3162 &os->eth.rx_unknown_protocol, 3163 &ns->eth.rx_unknown_protocol); 3164 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 3165 GLPRT_GOTCL(hw->port_info->lport), 3166 pf->offset_loaded, &os->eth.tx_bytes, 3167 &ns->eth.tx_bytes); 3168 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 3169 GLPRT_UPTCL(hw->port_info->lport), 3170 pf->offset_loaded, &os->eth.tx_unicast, 3171 &ns->eth.tx_unicast); 3172 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 3173 GLPRT_MPTCL(hw->port_info->lport), 3174 pf->offset_loaded, &os->eth.tx_multicast, 3175 &ns->eth.tx_multicast); 3176 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 3177 GLPRT_BPTCL(hw->port_info->lport), 3178 pf->offset_loaded, &os->eth.tx_broadcast, 3179 &ns->eth.tx_broadcast); 3180 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 3181 ns->eth.tx_broadcast) * ETHER_CRC_LEN; 3182 3183 /* GLPRT_TEPC not supported */ 3184 3185 /* additional port specific stats */ 3186 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 3187 pf->offset_loaded, &os->tx_dropped_link_down, 3188 &ns->tx_dropped_link_down); 3189 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 3190 pf->offset_loaded, &os->crc_errors, 3191 &ns->crc_errors); 3192 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 3193 pf->offset_loaded, &os->illegal_bytes, 3194 &ns->illegal_bytes); 3195 /* GLPRT_ERRBC not supported */ 3196 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 3197 pf->offset_loaded, &os->mac_local_faults, 3198 &ns->mac_local_faults); 3199 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 3200 pf->offset_loaded, &os->mac_remote_faults, 3201 &ns->mac_remote_faults); 3202 3203 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 3204 pf->offset_loaded, &os->rx_len_errors, 3205 &ns->rx_len_errors); 3206 3207 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 3208 pf->offset_loaded, &os->link_xon_rx, 3209 &ns->link_xon_rx); 3210 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 3211 pf->offset_loaded, &os->link_xoff_rx, 3212 &ns->link_xoff_rx); 3213 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 3214 pf->offset_loaded, &os->link_xon_tx, 3215 &ns->link_xon_tx); 3216 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 3217 pf->offset_loaded, &os->link_xoff_tx, 3218 &ns->link_xoff_tx); 3219 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 3220 GLPRT_PRC64L(hw->port_info->lport), 3221 pf->offset_loaded, &os->rx_size_64, 3222 &ns->rx_size_64); 3223 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 3224 GLPRT_PRC127L(hw->port_info->lport), 3225 pf->offset_loaded, &os->rx_size_127, 3226 &ns->rx_size_127); 3227 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 3228 GLPRT_PRC255L(hw->port_info->lport), 3229 pf->offset_loaded, &os->rx_size_255, 3230 &ns->rx_size_255); 3231 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 3232 GLPRT_PRC511L(hw->port_info->lport), 3233 pf->offset_loaded, &os->rx_size_511, 3234 &ns->rx_size_511); 3235 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 3236 GLPRT_PRC1023L(hw->port_info->lport), 3237 pf->offset_loaded, &os->rx_size_1023, 3238 &ns->rx_size_1023); 3239 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 3240 GLPRT_PRC1522L(hw->port_info->lport), 3241 pf->offset_loaded, &os->rx_size_1522, 3242 &ns->rx_size_1522); 3243 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 3244 GLPRT_PRC9522L(hw->port_info->lport), 3245 pf->offset_loaded, &os->rx_size_big, 3246 &ns->rx_size_big); 3247 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 3248 pf->offset_loaded, &os->rx_undersize, 3249 &ns->rx_undersize); 3250 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 3251 pf->offset_loaded, &os->rx_fragments, 3252 &ns->rx_fragments); 3253 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 3254 pf->offset_loaded, &os->rx_oversize, 3255 &ns->rx_oversize); 3256 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 3257 pf->offset_loaded, &os->rx_jabber, 3258 &ns->rx_jabber); 3259 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 3260 GLPRT_PTC64L(hw->port_info->lport), 3261 pf->offset_loaded, &os->tx_size_64, 3262 &ns->tx_size_64); 3263 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 3264 GLPRT_PTC127L(hw->port_info->lport), 3265 pf->offset_loaded, &os->tx_size_127, 3266 &ns->tx_size_127); 3267 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 3268 GLPRT_PTC255L(hw->port_info->lport), 3269 pf->offset_loaded, &os->tx_size_255, 3270 &ns->tx_size_255); 3271 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 3272 GLPRT_PTC511L(hw->port_info->lport), 3273 pf->offset_loaded, &os->tx_size_511, 3274 &ns->tx_size_511); 3275 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 3276 GLPRT_PTC1023L(hw->port_info->lport), 3277 pf->offset_loaded, &os->tx_size_1023, 3278 &ns->tx_size_1023); 3279 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 3280 GLPRT_PTC1522L(hw->port_info->lport), 3281 pf->offset_loaded, &os->tx_size_1522, 3282 &ns->tx_size_1522); 3283 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 3284 GLPRT_PTC9522L(hw->port_info->lport), 3285 pf->offset_loaded, &os->tx_size_big, 3286 &ns->tx_size_big); 3287 3288 /* GLPRT_MSPDC not supported */ 3289 /* GLPRT_XEC not supported */ 3290 3291 pf->offset_loaded = true; 3292 3293 if (pf->main_vsi) 3294 ice_update_vsi_stats(pf->main_vsi); 3295 } 3296 3297 /* Get all statistics of a port */ 3298 static int 3299 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3300 { 3301 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3302 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3303 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 3304 3305 /* call read registers - updates values, now write them to struct */ 3306 ice_read_stats_registers(pf, hw); 3307 3308 stats->ipackets = ns->eth.rx_unicast + 3309 ns->eth.rx_multicast + 3310 ns->eth.rx_broadcast - 3311 ns->eth.rx_discards - 3312 pf->main_vsi->eth_stats.rx_discards; 3313 stats->opackets = ns->eth.tx_unicast + 3314 ns->eth.tx_multicast + 3315 ns->eth.tx_broadcast; 3316 stats->ibytes = ns->eth.rx_bytes; 3317 stats->obytes = ns->eth.tx_bytes; 3318 stats->oerrors = ns->eth.tx_errors + 3319 pf->main_vsi->eth_stats.tx_errors; 3320 3321 /* Rx Errors */ 3322 stats->imissed = ns->eth.rx_discards + 3323 pf->main_vsi->eth_stats.rx_discards; 3324 stats->ierrors = ns->crc_errors + 3325 ns->rx_undersize + 3326 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 3327 3328 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 3329 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 3330 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 3331 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 3332 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 3333 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 3334 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 3335 pf->main_vsi->eth_stats.rx_discards); 3336 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3337 ns->eth.rx_unknown_protocol); 3338 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 3339 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 3340 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 3341 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 3342 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 3343 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 3344 pf->main_vsi->eth_stats.tx_discards); 3345 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 3346 3347 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 3348 ns->tx_dropped_link_down); 3349 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 3350 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 3351 ns->illegal_bytes); 3352 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 3353 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 3354 ns->mac_local_faults); 3355 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 3356 ns->mac_remote_faults); 3357 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 3358 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 3359 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 3360 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 3361 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 3362 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 3363 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 3364 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 3365 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 3366 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 3367 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 3368 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 3369 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 3370 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 3371 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 3372 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 3373 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 3374 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 3375 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 3376 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 3377 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 3378 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 3379 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 3380 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 3381 return 0; 3382 } 3383 3384 /* Reset the statistics */ 3385 static void 3386 ice_stats_reset(struct rte_eth_dev *dev) 3387 { 3388 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3389 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3390 3391 /* Mark PF and VSI stats to update the offset, aka "reset" */ 3392 pf->offset_loaded = false; 3393 if (pf->main_vsi) 3394 pf->main_vsi->offset_loaded = false; 3395 3396 /* read the stats, reading current register values into offset */ 3397 ice_read_stats_registers(pf, hw); 3398 } 3399 3400 static uint32_t 3401 ice_xstats_calc_num(void) 3402 { 3403 uint32_t num; 3404 3405 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 3406 3407 return num; 3408 } 3409 3410 static int 3411 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3412 unsigned int n) 3413 { 3414 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3415 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3416 unsigned int i; 3417 unsigned int count; 3418 struct ice_hw_port_stats *hw_stats = &pf->stats; 3419 3420 count = ice_xstats_calc_num(); 3421 if (n < count) 3422 return count; 3423 3424 ice_read_stats_registers(pf, hw); 3425 3426 if (!xstats) 3427 return 0; 3428 3429 count = 0; 3430 3431 /* Get stats from ice_eth_stats struct */ 3432 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 3433 xstats[count].value = 3434 *(uint64_t *)((char *)&hw_stats->eth + 3435 ice_stats_strings[i].offset); 3436 xstats[count].id = count; 3437 count++; 3438 } 3439 3440 /* Get individiual stats from ice_hw_port struct */ 3441 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 3442 xstats[count].value = 3443 *(uint64_t *)((char *)hw_stats + 3444 ice_hw_port_strings[i].offset); 3445 xstats[count].id = count; 3446 count++; 3447 } 3448 3449 return count; 3450 } 3451 3452 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3453 struct rte_eth_xstat_name *xstats_names, 3454 __rte_unused unsigned int limit) 3455 { 3456 unsigned int count = 0; 3457 unsigned int i; 3458 3459 if (!xstats_names) 3460 return ice_xstats_calc_num(); 3461 3462 /* Note: limit checked in rte_eth_xstats_names() */ 3463 3464 /* Get stats from ice_eth_stats struct */ 3465 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 3466 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 3467 sizeof(xstats_names[count].name)); 3468 count++; 3469 } 3470 3471 /* Get individiual stats from ice_hw_port struct */ 3472 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 3473 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 3474 sizeof(xstats_names[count].name)); 3475 count++; 3476 } 3477 3478 return count; 3479 } 3480 3481 static int 3482 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3483 struct rte_pci_device *pci_dev) 3484 { 3485 return rte_eth_dev_pci_generic_probe(pci_dev, 3486 sizeof(struct ice_adapter), 3487 ice_dev_init); 3488 } 3489 3490 static int 3491 ice_pci_remove(struct rte_pci_device *pci_dev) 3492 { 3493 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 3494 } 3495 3496 static struct rte_pci_driver rte_ice_pmd = { 3497 .id_table = pci_id_ice_map, 3498 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 3499 RTE_PCI_DRV_IOVA_AS_VA, 3500 .probe = ice_pci_probe, 3501 .remove = ice_pci_remove, 3502 }; 3503 3504 /** 3505 * Driver initialization routine. 3506 * Invoked once at EAL init time. 3507 * Register itself as the [Poll Mode] Driver of PCI devices. 3508 */ 3509 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 3510 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 3511 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 3512 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 3513 ICE_MAX_QP_NUM "=<int>"); 3514 3515 RTE_INIT(ice_init_log) 3516 { 3517 ice_logtype_init = rte_log_register("pmd.net.ice.init"); 3518 if (ice_logtype_init >= 0) 3519 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE); 3520 ice_logtype_driver = rte_log_register("pmd.net.ice.driver"); 3521 if (ice_logtype_driver >= 0) 3522 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE); 3523 } 3524