1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <rte_ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include "base/ice_sched.h" 14 #include "base/ice_flow.h" 15 #include "base/ice_dcb.h" 16 #include "base/ice_common.h" 17 18 #include "rte_pmd_ice.h" 19 #include "ice_ethdev.h" 20 #include "ice_rxtx.h" 21 #include "ice_generic_flow.h" 22 23 /* devargs */ 24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" 25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" 26 #define ICE_PROTO_XTR_ARG "proto_xtr" 27 28 static const char * const ice_valid_args[] = { 29 ICE_SAFE_MODE_SUPPORT_ARG, 30 ICE_PIPELINE_MODE_SUPPORT_ARG, 31 ICE_PROTO_XTR_ARG, 32 NULL 33 }; 34 35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = { 36 .name = "intel_pmd_dynfield_proto_xtr_metadata", 37 .size = sizeof(uint32_t), 38 .align = __alignof__(uint32_t), 39 .flags = 0, 40 }; 41 42 struct proto_xtr_ol_flag { 43 const struct rte_mbuf_dynflag param; 44 uint64_t *ol_flag; 45 bool required; 46 }; 47 48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX]; 49 50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = { 51 [PROTO_XTR_VLAN] = { 52 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" }, 53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask }, 54 [PROTO_XTR_IPV4] = { 55 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" }, 56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask }, 57 [PROTO_XTR_IPV6] = { 58 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" }, 59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask }, 60 [PROTO_XTR_IPV6_FLOW] = { 61 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" }, 62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask }, 63 [PROTO_XTR_TCP] = { 64 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" }, 65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask }, 66 [PROTO_XTR_IP_OFFSET] = { 67 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" }, 68 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask }, 69 }; 70 71 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 72 73 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package" 74 #define ICE_COMMS_PKG_NAME "ICE COMMS Package" 75 #define ICE_MAX_RES_DESC_NUM 1024 76 77 static int ice_dev_configure(struct rte_eth_dev *dev); 78 static int ice_dev_start(struct rte_eth_dev *dev); 79 static int ice_dev_stop(struct rte_eth_dev *dev); 80 static int ice_dev_close(struct rte_eth_dev *dev); 81 static int ice_dev_reset(struct rte_eth_dev *dev); 82 static int ice_dev_info_get(struct rte_eth_dev *dev, 83 struct rte_eth_dev_info *dev_info); 84 static int ice_link_update(struct rte_eth_dev *dev, 85 int wait_to_complete); 86 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 87 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 88 89 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 90 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 91 static int ice_rss_reta_update(struct rte_eth_dev *dev, 92 struct rte_eth_rss_reta_entry64 *reta_conf, 93 uint16_t reta_size); 94 static int ice_rss_reta_query(struct rte_eth_dev *dev, 95 struct rte_eth_rss_reta_entry64 *reta_conf, 96 uint16_t reta_size); 97 static int ice_rss_hash_update(struct rte_eth_dev *dev, 98 struct rte_eth_rss_conf *rss_conf); 99 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 100 struct rte_eth_rss_conf *rss_conf); 101 static int ice_promisc_enable(struct rte_eth_dev *dev); 102 static int ice_promisc_disable(struct rte_eth_dev *dev); 103 static int ice_allmulti_enable(struct rte_eth_dev *dev); 104 static int ice_allmulti_disable(struct rte_eth_dev *dev); 105 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 106 uint16_t vlan_id, 107 int on); 108 static int ice_macaddr_set(struct rte_eth_dev *dev, 109 struct rte_ether_addr *mac_addr); 110 static int ice_macaddr_add(struct rte_eth_dev *dev, 111 struct rte_ether_addr *mac_addr, 112 __rte_unused uint32_t index, 113 uint32_t pool); 114 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 115 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 116 uint16_t queue_id); 117 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 118 uint16_t queue_id); 119 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 120 size_t fw_size); 121 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 122 uint16_t pvid, int on); 123 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 124 static int ice_get_eeprom(struct rte_eth_dev *dev, 125 struct rte_dev_eeprom_info *eeprom); 126 static int ice_stats_get(struct rte_eth_dev *dev, 127 struct rte_eth_stats *stats); 128 static int ice_stats_reset(struct rte_eth_dev *dev); 129 static int ice_xstats_get(struct rte_eth_dev *dev, 130 struct rte_eth_xstat *xstats, unsigned int n); 131 static int ice_xstats_get_names(struct rte_eth_dev *dev, 132 struct rte_eth_xstat_name *xstats_names, 133 unsigned int limit); 134 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, 135 enum rte_filter_type filter_type, 136 enum rte_filter_op filter_op, 137 void *arg); 138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 139 struct rte_eth_udp_tunnel *udp_tunnel); 140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 141 struct rte_eth_udp_tunnel *udp_tunnel); 142 143 static const struct rte_pci_id pci_id_ice_map[] = { 144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) }, 145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) }, 146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) }, 147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) }, 148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) }, 149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) }, 153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) }, 154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) }, 155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) }, 156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) }, 157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) }, 158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) }, 159 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) }, 160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) }, 161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) }, 162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) }, 163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) }, 164 { .vendor_id = 0, /* sentinel */ }, 165 }; 166 167 static const struct eth_dev_ops ice_eth_dev_ops = { 168 .dev_configure = ice_dev_configure, 169 .dev_start = ice_dev_start, 170 .dev_stop = ice_dev_stop, 171 .dev_close = ice_dev_close, 172 .dev_reset = ice_dev_reset, 173 .dev_set_link_up = ice_dev_set_link_up, 174 .dev_set_link_down = ice_dev_set_link_down, 175 .rx_queue_start = ice_rx_queue_start, 176 .rx_queue_stop = ice_rx_queue_stop, 177 .tx_queue_start = ice_tx_queue_start, 178 .tx_queue_stop = ice_tx_queue_stop, 179 .rx_queue_setup = ice_rx_queue_setup, 180 .rx_queue_release = ice_rx_queue_release, 181 .tx_queue_setup = ice_tx_queue_setup, 182 .tx_queue_release = ice_tx_queue_release, 183 .dev_infos_get = ice_dev_info_get, 184 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 185 .link_update = ice_link_update, 186 .mtu_set = ice_mtu_set, 187 .mac_addr_set = ice_macaddr_set, 188 .mac_addr_add = ice_macaddr_add, 189 .mac_addr_remove = ice_macaddr_remove, 190 .vlan_filter_set = ice_vlan_filter_set, 191 .vlan_offload_set = ice_vlan_offload_set, 192 .reta_update = ice_rss_reta_update, 193 .reta_query = ice_rss_reta_query, 194 .rss_hash_update = ice_rss_hash_update, 195 .rss_hash_conf_get = ice_rss_hash_conf_get, 196 .promiscuous_enable = ice_promisc_enable, 197 .promiscuous_disable = ice_promisc_disable, 198 .allmulticast_enable = ice_allmulti_enable, 199 .allmulticast_disable = ice_allmulti_disable, 200 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 201 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 202 .fw_version_get = ice_fw_version_get, 203 .vlan_pvid_set = ice_vlan_pvid_set, 204 .rxq_info_get = ice_rxq_info_get, 205 .txq_info_get = ice_txq_info_get, 206 .rx_burst_mode_get = ice_rx_burst_mode_get, 207 .tx_burst_mode_get = ice_tx_burst_mode_get, 208 .get_eeprom_length = ice_get_eeprom_length, 209 .get_eeprom = ice_get_eeprom, 210 .stats_get = ice_stats_get, 211 .stats_reset = ice_stats_reset, 212 .xstats_get = ice_xstats_get, 213 .xstats_get_names = ice_xstats_get_names, 214 .xstats_reset = ice_stats_reset, 215 .filter_ctrl = ice_dev_filter_ctrl, 216 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, 217 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, 218 .tx_done_cleanup = ice_tx_done_cleanup, 219 .get_monitor_addr = ice_get_monitor_addr, 220 }; 221 222 /* store statistics names and its offset in stats structure */ 223 struct ice_xstats_name_off { 224 char name[RTE_ETH_XSTATS_NAME_SIZE]; 225 unsigned int offset; 226 }; 227 228 static const struct ice_xstats_name_off ice_stats_strings[] = { 229 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 230 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 231 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 232 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 233 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 234 rx_unknown_protocol)}, 235 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 236 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 237 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 238 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 239 }; 240 241 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 242 sizeof(ice_stats_strings[0])) 243 244 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 245 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 246 tx_dropped_link_down)}, 247 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 248 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 249 illegal_bytes)}, 250 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 251 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 252 mac_local_faults)}, 253 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 254 mac_remote_faults)}, 255 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 256 rx_len_errors)}, 257 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 258 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 259 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 260 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 261 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 262 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 263 rx_size_127)}, 264 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 265 rx_size_255)}, 266 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 267 rx_size_511)}, 268 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 269 rx_size_1023)}, 270 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 271 rx_size_1522)}, 272 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 273 rx_size_big)}, 274 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 275 rx_undersize)}, 276 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 277 rx_oversize)}, 278 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 279 mac_short_pkt_dropped)}, 280 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 281 rx_fragments)}, 282 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 283 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 284 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 285 tx_size_127)}, 286 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 287 tx_size_255)}, 288 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 289 tx_size_511)}, 290 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 291 tx_size_1023)}, 292 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 293 tx_size_1522)}, 294 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 295 tx_size_big)}, 296 }; 297 298 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 299 sizeof(ice_hw_port_strings[0])) 300 301 static void 302 ice_init_controlq_parameter(struct ice_hw *hw) 303 { 304 /* fields for adminq */ 305 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 306 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 307 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 308 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 309 310 /* fields for mailboxq, DPDK used as PF host */ 311 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 312 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 313 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 314 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 315 } 316 317 static int 318 lookup_proto_xtr_type(const char *xtr_name) 319 { 320 static struct { 321 const char *name; 322 enum proto_xtr_type type; 323 } xtr_type_map[] = { 324 { "vlan", PROTO_XTR_VLAN }, 325 { "ipv4", PROTO_XTR_IPV4 }, 326 { "ipv6", PROTO_XTR_IPV6 }, 327 { "ipv6_flow", PROTO_XTR_IPV6_FLOW }, 328 { "tcp", PROTO_XTR_TCP }, 329 { "ip_offset", PROTO_XTR_IP_OFFSET }, 330 }; 331 uint32_t i; 332 333 for (i = 0; i < RTE_DIM(xtr_type_map); i++) { 334 if (strcmp(xtr_name, xtr_type_map[i].name) == 0) 335 return xtr_type_map[i].type; 336 } 337 338 return -1; 339 } 340 341 /* 342 * Parse elem, the elem could be single number/range or '(' ')' group 343 * 1) A single number elem, it's just a simple digit. e.g. 9 344 * 2) A single range elem, two digits with a '-' between. e.g. 2-6 345 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6) 346 * Within group elem, '-' used for a range separator; 347 * ',' used for a single number. 348 */ 349 static int 350 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs) 351 { 352 const char *str = input; 353 char *end = NULL; 354 uint32_t min, max; 355 uint32_t idx; 356 357 while (isblank(*str)) 358 str++; 359 360 if (!isdigit(*str) && *str != '(') 361 return -1; 362 363 /* process single number or single range of number */ 364 if (*str != '(') { 365 errno = 0; 366 idx = strtoul(str, &end, 10); 367 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 368 return -1; 369 370 while (isblank(*end)) 371 end++; 372 373 min = idx; 374 max = idx; 375 376 /* process single <number>-<number> */ 377 if (*end == '-') { 378 end++; 379 while (isblank(*end)) 380 end++; 381 if (!isdigit(*end)) 382 return -1; 383 384 errno = 0; 385 idx = strtoul(end, &end, 10); 386 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 387 return -1; 388 389 max = idx; 390 while (isblank(*end)) 391 end++; 392 } 393 394 if (*end != ':') 395 return -1; 396 397 for (idx = RTE_MIN(min, max); 398 idx <= RTE_MAX(min, max); idx++) 399 devargs->proto_xtr[idx] = xtr_type; 400 401 return 0; 402 } 403 404 /* process set within bracket */ 405 str++; 406 while (isblank(*str)) 407 str++; 408 if (*str == '\0') 409 return -1; 410 411 min = ICE_MAX_QUEUE_NUM; 412 do { 413 /* go ahead to the first digit */ 414 while (isblank(*str)) 415 str++; 416 if (!isdigit(*str)) 417 return -1; 418 419 /* get the digit value */ 420 errno = 0; 421 idx = strtoul(str, &end, 10); 422 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 423 return -1; 424 425 /* go ahead to separator '-',',' and ')' */ 426 while (isblank(*end)) 427 end++; 428 if (*end == '-') { 429 if (min == ICE_MAX_QUEUE_NUM) 430 min = idx; 431 else /* avoid continuous '-' */ 432 return -1; 433 } else if (*end == ',' || *end == ')') { 434 max = idx; 435 if (min == ICE_MAX_QUEUE_NUM) 436 min = idx; 437 438 for (idx = RTE_MIN(min, max); 439 idx <= RTE_MAX(min, max); idx++) 440 devargs->proto_xtr[idx] = xtr_type; 441 442 min = ICE_MAX_QUEUE_NUM; 443 } else { 444 return -1; 445 } 446 447 str = end + 1; 448 } while (*end != ')' && *end != '\0'); 449 450 return 0; 451 } 452 453 static int 454 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs) 455 { 456 const char *queue_start; 457 uint32_t idx; 458 int xtr_type; 459 char xtr_name[32]; 460 461 while (isblank(*queues)) 462 queues++; 463 464 if (*queues != '[') { 465 xtr_type = lookup_proto_xtr_type(queues); 466 if (xtr_type < 0) 467 return -1; 468 469 devargs->proto_xtr_dflt = xtr_type; 470 471 return 0; 472 } 473 474 queues++; 475 do { 476 while (isblank(*queues)) 477 queues++; 478 if (*queues == '\0') 479 return -1; 480 481 queue_start = queues; 482 483 /* go across a complete bracket */ 484 if (*queue_start == '(') { 485 queues += strcspn(queues, ")"); 486 if (*queues != ')') 487 return -1; 488 } 489 490 /* scan the separator ':' */ 491 queues += strcspn(queues, ":"); 492 if (*queues++ != ':') 493 return -1; 494 while (isblank(*queues)) 495 queues++; 496 497 for (idx = 0; ; idx++) { 498 if (isblank(queues[idx]) || 499 queues[idx] == ',' || 500 queues[idx] == ']' || 501 queues[idx] == '\0') 502 break; 503 504 if (idx > sizeof(xtr_name) - 2) 505 return -1; 506 507 xtr_name[idx] = queues[idx]; 508 } 509 xtr_name[idx] = '\0'; 510 xtr_type = lookup_proto_xtr_type(xtr_name); 511 if (xtr_type < 0) 512 return -1; 513 514 queues += idx; 515 516 while (isblank(*queues) || *queues == ',' || *queues == ']') 517 queues++; 518 519 if (parse_queue_set(queue_start, xtr_type, devargs) < 0) 520 return -1; 521 } while (*queues != '\0'); 522 523 return 0; 524 } 525 526 static int 527 handle_proto_xtr_arg(__rte_unused const char *key, const char *value, 528 void *extra_args) 529 { 530 struct ice_devargs *devargs = extra_args; 531 532 if (value == NULL || extra_args == NULL) 533 return -EINVAL; 534 535 if (parse_queue_proto_xtr(value, devargs) < 0) { 536 PMD_DRV_LOG(ERR, 537 "The protocol extraction parameter is wrong : '%s'", 538 value); 539 return -1; 540 } 541 542 return 0; 543 } 544 545 static void 546 ice_check_proto_xtr_support(struct ice_hw *hw) 547 { 548 #define FLX_REG(val, fld, idx) \ 549 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ 550 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) 551 static struct { 552 uint32_t rxdid; 553 uint8_t opcode; 554 uint8_t protid_0; 555 uint8_t protid_1; 556 } xtr_sets[] = { 557 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN, 558 ICE_RX_OPC_EXTRACT, 559 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O}, 560 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4, 561 ICE_RX_OPC_EXTRACT, 562 ICE_PROT_IPV4_OF_OR_S, 563 ICE_PROT_IPV4_OF_OR_S }, 564 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6, 565 ICE_RX_OPC_EXTRACT, 566 ICE_PROT_IPV6_OF_OR_S, 567 ICE_PROT_IPV6_OF_OR_S }, 568 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW, 569 ICE_RX_OPC_EXTRACT, 570 ICE_PROT_IPV6_OF_OR_S, 571 ICE_PROT_IPV6_OF_OR_S }, 572 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP, 573 ICE_RX_OPC_EXTRACT, 574 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, 575 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET, 576 ICE_RX_OPC_PROTID, 577 ICE_PROT_IPV4_OF_OR_S, 578 ICE_PROT_IPV6_OF_OR_S }, 579 }; 580 uint32_t i; 581 582 for (i = 0; i < RTE_DIM(xtr_sets); i++) { 583 uint32_t rxdid = xtr_sets[i].rxdid; 584 uint32_t v; 585 586 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) { 587 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid)); 588 589 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 && 590 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode) 591 ice_proto_xtr_hw_support[i] = true; 592 } 593 594 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) { 595 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid)); 596 597 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 && 598 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode) 599 ice_proto_xtr_hw_support[i] = true; 600 } 601 } 602 } 603 604 static int 605 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 606 uint32_t num) 607 { 608 struct pool_entry *entry; 609 610 if (!pool || !num) 611 return -EINVAL; 612 613 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 614 if (!entry) { 615 PMD_INIT_LOG(ERR, 616 "Failed to allocate memory for resource pool"); 617 return -ENOMEM; 618 } 619 620 /* queue heap initialize */ 621 pool->num_free = num; 622 pool->num_alloc = 0; 623 pool->base = base; 624 LIST_INIT(&pool->alloc_list); 625 LIST_INIT(&pool->free_list); 626 627 /* Initialize element */ 628 entry->base = 0; 629 entry->len = num; 630 631 LIST_INSERT_HEAD(&pool->free_list, entry, next); 632 return 0; 633 } 634 635 static int 636 ice_res_pool_alloc(struct ice_res_pool_info *pool, 637 uint16_t num) 638 { 639 struct pool_entry *entry, *valid_entry; 640 641 if (!pool || !num) { 642 PMD_INIT_LOG(ERR, "Invalid parameter"); 643 return -EINVAL; 644 } 645 646 if (pool->num_free < num) { 647 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 648 num, pool->num_free); 649 return -ENOMEM; 650 } 651 652 valid_entry = NULL; 653 /* Lookup in free list and find most fit one */ 654 LIST_FOREACH(entry, &pool->free_list, next) { 655 if (entry->len >= num) { 656 /* Find best one */ 657 if (entry->len == num) { 658 valid_entry = entry; 659 break; 660 } 661 if (!valid_entry || 662 valid_entry->len > entry->len) 663 valid_entry = entry; 664 } 665 } 666 667 /* Not find one to satisfy the request, return */ 668 if (!valid_entry) { 669 PMD_INIT_LOG(ERR, "No valid entry found"); 670 return -ENOMEM; 671 } 672 /** 673 * The entry have equal queue number as requested, 674 * remove it from alloc_list. 675 */ 676 if (valid_entry->len == num) { 677 LIST_REMOVE(valid_entry, next); 678 } else { 679 /** 680 * The entry have more numbers than requested, 681 * create a new entry for alloc_list and minus its 682 * queue base and number in free_list. 683 */ 684 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 685 if (!entry) { 686 PMD_INIT_LOG(ERR, 687 "Failed to allocate memory for " 688 "resource pool"); 689 return -ENOMEM; 690 } 691 entry->base = valid_entry->base; 692 entry->len = num; 693 valid_entry->base += num; 694 valid_entry->len -= num; 695 valid_entry = entry; 696 } 697 698 /* Insert it into alloc list, not sorted */ 699 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 700 701 pool->num_free -= valid_entry->len; 702 pool->num_alloc += valid_entry->len; 703 704 return valid_entry->base + pool->base; 705 } 706 707 static void 708 ice_res_pool_destroy(struct ice_res_pool_info *pool) 709 { 710 struct pool_entry *entry, *next_entry; 711 712 if (!pool) 713 return; 714 715 for (entry = LIST_FIRST(&pool->alloc_list); 716 entry && (next_entry = LIST_NEXT(entry, next), 1); 717 entry = next_entry) { 718 LIST_REMOVE(entry, next); 719 rte_free(entry); 720 } 721 722 for (entry = LIST_FIRST(&pool->free_list); 723 entry && (next_entry = LIST_NEXT(entry, next), 1); 724 entry = next_entry) { 725 LIST_REMOVE(entry, next); 726 rte_free(entry); 727 } 728 729 pool->num_free = 0; 730 pool->num_alloc = 0; 731 pool->base = 0; 732 LIST_INIT(&pool->alloc_list); 733 LIST_INIT(&pool->free_list); 734 } 735 736 static void 737 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 738 { 739 /* Set VSI LUT selection */ 740 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 741 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 742 /* Set Hash scheme */ 743 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 744 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 745 /* enable TC */ 746 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 747 } 748 749 static enum ice_status 750 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 751 struct ice_aqc_vsi_props *info, 752 uint8_t enabled_tcmap) 753 { 754 uint16_t bsf, qp_idx; 755 756 /* default tc 0 now. Multi-TC supporting need to be done later. 757 * Configure TC and queue mapping parameters, for enabled TC, 758 * allocate qpnum_per_tc queues to this traffic. 759 */ 760 if (enabled_tcmap != 0x01) { 761 PMD_INIT_LOG(ERR, "only TC0 is supported"); 762 return -ENOTSUP; 763 } 764 765 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 766 bsf = rte_bsf32(vsi->nb_qps); 767 /* Adjust the queue number to actual queues that can be applied */ 768 vsi->nb_qps = 0x1 << bsf; 769 770 qp_idx = 0; 771 /* Set tc and queue mapping with VSI */ 772 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 773 ICE_AQ_VSI_TC_Q_OFFSET_S) | 774 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 775 776 /* Associate queue number with VSI */ 777 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 778 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 779 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 780 info->valid_sections |= 781 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 782 /* Set the info.ingress_table and info.egress_table 783 * for UP translate table. Now just set it to 1:1 map by default 784 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 785 */ 786 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 787 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 788 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 789 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 790 return 0; 791 } 792 793 static int 794 ice_init_mac_address(struct rte_eth_dev *dev) 795 { 796 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 797 798 if (!rte_is_unicast_ether_addr 799 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 800 PMD_INIT_LOG(ERR, "Invalid MAC address"); 801 return -EINVAL; 802 } 803 804 rte_ether_addr_copy( 805 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 806 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 807 808 dev->data->mac_addrs = 809 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0); 810 if (!dev->data->mac_addrs) { 811 PMD_INIT_LOG(ERR, 812 "Failed to allocate memory to store mac address"); 813 return -ENOMEM; 814 } 815 /* store it to dev data */ 816 rte_ether_addr_copy( 817 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 818 &dev->data->mac_addrs[0]); 819 return 0; 820 } 821 822 /* Find out specific MAC filter */ 823 static struct ice_mac_filter * 824 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 825 { 826 struct ice_mac_filter *f; 827 828 TAILQ_FOREACH(f, &vsi->mac_list, next) { 829 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 830 return f; 831 } 832 833 return NULL; 834 } 835 836 static int 837 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 838 { 839 struct ice_fltr_list_entry *m_list_itr = NULL; 840 struct ice_mac_filter *f; 841 struct LIST_HEAD_TYPE list_head; 842 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 843 int ret = 0; 844 845 /* If it's added and configured, return */ 846 f = ice_find_mac_filter(vsi, mac_addr); 847 if (f) { 848 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 849 return 0; 850 } 851 852 INIT_LIST_HEAD(&list_head); 853 854 m_list_itr = (struct ice_fltr_list_entry *) 855 ice_malloc(hw, sizeof(*m_list_itr)); 856 if (!m_list_itr) { 857 ret = -ENOMEM; 858 goto DONE; 859 } 860 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 861 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 862 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 863 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 864 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 865 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 866 m_list_itr->fltr_info.vsi_handle = vsi->idx; 867 868 LIST_ADD(&m_list_itr->list_entry, &list_head); 869 870 /* Add the mac */ 871 ret = ice_add_mac(hw, &list_head); 872 if (ret != ICE_SUCCESS) { 873 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 874 ret = -EINVAL; 875 goto DONE; 876 } 877 /* Add the mac addr into mac list */ 878 f = rte_zmalloc(NULL, sizeof(*f), 0); 879 if (!f) { 880 PMD_DRV_LOG(ERR, "failed to allocate memory"); 881 ret = -ENOMEM; 882 goto DONE; 883 } 884 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr); 885 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 886 vsi->mac_num++; 887 888 ret = 0; 889 890 DONE: 891 rte_free(m_list_itr); 892 return ret; 893 } 894 895 static int 896 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 897 { 898 struct ice_fltr_list_entry *m_list_itr = NULL; 899 struct ice_mac_filter *f; 900 struct LIST_HEAD_TYPE list_head; 901 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 902 int ret = 0; 903 904 /* Can't find it, return an error */ 905 f = ice_find_mac_filter(vsi, mac_addr); 906 if (!f) 907 return -EINVAL; 908 909 INIT_LIST_HEAD(&list_head); 910 911 m_list_itr = (struct ice_fltr_list_entry *) 912 ice_malloc(hw, sizeof(*m_list_itr)); 913 if (!m_list_itr) { 914 ret = -ENOMEM; 915 goto DONE; 916 } 917 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 918 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 919 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 920 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 921 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 922 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 923 m_list_itr->fltr_info.vsi_handle = vsi->idx; 924 925 LIST_ADD(&m_list_itr->list_entry, &list_head); 926 927 /* remove the mac filter */ 928 ret = ice_remove_mac(hw, &list_head); 929 if (ret != ICE_SUCCESS) { 930 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 931 ret = -EINVAL; 932 goto DONE; 933 } 934 935 /* Remove the mac addr from mac list */ 936 TAILQ_REMOVE(&vsi->mac_list, f, next); 937 rte_free(f); 938 vsi->mac_num--; 939 940 ret = 0; 941 DONE: 942 rte_free(m_list_itr); 943 return ret; 944 } 945 946 /* Find out specific VLAN filter */ 947 static struct ice_vlan_filter * 948 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 949 { 950 struct ice_vlan_filter *f; 951 952 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 953 if (vlan_id == f->vlan_info.vlan_id) 954 return f; 955 } 956 957 return NULL; 958 } 959 960 static int 961 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 962 { 963 struct ice_fltr_list_entry *v_list_itr = NULL; 964 struct ice_vlan_filter *f; 965 struct LIST_HEAD_TYPE list_head; 966 struct ice_hw *hw; 967 int ret = 0; 968 969 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID) 970 return -EINVAL; 971 972 hw = ICE_VSI_TO_HW(vsi); 973 974 /* If it's added and configured, return. */ 975 f = ice_find_vlan_filter(vsi, vlan_id); 976 if (f) { 977 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 978 return 0; 979 } 980 981 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 982 return 0; 983 984 INIT_LIST_HEAD(&list_head); 985 986 v_list_itr = (struct ice_fltr_list_entry *) 987 ice_malloc(hw, sizeof(*v_list_itr)); 988 if (!v_list_itr) { 989 ret = -ENOMEM; 990 goto DONE; 991 } 992 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 993 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 994 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 995 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 996 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 997 v_list_itr->fltr_info.vsi_handle = vsi->idx; 998 999 LIST_ADD(&v_list_itr->list_entry, &list_head); 1000 1001 /* Add the vlan */ 1002 ret = ice_add_vlan(hw, &list_head); 1003 if (ret != ICE_SUCCESS) { 1004 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 1005 ret = -EINVAL; 1006 goto DONE; 1007 } 1008 1009 /* Add vlan into vlan list */ 1010 f = rte_zmalloc(NULL, sizeof(*f), 0); 1011 if (!f) { 1012 PMD_DRV_LOG(ERR, "failed to allocate memory"); 1013 ret = -ENOMEM; 1014 goto DONE; 1015 } 1016 f->vlan_info.vlan_id = vlan_id; 1017 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 1018 vsi->vlan_num++; 1019 1020 ret = 0; 1021 1022 DONE: 1023 rte_free(v_list_itr); 1024 return ret; 1025 } 1026 1027 static int 1028 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 1029 { 1030 struct ice_fltr_list_entry *v_list_itr = NULL; 1031 struct ice_vlan_filter *f; 1032 struct LIST_HEAD_TYPE list_head; 1033 struct ice_hw *hw; 1034 int ret = 0; 1035 1036 /** 1037 * Vlan 0 is the generic filter for untagged packets 1038 * and can't be removed. 1039 */ 1040 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID) 1041 return -EINVAL; 1042 1043 hw = ICE_VSI_TO_HW(vsi); 1044 1045 /* Can't find it, return an error */ 1046 f = ice_find_vlan_filter(vsi, vlan_id); 1047 if (!f) 1048 return -EINVAL; 1049 1050 INIT_LIST_HEAD(&list_head); 1051 1052 v_list_itr = (struct ice_fltr_list_entry *) 1053 ice_malloc(hw, sizeof(*v_list_itr)); 1054 if (!v_list_itr) { 1055 ret = -ENOMEM; 1056 goto DONE; 1057 } 1058 1059 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 1060 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1061 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1062 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1063 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1064 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1065 1066 LIST_ADD(&v_list_itr->list_entry, &list_head); 1067 1068 /* remove the vlan filter */ 1069 ret = ice_remove_vlan(hw, &list_head); 1070 if (ret != ICE_SUCCESS) { 1071 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 1072 ret = -EINVAL; 1073 goto DONE; 1074 } 1075 1076 /* Remove the vlan id from vlan list */ 1077 TAILQ_REMOVE(&vsi->vlan_list, f, next); 1078 rte_free(f); 1079 vsi->vlan_num--; 1080 1081 ret = 0; 1082 DONE: 1083 rte_free(v_list_itr); 1084 return ret; 1085 } 1086 1087 static int 1088 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 1089 { 1090 struct ice_mac_filter *m_f; 1091 struct ice_vlan_filter *v_f; 1092 int ret = 0; 1093 1094 if (!vsi || !vsi->mac_num) 1095 return -EINVAL; 1096 1097 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 1098 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 1099 if (ret != ICE_SUCCESS) { 1100 ret = -EINVAL; 1101 goto DONE; 1102 } 1103 } 1104 1105 if (vsi->vlan_num == 0) 1106 return 0; 1107 1108 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 1109 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 1110 if (ret != ICE_SUCCESS) { 1111 ret = -EINVAL; 1112 goto DONE; 1113 } 1114 } 1115 1116 DONE: 1117 return ret; 1118 } 1119 1120 static int 1121 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 1122 { 1123 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1124 struct ice_vsi_ctx ctxt; 1125 uint8_t qinq_flags; 1126 int ret = 0; 1127 1128 /* Check if it has been already on or off */ 1129 if (vsi->info.valid_sections & 1130 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1131 if (on) { 1132 if ((vsi->info.outer_vlan_flags & 1133 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST) == 1134 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST) 1135 return 0; /* already on */ 1136 } else { 1137 if (!(vsi->info.outer_vlan_flags & 1138 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST)) 1139 return 0; /* already off */ 1140 } 1141 } 1142 1143 if (on) 1144 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST; 1145 else 1146 qinq_flags = 0; 1147 /* clear global insertion and use per packet insertion */ 1148 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT); 1149 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST); 1150 vsi->info.outer_vlan_flags |= qinq_flags; 1151 /* use default vlan type 0x8100 */ 1152 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1153 vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1154 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1155 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1156 ctxt.info.valid_sections = 1157 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1158 ctxt.vsi_num = vsi->vsi_id; 1159 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1160 if (ret) { 1161 PMD_DRV_LOG(INFO, 1162 "Update VSI failed to %s qinq stripping", 1163 on ? "enable" : "disable"); 1164 return -EINVAL; 1165 } 1166 1167 vsi->info.valid_sections |= 1168 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1169 1170 return ret; 1171 } 1172 1173 static int 1174 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 1175 { 1176 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1177 struct ice_vsi_ctx ctxt; 1178 uint8_t qinq_flags; 1179 int ret = 0; 1180 1181 /* Check if it has been already on or off */ 1182 if (vsi->info.valid_sections & 1183 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1184 if (on) { 1185 if ((vsi->info.outer_vlan_flags & 1186 ICE_AQ_VSI_OUTER_VLAN_EMODE_M) == 1187 ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW) 1188 return 0; /* already on */ 1189 } else { 1190 if ((vsi->info.outer_vlan_flags & 1191 ICE_AQ_VSI_OUTER_VLAN_EMODE_M) == 1192 ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH) 1193 return 0; /* already off */ 1194 } 1195 } 1196 1197 if (on) 1198 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW; 1199 else 1200 qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH; 1201 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M); 1202 vsi->info.outer_vlan_flags |= qinq_flags; 1203 /* use default vlan type 0x8100 */ 1204 vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1205 vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1206 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1207 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1208 ctxt.info.valid_sections = 1209 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1210 ctxt.vsi_num = vsi->vsi_id; 1211 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1212 if (ret) { 1213 PMD_DRV_LOG(INFO, 1214 "Update VSI failed to %s qinq stripping", 1215 on ? "enable" : "disable"); 1216 return -EINVAL; 1217 } 1218 1219 vsi->info.valid_sections |= 1220 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1221 1222 return ret; 1223 } 1224 1225 static int 1226 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 1227 { 1228 int ret; 1229 1230 ret = ice_vsi_config_qinq_stripping(vsi, on); 1231 if (ret) 1232 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 1233 1234 ret = ice_vsi_config_qinq_insertion(vsi, on); 1235 if (ret) 1236 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 1237 1238 return ret; 1239 } 1240 1241 /* Enable IRQ0 */ 1242 static void 1243 ice_pf_enable_irq0(struct ice_hw *hw) 1244 { 1245 /* reset the registers */ 1246 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 1247 ICE_READ_REG(hw, PFINT_OICR); 1248 1249 #ifdef ICE_LSE_SPT 1250 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 1251 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 1252 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 1253 1254 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 1255 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 1256 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 1257 PFINT_OICR_CTL_ITR_INDX_M) | 1258 PFINT_OICR_CTL_CAUSE_ENA_M); 1259 1260 ICE_WRITE_REG(hw, PFINT_FW_CTL, 1261 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 1262 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 1263 PFINT_FW_CTL_ITR_INDX_M) | 1264 PFINT_FW_CTL_CAUSE_ENA_M); 1265 #else 1266 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 1267 #endif 1268 1269 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1270 GLINT_DYN_CTL_INTENA_M | 1271 GLINT_DYN_CTL_CLEARPBA_M | 1272 GLINT_DYN_CTL_ITR_INDX_M); 1273 1274 ice_flush(hw); 1275 } 1276 1277 /* Disable IRQ0 */ 1278 static void 1279 ice_pf_disable_irq0(struct ice_hw *hw) 1280 { 1281 /* Disable all interrupt types */ 1282 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1283 ice_flush(hw); 1284 } 1285 1286 #ifdef ICE_LSE_SPT 1287 static void 1288 ice_handle_aq_msg(struct rte_eth_dev *dev) 1289 { 1290 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1291 struct ice_ctl_q_info *cq = &hw->adminq; 1292 struct ice_rq_event_info event; 1293 uint16_t pending, opcode; 1294 int ret; 1295 1296 event.buf_len = ICE_AQ_MAX_BUF_LEN; 1297 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 1298 if (!event.msg_buf) { 1299 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 1300 return; 1301 } 1302 1303 pending = 1; 1304 while (pending) { 1305 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 1306 1307 if (ret != ICE_SUCCESS) { 1308 PMD_DRV_LOG(INFO, 1309 "Failed to read msg from AdminQ, " 1310 "adminq_err: %u", 1311 hw->adminq.sq_last_status); 1312 break; 1313 } 1314 opcode = rte_le_to_cpu_16(event.desc.opcode); 1315 1316 switch (opcode) { 1317 case ice_aqc_opc_get_link_status: 1318 ret = ice_link_update(dev, 0); 1319 if (!ret) 1320 rte_eth_dev_callback_process 1321 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1322 break; 1323 default: 1324 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1325 opcode); 1326 break; 1327 } 1328 } 1329 rte_free(event.msg_buf); 1330 } 1331 #endif 1332 1333 /** 1334 * Interrupt handler triggered by NIC for handling 1335 * specific interrupt. 1336 * 1337 * @param handle 1338 * Pointer to interrupt handle. 1339 * @param param 1340 * The address of parameter (struct rte_eth_dev *) regsitered before. 1341 * 1342 * @return 1343 * void 1344 */ 1345 static void 1346 ice_interrupt_handler(void *param) 1347 { 1348 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1349 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1350 uint32_t oicr; 1351 uint32_t reg; 1352 uint8_t pf_num; 1353 uint8_t event; 1354 uint16_t queue; 1355 int ret; 1356 #ifdef ICE_LSE_SPT 1357 uint32_t int_fw_ctl; 1358 #endif 1359 1360 /* Disable interrupt */ 1361 ice_pf_disable_irq0(hw); 1362 1363 /* read out interrupt causes */ 1364 oicr = ICE_READ_REG(hw, PFINT_OICR); 1365 #ifdef ICE_LSE_SPT 1366 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1367 #endif 1368 1369 /* No interrupt event indicated */ 1370 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1371 PMD_DRV_LOG(INFO, "No interrupt event"); 1372 goto done; 1373 } 1374 1375 #ifdef ICE_LSE_SPT 1376 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1377 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1378 ice_handle_aq_msg(dev); 1379 } 1380 #else 1381 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1382 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1383 ret = ice_link_update(dev, 0); 1384 if (!ret) 1385 rte_eth_dev_callback_process 1386 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1387 } 1388 #endif 1389 1390 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1391 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1392 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1393 if (reg & GL_MDET_TX_PQM_VALID_M) { 1394 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1395 GL_MDET_TX_PQM_PF_NUM_S; 1396 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1397 GL_MDET_TX_PQM_MAL_TYPE_S; 1398 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1399 GL_MDET_TX_PQM_QNUM_S; 1400 1401 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1402 "%d by PQM on TX queue %d PF# %d", 1403 event, queue, pf_num); 1404 } 1405 1406 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1407 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1408 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1409 GL_MDET_TX_TCLAN_PF_NUM_S; 1410 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1411 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1412 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1413 GL_MDET_TX_TCLAN_QNUM_S; 1414 1415 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1416 "%d by TCLAN on TX queue %d PF# %d", 1417 event, queue, pf_num); 1418 } 1419 } 1420 done: 1421 /* Enable interrupt */ 1422 ice_pf_enable_irq0(hw); 1423 rte_intr_ack(dev->intr_handle); 1424 } 1425 1426 static void 1427 ice_init_proto_xtr(struct rte_eth_dev *dev) 1428 { 1429 struct ice_adapter *ad = 1430 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1431 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1432 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1433 const struct proto_xtr_ol_flag *ol_flag; 1434 bool proto_xtr_enable = false; 1435 int offset; 1436 uint16_t i; 1437 1438 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0); 1439 if (unlikely(pf->proto_xtr == NULL)) { 1440 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table"); 1441 return; 1442 } 1443 1444 for (i = 0; i < pf->lan_nb_qps; i++) { 1445 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ? 1446 ad->devargs.proto_xtr[i] : 1447 ad->devargs.proto_xtr_dflt; 1448 1449 if (pf->proto_xtr[i] != PROTO_XTR_NONE) { 1450 uint8_t type = pf->proto_xtr[i]; 1451 1452 ice_proto_xtr_ol_flag_params[type].required = true; 1453 proto_xtr_enable = true; 1454 } 1455 } 1456 1457 if (likely(!proto_xtr_enable)) 1458 return; 1459 1460 ice_check_proto_xtr_support(hw); 1461 1462 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param); 1463 if (unlikely(offset == -1)) { 1464 PMD_DRV_LOG(ERR, 1465 "Protocol extraction metadata is disabled in mbuf with error %d", 1466 -rte_errno); 1467 return; 1468 } 1469 1470 PMD_DRV_LOG(DEBUG, 1471 "Protocol extraction metadata offset in mbuf is : %d", 1472 offset); 1473 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset; 1474 1475 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) { 1476 ol_flag = &ice_proto_xtr_ol_flag_params[i]; 1477 1478 if (!ol_flag->required) 1479 continue; 1480 1481 if (!ice_proto_xtr_hw_support[i]) { 1482 PMD_DRV_LOG(ERR, 1483 "Protocol extraction type %u is not supported in hardware", 1484 i); 1485 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1486 break; 1487 } 1488 1489 offset = rte_mbuf_dynflag_register(&ol_flag->param); 1490 if (unlikely(offset == -1)) { 1491 PMD_DRV_LOG(ERR, 1492 "Protocol extraction offload '%s' failed to register with error %d", 1493 ol_flag->param.name, -rte_errno); 1494 1495 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1496 break; 1497 } 1498 1499 PMD_DRV_LOG(DEBUG, 1500 "Protocol extraction offload '%s' offset in mbuf is : %d", 1501 ol_flag->param.name, offset); 1502 *ol_flag->ol_flag = 1ULL << offset; 1503 } 1504 } 1505 1506 /* Initialize SW parameters of PF */ 1507 static int 1508 ice_pf_sw_init(struct rte_eth_dev *dev) 1509 { 1510 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1511 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1512 1513 pf->lan_nb_qp_max = 1514 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1515 hw->func_caps.common_cap.num_rxq); 1516 1517 pf->lan_nb_qps = pf->lan_nb_qp_max; 1518 1519 ice_init_proto_xtr(dev); 1520 1521 if (hw->func_caps.fd_fltr_guar > 0 || 1522 hw->func_caps.fd_fltr_best_effort > 0) { 1523 pf->flags |= ICE_FLAG_FDIR; 1524 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR; 1525 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps; 1526 } else { 1527 pf->fdir_nb_qps = 0; 1528 } 1529 pf->fdir_qp_offset = 0; 1530 1531 return 0; 1532 } 1533 1534 struct ice_vsi * 1535 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1536 { 1537 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1538 struct ice_vsi *vsi = NULL; 1539 struct ice_vsi_ctx vsi_ctx; 1540 int ret; 1541 struct rte_ether_addr broadcast = { 1542 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1543 struct rte_ether_addr mac_addr; 1544 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1545 uint8_t tc_bitmap = 0x1; 1546 uint16_t cfg; 1547 1548 /* hw->num_lports = 1 in NIC mode */ 1549 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1550 if (!vsi) 1551 return NULL; 1552 1553 vsi->idx = pf->next_vsi_idx; 1554 pf->next_vsi_idx++; 1555 vsi->type = type; 1556 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1557 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1558 vsi->vlan_anti_spoof_on = 0; 1559 vsi->vlan_filter_on = 1; 1560 TAILQ_INIT(&vsi->mac_list); 1561 TAILQ_INIT(&vsi->vlan_list); 1562 1563 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ 1564 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1565 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : 1566 hw->func_caps.common_cap.rss_table_size; 1567 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1568 1569 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1570 switch (type) { 1571 case ICE_VSI_PF: 1572 vsi->nb_qps = pf->lan_nb_qps; 1573 vsi->base_queue = 1; 1574 ice_vsi_config_default_rss(&vsi_ctx.info); 1575 vsi_ctx.alloc_from_pool = true; 1576 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1577 /* switch_id is queried by get_switch_config aq, which is done 1578 * by ice_init_hw 1579 */ 1580 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1581 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1582 /* Allow all untagged or tagged packets */ 1583 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; 1584 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; 1585 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1586 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1587 1588 /* FDIR */ 1589 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID | 1590 ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1591 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1592 cfg = ICE_AQ_VSI_FD_ENABLE; 1593 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1594 vsi_ctx.info.max_fd_fltr_dedicated = 1595 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar); 1596 vsi_ctx.info.max_fd_fltr_shared = 1597 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); 1598 1599 /* Enable VLAN/UP trip */ 1600 ret = ice_vsi_config_tc_queue_mapping(vsi, 1601 &vsi_ctx.info, 1602 ICE_DEFAULT_TCMAP); 1603 if (ret) { 1604 PMD_INIT_LOG(ERR, 1605 "tc queue mapping with vsi failed, " 1606 "err = %d", 1607 ret); 1608 goto fail_mem; 1609 } 1610 1611 break; 1612 case ICE_VSI_CTRL: 1613 vsi->nb_qps = pf->fdir_nb_qps; 1614 vsi->base_queue = ICE_FDIR_QUEUE_ID; 1615 vsi_ctx.alloc_from_pool = true; 1616 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1617 1618 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1619 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1620 cfg = ICE_AQ_VSI_FD_PROG_ENABLE; 1621 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1622 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1623 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1624 ret = ice_vsi_config_tc_queue_mapping(vsi, 1625 &vsi_ctx.info, 1626 ICE_DEFAULT_TCMAP); 1627 if (ret) { 1628 PMD_INIT_LOG(ERR, 1629 "tc queue mapping with vsi failed, " 1630 "err = %d", 1631 ret); 1632 goto fail_mem; 1633 } 1634 break; 1635 default: 1636 /* for other types of VSI */ 1637 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1638 goto fail_mem; 1639 } 1640 1641 /* VF has MSIX interrupt in VF range, don't allocate here */ 1642 if (type == ICE_VSI_PF) { 1643 ret = ice_res_pool_alloc(&pf->msix_pool, 1644 RTE_MIN(vsi->nb_qps, 1645 RTE_MAX_RXTX_INTR_VEC_ID)); 1646 if (ret < 0) { 1647 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1648 vsi->vsi_id, ret); 1649 } 1650 vsi->msix_intr = ret; 1651 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1652 } else if (type == ICE_VSI_CTRL) { 1653 ret = ice_res_pool_alloc(&pf->msix_pool, 1); 1654 if (ret < 0) { 1655 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", 1656 vsi->vsi_id, ret); 1657 } 1658 vsi->msix_intr = ret; 1659 vsi->nb_msix = 1; 1660 } else { 1661 vsi->msix_intr = 0; 1662 vsi->nb_msix = 0; 1663 } 1664 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1665 if (ret != ICE_SUCCESS) { 1666 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1667 goto fail_mem; 1668 } 1669 /* store vsi information is SW structure */ 1670 vsi->vsi_id = vsi_ctx.vsi_num; 1671 vsi->info = vsi_ctx.info; 1672 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1673 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1674 1675 if (type == ICE_VSI_PF) { 1676 /* MAC configuration */ 1677 rte_ether_addr_copy((struct rte_ether_addr *) 1678 hw->port_info->mac.perm_addr, 1679 &pf->dev_addr); 1680 1681 rte_ether_addr_copy(&pf->dev_addr, &mac_addr); 1682 ret = ice_add_mac_filter(vsi, &mac_addr); 1683 if (ret != ICE_SUCCESS) 1684 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1685 1686 rte_ether_addr_copy(&broadcast, &mac_addr); 1687 ret = ice_add_mac_filter(vsi, &mac_addr); 1688 if (ret != ICE_SUCCESS) 1689 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1690 } 1691 1692 /* At the beginning, only TC0. */ 1693 /* What we need here is the maximam number of the TX queues. 1694 * Currently vsi->nb_qps means it. 1695 * Correct it if any change. 1696 */ 1697 max_txqs[0] = vsi->nb_qps; 1698 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1699 tc_bitmap, max_txqs); 1700 if (ret != ICE_SUCCESS) 1701 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1702 1703 return vsi; 1704 fail_mem: 1705 rte_free(vsi); 1706 pf->next_vsi_idx--; 1707 return NULL; 1708 } 1709 1710 static int 1711 ice_send_driver_ver(struct ice_hw *hw) 1712 { 1713 struct ice_driver_ver dv; 1714 1715 /* we don't have driver version use 0 for dummy */ 1716 dv.major_ver = 0; 1717 dv.minor_ver = 0; 1718 dv.build_ver = 0; 1719 dv.subbuild_ver = 0; 1720 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1721 1722 return ice_aq_send_driver_ver(hw, &dv, NULL); 1723 } 1724 1725 static int 1726 ice_pf_setup(struct ice_pf *pf) 1727 { 1728 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1729 struct ice_vsi *vsi; 1730 uint16_t unused; 1731 1732 /* Clear all stats counters */ 1733 pf->offset_loaded = false; 1734 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1735 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1736 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1737 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1738 1739 /* force guaranteed filter pool for PF */ 1740 ice_alloc_fd_guar_item(hw, &unused, 1741 hw->func_caps.fd_fltr_guar); 1742 /* force shared filter pool for PF */ 1743 ice_alloc_fd_shrd_item(hw, &unused, 1744 hw->func_caps.fd_fltr_best_effort); 1745 1746 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1747 if (!vsi) { 1748 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1749 return -EINVAL; 1750 } 1751 1752 pf->main_vsi = vsi; 1753 1754 return 0; 1755 } 1756 1757 /* 1758 * Extract device serial number from PCIe Configuration Space and 1759 * determine the pkg file path according to the DSN. 1760 */ 1761 static int 1762 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file) 1763 { 1764 off_t pos; 1765 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; 1766 uint32_t dsn_low, dsn_high; 1767 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); 1768 1769 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN); 1770 1771 if (pos) { 1772 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4); 1773 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8); 1774 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, 1775 "ice-%08x%08x.pkg", dsn_high, dsn_low); 1776 } else { 1777 PMD_INIT_LOG(ERR, "Failed to read device serial number\n"); 1778 goto fail_dsn; 1779 } 1780 1781 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, 1782 ICE_MAX_PKG_FILENAME_SIZE); 1783 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1784 return 0; 1785 1786 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, 1787 ICE_MAX_PKG_FILENAME_SIZE); 1788 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1789 return 0; 1790 1791 fail_dsn: 1792 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); 1793 if (!access(pkg_file, 0)) 1794 return 0; 1795 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); 1796 return 0; 1797 } 1798 1799 enum ice_pkg_type 1800 ice_load_pkg_type(struct ice_hw *hw) 1801 { 1802 enum ice_pkg_type package_type; 1803 1804 /* store the activated package type (OS default or Comms) */ 1805 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME, 1806 ICE_PKG_NAME_SIZE)) 1807 package_type = ICE_PKG_TYPE_OS_DEFAULT; 1808 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, 1809 ICE_PKG_NAME_SIZE)) 1810 package_type = ICE_PKG_TYPE_COMMS; 1811 else 1812 package_type = ICE_PKG_TYPE_UNKNOWN; 1813 1814 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s", 1815 hw->active_pkg_ver.major, hw->active_pkg_ver.minor, 1816 hw->active_pkg_ver.update, hw->active_pkg_ver.draft, 1817 hw->active_pkg_name); 1818 1819 return package_type; 1820 } 1821 1822 static int ice_load_pkg(struct rte_eth_dev *dev) 1823 { 1824 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1825 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE]; 1826 int err; 1827 uint8_t *buf; 1828 int buf_len; 1829 FILE *file; 1830 struct stat fstat; 1831 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1832 struct ice_adapter *ad = 1833 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1834 1835 ice_pkg_file_search_path(pci_dev, pkg_file); 1836 1837 file = fopen(pkg_file, "rb"); 1838 if (!file) { 1839 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); 1840 return -1; 1841 } 1842 1843 err = stat(pkg_file, &fstat); 1844 if (err) { 1845 PMD_INIT_LOG(ERR, "failed to get file stats\n"); 1846 fclose(file); 1847 return err; 1848 } 1849 1850 buf_len = fstat.st_size; 1851 buf = rte_malloc(NULL, buf_len, 0); 1852 1853 if (!buf) { 1854 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", 1855 buf_len); 1856 fclose(file); 1857 return -1; 1858 } 1859 1860 err = fread(buf, buf_len, 1, file); 1861 if (err != 1) { 1862 PMD_INIT_LOG(ERR, "failed to read package data\n"); 1863 fclose(file); 1864 err = -1; 1865 goto fail_exit; 1866 } 1867 1868 fclose(file); 1869 1870 err = ice_copy_and_init_pkg(hw, buf, buf_len); 1871 if (err) { 1872 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1873 goto fail_exit; 1874 } 1875 1876 /* store the loaded pkg type info */ 1877 ad->active_pkg_type = ice_load_pkg_type(hw); 1878 1879 err = ice_init_hw_tbls(hw); 1880 if (err) { 1881 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); 1882 goto fail_init_tbls; 1883 } 1884 1885 return 0; 1886 1887 fail_init_tbls: 1888 rte_free(hw->pkg_copy); 1889 fail_exit: 1890 rte_free(buf); 1891 return err; 1892 } 1893 1894 static void 1895 ice_base_queue_get(struct ice_pf *pf) 1896 { 1897 uint32_t reg; 1898 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1899 1900 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); 1901 if (reg & PFLAN_RX_QALLOC_VALID_M) { 1902 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; 1903 } else { 1904 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" 1905 " index"); 1906 } 1907 } 1908 1909 static int 1910 parse_bool(const char *key, const char *value, void *args) 1911 { 1912 int *i = (int *)args; 1913 char *end; 1914 int num; 1915 1916 num = strtoul(value, &end, 10); 1917 1918 if (num != 0 && num != 1) { 1919 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 1920 "value must be 0 or 1", 1921 value, key); 1922 return -1; 1923 } 1924 1925 *i = num; 1926 return 0; 1927 } 1928 1929 static int ice_parse_devargs(struct rte_eth_dev *dev) 1930 { 1931 struct ice_adapter *ad = 1932 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1933 struct rte_devargs *devargs = dev->device->devargs; 1934 struct rte_kvargs *kvlist; 1935 int ret; 1936 1937 if (devargs == NULL) 1938 return 0; 1939 1940 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args); 1941 if (kvlist == NULL) { 1942 PMD_INIT_LOG(ERR, "Invalid kvargs key\n"); 1943 return -EINVAL; 1944 } 1945 1946 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE; 1947 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE, 1948 sizeof(ad->devargs.proto_xtr)); 1949 1950 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG, 1951 &handle_proto_xtr_arg, &ad->devargs); 1952 if (ret) 1953 goto bail; 1954 1955 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, 1956 &parse_bool, &ad->devargs.safe_mode_support); 1957 if (ret) 1958 goto bail; 1959 1960 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, 1961 &parse_bool, &ad->devargs.pipe_mode_support); 1962 if (ret) 1963 goto bail; 1964 1965 bail: 1966 rte_kvargs_free(kvlist); 1967 return ret; 1968 } 1969 1970 /* Forward LLDP packets to default VSI by set switch rules */ 1971 static int 1972 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on) 1973 { 1974 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1975 struct ice_fltr_list_entry *s_list_itr = NULL; 1976 struct LIST_HEAD_TYPE list_head; 1977 int ret = 0; 1978 1979 INIT_LIST_HEAD(&list_head); 1980 1981 s_list_itr = (struct ice_fltr_list_entry *) 1982 ice_malloc(hw, sizeof(*s_list_itr)); 1983 if (!s_list_itr) 1984 return -ENOMEM; 1985 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE; 1986 s_list_itr->fltr_info.vsi_handle = vsi->idx; 1987 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype = 1988 RTE_ETHER_TYPE_LLDP; 1989 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1990 s_list_itr->fltr_info.flag = ICE_FLTR_RX; 1991 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT; 1992 LIST_ADD(&s_list_itr->list_entry, &list_head); 1993 if (on) 1994 ret = ice_add_eth_mac(hw, &list_head); 1995 else 1996 ret = ice_remove_eth_mac(hw, &list_head); 1997 1998 rte_free(s_list_itr); 1999 return ret; 2000 } 2001 2002 static enum ice_status 2003 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, 2004 uint16_t num, uint16_t desc_id, 2005 uint16_t *prof_buf, uint16_t *num_prof) 2006 { 2007 struct ice_aqc_res_elem *resp_buf; 2008 int ret; 2009 uint16_t buf_len; 2010 bool res_shared = 1; 2011 struct ice_aq_desc aq_desc; 2012 struct ice_sq_cd *cd = NULL; 2013 struct ice_aqc_get_allocd_res_desc *cmd = 2014 &aq_desc.params.get_res_desc; 2015 2016 buf_len = sizeof(*resp_buf) * num; 2017 resp_buf = ice_malloc(hw, buf_len); 2018 if (!resp_buf) 2019 return -ENOMEM; 2020 2021 ice_fill_dflt_direct_cmd_desc(&aq_desc, 2022 ice_aqc_opc_get_allocd_res_desc); 2023 2024 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) & 2025 ICE_AQC_RES_TYPE_M) | (res_shared ? 2026 ICE_AQC_RES_TYPE_FLAG_SHARED : 0)); 2027 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id); 2028 2029 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd); 2030 if (!ret) 2031 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc); 2032 else 2033 goto exit; 2034 2035 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) * 2036 (*num_prof), ICE_NONDMA_TO_NONDMA); 2037 2038 exit: 2039 rte_free(resp_buf); 2040 return ret; 2041 } 2042 static int 2043 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type) 2044 { 2045 int ret; 2046 uint16_t prof_id; 2047 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM]; 2048 uint16_t first_desc = 1; 2049 uint16_t num_prof = 0; 2050 2051 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM, 2052 first_desc, prof_buf, &num_prof); 2053 if (ret) { 2054 PMD_INIT_LOG(ERR, "Failed to get fxp resource"); 2055 return ret; 2056 } 2057 2058 for (prof_id = 0; prof_id < num_prof; prof_id++) { 2059 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]); 2060 if (ret) { 2061 PMD_INIT_LOG(ERR, "Failed to free fxp resource"); 2062 return ret; 2063 } 2064 } 2065 return 0; 2066 } 2067 2068 static int 2069 ice_reset_fxp_resource(struct ice_hw *hw) 2070 { 2071 int ret; 2072 2073 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID); 2074 if (ret) { 2075 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource"); 2076 return ret; 2077 } 2078 2079 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID); 2080 if (ret) { 2081 PMD_INIT_LOG(ERR, "Failed to clearup rss resource"); 2082 return ret; 2083 } 2084 2085 return 0; 2086 } 2087 2088 static void 2089 ice_rss_ctx_init(struct ice_pf *pf) 2090 { 2091 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx)); 2092 } 2093 2094 static uint64_t 2095 ice_get_supported_rxdid(struct ice_hw *hw) 2096 { 2097 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */ 2098 uint32_t regval; 2099 int i; 2100 2101 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1); 2102 2103 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) { 2104 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0)); 2105 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) 2106 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) 2107 supported_rxdid |= BIT(i); 2108 } 2109 return supported_rxdid; 2110 } 2111 2112 static int 2113 ice_dev_init(struct rte_eth_dev *dev) 2114 { 2115 struct rte_pci_device *pci_dev; 2116 struct rte_intr_handle *intr_handle; 2117 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2118 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2119 struct ice_adapter *ad = 2120 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2121 struct ice_vsi *vsi; 2122 int ret; 2123 2124 dev->dev_ops = &ice_eth_dev_ops; 2125 dev->rx_queue_count = ice_rx_queue_count; 2126 dev->rx_descriptor_status = ice_rx_descriptor_status; 2127 dev->tx_descriptor_status = ice_tx_descriptor_status; 2128 dev->rx_pkt_burst = ice_recv_pkts; 2129 dev->tx_pkt_burst = ice_xmit_pkts; 2130 dev->tx_pkt_prepare = ice_prep_pkts; 2131 2132 /* for secondary processes, we don't initialise any further as primary 2133 * has already done this work. 2134 */ 2135 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2136 ice_set_rx_function(dev); 2137 ice_set_tx_function(dev); 2138 return 0; 2139 } 2140 2141 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2142 2143 ice_set_default_ptype_table(dev); 2144 pci_dev = RTE_DEV_TO_PCI(dev->device); 2145 intr_handle = &pci_dev->intr_handle; 2146 2147 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2148 pf->adapter->eth_dev = dev; 2149 pf->dev_data = dev->data; 2150 hw->back = pf->adapter; 2151 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 2152 hw->vendor_id = pci_dev->id.vendor_id; 2153 hw->device_id = pci_dev->id.device_id; 2154 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2155 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 2156 hw->bus.device = pci_dev->addr.devid; 2157 hw->bus.func = pci_dev->addr.function; 2158 2159 ret = ice_parse_devargs(dev); 2160 if (ret) { 2161 PMD_INIT_LOG(ERR, "Failed to parse devargs"); 2162 return -EINVAL; 2163 } 2164 2165 ice_init_controlq_parameter(hw); 2166 2167 ret = ice_init_hw(hw); 2168 if (ret) { 2169 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 2170 return -EINVAL; 2171 } 2172 2173 ret = ice_load_pkg(dev); 2174 if (ret) { 2175 if (ad->devargs.safe_mode_support == 0) { 2176 PMD_INIT_LOG(ERR, "Failed to load the DDP package," 2177 "Use safe-mode-support=1 to enter Safe Mode"); 2178 return ret; 2179 } 2180 2181 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 2182 "Entering Safe Mode"); 2183 ad->is_safe_mode = 1; 2184 } 2185 2186 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 2187 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 2188 hw->api_maj_ver, hw->api_min_ver); 2189 2190 ice_pf_sw_init(dev); 2191 ret = ice_init_mac_address(dev); 2192 if (ret) { 2193 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 2194 goto err_init_mac; 2195 } 2196 2197 ret = ice_res_pool_init(&pf->msix_pool, 1, 2198 hw->func_caps.common_cap.num_msix_vectors - 1); 2199 if (ret) { 2200 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 2201 goto err_msix_pool_init; 2202 } 2203 2204 ret = ice_pf_setup(pf); 2205 if (ret) { 2206 PMD_INIT_LOG(ERR, "Failed to setup PF"); 2207 goto err_pf_setup; 2208 } 2209 2210 ret = ice_send_driver_ver(hw); 2211 if (ret) { 2212 PMD_INIT_LOG(ERR, "Failed to send driver version"); 2213 goto err_pf_setup; 2214 } 2215 2216 vsi = pf->main_vsi; 2217 2218 /* Disable double vlan by default */ 2219 ice_vsi_config_double_vlan(vsi, false); 2220 2221 ret = ice_aq_stop_lldp(hw, true, false, NULL); 2222 if (ret != ICE_SUCCESS) 2223 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 2224 ret = ice_init_dcb(hw, true); 2225 if (ret != ICE_SUCCESS) 2226 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n"); 2227 /* Forward LLDP packets to default VSI */ 2228 ret = ice_vsi_config_sw_lldp(vsi, true); 2229 if (ret != ICE_SUCCESS) 2230 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n"); 2231 /* register callback func to eal lib */ 2232 rte_intr_callback_register(intr_handle, 2233 ice_interrupt_handler, dev); 2234 2235 ice_pf_enable_irq0(hw); 2236 2237 /* enable uio intr after callback register */ 2238 rte_intr_enable(intr_handle); 2239 2240 /* get base queue pairs index in the device */ 2241 ice_base_queue_get(pf); 2242 2243 /* Initialize RSS context for gtpu_eh */ 2244 ice_rss_ctx_init(pf); 2245 2246 if (!ad->is_safe_mode) { 2247 ret = ice_flow_init(ad); 2248 if (ret) { 2249 PMD_INIT_LOG(ERR, "Failed to initialize flow"); 2250 return ret; 2251 } 2252 } 2253 2254 ret = ice_reset_fxp_resource(hw); 2255 if (ret) { 2256 PMD_INIT_LOG(ERR, "Failed to reset fxp resource"); 2257 return ret; 2258 } 2259 2260 pf->supported_rxdid = ice_get_supported_rxdid(hw); 2261 2262 return 0; 2263 2264 err_pf_setup: 2265 ice_res_pool_destroy(&pf->msix_pool); 2266 err_msix_pool_init: 2267 rte_free(dev->data->mac_addrs); 2268 dev->data->mac_addrs = NULL; 2269 err_init_mac: 2270 ice_sched_cleanup_all(hw); 2271 rte_free(hw->port_info); 2272 ice_shutdown_all_ctrlq(hw); 2273 rte_free(pf->proto_xtr); 2274 2275 return ret; 2276 } 2277 2278 int 2279 ice_release_vsi(struct ice_vsi *vsi) 2280 { 2281 struct ice_hw *hw; 2282 struct ice_vsi_ctx vsi_ctx; 2283 enum ice_status ret; 2284 int error = 0; 2285 2286 if (!vsi) 2287 return error; 2288 2289 hw = ICE_VSI_TO_HW(vsi); 2290 2291 ice_remove_all_mac_vlan_filters(vsi); 2292 2293 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 2294 2295 vsi_ctx.vsi_num = vsi->vsi_id; 2296 vsi_ctx.info = vsi->info; 2297 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 2298 if (ret != ICE_SUCCESS) { 2299 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 2300 error = -1; 2301 } 2302 2303 rte_free(vsi->rss_lut); 2304 rte_free(vsi->rss_key); 2305 rte_free(vsi); 2306 return error; 2307 } 2308 2309 void 2310 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 2311 { 2312 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2313 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2314 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2315 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2316 uint16_t msix_intr, i; 2317 2318 /* disable interrupt and also clear all the exist config */ 2319 for (i = 0; i < vsi->nb_qps; i++) { 2320 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2321 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2322 rte_wmb(); 2323 } 2324 2325 if (rte_intr_allow_others(intr_handle)) 2326 /* vfio-pci */ 2327 for (i = 0; i < vsi->nb_msix; i++) { 2328 msix_intr = vsi->msix_intr + i; 2329 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2330 GLINT_DYN_CTL_WB_ON_ITR_M); 2331 } 2332 else 2333 /* igb_uio */ 2334 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 2335 } 2336 2337 static int 2338 ice_dev_stop(struct rte_eth_dev *dev) 2339 { 2340 struct rte_eth_dev_data *data = dev->data; 2341 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2342 struct ice_vsi *main_vsi = pf->main_vsi; 2343 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2344 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2345 uint16_t i; 2346 2347 /* avoid stopping again */ 2348 if (pf->adapter_stopped) 2349 return 0; 2350 2351 /* stop and clear all Rx queues */ 2352 for (i = 0; i < data->nb_rx_queues; i++) 2353 ice_rx_queue_stop(dev, i); 2354 2355 /* stop and clear all Tx queues */ 2356 for (i = 0; i < data->nb_tx_queues; i++) 2357 ice_tx_queue_stop(dev, i); 2358 2359 /* disable all queue interrupts */ 2360 ice_vsi_disable_queues_intr(main_vsi); 2361 2362 if (pf->init_link_up) 2363 ice_dev_set_link_up(dev); 2364 else 2365 ice_dev_set_link_down(dev); 2366 2367 /* Clean datapath event and queue/vec mapping */ 2368 rte_intr_efd_disable(intr_handle); 2369 if (intr_handle->intr_vec) { 2370 rte_free(intr_handle->intr_vec); 2371 intr_handle->intr_vec = NULL; 2372 } 2373 2374 pf->adapter_stopped = true; 2375 dev->data->dev_started = 0; 2376 2377 return 0; 2378 } 2379 2380 static int 2381 ice_dev_close(struct rte_eth_dev *dev) 2382 { 2383 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2384 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2385 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2386 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2387 struct ice_adapter *ad = 2388 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2389 int ret; 2390 2391 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2392 return 0; 2393 2394 /* Since stop will make link down, then the link event will be 2395 * triggered, disable the irq firstly to avoid the port_infoe etc 2396 * resources deallocation causing the interrupt service thread 2397 * crash. 2398 */ 2399 ice_pf_disable_irq0(hw); 2400 2401 ret = ice_dev_stop(dev); 2402 2403 if (!ad->is_safe_mode) 2404 ice_flow_uninit(ad); 2405 2406 /* release all queue resource */ 2407 ice_free_queues(dev); 2408 2409 ice_res_pool_destroy(&pf->msix_pool); 2410 ice_release_vsi(pf->main_vsi); 2411 ice_sched_cleanup_all(hw); 2412 ice_free_hw_tbls(hw); 2413 rte_free(hw->port_info); 2414 hw->port_info = NULL; 2415 ice_shutdown_all_ctrlq(hw); 2416 rte_free(pf->proto_xtr); 2417 pf->proto_xtr = NULL; 2418 2419 /* disable uio intr before callback unregister */ 2420 rte_intr_disable(intr_handle); 2421 2422 /* unregister callback func from eal lib */ 2423 rte_intr_callback_unregister(intr_handle, 2424 ice_interrupt_handler, dev); 2425 2426 return ret; 2427 } 2428 2429 static int 2430 ice_dev_uninit(struct rte_eth_dev *dev) 2431 { 2432 ice_dev_close(dev); 2433 2434 return 0; 2435 } 2436 2437 static bool 2438 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg) 2439 { 2440 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false; 2441 } 2442 2443 static void 2444 hash_cfg_reset(struct ice_rss_hash_cfg *cfg) 2445 { 2446 cfg->hash_flds = 0; 2447 cfg->addl_hdrs = 0; 2448 cfg->symm = 0; 2449 cfg->hdr_type = ICE_RSS_ANY_HEADERS; 2450 } 2451 2452 static int 2453 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2454 { 2455 enum ice_status status = ICE_SUCCESS; 2456 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2457 struct ice_vsi *vsi = pf->main_vsi; 2458 2459 if (!is_hash_cfg_valid(cfg)) 2460 return -ENOENT; 2461 2462 status = ice_rem_rss_cfg(hw, vsi->idx, cfg); 2463 if (status && status != ICE_ERR_DOES_NOT_EXIST) { 2464 PMD_DRV_LOG(ERR, 2465 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n", 2466 vsi->idx, status); 2467 return -EBUSY; 2468 } 2469 2470 return 0; 2471 } 2472 2473 static int 2474 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2475 { 2476 enum ice_status status = ICE_SUCCESS; 2477 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2478 struct ice_vsi *vsi = pf->main_vsi; 2479 2480 if (!is_hash_cfg_valid(cfg)) 2481 return -ENOENT; 2482 2483 status = ice_add_rss_cfg(hw, vsi->idx, cfg); 2484 if (status) { 2485 PMD_DRV_LOG(ERR, 2486 "ice_add_rss_cfg failed for VSI:%d, error:%d\n", 2487 vsi->idx, status); 2488 return -EBUSY; 2489 } 2490 2491 return 0; 2492 } 2493 2494 static int 2495 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2496 { 2497 int ret; 2498 2499 ret = ice_hash_moveout(pf, cfg); 2500 if (ret && (ret != -ENOENT)) 2501 return ret; 2502 2503 hash_cfg_reset(cfg); 2504 2505 return 0; 2506 } 2507 2508 static int 2509 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2510 u8 ctx_idx) 2511 { 2512 int ret; 2513 2514 switch (ctx_idx) { 2515 case ICE_HASH_GTPU_CTX_EH_IP: 2516 ret = ice_hash_remove(pf, 2517 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2518 if (ret && (ret != -ENOENT)) 2519 return ret; 2520 2521 ret = ice_hash_remove(pf, 2522 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2523 if (ret && (ret != -ENOENT)) 2524 return ret; 2525 2526 ret = ice_hash_remove(pf, 2527 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2528 if (ret && (ret != -ENOENT)) 2529 return ret; 2530 2531 ret = ice_hash_remove(pf, 2532 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2533 if (ret && (ret != -ENOENT)) 2534 return ret; 2535 2536 ret = ice_hash_remove(pf, 2537 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2538 if (ret && (ret != -ENOENT)) 2539 return ret; 2540 2541 ret = ice_hash_remove(pf, 2542 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2543 if (ret && (ret != -ENOENT)) 2544 return ret; 2545 2546 ret = ice_hash_remove(pf, 2547 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2548 if (ret && (ret != -ENOENT)) 2549 return ret; 2550 2551 ret = ice_hash_remove(pf, 2552 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2553 if (ret && (ret != -ENOENT)) 2554 return ret; 2555 2556 break; 2557 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 2558 ret = ice_hash_remove(pf, 2559 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2560 if (ret && (ret != -ENOENT)) 2561 return ret; 2562 2563 ret = ice_hash_remove(pf, 2564 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2565 if (ret && (ret != -ENOENT)) 2566 return ret; 2567 2568 ret = ice_hash_moveout(pf, 2569 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2570 if (ret && (ret != -ENOENT)) 2571 return ret; 2572 2573 ret = ice_hash_moveout(pf, 2574 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2575 if (ret && (ret != -ENOENT)) 2576 return ret; 2577 2578 ret = ice_hash_moveout(pf, 2579 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2580 if (ret && (ret != -ENOENT)) 2581 return ret; 2582 2583 ret = ice_hash_moveout(pf, 2584 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2585 if (ret && (ret != -ENOENT)) 2586 return ret; 2587 2588 break; 2589 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 2590 ret = ice_hash_remove(pf, 2591 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2592 if (ret && (ret != -ENOENT)) 2593 return ret; 2594 2595 ret = ice_hash_remove(pf, 2596 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2597 if (ret && (ret != -ENOENT)) 2598 return ret; 2599 2600 ret = ice_hash_moveout(pf, 2601 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2602 if (ret && (ret != -ENOENT)) 2603 return ret; 2604 2605 ret = ice_hash_moveout(pf, 2606 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2607 if (ret && (ret != -ENOENT)) 2608 return ret; 2609 2610 ret = ice_hash_moveout(pf, 2611 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2612 if (ret && (ret != -ENOENT)) 2613 return ret; 2614 2615 ret = ice_hash_moveout(pf, 2616 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2617 if (ret && (ret != -ENOENT)) 2618 return ret; 2619 2620 break; 2621 case ICE_HASH_GTPU_CTX_UP_IP: 2622 ret = ice_hash_remove(pf, 2623 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2624 if (ret && (ret != -ENOENT)) 2625 return ret; 2626 2627 ret = ice_hash_remove(pf, 2628 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2629 if (ret && (ret != -ENOENT)) 2630 return ret; 2631 2632 ret = ice_hash_moveout(pf, 2633 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2634 if (ret && (ret != -ENOENT)) 2635 return ret; 2636 2637 ret = ice_hash_moveout(pf, 2638 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2639 if (ret && (ret != -ENOENT)) 2640 return ret; 2641 2642 ret = ice_hash_moveout(pf, 2643 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2644 if (ret && (ret != -ENOENT)) 2645 return ret; 2646 2647 break; 2648 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 2649 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 2650 ret = ice_hash_moveout(pf, 2651 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2652 if (ret && (ret != -ENOENT)) 2653 return ret; 2654 2655 ret = ice_hash_moveout(pf, 2656 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2657 if (ret && (ret != -ENOENT)) 2658 return ret; 2659 2660 ret = ice_hash_moveout(pf, 2661 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2662 if (ret && (ret != -ENOENT)) 2663 return ret; 2664 2665 break; 2666 case ICE_HASH_GTPU_CTX_DW_IP: 2667 ret = ice_hash_remove(pf, 2668 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2669 if (ret && (ret != -ENOENT)) 2670 return ret; 2671 2672 ret = ice_hash_remove(pf, 2673 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2674 if (ret && (ret != -ENOENT)) 2675 return ret; 2676 2677 ret = ice_hash_moveout(pf, 2678 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2679 if (ret && (ret != -ENOENT)) 2680 return ret; 2681 2682 ret = ice_hash_moveout(pf, 2683 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2684 if (ret && (ret != -ENOENT)) 2685 return ret; 2686 2687 ret = ice_hash_moveout(pf, 2688 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2689 if (ret && (ret != -ENOENT)) 2690 return ret; 2691 2692 break; 2693 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 2694 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 2695 ret = ice_hash_moveout(pf, 2696 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2697 if (ret && (ret != -ENOENT)) 2698 return ret; 2699 2700 ret = ice_hash_moveout(pf, 2701 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2702 if (ret && (ret != -ENOENT)) 2703 return ret; 2704 2705 ret = ice_hash_moveout(pf, 2706 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2707 if (ret && (ret != -ENOENT)) 2708 return ret; 2709 2710 break; 2711 default: 2712 break; 2713 } 2714 2715 return 0; 2716 } 2717 2718 static u8 calc_gtpu_ctx_idx(uint32_t hdr) 2719 { 2720 u8 eh_idx, ip_idx; 2721 2722 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) 2723 eh_idx = 0; 2724 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP) 2725 eh_idx = 1; 2726 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN) 2727 eh_idx = 2; 2728 else 2729 return ICE_HASH_GTPU_CTX_MAX; 2730 2731 ip_idx = 0; 2732 if (hdr & ICE_FLOW_SEG_HDR_UDP) 2733 ip_idx = 1; 2734 else if (hdr & ICE_FLOW_SEG_HDR_TCP) 2735 ip_idx = 2; 2736 2737 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)) 2738 return eh_idx * 3 + ip_idx; 2739 else 2740 return ICE_HASH_GTPU_CTX_MAX; 2741 } 2742 2743 static int 2744 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr) 2745 { 2746 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2747 2748 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2749 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4, 2750 gtpu_ctx_idx); 2751 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2752 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6, 2753 gtpu_ctx_idx); 2754 2755 return 0; 2756 } 2757 2758 static int 2759 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2760 u8 ctx_idx, struct ice_rss_hash_cfg *cfg) 2761 { 2762 int ret; 2763 2764 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX) 2765 ctx->ctx[ctx_idx] = *cfg; 2766 2767 switch (ctx_idx) { 2768 case ICE_HASH_GTPU_CTX_EH_IP: 2769 break; 2770 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 2771 ret = ice_hash_moveback(pf, 2772 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2773 if (ret && (ret != -ENOENT)) 2774 return ret; 2775 2776 ret = ice_hash_moveback(pf, 2777 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 2778 if (ret && (ret != -ENOENT)) 2779 return ret; 2780 2781 ret = ice_hash_moveback(pf, 2782 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2783 if (ret && (ret != -ENOENT)) 2784 return ret; 2785 2786 ret = ice_hash_moveback(pf, 2787 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 2788 if (ret && (ret != -ENOENT)) 2789 return ret; 2790 2791 break; 2792 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 2793 ret = ice_hash_moveback(pf, 2794 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2795 if (ret && (ret != -ENOENT)) 2796 return ret; 2797 2798 ret = ice_hash_moveback(pf, 2799 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2800 if (ret && (ret != -ENOENT)) 2801 return ret; 2802 2803 ret = ice_hash_moveback(pf, 2804 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 2805 if (ret && (ret != -ENOENT)) 2806 return ret; 2807 2808 ret = ice_hash_moveback(pf, 2809 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 2810 if (ret && (ret != -ENOENT)) 2811 return ret; 2812 2813 break; 2814 case ICE_HASH_GTPU_CTX_UP_IP: 2815 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 2816 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 2817 case ICE_HASH_GTPU_CTX_DW_IP: 2818 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 2819 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 2820 ret = ice_hash_moveback(pf, 2821 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 2822 if (ret && (ret != -ENOENT)) 2823 return ret; 2824 2825 ret = ice_hash_moveback(pf, 2826 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2827 if (ret && (ret != -ENOENT)) 2828 return ret; 2829 2830 ret = ice_hash_moveback(pf, 2831 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2832 if (ret && (ret != -ENOENT)) 2833 return ret; 2834 2835 break; 2836 default: 2837 break; 2838 } 2839 2840 return 0; 2841 } 2842 2843 static int 2844 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2845 { 2846 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs); 2847 2848 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4) 2849 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4, 2850 gtpu_ctx_idx, cfg); 2851 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6) 2852 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6, 2853 gtpu_ctx_idx, cfg); 2854 2855 return 0; 2856 } 2857 2858 static void 2859 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr) 2860 { 2861 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 2862 2863 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX) 2864 return; 2865 2866 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 2867 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]); 2868 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 2869 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]); 2870 } 2871 2872 int 2873 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 2874 struct ice_rss_hash_cfg *cfg) 2875 { 2876 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2877 int ret; 2878 2879 ret = ice_rem_rss_cfg(hw, vsi_id, cfg); 2880 if (ret && ret != ICE_ERR_DOES_NOT_EXIST) 2881 PMD_DRV_LOG(ERR, "remove rss cfg failed\n"); 2882 2883 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs); 2884 2885 return 0; 2886 } 2887 2888 int 2889 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 2890 struct ice_rss_hash_cfg *cfg) 2891 { 2892 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2893 int ret; 2894 2895 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs); 2896 if (ret) 2897 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n"); 2898 2899 ret = ice_add_rss_cfg(hw, vsi_id, cfg); 2900 if (ret) 2901 PMD_DRV_LOG(ERR, "add rss cfg failed\n"); 2902 2903 ret = ice_add_rss_cfg_post(pf, cfg); 2904 if (ret) 2905 PMD_DRV_LOG(ERR, "add rss cfg post failed\n"); 2906 2907 return 0; 2908 } 2909 2910 static void 2911 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf) 2912 { 2913 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2914 struct ice_vsi *vsi = pf->main_vsi; 2915 struct ice_rss_hash_cfg cfg; 2916 int ret; 2917 2918 #define ICE_RSS_HF_ALL ( \ 2919 ETH_RSS_IPV4 | \ 2920 ETH_RSS_IPV6 | \ 2921 ETH_RSS_NONFRAG_IPV4_UDP | \ 2922 ETH_RSS_NONFRAG_IPV6_UDP | \ 2923 ETH_RSS_NONFRAG_IPV4_TCP | \ 2924 ETH_RSS_NONFRAG_IPV6_TCP | \ 2925 ETH_RSS_NONFRAG_IPV4_SCTP | \ 2926 ETH_RSS_NONFRAG_IPV6_SCTP) 2927 2928 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx); 2929 if (ret) 2930 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d", 2931 __func__, ret); 2932 2933 cfg.symm = 0; 2934 cfg.hdr_type = ICE_RSS_ANY_HEADERS; 2935 /* Configure RSS for IPv4 with src/dst addr as input set */ 2936 if (rss_hf & ETH_RSS_IPV4) { 2937 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 2938 cfg.hash_flds = ICE_FLOW_HASH_IPV4; 2939 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2940 if (ret) 2941 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", 2942 __func__, ret); 2943 } 2944 2945 /* Configure RSS for IPv6 with src/dst addr as input set */ 2946 if (rss_hf & ETH_RSS_IPV6) { 2947 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 2948 cfg.hash_flds = ICE_FLOW_HASH_IPV6; 2949 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2950 if (ret) 2951 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", 2952 __func__, ret); 2953 } 2954 2955 /* Configure RSS for udp4 with src/dst addr and port as input set */ 2956 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 2957 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 | 2958 ICE_FLOW_SEG_HDR_IPV_OTHER; 2959 cfg.hash_flds = ICE_HASH_UDP_IPV4; 2960 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2961 if (ret) 2962 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", 2963 __func__, ret); 2964 } 2965 2966 /* Configure RSS for udp6 with src/dst addr and port as input set */ 2967 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 2968 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 | 2969 ICE_FLOW_SEG_HDR_IPV_OTHER; 2970 cfg.hash_flds = ICE_HASH_UDP_IPV6; 2971 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2972 if (ret) 2973 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", 2974 __func__, ret); 2975 } 2976 2977 /* Configure RSS for tcp4 with src/dst addr and port as input set */ 2978 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 2979 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 | 2980 ICE_FLOW_SEG_HDR_IPV_OTHER; 2981 cfg.hash_flds = ICE_HASH_TCP_IPV4; 2982 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2983 if (ret) 2984 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", 2985 __func__, ret); 2986 } 2987 2988 /* Configure RSS for tcp6 with src/dst addr and port as input set */ 2989 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 2990 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 | 2991 ICE_FLOW_SEG_HDR_IPV_OTHER; 2992 cfg.hash_flds = ICE_HASH_TCP_IPV6; 2993 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 2994 if (ret) 2995 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", 2996 __func__, ret); 2997 } 2998 2999 /* Configure RSS for sctp4 with src/dst addr and port as input set */ 3000 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) { 3001 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 | 3002 ICE_FLOW_SEG_HDR_IPV_OTHER; 3003 cfg.hash_flds = ICE_HASH_SCTP_IPV4; 3004 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3005 if (ret) 3006 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 3007 __func__, ret); 3008 } 3009 3010 /* Configure RSS for sctp6 with src/dst addr and port as input set */ 3011 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) { 3012 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 | 3013 ICE_FLOW_SEG_HDR_IPV_OTHER; 3014 cfg.hash_flds = ICE_HASH_SCTP_IPV6; 3015 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3016 if (ret) 3017 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 3018 __func__, ret); 3019 } 3020 3021 if (rss_hf & ETH_RSS_IPV4) { 3022 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 | 3023 ICE_FLOW_SEG_HDR_IPV_OTHER; 3024 cfg.hash_flds = ICE_FLOW_HASH_IPV4; 3025 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3026 if (ret) 3027 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d", 3028 __func__, ret); 3029 3030 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 | 3031 ICE_FLOW_SEG_HDR_IPV_OTHER; 3032 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3033 if (ret) 3034 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d", 3035 __func__, ret); 3036 3037 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 | 3038 ICE_FLOW_SEG_HDR_IPV_OTHER; 3039 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3040 if (ret) 3041 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d", 3042 __func__, ret); 3043 } 3044 3045 if (rss_hf & ETH_RSS_IPV6) { 3046 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 | 3047 ICE_FLOW_SEG_HDR_IPV_OTHER; 3048 cfg.hash_flds = ICE_FLOW_HASH_IPV6; 3049 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3050 if (ret) 3051 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d", 3052 __func__, ret); 3053 3054 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 | 3055 ICE_FLOW_SEG_HDR_IPV_OTHER; 3056 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3057 if (ret) 3058 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d", 3059 __func__, ret); 3060 3061 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 | 3062 ICE_FLOW_SEG_HDR_IPV_OTHER; 3063 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3064 if (ret) 3065 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d", 3066 __func__, ret); 3067 } 3068 3069 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 3070 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP | 3071 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3072 cfg.hash_flds = ICE_HASH_UDP_IPV4; 3073 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3074 if (ret) 3075 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d", 3076 __func__, ret); 3077 3078 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP | 3079 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3080 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3081 if (ret) 3082 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d", 3083 __func__, ret); 3084 3085 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP | 3086 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3087 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3088 if (ret) 3089 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d", 3090 __func__, ret); 3091 } 3092 3093 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) { 3094 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP | 3095 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3096 cfg.hash_flds = ICE_HASH_UDP_IPV6; 3097 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3098 if (ret) 3099 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d", 3100 __func__, ret); 3101 3102 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP | 3103 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3104 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3105 if (ret) 3106 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d", 3107 __func__, ret); 3108 3109 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP | 3110 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3111 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3112 if (ret) 3113 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d", 3114 __func__, ret); 3115 } 3116 3117 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 3118 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP | 3119 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3120 cfg.hash_flds = ICE_HASH_TCP_IPV4; 3121 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3122 if (ret) 3123 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d", 3124 __func__, ret); 3125 3126 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP | 3127 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3128 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3129 if (ret) 3130 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d", 3131 __func__, ret); 3132 3133 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP | 3134 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3135 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3136 if (ret) 3137 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d", 3138 __func__, ret); 3139 } 3140 3141 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) { 3142 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP | 3143 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3144 cfg.hash_flds = ICE_HASH_TCP_IPV6; 3145 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3146 if (ret) 3147 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d", 3148 __func__, ret); 3149 3150 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP | 3151 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3152 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3153 if (ret) 3154 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d", 3155 __func__, ret); 3156 3157 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP | 3158 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3159 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3160 if (ret) 3161 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d", 3162 __func__, ret); 3163 } 3164 3165 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL; 3166 } 3167 3168 static int ice_init_rss(struct ice_pf *pf) 3169 { 3170 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3171 struct ice_vsi *vsi = pf->main_vsi; 3172 struct rte_eth_dev *dev = pf->adapter->eth_dev; 3173 struct ice_aq_get_set_rss_lut_params lut_params; 3174 struct rte_eth_rss_conf *rss_conf; 3175 struct ice_aqc_get_set_rss_keys key; 3176 uint16_t i, nb_q; 3177 int ret = 0; 3178 bool is_safe_mode = pf->adapter->is_safe_mode; 3179 uint32_t reg; 3180 3181 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 3182 nb_q = dev->data->nb_rx_queues; 3183 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 3184 vsi->rss_lut_size = pf->hash_lut_size; 3185 3186 if (nb_q == 0) { 3187 PMD_DRV_LOG(WARNING, 3188 "RSS is not supported as rx queues number is zero\n"); 3189 return 0; 3190 } 3191 3192 if (is_safe_mode) { 3193 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 3194 return 0; 3195 } 3196 3197 if (!vsi->rss_key) { 3198 vsi->rss_key = rte_zmalloc(NULL, 3199 vsi->rss_key_size, 0); 3200 if (vsi->rss_key == NULL) { 3201 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3202 return -ENOMEM; 3203 } 3204 } 3205 if (!vsi->rss_lut) { 3206 vsi->rss_lut = rte_zmalloc(NULL, 3207 vsi->rss_lut_size, 0); 3208 if (vsi->rss_lut == NULL) { 3209 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3210 rte_free(vsi->rss_key); 3211 vsi->rss_key = NULL; 3212 return -ENOMEM; 3213 } 3214 } 3215 /* configure RSS key */ 3216 if (!rss_conf->rss_key) { 3217 /* Calculate the default hash key */ 3218 for (i = 0; i <= vsi->rss_key_size; i++) 3219 vsi->rss_key[i] = (uint8_t)rte_rand(); 3220 } else { 3221 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 3222 RTE_MIN(rss_conf->rss_key_len, 3223 vsi->rss_key_size)); 3224 } 3225 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 3226 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 3227 if (ret) 3228 goto out; 3229 3230 /* init RSS LUT table */ 3231 for (i = 0; i < vsi->rss_lut_size; i++) 3232 vsi->rss_lut[i] = i % nb_q; 3233 3234 lut_params.vsi_handle = vsi->idx; 3235 lut_params.lut_size = vsi->rss_lut_size; 3236 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 3237 lut_params.lut = vsi->rss_lut; 3238 lut_params.global_lut_id = 0; 3239 ret = ice_aq_set_rss_lut(hw, &lut_params); 3240 if (ret) 3241 goto out; 3242 3243 /* Enable registers for symmetric_toeplitz function. */ 3244 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id)); 3245 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) | 3246 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S); 3247 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg); 3248 3249 /* RSS hash configuration */ 3250 ice_rss_hash_set(pf, rss_conf->rss_hf); 3251 3252 return 0; 3253 out: 3254 rte_free(vsi->rss_key); 3255 vsi->rss_key = NULL; 3256 rte_free(vsi->rss_lut); 3257 vsi->rss_lut = NULL; 3258 return -EINVAL; 3259 } 3260 3261 static int 3262 ice_dev_configure(struct rte_eth_dev *dev) 3263 { 3264 struct ice_adapter *ad = 3265 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 3266 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3267 int ret; 3268 3269 /* Initialize to TRUE. If any of Rx queues doesn't meet the 3270 * bulk allocation or vector Rx preconditions we will reset it. 3271 */ 3272 ad->rx_bulk_alloc_allowed = true; 3273 ad->tx_simple_allowed = true; 3274 3275 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 3276 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 3277 3278 if (dev->data->nb_rx_queues) { 3279 ret = ice_init_rss(pf); 3280 if (ret) { 3281 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 3282 return ret; 3283 } 3284 } 3285 3286 return 0; 3287 } 3288 3289 static void 3290 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 3291 int base_queue, int nb_queue) 3292 { 3293 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3294 uint32_t val, val_tx; 3295 int i; 3296 3297 for (i = 0; i < nb_queue; i++) { 3298 /*do actual bind*/ 3299 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 3300 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 3301 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 3302 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 3303 3304 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 3305 base_queue + i, msix_vect); 3306 /* set ITR0 value */ 3307 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); 3308 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 3309 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 3310 } 3311 } 3312 3313 void 3314 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 3315 { 3316 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 3317 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3318 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3319 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3320 uint16_t msix_vect = vsi->msix_intr; 3321 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 3322 uint16_t queue_idx = 0; 3323 int record = 0; 3324 int i; 3325 3326 /* clear Rx/Tx queue interrupt */ 3327 for (i = 0; i < vsi->nb_used_qps; i++) { 3328 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 3329 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 3330 } 3331 3332 /* PF bind interrupt */ 3333 if (rte_intr_dp_is_en(intr_handle)) { 3334 queue_idx = 0; 3335 record = 1; 3336 } 3337 3338 for (i = 0; i < vsi->nb_used_qps; i++) { 3339 if (nb_msix <= 1) { 3340 if (!rte_intr_allow_others(intr_handle)) 3341 msix_vect = ICE_MISC_VEC_ID; 3342 3343 /* uio mapping all queue to one msix_vect */ 3344 __vsi_queues_bind_intr(vsi, msix_vect, 3345 vsi->base_queue + i, 3346 vsi->nb_used_qps - i); 3347 3348 for (; !!record && i < vsi->nb_used_qps; i++) 3349 intr_handle->intr_vec[queue_idx + i] = 3350 msix_vect; 3351 break; 3352 } 3353 3354 /* vfio 1:1 queue/msix_vect mapping */ 3355 __vsi_queues_bind_intr(vsi, msix_vect, 3356 vsi->base_queue + i, 1); 3357 3358 if (!!record) 3359 intr_handle->intr_vec[queue_idx + i] = msix_vect; 3360 3361 msix_vect++; 3362 nb_msix--; 3363 } 3364 } 3365 3366 void 3367 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 3368 { 3369 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 3370 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3371 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3372 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3373 uint16_t msix_intr, i; 3374 3375 if (rte_intr_allow_others(intr_handle)) 3376 for (i = 0; i < vsi->nb_used_qps; i++) { 3377 msix_intr = vsi->msix_intr + i; 3378 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 3379 GLINT_DYN_CTL_INTENA_M | 3380 GLINT_DYN_CTL_CLEARPBA_M | 3381 GLINT_DYN_CTL_ITR_INDX_M | 3382 GLINT_DYN_CTL_WB_ON_ITR_M); 3383 } 3384 else 3385 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 3386 GLINT_DYN_CTL_INTENA_M | 3387 GLINT_DYN_CTL_CLEARPBA_M | 3388 GLINT_DYN_CTL_ITR_INDX_M | 3389 GLINT_DYN_CTL_WB_ON_ITR_M); 3390 } 3391 3392 static int 3393 ice_rxq_intr_setup(struct rte_eth_dev *dev) 3394 { 3395 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3396 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3397 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3398 struct ice_vsi *vsi = pf->main_vsi; 3399 uint32_t intr_vector = 0; 3400 3401 rte_intr_disable(intr_handle); 3402 3403 /* check and configure queue intr-vector mapping */ 3404 if ((rte_intr_cap_multiple(intr_handle) || 3405 !RTE_ETH_DEV_SRIOV(dev).active) && 3406 dev->data->dev_conf.intr_conf.rxq != 0) { 3407 intr_vector = dev->data->nb_rx_queues; 3408 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 3409 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 3410 ICE_MAX_INTR_QUEUE_NUM); 3411 return -ENOTSUP; 3412 } 3413 if (rte_intr_efd_enable(intr_handle, intr_vector)) 3414 return -1; 3415 } 3416 3417 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 3418 intr_handle->intr_vec = 3419 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 3420 0); 3421 if (!intr_handle->intr_vec) { 3422 PMD_DRV_LOG(ERR, 3423 "Failed to allocate %d rx_queues intr_vec", 3424 dev->data->nb_rx_queues); 3425 return -ENOMEM; 3426 } 3427 } 3428 3429 /* Map queues with MSIX interrupt */ 3430 vsi->nb_used_qps = dev->data->nb_rx_queues; 3431 ice_vsi_queues_bind_intr(vsi); 3432 3433 /* Enable interrupts for all the queues */ 3434 ice_vsi_enable_queues_intr(vsi); 3435 3436 rte_intr_enable(intr_handle); 3437 3438 return 0; 3439 } 3440 3441 static void 3442 ice_get_init_link_status(struct rte_eth_dev *dev) 3443 { 3444 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3445 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3446 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3447 struct ice_link_status link_status; 3448 int ret; 3449 3450 ret = ice_aq_get_link_info(hw->port_info, enable_lse, 3451 &link_status, NULL); 3452 if (ret != ICE_SUCCESS) { 3453 PMD_DRV_LOG(ERR, "Failed to get link info"); 3454 pf->init_link_up = false; 3455 return; 3456 } 3457 3458 if (link_status.link_info & ICE_AQ_LINK_UP) 3459 pf->init_link_up = true; 3460 } 3461 3462 static int 3463 ice_dev_start(struct rte_eth_dev *dev) 3464 { 3465 struct rte_eth_dev_data *data = dev->data; 3466 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3467 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3468 struct ice_vsi *vsi = pf->main_vsi; 3469 uint16_t nb_rxq = 0; 3470 uint16_t nb_txq, i; 3471 uint16_t max_frame_size; 3472 int mask, ret; 3473 3474 /* program Tx queues' context in hardware */ 3475 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 3476 ret = ice_tx_queue_start(dev, nb_txq); 3477 if (ret) { 3478 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 3479 goto tx_err; 3480 } 3481 } 3482 3483 /* program Rx queues' context in hardware*/ 3484 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 3485 ret = ice_rx_queue_start(dev, nb_rxq); 3486 if (ret) { 3487 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 3488 goto rx_err; 3489 } 3490 } 3491 3492 ice_set_rx_function(dev); 3493 ice_set_tx_function(dev); 3494 3495 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 3496 ETH_VLAN_EXTEND_MASK; 3497 ret = ice_vlan_offload_set(dev, mask); 3498 if (ret) { 3499 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 3500 goto rx_err; 3501 } 3502 3503 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 3504 if (ice_rxq_intr_setup(dev)) 3505 return -EIO; 3506 3507 /* Enable receiving broadcast packets and transmitting packets */ 3508 ret = ice_set_vsi_promisc(hw, vsi->idx, 3509 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 3510 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 3511 0); 3512 if (ret != ICE_SUCCESS) 3513 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 3514 3515 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 3516 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 3517 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 3518 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 3519 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 3520 ICE_AQ_LINK_EVENT_AN_COMPLETED | 3521 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 3522 NULL); 3523 if (ret != ICE_SUCCESS) 3524 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 3525 3526 ice_get_init_link_status(dev); 3527 3528 ice_dev_set_link_up(dev); 3529 3530 /* Call get_link_info aq commond to enable/disable LSE */ 3531 ice_link_update(dev, 0); 3532 3533 pf->adapter_stopped = false; 3534 3535 /* Set the max frame size to default value*/ 3536 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ? 3537 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len : 3538 ICE_FRAME_SIZE_MAX; 3539 3540 /* Set the max frame size to HW*/ 3541 ice_aq_set_mac_cfg(hw, max_frame_size, NULL); 3542 3543 return 0; 3544 3545 /* stop the started queues if failed to start all queues */ 3546 rx_err: 3547 for (i = 0; i < nb_rxq; i++) 3548 ice_rx_queue_stop(dev, i); 3549 tx_err: 3550 for (i = 0; i < nb_txq; i++) 3551 ice_tx_queue_stop(dev, i); 3552 3553 return -EIO; 3554 } 3555 3556 static int 3557 ice_dev_reset(struct rte_eth_dev *dev) 3558 { 3559 int ret; 3560 3561 if (dev->data->sriov.active) 3562 return -ENOTSUP; 3563 3564 ret = ice_dev_uninit(dev); 3565 if (ret) { 3566 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 3567 return -ENXIO; 3568 } 3569 3570 ret = ice_dev_init(dev); 3571 if (ret) { 3572 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 3573 return -ENXIO; 3574 } 3575 3576 return 0; 3577 } 3578 3579 static int 3580 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3581 { 3582 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3583 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3584 struct ice_vsi *vsi = pf->main_vsi; 3585 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 3586 bool is_safe_mode = pf->adapter->is_safe_mode; 3587 u64 phy_type_low; 3588 u64 phy_type_high; 3589 3590 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 3591 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 3592 dev_info->max_rx_queues = vsi->nb_qps; 3593 dev_info->max_tx_queues = vsi->nb_qps; 3594 dev_info->max_mac_addrs = vsi->max_macaddrs; 3595 dev_info->max_vfs = pci_dev->max_vfs; 3596 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 3597 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3598 3599 dev_info->rx_offload_capa = 3600 DEV_RX_OFFLOAD_VLAN_STRIP | 3601 DEV_RX_OFFLOAD_JUMBO_FRAME | 3602 DEV_RX_OFFLOAD_KEEP_CRC | 3603 DEV_RX_OFFLOAD_SCATTER | 3604 DEV_RX_OFFLOAD_VLAN_FILTER; 3605 dev_info->tx_offload_capa = 3606 DEV_TX_OFFLOAD_VLAN_INSERT | 3607 DEV_TX_OFFLOAD_TCP_TSO | 3608 DEV_TX_OFFLOAD_MULTI_SEGS | 3609 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3610 dev_info->flow_type_rss_offloads = 0; 3611 3612 if (!is_safe_mode) { 3613 dev_info->rx_offload_capa |= 3614 DEV_RX_OFFLOAD_IPV4_CKSUM | 3615 DEV_RX_OFFLOAD_UDP_CKSUM | 3616 DEV_RX_OFFLOAD_TCP_CKSUM | 3617 DEV_RX_OFFLOAD_QINQ_STRIP | 3618 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3619 DEV_RX_OFFLOAD_VLAN_EXTEND | 3620 DEV_RX_OFFLOAD_RSS_HASH; 3621 dev_info->tx_offload_capa |= 3622 DEV_TX_OFFLOAD_QINQ_INSERT | 3623 DEV_TX_OFFLOAD_IPV4_CKSUM | 3624 DEV_TX_OFFLOAD_UDP_CKSUM | 3625 DEV_TX_OFFLOAD_TCP_CKSUM | 3626 DEV_TX_OFFLOAD_SCTP_CKSUM | 3627 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3628 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 3629 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 3630 } 3631 3632 dev_info->rx_queue_offload_capa = 0; 3633 dev_info->tx_queue_offload_capa = 0; 3634 3635 dev_info->reta_size = pf->hash_lut_size; 3636 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 3637 3638 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3639 .rx_thresh = { 3640 .pthresh = ICE_DEFAULT_RX_PTHRESH, 3641 .hthresh = ICE_DEFAULT_RX_HTHRESH, 3642 .wthresh = ICE_DEFAULT_RX_WTHRESH, 3643 }, 3644 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 3645 .rx_drop_en = 0, 3646 .offloads = 0, 3647 }; 3648 3649 dev_info->default_txconf = (struct rte_eth_txconf) { 3650 .tx_thresh = { 3651 .pthresh = ICE_DEFAULT_TX_PTHRESH, 3652 .hthresh = ICE_DEFAULT_TX_HTHRESH, 3653 .wthresh = ICE_DEFAULT_TX_WTHRESH, 3654 }, 3655 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 3656 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 3657 .offloads = 0, 3658 }; 3659 3660 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3661 .nb_max = ICE_MAX_RING_DESC, 3662 .nb_min = ICE_MIN_RING_DESC, 3663 .nb_align = ICE_ALIGN_RING_DESC, 3664 }; 3665 3666 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3667 .nb_max = ICE_MAX_RING_DESC, 3668 .nb_min = ICE_MIN_RING_DESC, 3669 .nb_align = ICE_ALIGN_RING_DESC, 3670 }; 3671 3672 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3673 ETH_LINK_SPEED_100M | 3674 ETH_LINK_SPEED_1G | 3675 ETH_LINK_SPEED_2_5G | 3676 ETH_LINK_SPEED_5G | 3677 ETH_LINK_SPEED_10G | 3678 ETH_LINK_SPEED_20G | 3679 ETH_LINK_SPEED_25G; 3680 3681 phy_type_low = hw->port_info->phy.phy_type_low; 3682 phy_type_high = hw->port_info->phy.phy_type_high; 3683 3684 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 3685 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 3686 3687 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 3688 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 3689 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 3690 3691 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 3692 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 3693 3694 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 3695 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 3696 dev_info->default_rxportconf.nb_queues = 1; 3697 dev_info->default_txportconf.nb_queues = 1; 3698 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 3699 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 3700 3701 return 0; 3702 } 3703 3704 static inline int 3705 ice_atomic_read_link_status(struct rte_eth_dev *dev, 3706 struct rte_eth_link *link) 3707 { 3708 struct rte_eth_link *dst = link; 3709 struct rte_eth_link *src = &dev->data->dev_link; 3710 3711 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3712 *(uint64_t *)src) == 0) 3713 return -1; 3714 3715 return 0; 3716 } 3717 3718 static inline int 3719 ice_atomic_write_link_status(struct rte_eth_dev *dev, 3720 struct rte_eth_link *link) 3721 { 3722 struct rte_eth_link *dst = &dev->data->dev_link; 3723 struct rte_eth_link *src = link; 3724 3725 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3726 *(uint64_t *)src) == 0) 3727 return -1; 3728 3729 return 0; 3730 } 3731 3732 static int 3733 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 3734 { 3735 #define CHECK_INTERVAL 100 /* 100ms */ 3736 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 3737 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3738 struct ice_link_status link_status; 3739 struct rte_eth_link link, old; 3740 int status; 3741 unsigned int rep_cnt = MAX_REPEAT_TIME; 3742 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3743 3744 memset(&link, 0, sizeof(link)); 3745 memset(&old, 0, sizeof(old)); 3746 memset(&link_status, 0, sizeof(link_status)); 3747 ice_atomic_read_link_status(dev, &old); 3748 3749 do { 3750 /* Get link status information from hardware */ 3751 status = ice_aq_get_link_info(hw->port_info, enable_lse, 3752 &link_status, NULL); 3753 if (status != ICE_SUCCESS) { 3754 link.link_speed = ETH_SPEED_NUM_100M; 3755 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3756 PMD_DRV_LOG(ERR, "Failed to get link info"); 3757 goto out; 3758 } 3759 3760 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 3761 if (!wait_to_complete || link.link_status) 3762 break; 3763 3764 rte_delay_ms(CHECK_INTERVAL); 3765 } while (--rep_cnt); 3766 3767 if (!link.link_status) 3768 goto out; 3769 3770 /* Full-duplex operation at all supported speeds */ 3771 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3772 3773 /* Parse the link status */ 3774 switch (link_status.link_speed) { 3775 case ICE_AQ_LINK_SPEED_10MB: 3776 link.link_speed = ETH_SPEED_NUM_10M; 3777 break; 3778 case ICE_AQ_LINK_SPEED_100MB: 3779 link.link_speed = ETH_SPEED_NUM_100M; 3780 break; 3781 case ICE_AQ_LINK_SPEED_1000MB: 3782 link.link_speed = ETH_SPEED_NUM_1G; 3783 break; 3784 case ICE_AQ_LINK_SPEED_2500MB: 3785 link.link_speed = ETH_SPEED_NUM_2_5G; 3786 break; 3787 case ICE_AQ_LINK_SPEED_5GB: 3788 link.link_speed = ETH_SPEED_NUM_5G; 3789 break; 3790 case ICE_AQ_LINK_SPEED_10GB: 3791 link.link_speed = ETH_SPEED_NUM_10G; 3792 break; 3793 case ICE_AQ_LINK_SPEED_20GB: 3794 link.link_speed = ETH_SPEED_NUM_20G; 3795 break; 3796 case ICE_AQ_LINK_SPEED_25GB: 3797 link.link_speed = ETH_SPEED_NUM_25G; 3798 break; 3799 case ICE_AQ_LINK_SPEED_40GB: 3800 link.link_speed = ETH_SPEED_NUM_40G; 3801 break; 3802 case ICE_AQ_LINK_SPEED_50GB: 3803 link.link_speed = ETH_SPEED_NUM_50G; 3804 break; 3805 case ICE_AQ_LINK_SPEED_100GB: 3806 link.link_speed = ETH_SPEED_NUM_100G; 3807 break; 3808 case ICE_AQ_LINK_SPEED_UNKNOWN: 3809 PMD_DRV_LOG(ERR, "Unknown link speed"); 3810 link.link_speed = ETH_SPEED_NUM_UNKNOWN; 3811 break; 3812 default: 3813 PMD_DRV_LOG(ERR, "None link speed"); 3814 link.link_speed = ETH_SPEED_NUM_NONE; 3815 break; 3816 } 3817 3818 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 3819 ETH_LINK_SPEED_FIXED); 3820 3821 out: 3822 ice_atomic_write_link_status(dev, &link); 3823 if (link.link_status == old.link_status) 3824 return -1; 3825 3826 return 0; 3827 } 3828 3829 /* Force the physical link state by getting the current PHY capabilities from 3830 * hardware and setting the PHY config based on the determined capabilities. If 3831 * link changes, link event will be triggered because both the Enable Automatic 3832 * Link Update and LESM Enable bits are set when setting the PHY capabilities. 3833 */ 3834 static enum ice_status 3835 ice_force_phys_link_state(struct ice_hw *hw, bool link_up) 3836 { 3837 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3838 struct ice_aqc_get_phy_caps_data *pcaps; 3839 struct ice_port_info *pi; 3840 enum ice_status status; 3841 3842 if (!hw || !hw->port_info) 3843 return ICE_ERR_PARAM; 3844 3845 pi = hw->port_info; 3846 3847 pcaps = (struct ice_aqc_get_phy_caps_data *) 3848 ice_malloc(hw, sizeof(*pcaps)); 3849 if (!pcaps) 3850 return ICE_ERR_NO_MEMORY; 3851 3852 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3853 pcaps, NULL); 3854 if (status) 3855 goto out; 3856 3857 /* No change in link */ 3858 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) && 3859 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) 3860 goto out; 3861 3862 cfg.phy_type_low = pcaps->phy_type_low; 3863 cfg.phy_type_high = pcaps->phy_type_high; 3864 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3865 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an; 3866 cfg.eee_cap = pcaps->eee_cap; 3867 cfg.eeer_value = pcaps->eeer_value; 3868 cfg.link_fec_opt = pcaps->link_fec_options; 3869 if (link_up) 3870 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 3871 else 3872 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 3873 3874 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3875 3876 out: 3877 ice_free(hw, pcaps); 3878 return status; 3879 } 3880 3881 static int 3882 ice_dev_set_link_up(struct rte_eth_dev *dev) 3883 { 3884 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3885 3886 return ice_force_phys_link_state(hw, true); 3887 } 3888 3889 static int 3890 ice_dev_set_link_down(struct rte_eth_dev *dev) 3891 { 3892 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3893 3894 return ice_force_phys_link_state(hw, false); 3895 } 3896 3897 static int 3898 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3899 { 3900 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3901 struct rte_eth_dev_data *dev_data = pf->dev_data; 3902 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 3903 3904 /* check if mtu is within the allowed range */ 3905 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 3906 return -EINVAL; 3907 3908 /* mtu setting is forbidden if port is start */ 3909 if (dev_data->dev_started) { 3910 PMD_DRV_LOG(ERR, 3911 "port %d must be stopped before configuration", 3912 dev_data->port_id); 3913 return -EBUSY; 3914 } 3915 3916 if (frame_size > ICE_ETH_MAX_LEN) 3917 dev_data->dev_conf.rxmode.offloads |= 3918 DEV_RX_OFFLOAD_JUMBO_FRAME; 3919 else 3920 dev_data->dev_conf.rxmode.offloads &= 3921 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 3922 3923 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3924 3925 return 0; 3926 } 3927 3928 static int ice_macaddr_set(struct rte_eth_dev *dev, 3929 struct rte_ether_addr *mac_addr) 3930 { 3931 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3932 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3933 struct ice_vsi *vsi = pf->main_vsi; 3934 struct ice_mac_filter *f; 3935 uint8_t flags = 0; 3936 int ret; 3937 3938 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 3939 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 3940 return -EINVAL; 3941 } 3942 3943 TAILQ_FOREACH(f, &vsi->mac_list, next) { 3944 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 3945 break; 3946 } 3947 3948 if (!f) { 3949 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 3950 return -EIO; 3951 } 3952 3953 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 3954 if (ret != ICE_SUCCESS) { 3955 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 3956 return -EIO; 3957 } 3958 ret = ice_add_mac_filter(vsi, mac_addr); 3959 if (ret != ICE_SUCCESS) { 3960 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 3961 return -EIO; 3962 } 3963 rte_ether_addr_copy(mac_addr, &pf->dev_addr); 3964 3965 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 3966 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 3967 if (ret != ICE_SUCCESS) 3968 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 3969 3970 return 0; 3971 } 3972 3973 /* Add a MAC address, and update filters */ 3974 static int 3975 ice_macaddr_add(struct rte_eth_dev *dev, 3976 struct rte_ether_addr *mac_addr, 3977 __rte_unused uint32_t index, 3978 __rte_unused uint32_t pool) 3979 { 3980 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3981 struct ice_vsi *vsi = pf->main_vsi; 3982 int ret; 3983 3984 ret = ice_add_mac_filter(vsi, mac_addr); 3985 if (ret != ICE_SUCCESS) { 3986 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 3987 return -EINVAL; 3988 } 3989 3990 return ICE_SUCCESS; 3991 } 3992 3993 /* Remove a MAC address, and update filters */ 3994 static void 3995 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 3996 { 3997 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3998 struct ice_vsi *vsi = pf->main_vsi; 3999 struct rte_eth_dev_data *data = dev->data; 4000 struct rte_ether_addr *macaddr; 4001 int ret; 4002 4003 macaddr = &data->mac_addrs[index]; 4004 ret = ice_remove_mac_filter(vsi, macaddr); 4005 if (ret) { 4006 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 4007 return; 4008 } 4009 } 4010 4011 static int 4012 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 4013 { 4014 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4015 struct ice_vsi *vsi = pf->main_vsi; 4016 int ret; 4017 4018 PMD_INIT_FUNC_TRACE(); 4019 4020 if (on) { 4021 ret = ice_add_vlan_filter(vsi, vlan_id); 4022 if (ret < 0) { 4023 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 4024 return -EINVAL; 4025 } 4026 } else { 4027 ret = ice_remove_vlan_filter(vsi, vlan_id); 4028 if (ret < 0) { 4029 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 4030 return -EINVAL; 4031 } 4032 } 4033 4034 return 0; 4035 } 4036 4037 /* Configure vlan filter on or off */ 4038 static int 4039 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 4040 { 4041 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4042 struct ice_vsi_ctx ctxt; 4043 uint8_t sec_flags, sw_flags2; 4044 int ret = 0; 4045 4046 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 4047 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 4048 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 4049 4050 if (on) { 4051 vsi->info.sec_flags |= sec_flags; 4052 vsi->info.sw_flags2 |= sw_flags2; 4053 } else { 4054 vsi->info.sec_flags &= ~sec_flags; 4055 vsi->info.sw_flags2 &= ~sw_flags2; 4056 } 4057 vsi->info.sw_id = hw->port_info->sw_id; 4058 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4059 ctxt.info.valid_sections = 4060 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 4061 ICE_AQ_VSI_PROP_SECURITY_VALID); 4062 ctxt.vsi_num = vsi->vsi_id; 4063 4064 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4065 if (ret) { 4066 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 4067 on ? "enable" : "disable"); 4068 return -EINVAL; 4069 } else { 4070 vsi->info.valid_sections |= 4071 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 4072 ICE_AQ_VSI_PROP_SECURITY_VALID); 4073 } 4074 4075 /* consist with other drivers, allow untagged packet when vlan filter on */ 4076 if (on) 4077 ret = ice_add_vlan_filter(vsi, 0); 4078 else 4079 ret = ice_remove_vlan_filter(vsi, 0); 4080 4081 return 0; 4082 } 4083 4084 static int 4085 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 4086 { 4087 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4088 struct ice_vsi_ctx ctxt; 4089 uint8_t vlan_flags; 4090 int ret = 0; 4091 4092 /* Check if it has been already on or off */ 4093 if (vsi->info.valid_sections & 4094 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 4095 if (on) { 4096 if ((vsi->info.inner_vlan_flags & 4097 ICE_AQ_VSI_INNER_VLAN_EMODE_M) == 4098 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH) 4099 return 0; /* already on */ 4100 } else { 4101 if ((vsi->info.inner_vlan_flags & 4102 ICE_AQ_VSI_INNER_VLAN_EMODE_M) == 4103 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING) 4104 return 0; /* already off */ 4105 } 4106 } 4107 4108 if (on) 4109 vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH; 4110 else 4111 vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; 4112 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_EMODE_M); 4113 vsi->info.inner_vlan_flags |= vlan_flags; 4114 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4115 ctxt.info.valid_sections = 4116 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4117 ctxt.vsi_num = vsi->vsi_id; 4118 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4119 if (ret) { 4120 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 4121 on ? "enable" : "disable"); 4122 return -EINVAL; 4123 } 4124 4125 vsi->info.valid_sections |= 4126 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4127 4128 return ret; 4129 } 4130 4131 static int 4132 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 4133 { 4134 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4135 struct ice_vsi *vsi = pf->main_vsi; 4136 struct rte_eth_rxmode *rxmode; 4137 4138 rxmode = &dev->data->dev_conf.rxmode; 4139 if (mask & ETH_VLAN_FILTER_MASK) { 4140 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 4141 ice_vsi_config_vlan_filter(vsi, true); 4142 else 4143 ice_vsi_config_vlan_filter(vsi, false); 4144 } 4145 4146 if (mask & ETH_VLAN_STRIP_MASK) { 4147 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 4148 ice_vsi_config_vlan_stripping(vsi, true); 4149 else 4150 ice_vsi_config_vlan_stripping(vsi, false); 4151 } 4152 4153 if (mask & ETH_VLAN_EXTEND_MASK) { 4154 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 4155 ice_vsi_config_double_vlan(vsi, true); 4156 else 4157 ice_vsi_config_double_vlan(vsi, false); 4158 } 4159 4160 return 0; 4161 } 4162 4163 static int 4164 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4165 { 4166 struct ice_aq_get_set_rss_lut_params lut_params; 4167 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 4168 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4169 int ret; 4170 4171 if (!lut) 4172 return -EINVAL; 4173 4174 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 4175 lut_params.vsi_handle = vsi->idx; 4176 lut_params.lut_size = lut_size; 4177 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 4178 lut_params.lut = lut; 4179 lut_params.global_lut_id = 0; 4180 ret = ice_aq_get_rss_lut(hw, &lut_params); 4181 if (ret) { 4182 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 4183 return -EINVAL; 4184 } 4185 } else { 4186 uint64_t *lut_dw = (uint64_t *)lut; 4187 uint16_t i, lut_size_dw = lut_size / 4; 4188 4189 for (i = 0; i < lut_size_dw; i++) 4190 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 4191 } 4192 4193 return 0; 4194 } 4195 4196 static int 4197 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4198 { 4199 struct ice_aq_get_set_rss_lut_params lut_params; 4200 struct ice_pf *pf; 4201 struct ice_hw *hw; 4202 int ret; 4203 4204 if (!vsi || !lut) 4205 return -EINVAL; 4206 4207 pf = ICE_VSI_TO_PF(vsi); 4208 hw = ICE_VSI_TO_HW(vsi); 4209 4210 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 4211 lut_params.vsi_handle = vsi->idx; 4212 lut_params.lut_size = lut_size; 4213 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 4214 lut_params.lut = lut; 4215 lut_params.global_lut_id = 0; 4216 ret = ice_aq_set_rss_lut(hw, &lut_params); 4217 if (ret) { 4218 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 4219 return -EINVAL; 4220 } 4221 } else { 4222 uint64_t *lut_dw = (uint64_t *)lut; 4223 uint16_t i, lut_size_dw = lut_size / 4; 4224 4225 for (i = 0; i < lut_size_dw; i++) 4226 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 4227 4228 ice_flush(hw); 4229 } 4230 4231 return 0; 4232 } 4233 4234 static int 4235 ice_rss_reta_update(struct rte_eth_dev *dev, 4236 struct rte_eth_rss_reta_entry64 *reta_conf, 4237 uint16_t reta_size) 4238 { 4239 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4240 uint16_t i, lut_size = pf->hash_lut_size; 4241 uint16_t idx, shift; 4242 uint8_t *lut; 4243 int ret; 4244 4245 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 4246 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 4247 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 4248 PMD_DRV_LOG(ERR, 4249 "The size of hash lookup table configured (%d)" 4250 "doesn't match the number hardware can " 4251 "supported (128, 512, 2048)", 4252 reta_size); 4253 return -EINVAL; 4254 } 4255 4256 /* It MUST use the current LUT size to get the RSS lookup table, 4257 * otherwise if will fail with -100 error code. 4258 */ 4259 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 4260 if (!lut) { 4261 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4262 return -ENOMEM; 4263 } 4264 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 4265 if (ret) 4266 goto out; 4267 4268 for (i = 0; i < reta_size; i++) { 4269 idx = i / RTE_RETA_GROUP_SIZE; 4270 shift = i % RTE_RETA_GROUP_SIZE; 4271 if (reta_conf[idx].mask & (1ULL << shift)) 4272 lut[i] = reta_conf[idx].reta[shift]; 4273 } 4274 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 4275 if (ret == 0 && lut_size != reta_size) { 4276 PMD_DRV_LOG(INFO, 4277 "The size of hash lookup table is changed from (%d) to (%d)", 4278 lut_size, reta_size); 4279 pf->hash_lut_size = reta_size; 4280 } 4281 4282 out: 4283 rte_free(lut); 4284 4285 return ret; 4286 } 4287 4288 static int 4289 ice_rss_reta_query(struct rte_eth_dev *dev, 4290 struct rte_eth_rss_reta_entry64 *reta_conf, 4291 uint16_t reta_size) 4292 { 4293 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4294 uint16_t i, lut_size = pf->hash_lut_size; 4295 uint16_t idx, shift; 4296 uint8_t *lut; 4297 int ret; 4298 4299 if (reta_size != lut_size) { 4300 PMD_DRV_LOG(ERR, 4301 "The size of hash lookup table configured (%d)" 4302 "doesn't match the number hardware can " 4303 "supported (%d)", 4304 reta_size, lut_size); 4305 return -EINVAL; 4306 } 4307 4308 lut = rte_zmalloc(NULL, reta_size, 0); 4309 if (!lut) { 4310 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4311 return -ENOMEM; 4312 } 4313 4314 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 4315 if (ret) 4316 goto out; 4317 4318 for (i = 0; i < reta_size; i++) { 4319 idx = i / RTE_RETA_GROUP_SIZE; 4320 shift = i % RTE_RETA_GROUP_SIZE; 4321 if (reta_conf[idx].mask & (1ULL << shift)) 4322 reta_conf[idx].reta[shift] = lut[i]; 4323 } 4324 4325 out: 4326 rte_free(lut); 4327 4328 return ret; 4329 } 4330 4331 static int 4332 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 4333 { 4334 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4335 int ret = 0; 4336 4337 if (!key || key_len == 0) { 4338 PMD_DRV_LOG(DEBUG, "No key to be configured"); 4339 return 0; 4340 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 4341 sizeof(uint32_t)) { 4342 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 4343 return -EINVAL; 4344 } 4345 4346 struct ice_aqc_get_set_rss_keys *key_dw = 4347 (struct ice_aqc_get_set_rss_keys *)key; 4348 4349 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 4350 if (ret) { 4351 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 4352 ret = -EINVAL; 4353 } 4354 4355 return ret; 4356 } 4357 4358 static int 4359 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 4360 { 4361 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4362 int ret; 4363 4364 if (!key || !key_len) 4365 return -EINVAL; 4366 4367 ret = ice_aq_get_rss_key 4368 (hw, vsi->idx, 4369 (struct ice_aqc_get_set_rss_keys *)key); 4370 if (ret) { 4371 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 4372 return -EINVAL; 4373 } 4374 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 4375 4376 return 0; 4377 } 4378 4379 static int 4380 ice_rss_hash_update(struct rte_eth_dev *dev, 4381 struct rte_eth_rss_conf *rss_conf) 4382 { 4383 enum ice_status status = ICE_SUCCESS; 4384 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4385 struct ice_vsi *vsi = pf->main_vsi; 4386 4387 /* set hash key */ 4388 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 4389 if (status) 4390 return status; 4391 4392 if (rss_conf->rss_hf == 0) 4393 return 0; 4394 4395 /* RSS hash configuration */ 4396 ice_rss_hash_set(pf, rss_conf->rss_hf); 4397 4398 return 0; 4399 } 4400 4401 static int 4402 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 4403 struct rte_eth_rss_conf *rss_conf) 4404 { 4405 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4406 struct ice_vsi *vsi = pf->main_vsi; 4407 4408 ice_get_rss_key(vsi, rss_conf->rss_key, 4409 &rss_conf->rss_key_len); 4410 4411 rss_conf->rss_hf = pf->rss_hf; 4412 return 0; 4413 } 4414 4415 static int 4416 ice_promisc_enable(struct rte_eth_dev *dev) 4417 { 4418 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4419 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4420 struct ice_vsi *vsi = pf->main_vsi; 4421 enum ice_status status; 4422 uint8_t pmask; 4423 int ret = 0; 4424 4425 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 4426 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4427 4428 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4429 switch (status) { 4430 case ICE_ERR_ALREADY_EXISTS: 4431 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 4432 case ICE_SUCCESS: 4433 break; 4434 default: 4435 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 4436 ret = -EAGAIN; 4437 } 4438 4439 return ret; 4440 } 4441 4442 static int 4443 ice_promisc_disable(struct rte_eth_dev *dev) 4444 { 4445 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4446 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4447 struct ice_vsi *vsi = pf->main_vsi; 4448 enum ice_status status; 4449 uint8_t pmask; 4450 int ret = 0; 4451 4452 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 4453 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4454 4455 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 4456 if (status != ICE_SUCCESS) { 4457 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 4458 ret = -EAGAIN; 4459 } 4460 4461 return ret; 4462 } 4463 4464 static int 4465 ice_allmulti_enable(struct rte_eth_dev *dev) 4466 { 4467 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4468 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4469 struct ice_vsi *vsi = pf->main_vsi; 4470 enum ice_status status; 4471 uint8_t pmask; 4472 int ret = 0; 4473 4474 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4475 4476 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4477 4478 switch (status) { 4479 case ICE_ERR_ALREADY_EXISTS: 4480 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled"); 4481 case ICE_SUCCESS: 4482 break; 4483 default: 4484 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 4485 ret = -EAGAIN; 4486 } 4487 4488 return ret; 4489 } 4490 4491 static int 4492 ice_allmulti_disable(struct rte_eth_dev *dev) 4493 { 4494 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4495 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4496 struct ice_vsi *vsi = pf->main_vsi; 4497 enum ice_status status; 4498 uint8_t pmask; 4499 int ret = 0; 4500 4501 if (dev->data->promiscuous == 1) 4502 return 0; /* must remain in all_multicast mode */ 4503 4504 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 4505 4506 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 4507 if (status != ICE_SUCCESS) { 4508 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 4509 ret = -EAGAIN; 4510 } 4511 4512 return ret; 4513 } 4514 4515 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 4516 uint16_t queue_id) 4517 { 4518 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 4519 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4520 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4521 uint32_t val; 4522 uint16_t msix_intr; 4523 4524 msix_intr = intr_handle->intr_vec[queue_id]; 4525 4526 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 4527 GLINT_DYN_CTL_ITR_INDX_M; 4528 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 4529 4530 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 4531 rte_intr_ack(&pci_dev->intr_handle); 4532 4533 return 0; 4534 } 4535 4536 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 4537 uint16_t queue_id) 4538 { 4539 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 4540 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4541 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4542 uint16_t msix_intr; 4543 4544 msix_intr = intr_handle->intr_vec[queue_id]; 4545 4546 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 4547 4548 return 0; 4549 } 4550 4551 static int 4552 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 4553 { 4554 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4555 u8 ver, patch; 4556 u16 build; 4557 int ret; 4558 4559 ver = hw->flash.orom.major; 4560 patch = hw->flash.orom.patch; 4561 build = hw->flash.orom.build; 4562 4563 ret = snprintf(fw_version, fw_size, 4564 "%x.%02x 0x%08x %d.%d.%d", 4565 hw->flash.nvm.major, 4566 hw->flash.nvm.minor, 4567 hw->flash.nvm.eetrack, 4568 ver, build, patch); 4569 4570 /* add the size of '\0' */ 4571 ret += 1; 4572 if (fw_size < (u32)ret) 4573 return ret; 4574 else 4575 return 0; 4576 } 4577 4578 static int 4579 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 4580 { 4581 struct ice_hw *hw; 4582 struct ice_vsi_ctx ctxt; 4583 uint8_t vlan_flags = 0; 4584 int ret; 4585 4586 if (!vsi || !info) { 4587 PMD_DRV_LOG(ERR, "invalid parameters"); 4588 return -EINVAL; 4589 } 4590 4591 if (info->on) { 4592 vsi->info.port_based_inner_vlan = info->config.pvid; 4593 /** 4594 * If insert pvid is enabled, only tagged pkts are 4595 * allowed to be sent out. 4596 */ 4597 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | 4598 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; 4599 } else { 4600 vsi->info.port_based_inner_vlan = 0; 4601 if (info->config.reject.tagged == 0) 4602 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED; 4603 4604 if (info->config.reject.untagged == 0) 4605 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; 4606 } 4607 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | 4608 ICE_AQ_VSI_INNER_VLAN_EMODE_M); 4609 vsi->info.inner_vlan_flags |= vlan_flags; 4610 memset(&ctxt, 0, sizeof(ctxt)); 4611 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4612 ctxt.info.valid_sections = 4613 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4614 ctxt.vsi_num = vsi->vsi_id; 4615 4616 hw = ICE_VSI_TO_HW(vsi); 4617 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4618 if (ret != ICE_SUCCESS) { 4619 PMD_DRV_LOG(ERR, 4620 "update VSI for VLAN insert failed, err %d", 4621 ret); 4622 return -EINVAL; 4623 } 4624 4625 vsi->info.valid_sections |= 4626 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4627 4628 return ret; 4629 } 4630 4631 static int 4632 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 4633 { 4634 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4635 struct ice_vsi *vsi = pf->main_vsi; 4636 struct rte_eth_dev_data *data = pf->dev_data; 4637 struct ice_vsi_vlan_pvid_info info; 4638 int ret; 4639 4640 memset(&info, 0, sizeof(info)); 4641 info.on = on; 4642 if (info.on) { 4643 info.config.pvid = pvid; 4644 } else { 4645 info.config.reject.tagged = 4646 data->dev_conf.txmode.hw_vlan_reject_tagged; 4647 info.config.reject.untagged = 4648 data->dev_conf.txmode.hw_vlan_reject_untagged; 4649 } 4650 4651 ret = ice_vsi_vlan_pvid_set(vsi, &info); 4652 if (ret < 0) { 4653 PMD_DRV_LOG(ERR, "Failed to set pvid."); 4654 return -EINVAL; 4655 } 4656 4657 return 0; 4658 } 4659 4660 static int 4661 ice_get_eeprom_length(struct rte_eth_dev *dev) 4662 { 4663 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4664 4665 return hw->flash.flash_size; 4666 } 4667 4668 static int 4669 ice_get_eeprom(struct rte_eth_dev *dev, 4670 struct rte_dev_eeprom_info *eeprom) 4671 { 4672 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4673 enum ice_status status = ICE_SUCCESS; 4674 uint8_t *data = eeprom->data; 4675 4676 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4677 4678 status = ice_acquire_nvm(hw, ICE_RES_READ); 4679 if (status) { 4680 PMD_DRV_LOG(ERR, "acquire nvm failed."); 4681 return -EIO; 4682 } 4683 4684 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length, 4685 data, false); 4686 4687 ice_release_nvm(hw); 4688 4689 if (status) { 4690 PMD_DRV_LOG(ERR, "EEPROM read failed."); 4691 return -EIO; 4692 } 4693 4694 return 0; 4695 } 4696 4697 static void 4698 ice_stat_update_32(struct ice_hw *hw, 4699 uint32_t reg, 4700 bool offset_loaded, 4701 uint64_t *offset, 4702 uint64_t *stat) 4703 { 4704 uint64_t new_data; 4705 4706 new_data = (uint64_t)ICE_READ_REG(hw, reg); 4707 if (!offset_loaded) 4708 *offset = new_data; 4709 4710 if (new_data >= *offset) 4711 *stat = (uint64_t)(new_data - *offset); 4712 else 4713 *stat = (uint64_t)((new_data + 4714 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 4715 - *offset); 4716 } 4717 4718 static void 4719 ice_stat_update_40(struct ice_hw *hw, 4720 uint32_t hireg, 4721 uint32_t loreg, 4722 bool offset_loaded, 4723 uint64_t *offset, 4724 uint64_t *stat) 4725 { 4726 uint64_t new_data; 4727 4728 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 4729 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 4730 ICE_32_BIT_WIDTH; 4731 4732 if (!offset_loaded) 4733 *offset = new_data; 4734 4735 if (new_data >= *offset) 4736 *stat = new_data - *offset; 4737 else 4738 *stat = (uint64_t)((new_data + 4739 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 4740 *offset); 4741 4742 *stat &= ICE_40_BIT_MASK; 4743 } 4744 4745 /* Get all the statistics of a VSI */ 4746 static void 4747 ice_update_vsi_stats(struct ice_vsi *vsi) 4748 { 4749 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 4750 struct ice_eth_stats *nes = &vsi->eth_stats; 4751 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4752 int idx = rte_le_to_cpu_16(vsi->vsi_id); 4753 4754 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 4755 vsi->offset_loaded, &oes->rx_bytes, 4756 &nes->rx_bytes); 4757 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 4758 vsi->offset_loaded, &oes->rx_unicast, 4759 &nes->rx_unicast); 4760 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 4761 vsi->offset_loaded, &oes->rx_multicast, 4762 &nes->rx_multicast); 4763 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 4764 vsi->offset_loaded, &oes->rx_broadcast, 4765 &nes->rx_broadcast); 4766 /* enlarge the limitation when rx_bytes overflowed */ 4767 if (vsi->offset_loaded) { 4768 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes) 4769 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4770 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes); 4771 } 4772 vsi->old_rx_bytes = nes->rx_bytes; 4773 /* exclude CRC bytes */ 4774 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 4775 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 4776 4777 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 4778 &oes->rx_discards, &nes->rx_discards); 4779 /* GLV_REPC not supported */ 4780 /* GLV_RMPC not supported */ 4781 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 4782 &oes->rx_unknown_protocol, 4783 &nes->rx_unknown_protocol); 4784 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 4785 vsi->offset_loaded, &oes->tx_bytes, 4786 &nes->tx_bytes); 4787 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 4788 vsi->offset_loaded, &oes->tx_unicast, 4789 &nes->tx_unicast); 4790 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 4791 vsi->offset_loaded, &oes->tx_multicast, 4792 &nes->tx_multicast); 4793 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 4794 vsi->offset_loaded, &oes->tx_broadcast, 4795 &nes->tx_broadcast); 4796 /* GLV_TDPC not supported */ 4797 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 4798 &oes->tx_errors, &nes->tx_errors); 4799 /* enlarge the limitation when tx_bytes overflowed */ 4800 if (vsi->offset_loaded) { 4801 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes) 4802 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4803 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes); 4804 } 4805 vsi->old_tx_bytes = nes->tx_bytes; 4806 vsi->offset_loaded = true; 4807 4808 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 4809 vsi->vsi_id); 4810 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 4811 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 4812 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 4813 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 4814 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 4815 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 4816 nes->rx_unknown_protocol); 4817 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 4818 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 4819 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 4820 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 4821 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 4822 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 4823 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 4824 vsi->vsi_id); 4825 } 4826 4827 static void 4828 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 4829 { 4830 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 4831 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 4832 4833 /* Get statistics of struct ice_eth_stats */ 4834 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 4835 GLPRT_GORCL(hw->port_info->lport), 4836 pf->offset_loaded, &os->eth.rx_bytes, 4837 &ns->eth.rx_bytes); 4838 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 4839 GLPRT_UPRCL(hw->port_info->lport), 4840 pf->offset_loaded, &os->eth.rx_unicast, 4841 &ns->eth.rx_unicast); 4842 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 4843 GLPRT_MPRCL(hw->port_info->lport), 4844 pf->offset_loaded, &os->eth.rx_multicast, 4845 &ns->eth.rx_multicast); 4846 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 4847 GLPRT_BPRCL(hw->port_info->lport), 4848 pf->offset_loaded, &os->eth.rx_broadcast, 4849 &ns->eth.rx_broadcast); 4850 ice_stat_update_32(hw, PRTRPB_RDPC, 4851 pf->offset_loaded, &os->eth.rx_discards, 4852 &ns->eth.rx_discards); 4853 /* enlarge the limitation when rx_bytes overflowed */ 4854 if (pf->offset_loaded) { 4855 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes) 4856 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4857 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes); 4858 } 4859 pf->old_rx_bytes = ns->eth.rx_bytes; 4860 4861 /* Workaround: CRC size should not be included in byte statistics, 4862 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 4863 * packet. 4864 */ 4865 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 4866 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 4867 4868 /* GLPRT_REPC not supported */ 4869 /* GLPRT_RMPC not supported */ 4870 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 4871 pf->offset_loaded, 4872 &os->eth.rx_unknown_protocol, 4873 &ns->eth.rx_unknown_protocol); 4874 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 4875 GLPRT_GOTCL(hw->port_info->lport), 4876 pf->offset_loaded, &os->eth.tx_bytes, 4877 &ns->eth.tx_bytes); 4878 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 4879 GLPRT_UPTCL(hw->port_info->lport), 4880 pf->offset_loaded, &os->eth.tx_unicast, 4881 &ns->eth.tx_unicast); 4882 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 4883 GLPRT_MPTCL(hw->port_info->lport), 4884 pf->offset_loaded, &os->eth.tx_multicast, 4885 &ns->eth.tx_multicast); 4886 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 4887 GLPRT_BPTCL(hw->port_info->lport), 4888 pf->offset_loaded, &os->eth.tx_broadcast, 4889 &ns->eth.tx_broadcast); 4890 /* enlarge the limitation when tx_bytes overflowed */ 4891 if (pf->offset_loaded) { 4892 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes) 4893 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4894 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes); 4895 } 4896 pf->old_tx_bytes = ns->eth.tx_bytes; 4897 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 4898 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 4899 4900 /* GLPRT_TEPC not supported */ 4901 4902 /* additional port specific stats */ 4903 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 4904 pf->offset_loaded, &os->tx_dropped_link_down, 4905 &ns->tx_dropped_link_down); 4906 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 4907 pf->offset_loaded, &os->crc_errors, 4908 &ns->crc_errors); 4909 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 4910 pf->offset_loaded, &os->illegal_bytes, 4911 &ns->illegal_bytes); 4912 /* GLPRT_ERRBC not supported */ 4913 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 4914 pf->offset_loaded, &os->mac_local_faults, 4915 &ns->mac_local_faults); 4916 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 4917 pf->offset_loaded, &os->mac_remote_faults, 4918 &ns->mac_remote_faults); 4919 4920 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 4921 pf->offset_loaded, &os->rx_len_errors, 4922 &ns->rx_len_errors); 4923 4924 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 4925 pf->offset_loaded, &os->link_xon_rx, 4926 &ns->link_xon_rx); 4927 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 4928 pf->offset_loaded, &os->link_xoff_rx, 4929 &ns->link_xoff_rx); 4930 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 4931 pf->offset_loaded, &os->link_xon_tx, 4932 &ns->link_xon_tx); 4933 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 4934 pf->offset_loaded, &os->link_xoff_tx, 4935 &ns->link_xoff_tx); 4936 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 4937 GLPRT_PRC64L(hw->port_info->lport), 4938 pf->offset_loaded, &os->rx_size_64, 4939 &ns->rx_size_64); 4940 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 4941 GLPRT_PRC127L(hw->port_info->lport), 4942 pf->offset_loaded, &os->rx_size_127, 4943 &ns->rx_size_127); 4944 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 4945 GLPRT_PRC255L(hw->port_info->lport), 4946 pf->offset_loaded, &os->rx_size_255, 4947 &ns->rx_size_255); 4948 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 4949 GLPRT_PRC511L(hw->port_info->lport), 4950 pf->offset_loaded, &os->rx_size_511, 4951 &ns->rx_size_511); 4952 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 4953 GLPRT_PRC1023L(hw->port_info->lport), 4954 pf->offset_loaded, &os->rx_size_1023, 4955 &ns->rx_size_1023); 4956 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 4957 GLPRT_PRC1522L(hw->port_info->lport), 4958 pf->offset_loaded, &os->rx_size_1522, 4959 &ns->rx_size_1522); 4960 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 4961 GLPRT_PRC9522L(hw->port_info->lport), 4962 pf->offset_loaded, &os->rx_size_big, 4963 &ns->rx_size_big); 4964 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 4965 pf->offset_loaded, &os->rx_undersize, 4966 &ns->rx_undersize); 4967 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 4968 pf->offset_loaded, &os->rx_fragments, 4969 &ns->rx_fragments); 4970 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 4971 pf->offset_loaded, &os->rx_oversize, 4972 &ns->rx_oversize); 4973 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 4974 pf->offset_loaded, &os->rx_jabber, 4975 &ns->rx_jabber); 4976 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 4977 GLPRT_PTC64L(hw->port_info->lport), 4978 pf->offset_loaded, &os->tx_size_64, 4979 &ns->tx_size_64); 4980 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 4981 GLPRT_PTC127L(hw->port_info->lport), 4982 pf->offset_loaded, &os->tx_size_127, 4983 &ns->tx_size_127); 4984 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 4985 GLPRT_PTC255L(hw->port_info->lport), 4986 pf->offset_loaded, &os->tx_size_255, 4987 &ns->tx_size_255); 4988 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 4989 GLPRT_PTC511L(hw->port_info->lport), 4990 pf->offset_loaded, &os->tx_size_511, 4991 &ns->tx_size_511); 4992 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 4993 GLPRT_PTC1023L(hw->port_info->lport), 4994 pf->offset_loaded, &os->tx_size_1023, 4995 &ns->tx_size_1023); 4996 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 4997 GLPRT_PTC1522L(hw->port_info->lport), 4998 pf->offset_loaded, &os->tx_size_1522, 4999 &ns->tx_size_1522); 5000 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 5001 GLPRT_PTC9522L(hw->port_info->lport), 5002 pf->offset_loaded, &os->tx_size_big, 5003 &ns->tx_size_big); 5004 5005 /* GLPRT_MSPDC not supported */ 5006 /* GLPRT_XEC not supported */ 5007 5008 pf->offset_loaded = true; 5009 5010 if (pf->main_vsi) 5011 ice_update_vsi_stats(pf->main_vsi); 5012 } 5013 5014 /* Get all statistics of a port */ 5015 static int 5016 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 5017 { 5018 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5019 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5020 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 5021 5022 /* call read registers - updates values, now write them to struct */ 5023 ice_read_stats_registers(pf, hw); 5024 5025 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 5026 pf->main_vsi->eth_stats.rx_multicast + 5027 pf->main_vsi->eth_stats.rx_broadcast - 5028 pf->main_vsi->eth_stats.rx_discards; 5029 stats->opackets = ns->eth.tx_unicast + 5030 ns->eth.tx_multicast + 5031 ns->eth.tx_broadcast; 5032 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 5033 stats->obytes = ns->eth.tx_bytes; 5034 stats->oerrors = ns->eth.tx_errors + 5035 pf->main_vsi->eth_stats.tx_errors; 5036 5037 /* Rx Errors */ 5038 stats->imissed = ns->eth.rx_discards + 5039 pf->main_vsi->eth_stats.rx_discards; 5040 stats->ierrors = ns->crc_errors + 5041 ns->rx_undersize + 5042 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 5043 5044 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 5045 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 5046 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 5047 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 5048 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 5049 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 5050 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 5051 pf->main_vsi->eth_stats.rx_discards); 5052 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 5053 ns->eth.rx_unknown_protocol); 5054 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 5055 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 5056 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 5057 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 5058 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 5059 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 5060 pf->main_vsi->eth_stats.tx_discards); 5061 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 5062 5063 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 5064 ns->tx_dropped_link_down); 5065 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 5066 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 5067 ns->illegal_bytes); 5068 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 5069 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 5070 ns->mac_local_faults); 5071 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 5072 ns->mac_remote_faults); 5073 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 5074 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 5075 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 5076 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 5077 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 5078 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 5079 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 5080 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 5081 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 5082 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 5083 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 5084 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 5085 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 5086 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 5087 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 5088 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 5089 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 5090 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 5091 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 5092 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 5093 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 5094 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 5095 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 5096 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 5097 return 0; 5098 } 5099 5100 /* Reset the statistics */ 5101 static int 5102 ice_stats_reset(struct rte_eth_dev *dev) 5103 { 5104 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5105 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5106 5107 /* Mark PF and VSI stats to update the offset, aka "reset" */ 5108 pf->offset_loaded = false; 5109 if (pf->main_vsi) 5110 pf->main_vsi->offset_loaded = false; 5111 5112 /* read the stats, reading current register values into offset */ 5113 ice_read_stats_registers(pf, hw); 5114 5115 return 0; 5116 } 5117 5118 static uint32_t 5119 ice_xstats_calc_num(void) 5120 { 5121 uint32_t num; 5122 5123 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 5124 5125 return num; 5126 } 5127 5128 static int 5129 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 5130 unsigned int n) 5131 { 5132 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5133 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5134 unsigned int i; 5135 unsigned int count; 5136 struct ice_hw_port_stats *hw_stats = &pf->stats; 5137 5138 count = ice_xstats_calc_num(); 5139 if (n < count) 5140 return count; 5141 5142 ice_read_stats_registers(pf, hw); 5143 5144 if (!xstats) 5145 return 0; 5146 5147 count = 0; 5148 5149 /* Get stats from ice_eth_stats struct */ 5150 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 5151 xstats[count].value = 5152 *(uint64_t *)((char *)&hw_stats->eth + 5153 ice_stats_strings[i].offset); 5154 xstats[count].id = count; 5155 count++; 5156 } 5157 5158 /* Get individiual stats from ice_hw_port struct */ 5159 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 5160 xstats[count].value = 5161 *(uint64_t *)((char *)hw_stats + 5162 ice_hw_port_strings[i].offset); 5163 xstats[count].id = count; 5164 count++; 5165 } 5166 5167 return count; 5168 } 5169 5170 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 5171 struct rte_eth_xstat_name *xstats_names, 5172 __rte_unused unsigned int limit) 5173 { 5174 unsigned int count = 0; 5175 unsigned int i; 5176 5177 if (!xstats_names) 5178 return ice_xstats_calc_num(); 5179 5180 /* Note: limit checked in rte_eth_xstats_names() */ 5181 5182 /* Get stats from ice_eth_stats struct */ 5183 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 5184 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 5185 sizeof(xstats_names[count].name)); 5186 count++; 5187 } 5188 5189 /* Get individiual stats from ice_hw_port struct */ 5190 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 5191 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 5192 sizeof(xstats_names[count].name)); 5193 count++; 5194 } 5195 5196 return count; 5197 } 5198 5199 static int 5200 ice_dev_filter_ctrl(struct rte_eth_dev *dev, 5201 enum rte_filter_type filter_type, 5202 enum rte_filter_op filter_op, 5203 void *arg) 5204 { 5205 int ret = 0; 5206 5207 if (!dev) 5208 return -EINVAL; 5209 5210 switch (filter_type) { 5211 case RTE_ETH_FILTER_GENERIC: 5212 if (filter_op != RTE_ETH_FILTER_GET) 5213 return -EINVAL; 5214 *(const void **)arg = &ice_flow_ops; 5215 break; 5216 default: 5217 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 5218 filter_type); 5219 ret = -EINVAL; 5220 break; 5221 } 5222 5223 return ret; 5224 } 5225 5226 /* Add UDP tunneling port */ 5227 static int 5228 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 5229 struct rte_eth_udp_tunnel *udp_tunnel) 5230 { 5231 int ret = 0; 5232 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5233 5234 if (udp_tunnel == NULL) 5235 return -EINVAL; 5236 5237 switch (udp_tunnel->prot_type) { 5238 case RTE_TUNNEL_TYPE_VXLAN: 5239 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); 5240 break; 5241 default: 5242 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5243 ret = -EINVAL; 5244 break; 5245 } 5246 5247 return ret; 5248 } 5249 5250 /* Delete UDP tunneling port */ 5251 static int 5252 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 5253 struct rte_eth_udp_tunnel *udp_tunnel) 5254 { 5255 int ret = 0; 5256 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5257 5258 if (udp_tunnel == NULL) 5259 return -EINVAL; 5260 5261 switch (udp_tunnel->prot_type) { 5262 case RTE_TUNNEL_TYPE_VXLAN: 5263 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); 5264 break; 5265 default: 5266 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5267 ret = -EINVAL; 5268 break; 5269 } 5270 5271 return ret; 5272 } 5273 5274 static int 5275 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5276 struct rte_pci_device *pci_dev) 5277 { 5278 return rte_eth_dev_pci_generic_probe(pci_dev, 5279 sizeof(struct ice_adapter), 5280 ice_dev_init); 5281 } 5282 5283 static int 5284 ice_pci_remove(struct rte_pci_device *pci_dev) 5285 { 5286 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 5287 } 5288 5289 static struct rte_pci_driver rte_ice_pmd = { 5290 .id_table = pci_id_ice_map, 5291 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 5292 .probe = ice_pci_probe, 5293 .remove = ice_pci_remove, 5294 }; 5295 5296 /** 5297 * Driver initialization routine. 5298 * Invoked once at EAL init time. 5299 * Register itself as the [Poll Mode] Driver of PCI devices. 5300 */ 5301 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 5302 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 5303 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 5304 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 5305 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>" 5306 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" 5307 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"); 5308 5309 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE); 5310 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE); 5311 #ifdef RTE_LIBRTE_ICE_DEBUG_RX 5312 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG); 5313 #endif 5314 #ifdef RTE_LIBRTE_ICE_DEBUG_TX 5315 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG); 5316 #endif 5317 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE 5318 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG); 5319 #endif 5320