1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2016 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <stdarg.h> 10 11 #include <rte_string_fns.h> 12 #include <rte_common.h> 13 #include <rte_interrupts.h> 14 #include <rte_byteorder.h> 15 #include <rte_log.h> 16 #include <rte_debug.h> 17 #include <rte_pci.h> 18 #include <rte_bus_pci.h> 19 #include <rte_ether.h> 20 #include <ethdev_driver.h> 21 #include <ethdev_pci.h> 22 #include <rte_memory.h> 23 #include <rte_eal.h> 24 #include <rte_malloc.h> 25 #include <rte_dev.h> 26 27 #include "e1000_logs.h" 28 #include "base/e1000_api.h" 29 #include "e1000_ethdev.h" 30 #include "igb_regs.h" 31 32 /* 33 * Default values for port configuration 34 */ 35 #define IGB_DEFAULT_RX_FREE_THRESH 32 36 37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) 38 #define IGB_DEFAULT_RX_HTHRESH 8 39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4) 40 41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 42 #define IGB_DEFAULT_TX_HTHRESH 1 43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16) 44 45 /* Bit shift and mask */ 46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2) 47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t) 48 #define IGB_8_BIT_WIDTH CHAR_BIT 49 #define IGB_8_BIT_MASK UINT8_MAX 50 51 /* Additional timesync values. */ 52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL 53 #define E1000_ETQF_FILTER_1588 3 54 #define IGB_82576_TSYNC_SHIFT 16 55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) 56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) 57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000 58 59 #define E1000_VTIVAR_MISC 0x01740 60 #define E1000_VTIVAR_MISC_MASK 0xFF 61 #define E1000_VTIVAR_VALID 0x80 62 #define E1000_VTIVAR_MISC_MAILBOX 0 63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3 64 65 /* External VLAN Enable bit mask */ 66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26) 67 68 /* External VLAN Ether Type bit mask and shift */ 69 #define E1000_VET_VET_EXT 0xFFFF0000 70 #define E1000_VET_VET_EXT_SHIFT 16 71 72 /* MSI-X other interrupt vector */ 73 #define IGB_MSIX_OTHER_INTR_VEC 0 74 75 static int eth_igb_configure(struct rte_eth_dev *dev); 76 static int eth_igb_start(struct rte_eth_dev *dev); 77 static int eth_igb_stop(struct rte_eth_dev *dev); 78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev); 79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev); 80 static int eth_igb_close(struct rte_eth_dev *dev); 81 static int eth_igb_reset(struct rte_eth_dev *dev); 82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev); 83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev); 84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev); 85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev); 86 static int eth_igb_link_update(struct rte_eth_dev *dev, 87 int wait_to_complete); 88 static int eth_igb_stats_get(struct rte_eth_dev *dev, 89 struct rte_eth_stats *rte_stats); 90 static int eth_igb_xstats_get(struct rte_eth_dev *dev, 91 struct rte_eth_xstat *xstats, unsigned n); 92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, 93 const uint64_t *ids, 94 uint64_t *values, unsigned int n); 95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev, 96 struct rte_eth_xstat_name *xstats_names, 97 unsigned int size); 98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev, 99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 100 unsigned int limit); 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev); 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev); 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev, 104 char *fw_version, size_t fw_size); 105 static int eth_igb_infos_get(struct rte_eth_dev *dev, 106 struct rte_eth_dev_info *dev_info); 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev); 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev, 109 struct rte_eth_dev_info *dev_info); 110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, 111 struct rte_eth_fc_conf *fc_conf); 112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, 113 struct rte_eth_fc_conf *fc_conf); 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev); 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev); 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev, 118 struct rte_intr_handle *handle); 119 static void eth_igb_interrupt_handler(void *param); 120 static int igb_hardware_init(struct e1000_hw *hw); 121 static void igb_hw_control_acquire(struct e1000_hw *hw); 122 static void igb_hw_control_release(struct e1000_hw *hw); 123 static void igb_init_manageability(struct e1000_hw *hw); 124 static void igb_release_manageability(struct e1000_hw *hw); 125 126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 127 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev, 129 uint16_t vlan_id, int on); 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, 131 enum rte_vlan_type vlan_type, 132 uint16_t tpid_id); 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask); 134 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev); 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev); 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev); 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev); 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev); 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev); 141 142 static int eth_igb_led_on(struct rte_eth_dev *dev); 143 static int eth_igb_led_off(struct rte_eth_dev *dev); 144 145 static void igb_intr_disable(struct rte_eth_dev *dev); 146 static int igb_get_rx_buffer_size(struct e1000_hw *hw); 147 static int eth_igb_rar_set(struct rte_eth_dev *dev, 148 struct rte_ether_addr *mac_addr, 149 uint32_t index, uint32_t pool); 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index); 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev, 152 struct rte_ether_addr *addr); 153 154 static void igbvf_intr_disable(struct e1000_hw *hw); 155 static int igbvf_dev_configure(struct rte_eth_dev *dev); 156 static int igbvf_dev_start(struct rte_eth_dev *dev); 157 static int igbvf_dev_stop(struct rte_eth_dev *dev); 158 static int igbvf_dev_close(struct rte_eth_dev *dev); 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev); 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev); 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev); 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev); 163 static int eth_igbvf_link_update(struct e1000_hw *hw); 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev, 165 struct rte_eth_stats *rte_stats); 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev, 167 struct rte_eth_xstat *xstats, unsigned n); 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev, 169 struct rte_eth_xstat_name *xstats_names, 170 unsigned limit); 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev); 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev, 173 uint16_t vlan_id, int on); 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on); 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on); 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev, 177 struct rte_ether_addr *addr); 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev); 179 static int igbvf_get_regs(struct rte_eth_dev *dev, 180 struct rte_dev_reg_info *regs); 181 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev, 183 struct rte_eth_rss_reta_entry64 *reta_conf, 184 uint16_t reta_size); 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev, 186 struct rte_eth_rss_reta_entry64 *reta_conf, 187 uint16_t reta_size); 188 189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev, 190 struct rte_eth_ntuple_filter *ntuple_filter); 191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev, 192 struct rte_eth_ntuple_filter *ntuple_filter); 193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev, 194 struct rte_eth_ntuple_filter *ntuple_filter); 195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev, 196 struct rte_eth_ntuple_filter *ntuple_filter); 197 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev, 198 enum rte_filter_type filter_type, 199 enum rte_filter_op filter_op, 200 void *arg); 201 static int eth_igb_get_reg_length(struct rte_eth_dev *dev); 202 static int eth_igb_get_regs(struct rte_eth_dev *dev, 203 struct rte_dev_reg_info *regs); 204 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev); 205 static int eth_igb_get_eeprom(struct rte_eth_dev *dev, 206 struct rte_dev_eeprom_info *eeprom); 207 static int eth_igb_set_eeprom(struct rte_eth_dev *dev, 208 struct rte_dev_eeprom_info *eeprom); 209 static int eth_igb_get_module_info(struct rte_eth_dev *dev, 210 struct rte_eth_dev_module_info *modinfo); 211 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev, 212 struct rte_dev_eeprom_info *info); 213 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev, 214 struct rte_ether_addr *mc_addr_set, 215 uint32_t nb_mc_addr); 216 static int igb_timesync_enable(struct rte_eth_dev *dev); 217 static int igb_timesync_disable(struct rte_eth_dev *dev); 218 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 219 struct timespec *timestamp, 220 uint32_t flags); 221 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 222 struct timespec *timestamp); 223 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 224 static int igb_timesync_read_time(struct rte_eth_dev *dev, 225 struct timespec *timestamp); 226 static int igb_timesync_write_time(struct rte_eth_dev *dev, 227 const struct timespec *timestamp); 228 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, 229 uint16_t queue_id); 230 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, 231 uint16_t queue_id); 232 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction, 233 uint8_t queue, uint8_t msix_vector); 234 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector, 235 uint8_t index, uint8_t offset); 236 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev); 237 static void eth_igbvf_interrupt_handler(void *param); 238 static void igbvf_mbx_process(struct rte_eth_dev *dev); 239 static int igb_filter_restore(struct rte_eth_dev *dev); 240 241 /* 242 * Define VF Stats MACRO for Non "cleared on read" register 243 */ 244 #define UPDATE_VF_STAT(reg, last, cur) \ 245 { \ 246 u32 latest = E1000_READ_REG(hw, reg); \ 247 cur += (latest - last) & UINT_MAX; \ 248 last = latest; \ 249 } 250 251 #define IGB_FC_PAUSE_TIME 0x0680 252 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */ 253 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */ 254 255 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */ 256 257 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full; 258 259 /* 260 * The set of PCI devices this driver supports 261 */ 262 static const struct rte_pci_id pci_id_igb_map[] = { 263 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) }, 264 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) }, 265 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) }, 266 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) }, 267 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) }, 268 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) }, 269 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) }, 270 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) }, 271 272 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) }, 273 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) }, 274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) }, 275 276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) }, 277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) }, 278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) }, 279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) }, 280 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) }, 281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) }, 282 283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) }, 284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) }, 285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) }, 286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) }, 287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) }, 288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) }, 289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) }, 290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) }, 291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) }, 292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) }, 293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) }, 294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) }, 295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) }, 296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) }, 297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) }, 299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) }, 301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) }, 302 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) }, 303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) }, 304 { .vendor_id = 0, /* sentinel */ }, 305 }; 306 307 /* 308 * The set of PCI devices this driver supports (for 82576&I350 VF) 309 */ 310 static const struct rte_pci_id pci_id_igbvf_map[] = { 311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) }, 312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) }, 313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) }, 314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) }, 315 { .vendor_id = 0, /* sentinel */ }, 316 }; 317 318 static const struct rte_eth_desc_lim rx_desc_lim = { 319 .nb_max = E1000_MAX_RING_DESC, 320 .nb_min = E1000_MIN_RING_DESC, 321 .nb_align = IGB_RXD_ALIGN, 322 }; 323 324 static const struct rte_eth_desc_lim tx_desc_lim = { 325 .nb_max = E1000_MAX_RING_DESC, 326 .nb_min = E1000_MIN_RING_DESC, 327 .nb_align = IGB_RXD_ALIGN, 328 .nb_seg_max = IGB_TX_MAX_SEG, 329 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG, 330 }; 331 332 static const struct eth_dev_ops eth_igb_ops = { 333 .dev_configure = eth_igb_configure, 334 .dev_start = eth_igb_start, 335 .dev_stop = eth_igb_stop, 336 .dev_set_link_up = eth_igb_dev_set_link_up, 337 .dev_set_link_down = eth_igb_dev_set_link_down, 338 .dev_close = eth_igb_close, 339 .dev_reset = eth_igb_reset, 340 .promiscuous_enable = eth_igb_promiscuous_enable, 341 .promiscuous_disable = eth_igb_promiscuous_disable, 342 .allmulticast_enable = eth_igb_allmulticast_enable, 343 .allmulticast_disable = eth_igb_allmulticast_disable, 344 .link_update = eth_igb_link_update, 345 .stats_get = eth_igb_stats_get, 346 .xstats_get = eth_igb_xstats_get, 347 .xstats_get_by_id = eth_igb_xstats_get_by_id, 348 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id, 349 .xstats_get_names = eth_igb_xstats_get_names, 350 .stats_reset = eth_igb_stats_reset, 351 .xstats_reset = eth_igb_xstats_reset, 352 .fw_version_get = eth_igb_fw_version_get, 353 .dev_infos_get = eth_igb_infos_get, 354 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get, 355 .mtu_set = eth_igb_mtu_set, 356 .vlan_filter_set = eth_igb_vlan_filter_set, 357 .vlan_tpid_set = eth_igb_vlan_tpid_set, 358 .vlan_offload_set = eth_igb_vlan_offload_set, 359 .rx_queue_setup = eth_igb_rx_queue_setup, 360 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable, 361 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable, 362 .rx_queue_release = eth_igb_rx_queue_release, 363 .tx_queue_setup = eth_igb_tx_queue_setup, 364 .tx_queue_release = eth_igb_tx_queue_release, 365 .tx_done_cleanup = eth_igb_tx_done_cleanup, 366 .dev_led_on = eth_igb_led_on, 367 .dev_led_off = eth_igb_led_off, 368 .flow_ctrl_get = eth_igb_flow_ctrl_get, 369 .flow_ctrl_set = eth_igb_flow_ctrl_set, 370 .mac_addr_add = eth_igb_rar_set, 371 .mac_addr_remove = eth_igb_rar_clear, 372 .mac_addr_set = eth_igb_default_mac_addr_set, 373 .reta_update = eth_igb_rss_reta_update, 374 .reta_query = eth_igb_rss_reta_query, 375 .rss_hash_update = eth_igb_rss_hash_update, 376 .rss_hash_conf_get = eth_igb_rss_hash_conf_get, 377 .filter_ctrl = eth_igb_filter_ctrl, 378 .set_mc_addr_list = eth_igb_set_mc_addr_list, 379 .rxq_info_get = igb_rxq_info_get, 380 .txq_info_get = igb_txq_info_get, 381 .timesync_enable = igb_timesync_enable, 382 .timesync_disable = igb_timesync_disable, 383 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp, 384 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp, 385 .get_reg = eth_igb_get_regs, 386 .get_eeprom_length = eth_igb_get_eeprom_length, 387 .get_eeprom = eth_igb_get_eeprom, 388 .set_eeprom = eth_igb_set_eeprom, 389 .get_module_info = eth_igb_get_module_info, 390 .get_module_eeprom = eth_igb_get_module_eeprom, 391 .timesync_adjust_time = igb_timesync_adjust_time, 392 .timesync_read_time = igb_timesync_read_time, 393 .timesync_write_time = igb_timesync_write_time, 394 }; 395 396 /* 397 * dev_ops for virtual function, bare necessities for basic vf 398 * operation have been implemented 399 */ 400 static const struct eth_dev_ops igbvf_eth_dev_ops = { 401 .dev_configure = igbvf_dev_configure, 402 .dev_start = igbvf_dev_start, 403 .dev_stop = igbvf_dev_stop, 404 .dev_close = igbvf_dev_close, 405 .promiscuous_enable = igbvf_promiscuous_enable, 406 .promiscuous_disable = igbvf_promiscuous_disable, 407 .allmulticast_enable = igbvf_allmulticast_enable, 408 .allmulticast_disable = igbvf_allmulticast_disable, 409 .link_update = eth_igb_link_update, 410 .stats_get = eth_igbvf_stats_get, 411 .xstats_get = eth_igbvf_xstats_get, 412 .xstats_get_names = eth_igbvf_xstats_get_names, 413 .stats_reset = eth_igbvf_stats_reset, 414 .xstats_reset = eth_igbvf_stats_reset, 415 .vlan_filter_set = igbvf_vlan_filter_set, 416 .dev_infos_get = eth_igbvf_infos_get, 417 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get, 418 .rx_queue_setup = eth_igb_rx_queue_setup, 419 .rx_queue_release = eth_igb_rx_queue_release, 420 .tx_queue_setup = eth_igb_tx_queue_setup, 421 .tx_queue_release = eth_igb_tx_queue_release, 422 .tx_done_cleanup = eth_igb_tx_done_cleanup, 423 .set_mc_addr_list = eth_igb_set_mc_addr_list, 424 .rxq_info_get = igb_rxq_info_get, 425 .txq_info_get = igb_txq_info_get, 426 .mac_addr_set = igbvf_default_mac_addr_set, 427 .get_reg = igbvf_get_regs, 428 }; 429 430 /* store statistics names and its offset in stats structure */ 431 struct rte_igb_xstats_name_off { 432 char name[RTE_ETH_XSTATS_NAME_SIZE]; 433 unsigned offset; 434 }; 435 436 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = { 437 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)}, 438 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)}, 439 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)}, 440 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)}, 441 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)}, 442 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)}, 443 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats, 444 ecol)}, 445 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)}, 446 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)}, 447 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)}, 448 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)}, 449 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)}, 450 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)}, 451 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)}, 452 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)}, 453 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)}, 454 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)}, 455 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats, 456 fcruc)}, 457 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)}, 458 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)}, 459 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)}, 460 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)}, 461 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats, 462 prc1023)}, 463 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats, 464 prc1522)}, 465 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)}, 466 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)}, 467 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)}, 468 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)}, 469 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)}, 470 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)}, 471 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)}, 472 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)}, 473 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)}, 474 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)}, 475 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)}, 476 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)}, 477 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)}, 478 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)}, 479 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)}, 480 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)}, 481 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)}, 482 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats, 483 ptc1023)}, 484 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats, 485 ptc1522)}, 486 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)}, 487 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)}, 488 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)}, 489 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)}, 490 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)}, 491 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)}, 492 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)}, 493 494 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)}, 495 }; 496 497 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \ 498 sizeof(rte_igb_stats_strings[0])) 499 500 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = { 501 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)}, 502 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)}, 503 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)}, 504 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)}, 505 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)}, 506 }; 507 508 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \ 509 sizeof(rte_igbvf_stats_strings[0])) 510 511 512 static inline void 513 igb_intr_enable(struct rte_eth_dev *dev) 514 { 515 struct e1000_interrupt *intr = 516 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 517 struct e1000_hw *hw = 518 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 519 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 520 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 521 522 if (rte_intr_allow_others(intr_handle) && 523 dev->data->dev_conf.intr_conf.lsc != 0) { 524 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC); 525 } 526 527 E1000_WRITE_REG(hw, E1000_IMS, intr->mask); 528 E1000_WRITE_FLUSH(hw); 529 } 530 531 static void 532 igb_intr_disable(struct rte_eth_dev *dev) 533 { 534 struct e1000_hw *hw = 535 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 536 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 537 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 538 539 if (rte_intr_allow_others(intr_handle) && 540 dev->data->dev_conf.intr_conf.lsc != 0) { 541 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC); 542 } 543 544 E1000_WRITE_REG(hw, E1000_IMC, ~0); 545 E1000_WRITE_FLUSH(hw); 546 } 547 548 static inline void 549 igbvf_intr_enable(struct rte_eth_dev *dev) 550 { 551 struct e1000_hw *hw = 552 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 553 554 /* only for mailbox */ 555 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX); 556 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX); 557 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX); 558 E1000_WRITE_FLUSH(hw); 559 } 560 561 /* only for mailbox now. If RX/TX needed, should extend this function. */ 562 static void 563 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector) 564 { 565 uint32_t tmp = 0; 566 567 /* mailbox */ 568 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK); 569 tmp |= E1000_VTIVAR_VALID; 570 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp); 571 } 572 573 static void 574 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev) 575 { 576 struct e1000_hw *hw = 577 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 578 579 /* Configure VF other cause ivar */ 580 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX); 581 } 582 583 static inline int32_t 584 igb_pf_reset_hw(struct e1000_hw *hw) 585 { 586 uint32_t ctrl_ext; 587 int32_t status; 588 589 status = e1000_reset_hw(hw); 590 591 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 592 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 593 ctrl_ext |= E1000_CTRL_EXT_PFRSTD; 594 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 595 E1000_WRITE_FLUSH(hw); 596 597 return status; 598 } 599 600 static void 601 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev) 602 { 603 struct e1000_hw *hw = 604 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 605 606 607 hw->vendor_id = pci_dev->id.vendor_id; 608 hw->device_id = pci_dev->id.device_id; 609 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 610 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 611 612 e1000_set_mac_type(hw); 613 614 /* need to check if it is a vf device below */ 615 } 616 617 static int 618 igb_reset_swfw_lock(struct e1000_hw *hw) 619 { 620 int ret_val; 621 622 /* 623 * Do mac ops initialization manually here, since we will need 624 * some function pointers set by this call. 625 */ 626 ret_val = e1000_init_mac_params(hw); 627 if (ret_val) 628 return ret_val; 629 630 /* 631 * SMBI lock should not fail in this early stage. If this is the case, 632 * it is due to an improper exit of the application. 633 * So force the release of the faulty lock. 634 */ 635 if (e1000_get_hw_semaphore_generic(hw) < 0) { 636 PMD_DRV_LOG(DEBUG, "SMBI lock released"); 637 } 638 e1000_put_hw_semaphore_generic(hw); 639 640 if (hw->mac.ops.acquire_swfw_sync != NULL) { 641 uint16_t mask; 642 643 /* 644 * Phy lock should not fail in this early stage. If this is the case, 645 * it is due to an improper exit of the application. 646 * So force the release of the faulty lock. 647 */ 648 mask = E1000_SWFW_PHY0_SM << hw->bus.func; 649 if (hw->bus.func > E1000_FUNC_1) 650 mask <<= 2; 651 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { 652 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", 653 hw->bus.func); 654 } 655 hw->mac.ops.release_swfw_sync(hw, mask); 656 657 /* 658 * This one is more tricky since it is common to all ports; but 659 * swfw_sync retries last long enough (1s) to be almost sure that if 660 * lock can not be taken it is due to an improper lock of the 661 * semaphore. 662 */ 663 mask = E1000_SWFW_EEP_SM; 664 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { 665 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 666 } 667 hw->mac.ops.release_swfw_sync(hw, mask); 668 } 669 670 return E1000_SUCCESS; 671 } 672 673 /* Remove all ntuple filters of the device */ 674 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 675 { 676 struct e1000_filter_info *filter_info = 677 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 678 struct e1000_5tuple_filter *p_5tuple; 679 struct e1000_2tuple_filter *p_2tuple; 680 681 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 682 TAILQ_REMOVE(&filter_info->fivetuple_list, 683 p_5tuple, entries); 684 rte_free(p_5tuple); 685 } 686 filter_info->fivetuple_mask = 0; 687 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) { 688 TAILQ_REMOVE(&filter_info->twotuple_list, 689 p_2tuple, entries); 690 rte_free(p_2tuple); 691 } 692 filter_info->twotuple_mask = 0; 693 694 return 0; 695 } 696 697 /* Remove all flex filters of the device */ 698 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev) 699 { 700 struct e1000_filter_info *filter_info = 701 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 702 struct e1000_flex_filter *p_flex; 703 704 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) { 705 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries); 706 rte_free(p_flex); 707 } 708 filter_info->flex_mask = 0; 709 710 return 0; 711 } 712 713 static int 714 eth_igb_dev_init(struct rte_eth_dev *eth_dev) 715 { 716 int error = 0; 717 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 718 struct e1000_hw *hw = 719 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 720 struct e1000_vfta * shadow_vfta = 721 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 722 struct e1000_filter_info *filter_info = 723 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 724 struct e1000_adapter *adapter = 725 E1000_DEV_PRIVATE(eth_dev->data->dev_private); 726 727 uint32_t ctrl_ext; 728 729 eth_dev->dev_ops = ð_igb_ops; 730 eth_dev->rx_queue_count = eth_igb_rx_queue_count; 731 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done; 732 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status; 733 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status; 734 eth_dev->rx_pkt_burst = ð_igb_recv_pkts; 735 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts; 736 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts; 737 738 /* for secondary processes, we don't initialise any further as primary 739 * has already done this work. Only check we don't need a different 740 * RX function */ 741 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 742 if (eth_dev->data->scattered_rx) 743 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts; 744 return 0; 745 } 746 747 rte_eth_copy_pci_info(eth_dev, pci_dev); 748 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 749 750 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr; 751 752 igb_identify_hardware(eth_dev, pci_dev); 753 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) { 754 error = -EIO; 755 goto err_late; 756 } 757 758 e1000_get_bus_info(hw); 759 760 /* Reset any pending lock */ 761 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) { 762 error = -EIO; 763 goto err_late; 764 } 765 766 /* Finish initialization */ 767 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) { 768 error = -EIO; 769 goto err_late; 770 } 771 772 hw->mac.autoneg = 1; 773 hw->phy.autoneg_wait_to_complete = 0; 774 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX; 775 776 /* Copper options */ 777 if (hw->phy.media_type == e1000_media_type_copper) { 778 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 779 hw->phy.disable_polarity_correction = 0; 780 hw->phy.ms_type = e1000_ms_hw_default; 781 } 782 783 /* 784 * Start from a known state, this is important in reading the nvm 785 * and mac from that. 786 */ 787 igb_pf_reset_hw(hw); 788 789 /* Make sure we have a good EEPROM before we read from it */ 790 if (e1000_validate_nvm_checksum(hw) < 0) { 791 /* 792 * Some PCI-E parts fail the first check due to 793 * the link being in sleep state, call it again, 794 * if it fails a second time its a real issue. 795 */ 796 if (e1000_validate_nvm_checksum(hw) < 0) { 797 PMD_INIT_LOG(ERR, "EEPROM checksum invalid"); 798 error = -EIO; 799 goto err_late; 800 } 801 } 802 803 /* Read the permanent MAC address out of the EEPROM */ 804 if (e1000_read_mac_addr(hw) != 0) { 805 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address"); 806 error = -EIO; 807 goto err_late; 808 } 809 810 /* Allocate memory for storing MAC addresses */ 811 eth_dev->data->mac_addrs = rte_zmalloc("e1000", 812 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0); 813 if (eth_dev->data->mac_addrs == NULL) { 814 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to " 815 "store MAC addresses", 816 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count); 817 error = -ENOMEM; 818 goto err_late; 819 } 820 821 /* Copy the permanent MAC address */ 822 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, 823 ð_dev->data->mac_addrs[0]); 824 825 /* initialize the vfta */ 826 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 827 828 /* Now initialize the hardware */ 829 if (igb_hardware_init(hw) != 0) { 830 PMD_INIT_LOG(ERR, "Hardware initialization failed"); 831 rte_free(eth_dev->data->mac_addrs); 832 eth_dev->data->mac_addrs = NULL; 833 error = -ENODEV; 834 goto err_late; 835 } 836 hw->mac.get_link_status = 1; 837 adapter->stopped = 0; 838 839 /* Indicate SOL/IDER usage */ 840 if (e1000_check_reset_block(hw) < 0) { 841 PMD_INIT_LOG(ERR, "PHY reset is blocked due to" 842 "SOL/IDER session"); 843 } 844 845 /* initialize PF if max_vfs not zero */ 846 igb_pf_host_init(eth_dev); 847 848 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 849 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 850 ctrl_ext |= E1000_CTRL_EXT_PFRSTD; 851 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 852 E1000_WRITE_FLUSH(hw); 853 854 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x", 855 eth_dev->data->port_id, pci_dev->id.vendor_id, 856 pci_dev->id.device_id); 857 858 rte_intr_callback_register(&pci_dev->intr_handle, 859 eth_igb_interrupt_handler, 860 (void *)eth_dev); 861 862 /* enable uio/vfio intr/eventfd mapping */ 863 rte_intr_enable(&pci_dev->intr_handle); 864 865 /* enable support intr */ 866 igb_intr_enable(eth_dev); 867 868 eth_igb_dev_set_link_down(eth_dev); 869 870 /* initialize filter info */ 871 memset(filter_info, 0, 872 sizeof(struct e1000_filter_info)); 873 874 TAILQ_INIT(&filter_info->flex_list); 875 TAILQ_INIT(&filter_info->twotuple_list); 876 TAILQ_INIT(&filter_info->fivetuple_list); 877 878 TAILQ_INIT(&igb_filter_ntuple_list); 879 TAILQ_INIT(&igb_filter_ethertype_list); 880 TAILQ_INIT(&igb_filter_syn_list); 881 TAILQ_INIT(&igb_filter_flex_list); 882 TAILQ_INIT(&igb_filter_rss_list); 883 TAILQ_INIT(&igb_flow_list); 884 885 return 0; 886 887 err_late: 888 igb_hw_control_release(hw); 889 890 return error; 891 } 892 893 static int 894 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev) 895 { 896 PMD_INIT_FUNC_TRACE(); 897 898 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 899 return 0; 900 901 eth_igb_close(eth_dev); 902 903 return 0; 904 } 905 906 /* 907 * Virtual Function device init 908 */ 909 static int 910 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev) 911 { 912 struct rte_pci_device *pci_dev; 913 struct rte_intr_handle *intr_handle; 914 struct e1000_adapter *adapter = 915 E1000_DEV_PRIVATE(eth_dev->data->dev_private); 916 struct e1000_hw *hw = 917 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 918 int diag; 919 struct rte_ether_addr *perm_addr = 920 (struct rte_ether_addr *)hw->mac.perm_addr; 921 922 PMD_INIT_FUNC_TRACE(); 923 924 eth_dev->dev_ops = &igbvf_eth_dev_ops; 925 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done; 926 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status; 927 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status; 928 eth_dev->rx_pkt_burst = ð_igb_recv_pkts; 929 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts; 930 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts; 931 932 /* for secondary processes, we don't initialise any further as primary 933 * has already done this work. Only check we don't need a different 934 * RX function */ 935 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 936 if (eth_dev->data->scattered_rx) 937 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts; 938 return 0; 939 } 940 941 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 942 rte_eth_copy_pci_info(eth_dev, pci_dev); 943 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 944 945 hw->device_id = pci_dev->id.device_id; 946 hw->vendor_id = pci_dev->id.vendor_id; 947 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 948 adapter->stopped = 0; 949 950 /* Initialize the shared code (base driver) */ 951 diag = e1000_setup_init_funcs(hw, TRUE); 952 if (diag != 0) { 953 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d", 954 diag); 955 return -EIO; 956 } 957 958 /* init_mailbox_params */ 959 hw->mbx.ops.init_params(hw); 960 961 /* Disable the interrupts for VF */ 962 igbvf_intr_disable(hw); 963 964 diag = hw->mac.ops.reset_hw(hw); 965 966 /* Allocate memory for storing MAC addresses */ 967 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN * 968 hw->mac.rar_entry_count, 0); 969 if (eth_dev->data->mac_addrs == NULL) { 970 PMD_INIT_LOG(ERR, 971 "Failed to allocate %d bytes needed to store MAC " 972 "addresses", 973 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count); 974 return -ENOMEM; 975 } 976 977 /* Generate a random MAC address, if none was assigned by PF. */ 978 if (rte_is_zero_ether_addr(perm_addr)) { 979 rte_eth_random_addr(perm_addr->addr_bytes); 980 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 981 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 982 "%02x:%02x:%02x:%02x:%02x:%02x", 983 perm_addr->addr_bytes[0], 984 perm_addr->addr_bytes[1], 985 perm_addr->addr_bytes[2], 986 perm_addr->addr_bytes[3], 987 perm_addr->addr_bytes[4], 988 perm_addr->addr_bytes[5]); 989 } 990 991 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0); 992 if (diag) { 993 rte_free(eth_dev->data->mac_addrs); 994 eth_dev->data->mac_addrs = NULL; 995 return diag; 996 } 997 /* Copy the permanent MAC address */ 998 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 999 ð_dev->data->mac_addrs[0]); 1000 1001 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x " 1002 "mac.type=%s", 1003 eth_dev->data->port_id, pci_dev->id.vendor_id, 1004 pci_dev->id.device_id, "igb_mac_82576_vf"); 1005 1006 intr_handle = &pci_dev->intr_handle; 1007 rte_intr_callback_register(intr_handle, 1008 eth_igbvf_interrupt_handler, eth_dev); 1009 1010 return 0; 1011 } 1012 1013 static int 1014 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev) 1015 { 1016 PMD_INIT_FUNC_TRACE(); 1017 1018 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1019 return 0; 1020 1021 igbvf_dev_close(eth_dev); 1022 1023 return 0; 1024 } 1025 1026 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1027 struct rte_pci_device *pci_dev) 1028 { 1029 return rte_eth_dev_pci_generic_probe(pci_dev, 1030 sizeof(struct e1000_adapter), eth_igb_dev_init); 1031 } 1032 1033 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev) 1034 { 1035 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit); 1036 } 1037 1038 static struct rte_pci_driver rte_igb_pmd = { 1039 .id_table = pci_id_igb_map, 1040 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1041 .probe = eth_igb_pci_probe, 1042 .remove = eth_igb_pci_remove, 1043 }; 1044 1045 1046 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1047 struct rte_pci_device *pci_dev) 1048 { 1049 return rte_eth_dev_pci_generic_probe(pci_dev, 1050 sizeof(struct e1000_adapter), eth_igbvf_dev_init); 1051 } 1052 1053 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev) 1054 { 1055 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit); 1056 } 1057 1058 /* 1059 * virtual function driver struct 1060 */ 1061 static struct rte_pci_driver rte_igbvf_pmd = { 1062 .id_table = pci_id_igbvf_map, 1063 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1064 .probe = eth_igbvf_pci_probe, 1065 .remove = eth_igbvf_pci_remove, 1066 }; 1067 1068 static void 1069 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1070 { 1071 struct e1000_hw *hw = 1072 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1073 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */ 1074 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 1075 rctl |= E1000_RCTL_VFE; 1076 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1077 } 1078 1079 static int 1080 igb_check_mq_mode(struct rte_eth_dev *dev) 1081 { 1082 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1083 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 1084 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1085 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1086 1087 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) || 1088 tx_mq_mode == ETH_MQ_TX_DCB || 1089 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) { 1090 PMD_INIT_LOG(ERR, "DCB mode is not supported."); 1091 return -EINVAL; 1092 } 1093 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 1094 /* Check multi-queue mode. 1095 * To no break software we accept ETH_MQ_RX_NONE as this might 1096 * be used to turn off VLAN filter. 1097 */ 1098 1099 if (rx_mq_mode == ETH_MQ_RX_NONE || 1100 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 1101 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 1102 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1; 1103 } else { 1104 /* Only support one queue on VFs. 1105 * RSS together with SRIOV is not supported. 1106 */ 1107 PMD_INIT_LOG(ERR, "SRIOV is active," 1108 " wrong mq_mode rx %d.", 1109 rx_mq_mode); 1110 return -EINVAL; 1111 } 1112 /* TX mode is not used here, so mode might be ignored.*/ 1113 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) { 1114 /* SRIOV only works in VMDq enable mode */ 1115 PMD_INIT_LOG(WARNING, "SRIOV is active," 1116 " TX mode %d is not supported. " 1117 " Driver will behave as %d mode.", 1118 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY); 1119 } 1120 1121 /* check valid queue number */ 1122 if ((nb_rx_q > 1) || (nb_tx_q > 1)) { 1123 PMD_INIT_LOG(ERR, "SRIOV is active," 1124 " only support one queue on VFs."); 1125 return -EINVAL; 1126 } 1127 } else { 1128 /* To no break software that set invalid mode, only display 1129 * warning if invalid mode is used. 1130 */ 1131 if (rx_mq_mode != ETH_MQ_RX_NONE && 1132 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY && 1133 rx_mq_mode != ETH_MQ_RX_RSS) { 1134 /* RSS together with VMDq not supported*/ 1135 PMD_INIT_LOG(ERR, "RX mode %d is not supported.", 1136 rx_mq_mode); 1137 return -EINVAL; 1138 } 1139 1140 if (tx_mq_mode != ETH_MQ_TX_NONE && 1141 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) { 1142 PMD_INIT_LOG(WARNING, "TX mode %d is not supported." 1143 " Due to txmode is meaningless in this" 1144 " driver, just ignore.", 1145 tx_mq_mode); 1146 } 1147 } 1148 return 0; 1149 } 1150 1151 static int 1152 eth_igb_configure(struct rte_eth_dev *dev) 1153 { 1154 struct e1000_interrupt *intr = 1155 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 1156 int ret; 1157 1158 PMD_INIT_FUNC_TRACE(); 1159 1160 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1161 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1162 1163 /* multipe queue mode checking */ 1164 ret = igb_check_mq_mode(dev); 1165 if (ret != 0) { 1166 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.", 1167 ret); 1168 return ret; 1169 } 1170 1171 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE; 1172 PMD_INIT_FUNC_TRACE(); 1173 1174 return 0; 1175 } 1176 1177 static void 1178 eth_igb_rxtx_control(struct rte_eth_dev *dev, 1179 bool enable) 1180 { 1181 struct e1000_hw *hw = 1182 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1183 uint32_t tctl, rctl; 1184 1185 tctl = E1000_READ_REG(hw, E1000_TCTL); 1186 rctl = E1000_READ_REG(hw, E1000_RCTL); 1187 1188 if (enable) { 1189 /* enable Tx/Rx */ 1190 tctl |= E1000_TCTL_EN; 1191 rctl |= E1000_RCTL_EN; 1192 } else { 1193 /* disable Tx/Rx */ 1194 tctl &= ~E1000_TCTL_EN; 1195 rctl &= ~E1000_RCTL_EN; 1196 } 1197 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1198 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1199 E1000_WRITE_FLUSH(hw); 1200 } 1201 1202 static int 1203 eth_igb_start(struct rte_eth_dev *dev) 1204 { 1205 struct e1000_hw *hw = 1206 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1207 struct e1000_adapter *adapter = 1208 E1000_DEV_PRIVATE(dev->data->dev_private); 1209 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1210 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1211 int ret, mask; 1212 uint32_t intr_vector = 0; 1213 uint32_t ctrl_ext; 1214 uint32_t *speeds; 1215 int num_speeds; 1216 bool autoneg; 1217 1218 PMD_INIT_FUNC_TRACE(); 1219 1220 /* disable uio/vfio intr/eventfd mapping */ 1221 rte_intr_disable(intr_handle); 1222 1223 /* Power up the phy. Needed to make the link go Up */ 1224 eth_igb_dev_set_link_up(dev); 1225 1226 /* 1227 * Packet Buffer Allocation (PBA) 1228 * Writing PBA sets the receive portion of the buffer 1229 * the remainder is used for the transmit buffer. 1230 */ 1231 if (hw->mac.type == e1000_82575) { 1232 uint32_t pba; 1233 1234 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1235 E1000_WRITE_REG(hw, E1000_PBA, pba); 1236 } 1237 1238 /* Put the address into the Receive Address Array */ 1239 e1000_rar_set(hw, hw->mac.addr, 0); 1240 1241 /* Initialize the hardware */ 1242 if (igb_hardware_init(hw)) { 1243 PMD_INIT_LOG(ERR, "Unable to initialize the hardware"); 1244 return -EIO; 1245 } 1246 adapter->stopped = 0; 1247 1248 E1000_WRITE_REG(hw, E1000_VET, 1249 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN); 1250 1251 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1252 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1253 ctrl_ext |= E1000_CTRL_EXT_PFRSTD; 1254 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1255 E1000_WRITE_FLUSH(hw); 1256 1257 /* configure PF module if SRIOV enabled */ 1258 igb_pf_host_configure(dev); 1259 1260 /* check and configure queue intr-vector mapping */ 1261 if ((rte_intr_cap_multiple(intr_handle) || 1262 !RTE_ETH_DEV_SRIOV(dev).active) && 1263 dev->data->dev_conf.intr_conf.rxq != 0) { 1264 intr_vector = dev->data->nb_rx_queues; 1265 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1266 return -1; 1267 } 1268 1269 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1270 intr_handle->intr_vec = 1271 rte_zmalloc("intr_vec", 1272 dev->data->nb_rx_queues * sizeof(int), 0); 1273 if (intr_handle->intr_vec == NULL) { 1274 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 1275 " intr_vec", dev->data->nb_rx_queues); 1276 return -ENOMEM; 1277 } 1278 } 1279 1280 /* confiugre msix for rx interrupt */ 1281 eth_igb_configure_msix_intr(dev); 1282 1283 /* Configure for OS presence */ 1284 igb_init_manageability(hw); 1285 1286 eth_igb_tx_init(dev); 1287 1288 /* This can fail when allocating mbufs for descriptor rings */ 1289 ret = eth_igb_rx_init(dev); 1290 if (ret) { 1291 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 1292 igb_dev_clear_queues(dev); 1293 return ret; 1294 } 1295 1296 e1000_clear_hw_cntrs_base_generic(hw); 1297 1298 /* 1299 * VLAN Offload Settings 1300 */ 1301 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \ 1302 ETH_VLAN_EXTEND_MASK; 1303 ret = eth_igb_vlan_offload_set(dev, mask); 1304 if (ret) { 1305 PMD_INIT_LOG(ERR, "Unable to set vlan offload"); 1306 igb_dev_clear_queues(dev); 1307 return ret; 1308 } 1309 1310 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 1311 /* Enable VLAN filter since VMDq always use VLAN filter */ 1312 igb_vmdq_vlan_hw_filter_enable(dev); 1313 } 1314 1315 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) || 1316 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) || 1317 (hw->mac.type == e1000_i211)) { 1318 /* Configure EITR with the maximum possible value (0xFFFF) */ 1319 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF); 1320 } 1321 1322 /* Setup link speed and duplex */ 1323 speeds = &dev->data->dev_conf.link_speeds; 1324 if (*speeds == ETH_LINK_SPEED_AUTONEG) { 1325 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX; 1326 hw->mac.autoneg = 1; 1327 } else { 1328 num_speeds = 0; 1329 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0; 1330 1331 /* Reset */ 1332 hw->phy.autoneg_advertised = 0; 1333 1334 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M | 1335 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M | 1336 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) { 1337 num_speeds = -1; 1338 goto error_invalid_config; 1339 } 1340 if (*speeds & ETH_LINK_SPEED_10M_HD) { 1341 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF; 1342 num_speeds++; 1343 } 1344 if (*speeds & ETH_LINK_SPEED_10M) { 1345 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL; 1346 num_speeds++; 1347 } 1348 if (*speeds & ETH_LINK_SPEED_100M_HD) { 1349 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF; 1350 num_speeds++; 1351 } 1352 if (*speeds & ETH_LINK_SPEED_100M) { 1353 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL; 1354 num_speeds++; 1355 } 1356 if (*speeds & ETH_LINK_SPEED_1G) { 1357 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL; 1358 num_speeds++; 1359 } 1360 if (num_speeds == 0 || (!autoneg && (num_speeds > 1))) 1361 goto error_invalid_config; 1362 1363 /* Set/reset the mac.autoneg based on the link speed, 1364 * fixed or not 1365 */ 1366 if (!autoneg) { 1367 hw->mac.autoneg = 0; 1368 hw->mac.forced_speed_duplex = 1369 hw->phy.autoneg_advertised; 1370 } else { 1371 hw->mac.autoneg = 1; 1372 } 1373 } 1374 1375 e1000_setup_link(hw); 1376 1377 if (rte_intr_allow_others(intr_handle)) { 1378 /* check if lsc interrupt is enabled */ 1379 if (dev->data->dev_conf.intr_conf.lsc != 0) 1380 eth_igb_lsc_interrupt_setup(dev, TRUE); 1381 else 1382 eth_igb_lsc_interrupt_setup(dev, FALSE); 1383 } else { 1384 rte_intr_callback_unregister(intr_handle, 1385 eth_igb_interrupt_handler, 1386 (void *)dev); 1387 if (dev->data->dev_conf.intr_conf.lsc != 0) 1388 PMD_INIT_LOG(INFO, "lsc won't enable because of" 1389 " no intr multiplex"); 1390 } 1391 1392 /* check if rxq interrupt is enabled */ 1393 if (dev->data->dev_conf.intr_conf.rxq != 0 && 1394 rte_intr_dp_is_en(intr_handle)) 1395 eth_igb_rxq_interrupt_setup(dev); 1396 1397 /* enable uio/vfio intr/eventfd mapping */ 1398 rte_intr_enable(intr_handle); 1399 1400 /* resume enabled intr since hw reset */ 1401 igb_intr_enable(dev); 1402 1403 /* restore all types filter */ 1404 igb_filter_restore(dev); 1405 1406 eth_igb_rxtx_control(dev, true); 1407 eth_igb_link_update(dev, 0); 1408 1409 PMD_INIT_LOG(DEBUG, "<<"); 1410 1411 return 0; 1412 1413 error_invalid_config: 1414 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u", 1415 dev->data->dev_conf.link_speeds, dev->data->port_id); 1416 igb_dev_clear_queues(dev); 1417 return -EINVAL; 1418 } 1419 1420 /********************************************************************* 1421 * 1422 * This routine disables all traffic on the adapter by issuing a 1423 * global reset on the MAC. 1424 * 1425 **********************************************************************/ 1426 static int 1427 eth_igb_stop(struct rte_eth_dev *dev) 1428 { 1429 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1430 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1431 struct rte_eth_link link; 1432 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1433 struct e1000_adapter *adapter = 1434 E1000_DEV_PRIVATE(dev->data->dev_private); 1435 1436 if (adapter->stopped) 1437 return 0; 1438 1439 eth_igb_rxtx_control(dev, false); 1440 1441 igb_intr_disable(dev); 1442 1443 /* disable intr eventfd mapping */ 1444 rte_intr_disable(intr_handle); 1445 1446 igb_pf_reset_hw(hw); 1447 E1000_WRITE_REG(hw, E1000_WUC, 0); 1448 1449 /* Set bit for Go Link disconnect if PHY reset is not blocked */ 1450 if (hw->mac.type >= e1000_82580 && 1451 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) { 1452 uint32_t phpm_reg; 1453 1454 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1455 phpm_reg |= E1000_82580_PM_GO_LINKD; 1456 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1457 } 1458 1459 /* Power down the phy. Needed to make the link go Down */ 1460 eth_igb_dev_set_link_down(dev); 1461 1462 igb_dev_clear_queues(dev); 1463 1464 /* clear the recorded link status */ 1465 memset(&link, 0, sizeof(link)); 1466 rte_eth_linkstatus_set(dev, &link); 1467 1468 if (!rte_intr_allow_others(intr_handle)) 1469 /* resume to the default handler */ 1470 rte_intr_callback_register(intr_handle, 1471 eth_igb_interrupt_handler, 1472 (void *)dev); 1473 1474 /* Clean datapath event and queue/vec mapping */ 1475 rte_intr_efd_disable(intr_handle); 1476 if (intr_handle->intr_vec != NULL) { 1477 rte_free(intr_handle->intr_vec); 1478 intr_handle->intr_vec = NULL; 1479 } 1480 1481 adapter->stopped = true; 1482 dev->data->dev_started = 0; 1483 1484 return 0; 1485 } 1486 1487 static int 1488 eth_igb_dev_set_link_up(struct rte_eth_dev *dev) 1489 { 1490 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1491 1492 if (hw->phy.media_type == e1000_media_type_copper) 1493 e1000_power_up_phy(hw); 1494 else 1495 e1000_power_up_fiber_serdes_link(hw); 1496 1497 return 0; 1498 } 1499 1500 static int 1501 eth_igb_dev_set_link_down(struct rte_eth_dev *dev) 1502 { 1503 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1504 1505 if (hw->phy.media_type == e1000_media_type_copper) 1506 e1000_power_down_phy(hw); 1507 else 1508 e1000_shutdown_fiber_serdes_link(hw); 1509 1510 return 0; 1511 } 1512 1513 static int 1514 eth_igb_close(struct rte_eth_dev *dev) 1515 { 1516 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1517 struct rte_eth_link link; 1518 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1519 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1520 struct e1000_filter_info *filter_info = 1521 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 1522 int ret; 1523 1524 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1525 return 0; 1526 1527 ret = eth_igb_stop(dev); 1528 1529 e1000_phy_hw_reset(hw); 1530 igb_release_manageability(hw); 1531 igb_hw_control_release(hw); 1532 1533 /* Clear bit for Go Link disconnect if PHY reset is not blocked */ 1534 if (hw->mac.type >= e1000_82580 && 1535 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) { 1536 uint32_t phpm_reg; 1537 1538 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1539 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1540 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1541 } 1542 1543 igb_dev_free_queues(dev); 1544 1545 if (intr_handle->intr_vec) { 1546 rte_free(intr_handle->intr_vec); 1547 intr_handle->intr_vec = NULL; 1548 } 1549 1550 memset(&link, 0, sizeof(link)); 1551 rte_eth_linkstatus_set(dev, &link); 1552 1553 /* Reset any pending lock */ 1554 igb_reset_swfw_lock(hw); 1555 1556 /* uninitialize PF if max_vfs not zero */ 1557 igb_pf_host_uninit(dev); 1558 1559 rte_intr_callback_unregister(intr_handle, 1560 eth_igb_interrupt_handler, dev); 1561 1562 /* clear the SYN filter info */ 1563 filter_info->syn_info = 0; 1564 1565 /* clear the ethertype filters info */ 1566 filter_info->ethertype_mask = 0; 1567 memset(filter_info->ethertype_filters, 0, 1568 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter)); 1569 1570 /* clear the rss filter info */ 1571 memset(&filter_info->rss_info, 0, 1572 sizeof(struct igb_rte_flow_rss_conf)); 1573 1574 /* remove all ntuple filters of the device */ 1575 igb_ntuple_filter_uninit(dev); 1576 1577 /* remove all flex filters of the device */ 1578 igb_flex_filter_uninit(dev); 1579 1580 /* clear all the filters list */ 1581 igb_filterlist_flush(dev); 1582 1583 return ret; 1584 } 1585 1586 /* 1587 * Reset PF device. 1588 */ 1589 static int 1590 eth_igb_reset(struct rte_eth_dev *dev) 1591 { 1592 int ret; 1593 1594 /* When a DPDK PMD PF begin to reset PF port, it should notify all 1595 * its VF to make them align with it. The detailed notification 1596 * mechanism is PMD specific and is currently not implemented. 1597 * To avoid unexpected behavior in VF, currently reset of PF with 1598 * SR-IOV activation is not supported. It might be supported later. 1599 */ 1600 if (dev->data->sriov.active) 1601 return -ENOTSUP; 1602 1603 ret = eth_igb_dev_uninit(dev); 1604 if (ret) 1605 return ret; 1606 1607 ret = eth_igb_dev_init(dev); 1608 1609 return ret; 1610 } 1611 1612 1613 static int 1614 igb_get_rx_buffer_size(struct e1000_hw *hw) 1615 { 1616 uint32_t rx_buf_size; 1617 if (hw->mac.type == e1000_82576) { 1618 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10; 1619 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) { 1620 /* PBS needs to be translated according to a lookup table */ 1621 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf); 1622 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size); 1623 rx_buf_size = (rx_buf_size << 10); 1624 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { 1625 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10; 1626 } else { 1627 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10; 1628 } 1629 1630 return rx_buf_size; 1631 } 1632 1633 /********************************************************************* 1634 * 1635 * Initialize the hardware 1636 * 1637 **********************************************************************/ 1638 static int 1639 igb_hardware_init(struct e1000_hw *hw) 1640 { 1641 uint32_t rx_buf_size; 1642 int diag; 1643 1644 /* Let the firmware know the OS is in control */ 1645 igb_hw_control_acquire(hw); 1646 1647 /* 1648 * These parameters control the automatic generation (Tx) and 1649 * response (Rx) to Ethernet PAUSE frames. 1650 * - High water mark should allow for at least two standard size (1518) 1651 * frames to be received after sending an XOFF. 1652 * - Low water mark works best when it is very near the high water mark. 1653 * This allows the receiver to restart by sending XON when it has 1654 * drained a bit. Here we use an arbitrary value of 1500 which will 1655 * restart after one full frame is pulled from the buffer. There 1656 * could be several smaller frames in the buffer and if so they will 1657 * not trigger the XON until their total number reduces the buffer 1658 * by 1500. 1659 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1660 */ 1661 rx_buf_size = igb_get_rx_buffer_size(hw); 1662 1663 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2); 1664 hw->fc.low_water = hw->fc.high_water - 1500; 1665 hw->fc.pause_time = IGB_FC_PAUSE_TIME; 1666 hw->fc.send_xon = 1; 1667 1668 /* Set Flow control, use the tunable location if sane */ 1669 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4)) 1670 hw->fc.requested_mode = igb_fc_setting; 1671 else 1672 hw->fc.requested_mode = e1000_fc_none; 1673 1674 /* Issue a global reset */ 1675 igb_pf_reset_hw(hw); 1676 E1000_WRITE_REG(hw, E1000_WUC, 0); 1677 1678 diag = e1000_init_hw(hw); 1679 if (diag < 0) 1680 return diag; 1681 1682 E1000_WRITE_REG(hw, E1000_VET, 1683 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN); 1684 e1000_get_phy_info(hw); 1685 e1000_check_for_link(hw); 1686 1687 return 0; 1688 } 1689 1690 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */ 1691 static void 1692 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats) 1693 { 1694 int pause_frames; 1695 1696 uint64_t old_gprc = stats->gprc; 1697 uint64_t old_gptc = stats->gptc; 1698 uint64_t old_tpr = stats->tpr; 1699 uint64_t old_tpt = stats->tpt; 1700 uint64_t old_rpthc = stats->rpthc; 1701 uint64_t old_hgptc = stats->hgptc; 1702 1703 if(hw->phy.media_type == e1000_media_type_copper || 1704 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 1705 stats->symerrs += 1706 E1000_READ_REG(hw,E1000_SYMERRS); 1707 stats->sec += E1000_READ_REG(hw, E1000_SEC); 1708 } 1709 1710 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS); 1711 stats->mpc += E1000_READ_REG(hw, E1000_MPC); 1712 stats->scc += E1000_READ_REG(hw, E1000_SCC); 1713 stats->ecol += E1000_READ_REG(hw, E1000_ECOL); 1714 1715 stats->mcc += E1000_READ_REG(hw, E1000_MCC); 1716 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL); 1717 stats->colc += E1000_READ_REG(hw, E1000_COLC); 1718 stats->dc += E1000_READ_REG(hw, E1000_DC); 1719 stats->rlec += E1000_READ_REG(hw, E1000_RLEC); 1720 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC); 1721 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC); 1722 /* 1723 ** For watchdog management we need to know if we have been 1724 ** paused during the last interval, so capture that here. 1725 */ 1726 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC); 1727 stats->xoffrxc += pause_frames; 1728 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC); 1729 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC); 1730 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64); 1731 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127); 1732 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255); 1733 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511); 1734 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023); 1735 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522); 1736 stats->gprc += E1000_READ_REG(hw, E1000_GPRC); 1737 stats->bprc += E1000_READ_REG(hw, E1000_BPRC); 1738 stats->mprc += E1000_READ_REG(hw, E1000_MPRC); 1739 stats->gptc += E1000_READ_REG(hw, E1000_GPTC); 1740 1741 /* For the 64-bit byte counters the low dword must be read first. */ 1742 /* Both registers clear on the read of the high dword */ 1743 1744 /* Workaround CRC bytes included in size, take away 4 bytes/packet */ 1745 stats->gorc += E1000_READ_REG(hw, E1000_GORCL); 1746 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32); 1747 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN; 1748 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL); 1749 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32); 1750 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN; 1751 1752 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC); 1753 stats->ruc += E1000_READ_REG(hw, E1000_RUC); 1754 stats->rfc += E1000_READ_REG(hw, E1000_RFC); 1755 stats->roc += E1000_READ_REG(hw, E1000_ROC); 1756 stats->rjc += E1000_READ_REG(hw, E1000_RJC); 1757 1758 stats->tpr += E1000_READ_REG(hw, E1000_TPR); 1759 stats->tpt += E1000_READ_REG(hw, E1000_TPT); 1760 1761 stats->tor += E1000_READ_REG(hw, E1000_TORL); 1762 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32); 1763 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 1764 stats->tot += E1000_READ_REG(hw, E1000_TOTL); 1765 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32); 1766 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN; 1767 1768 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64); 1769 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127); 1770 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255); 1771 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511); 1772 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023); 1773 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522); 1774 stats->mptc += E1000_READ_REG(hw, E1000_MPTC); 1775 stats->bptc += E1000_READ_REG(hw, E1000_BPTC); 1776 1777 /* Interrupt Counts */ 1778 1779 stats->iac += E1000_READ_REG(hw, E1000_IAC); 1780 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC); 1781 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC); 1782 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC); 1783 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC); 1784 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC); 1785 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC); 1786 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC); 1787 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC); 1788 1789 /* Host to Card Statistics */ 1790 1791 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC); 1792 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC); 1793 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC); 1794 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC); 1795 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC); 1796 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC); 1797 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC); 1798 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL); 1799 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32); 1800 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN; 1801 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL); 1802 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32); 1803 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN; 1804 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS); 1805 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC); 1806 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC); 1807 1808 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC); 1809 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC); 1810 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS); 1811 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR); 1812 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC); 1813 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC); 1814 } 1815 1816 static int 1817 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats) 1818 { 1819 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1820 struct e1000_hw_stats *stats = 1821 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1822 1823 igb_read_stats_registers(hw, stats); 1824 1825 if (rte_stats == NULL) 1826 return -EINVAL; 1827 1828 /* Rx Errors */ 1829 rte_stats->imissed = stats->mpc; 1830 rte_stats->ierrors = stats->crcerrs + 1831 stats->rlec + stats->ruc + stats->roc + 1832 stats->rxerrc + stats->algnerrc + stats->cexterr; 1833 1834 /* Tx Errors */ 1835 rte_stats->oerrors = stats->ecol + stats->latecol; 1836 1837 rte_stats->ipackets = stats->gprc; 1838 rte_stats->opackets = stats->gptc; 1839 rte_stats->ibytes = stats->gorc; 1840 rte_stats->obytes = stats->gotc; 1841 return 0; 1842 } 1843 1844 static int 1845 eth_igb_stats_reset(struct rte_eth_dev *dev) 1846 { 1847 struct e1000_hw_stats *hw_stats = 1848 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1849 1850 /* HW registers are cleared on read */ 1851 eth_igb_stats_get(dev, NULL); 1852 1853 /* Reset software totals */ 1854 memset(hw_stats, 0, sizeof(*hw_stats)); 1855 1856 return 0; 1857 } 1858 1859 static int 1860 eth_igb_xstats_reset(struct rte_eth_dev *dev) 1861 { 1862 struct e1000_hw_stats *stats = 1863 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1864 1865 /* HW registers are cleared on read */ 1866 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS); 1867 1868 /* Reset software totals */ 1869 memset(stats, 0, sizeof(*stats)); 1870 1871 return 0; 1872 } 1873 1874 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1875 struct rte_eth_xstat_name *xstats_names, 1876 __rte_unused unsigned int size) 1877 { 1878 unsigned i; 1879 1880 if (xstats_names == NULL) 1881 return IGB_NB_XSTATS; 1882 1883 /* Note: limit checked in rte_eth_xstats_names() */ 1884 1885 for (i = 0; i < IGB_NB_XSTATS; i++) { 1886 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name, 1887 sizeof(xstats_names[i].name)); 1888 } 1889 1890 return IGB_NB_XSTATS; 1891 } 1892 1893 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev, 1894 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 1895 unsigned int limit) 1896 { 1897 unsigned int i; 1898 1899 if (!ids) { 1900 if (xstats_names == NULL) 1901 return IGB_NB_XSTATS; 1902 1903 for (i = 0; i < IGB_NB_XSTATS; i++) 1904 strlcpy(xstats_names[i].name, 1905 rte_igb_stats_strings[i].name, 1906 sizeof(xstats_names[i].name)); 1907 1908 return IGB_NB_XSTATS; 1909 1910 } else { 1911 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS]; 1912 1913 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 1914 IGB_NB_XSTATS); 1915 1916 for (i = 0; i < limit; i++) { 1917 if (ids[i] >= IGB_NB_XSTATS) { 1918 PMD_INIT_LOG(ERR, "id value isn't valid"); 1919 return -1; 1920 } 1921 strcpy(xstats_names[i].name, 1922 xstats_names_copy[ids[i]].name); 1923 } 1924 return limit; 1925 } 1926 } 1927 1928 static int 1929 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1930 unsigned n) 1931 { 1932 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1933 struct e1000_hw_stats *hw_stats = 1934 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1935 unsigned i; 1936 1937 if (n < IGB_NB_XSTATS) 1938 return IGB_NB_XSTATS; 1939 1940 igb_read_stats_registers(hw, hw_stats); 1941 1942 /* If this is a reset xstats is NULL, and we have cleared the 1943 * registers by reading them. 1944 */ 1945 if (!xstats) 1946 return 0; 1947 1948 /* Extended stats */ 1949 for (i = 0; i < IGB_NB_XSTATS; i++) { 1950 xstats[i].id = i; 1951 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 1952 rte_igb_stats_strings[i].offset); 1953 } 1954 1955 return IGB_NB_XSTATS; 1956 } 1957 1958 static int 1959 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1960 uint64_t *values, unsigned int n) 1961 { 1962 unsigned int i; 1963 1964 if (!ids) { 1965 struct e1000_hw *hw = 1966 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1967 struct e1000_hw_stats *hw_stats = 1968 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1969 1970 if (n < IGB_NB_XSTATS) 1971 return IGB_NB_XSTATS; 1972 1973 igb_read_stats_registers(hw, hw_stats); 1974 1975 /* If this is a reset xstats is NULL, and we have cleared the 1976 * registers by reading them. 1977 */ 1978 if (!values) 1979 return 0; 1980 1981 /* Extended stats */ 1982 for (i = 0; i < IGB_NB_XSTATS; i++) 1983 values[i] = *(uint64_t *)(((char *)hw_stats) + 1984 rte_igb_stats_strings[i].offset); 1985 1986 return IGB_NB_XSTATS; 1987 1988 } else { 1989 uint64_t values_copy[IGB_NB_XSTATS]; 1990 1991 eth_igb_xstats_get_by_id(dev, NULL, values_copy, 1992 IGB_NB_XSTATS); 1993 1994 for (i = 0; i < n; i++) { 1995 if (ids[i] >= IGB_NB_XSTATS) { 1996 PMD_INIT_LOG(ERR, "id value isn't valid"); 1997 return -1; 1998 } 1999 values[i] = values_copy[ids[i]]; 2000 } 2001 return n; 2002 } 2003 } 2004 2005 static void 2006 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats) 2007 { 2008 /* Good Rx packets, include VF loopback */ 2009 UPDATE_VF_STAT(E1000_VFGPRC, 2010 hw_stats->last_gprc, hw_stats->gprc); 2011 2012 /* Good Rx octets, include VF loopback */ 2013 UPDATE_VF_STAT(E1000_VFGORC, 2014 hw_stats->last_gorc, hw_stats->gorc); 2015 2016 /* Good Tx packets, include VF loopback */ 2017 UPDATE_VF_STAT(E1000_VFGPTC, 2018 hw_stats->last_gptc, hw_stats->gptc); 2019 2020 /* Good Tx octets, include VF loopback */ 2021 UPDATE_VF_STAT(E1000_VFGOTC, 2022 hw_stats->last_gotc, hw_stats->gotc); 2023 2024 /* Rx Multicst packets */ 2025 UPDATE_VF_STAT(E1000_VFMPRC, 2026 hw_stats->last_mprc, hw_stats->mprc); 2027 2028 /* Good Rx loopback packets */ 2029 UPDATE_VF_STAT(E1000_VFGPRLBC, 2030 hw_stats->last_gprlbc, hw_stats->gprlbc); 2031 2032 /* Good Rx loopback octets */ 2033 UPDATE_VF_STAT(E1000_VFGORLBC, 2034 hw_stats->last_gorlbc, hw_stats->gorlbc); 2035 2036 /* Good Tx loopback packets */ 2037 UPDATE_VF_STAT(E1000_VFGPTLBC, 2038 hw_stats->last_gptlbc, hw_stats->gptlbc); 2039 2040 /* Good Tx loopback octets */ 2041 UPDATE_VF_STAT(E1000_VFGOTLBC, 2042 hw_stats->last_gotlbc, hw_stats->gotlbc); 2043 } 2044 2045 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 2046 struct rte_eth_xstat_name *xstats_names, 2047 __rte_unused unsigned limit) 2048 { 2049 unsigned i; 2050 2051 if (xstats_names != NULL) 2052 for (i = 0; i < IGBVF_NB_XSTATS; i++) { 2053 strlcpy(xstats_names[i].name, 2054 rte_igbvf_stats_strings[i].name, 2055 sizeof(xstats_names[i].name)); 2056 } 2057 return IGBVF_NB_XSTATS; 2058 } 2059 2060 static int 2061 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 2062 unsigned n) 2063 { 2064 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2065 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *) 2066 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 2067 unsigned i; 2068 2069 if (n < IGBVF_NB_XSTATS) 2070 return IGBVF_NB_XSTATS; 2071 2072 igbvf_read_stats_registers(hw, hw_stats); 2073 2074 if (!xstats) 2075 return 0; 2076 2077 for (i = 0; i < IGBVF_NB_XSTATS; i++) { 2078 xstats[i].id = i; 2079 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 2080 rte_igbvf_stats_strings[i].offset); 2081 } 2082 2083 return IGBVF_NB_XSTATS; 2084 } 2085 2086 static int 2087 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats) 2088 { 2089 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2090 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *) 2091 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 2092 2093 igbvf_read_stats_registers(hw, hw_stats); 2094 2095 if (rte_stats == NULL) 2096 return -EINVAL; 2097 2098 rte_stats->ipackets = hw_stats->gprc; 2099 rte_stats->ibytes = hw_stats->gorc; 2100 rte_stats->opackets = hw_stats->gptc; 2101 rte_stats->obytes = hw_stats->gotc; 2102 return 0; 2103 } 2104 2105 static int 2106 eth_igbvf_stats_reset(struct rte_eth_dev *dev) 2107 { 2108 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*) 2109 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 2110 2111 /* Sync HW register to the last stats */ 2112 eth_igbvf_stats_get(dev, NULL); 2113 2114 /* reset HW current stats*/ 2115 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) - 2116 offsetof(struct e1000_vf_stats, gprc)); 2117 2118 return 0; 2119 } 2120 2121 static int 2122 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 2123 size_t fw_size) 2124 { 2125 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2126 struct e1000_fw_version fw; 2127 int ret; 2128 2129 e1000_get_fw_version(hw, &fw); 2130 2131 switch (hw->mac.type) { 2132 case e1000_i210: 2133 case e1000_i211: 2134 if (!(e1000_get_flash_presence_i210(hw))) { 2135 ret = snprintf(fw_version, fw_size, 2136 "%2d.%2d-%d", 2137 fw.invm_major, fw.invm_minor, 2138 fw.invm_img_type); 2139 break; 2140 } 2141 /* fall through */ 2142 default: 2143 /* if option rom is valid, display its version too */ 2144 if (fw.or_valid) { 2145 ret = snprintf(fw_version, fw_size, 2146 "%d.%d, 0x%08x, %d.%d.%d", 2147 fw.eep_major, fw.eep_minor, fw.etrack_id, 2148 fw.or_major, fw.or_build, fw.or_patch); 2149 /* no option rom */ 2150 } else { 2151 if (fw.etrack_id != 0X0000) { 2152 ret = snprintf(fw_version, fw_size, 2153 "%d.%d, 0x%08x", 2154 fw.eep_major, fw.eep_minor, 2155 fw.etrack_id); 2156 } else { 2157 ret = snprintf(fw_version, fw_size, 2158 "%d.%d.%d", 2159 fw.eep_major, fw.eep_minor, 2160 fw.eep_build); 2161 } 2162 } 2163 break; 2164 } 2165 2166 ret += 1; /* add the size of '\0' */ 2167 if (fw_size < (u32)ret) 2168 return ret; 2169 else 2170 return 0; 2171 } 2172 2173 static int 2174 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2175 { 2176 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2177 2178 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */ 2179 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */ 2180 dev_info->max_mac_addrs = hw->mac.rar_entry_count; 2181 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev); 2182 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) | 2183 dev_info->rx_queue_offload_capa; 2184 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev); 2185 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) | 2186 dev_info->tx_queue_offload_capa; 2187 2188 switch (hw->mac.type) { 2189 case e1000_82575: 2190 dev_info->max_rx_queues = 4; 2191 dev_info->max_tx_queues = 4; 2192 dev_info->max_vmdq_pools = 0; 2193 break; 2194 2195 case e1000_82576: 2196 dev_info->max_rx_queues = 16; 2197 dev_info->max_tx_queues = 16; 2198 dev_info->max_vmdq_pools = ETH_8_POOLS; 2199 dev_info->vmdq_queue_num = 16; 2200 break; 2201 2202 case e1000_82580: 2203 dev_info->max_rx_queues = 8; 2204 dev_info->max_tx_queues = 8; 2205 dev_info->max_vmdq_pools = ETH_8_POOLS; 2206 dev_info->vmdq_queue_num = 8; 2207 break; 2208 2209 case e1000_i350: 2210 dev_info->max_rx_queues = 8; 2211 dev_info->max_tx_queues = 8; 2212 dev_info->max_vmdq_pools = ETH_8_POOLS; 2213 dev_info->vmdq_queue_num = 8; 2214 break; 2215 2216 case e1000_i354: 2217 dev_info->max_rx_queues = 8; 2218 dev_info->max_tx_queues = 8; 2219 break; 2220 2221 case e1000_i210: 2222 dev_info->max_rx_queues = 4; 2223 dev_info->max_tx_queues = 4; 2224 dev_info->max_vmdq_pools = 0; 2225 break; 2226 2227 case e1000_i211: 2228 dev_info->max_rx_queues = 2; 2229 dev_info->max_tx_queues = 2; 2230 dev_info->max_vmdq_pools = 0; 2231 break; 2232 2233 default: 2234 /* Should not happen */ 2235 return -EINVAL; 2236 } 2237 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t); 2238 dev_info->reta_size = ETH_RSS_RETA_SIZE_128; 2239 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL; 2240 2241 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2242 .rx_thresh = { 2243 .pthresh = IGB_DEFAULT_RX_PTHRESH, 2244 .hthresh = IGB_DEFAULT_RX_HTHRESH, 2245 .wthresh = IGB_DEFAULT_RX_WTHRESH, 2246 }, 2247 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH, 2248 .rx_drop_en = 0, 2249 .offloads = 0, 2250 }; 2251 2252 dev_info->default_txconf = (struct rte_eth_txconf) { 2253 .tx_thresh = { 2254 .pthresh = IGB_DEFAULT_TX_PTHRESH, 2255 .hthresh = IGB_DEFAULT_TX_HTHRESH, 2256 .wthresh = IGB_DEFAULT_TX_WTHRESH, 2257 }, 2258 .offloads = 0, 2259 }; 2260 2261 dev_info->rx_desc_lim = rx_desc_lim; 2262 dev_info->tx_desc_lim = tx_desc_lim; 2263 2264 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M | 2265 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M | 2266 ETH_LINK_SPEED_1G; 2267 2268 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD; 2269 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 2270 2271 return 0; 2272 } 2273 2274 static const uint32_t * 2275 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev) 2276 { 2277 static const uint32_t ptypes[] = { 2278 /* refers to igb_rxd_pkt_info_to_pkt_type() */ 2279 RTE_PTYPE_L2_ETHER, 2280 RTE_PTYPE_L3_IPV4, 2281 RTE_PTYPE_L3_IPV4_EXT, 2282 RTE_PTYPE_L3_IPV6, 2283 RTE_PTYPE_L3_IPV6_EXT, 2284 RTE_PTYPE_L4_TCP, 2285 RTE_PTYPE_L4_UDP, 2286 RTE_PTYPE_L4_SCTP, 2287 RTE_PTYPE_TUNNEL_IP, 2288 RTE_PTYPE_INNER_L3_IPV6, 2289 RTE_PTYPE_INNER_L3_IPV6_EXT, 2290 RTE_PTYPE_INNER_L4_TCP, 2291 RTE_PTYPE_INNER_L4_UDP, 2292 RTE_PTYPE_UNKNOWN 2293 }; 2294 2295 if (dev->rx_pkt_burst == eth_igb_recv_pkts || 2296 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts) 2297 return ptypes; 2298 return NULL; 2299 } 2300 2301 static int 2302 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2303 { 2304 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2305 2306 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */ 2307 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */ 2308 dev_info->max_mac_addrs = hw->mac.rar_entry_count; 2309 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 2310 DEV_TX_OFFLOAD_IPV4_CKSUM | 2311 DEV_TX_OFFLOAD_UDP_CKSUM | 2312 DEV_TX_OFFLOAD_TCP_CKSUM | 2313 DEV_TX_OFFLOAD_SCTP_CKSUM | 2314 DEV_TX_OFFLOAD_TCP_TSO; 2315 switch (hw->mac.type) { 2316 case e1000_vfadapt: 2317 dev_info->max_rx_queues = 2; 2318 dev_info->max_tx_queues = 2; 2319 break; 2320 case e1000_vfadapt_i350: 2321 dev_info->max_rx_queues = 1; 2322 dev_info->max_tx_queues = 1; 2323 break; 2324 default: 2325 /* Should not happen */ 2326 return -EINVAL; 2327 } 2328 2329 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev); 2330 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) | 2331 dev_info->rx_queue_offload_capa; 2332 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev); 2333 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) | 2334 dev_info->tx_queue_offload_capa; 2335 2336 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2337 .rx_thresh = { 2338 .pthresh = IGB_DEFAULT_RX_PTHRESH, 2339 .hthresh = IGB_DEFAULT_RX_HTHRESH, 2340 .wthresh = IGB_DEFAULT_RX_WTHRESH, 2341 }, 2342 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH, 2343 .rx_drop_en = 0, 2344 .offloads = 0, 2345 }; 2346 2347 dev_info->default_txconf = (struct rte_eth_txconf) { 2348 .tx_thresh = { 2349 .pthresh = IGB_DEFAULT_TX_PTHRESH, 2350 .hthresh = IGB_DEFAULT_TX_HTHRESH, 2351 .wthresh = IGB_DEFAULT_TX_WTHRESH, 2352 }, 2353 .offloads = 0, 2354 }; 2355 2356 dev_info->rx_desc_lim = rx_desc_lim; 2357 dev_info->tx_desc_lim = tx_desc_lim; 2358 2359 return 0; 2360 } 2361 2362 /* return 0 means link status changed, -1 means not changed */ 2363 static int 2364 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2365 { 2366 struct e1000_hw *hw = 2367 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2368 struct rte_eth_link link; 2369 int link_check, count; 2370 2371 link_check = 0; 2372 hw->mac.get_link_status = 1; 2373 2374 /* possible wait-to-complete in up to 9 seconds */ 2375 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) { 2376 /* Read the real link status */ 2377 switch (hw->phy.media_type) { 2378 case e1000_media_type_copper: 2379 /* Do the work to read phy */ 2380 e1000_check_for_link(hw); 2381 link_check = !hw->mac.get_link_status; 2382 break; 2383 2384 case e1000_media_type_fiber: 2385 e1000_check_for_link(hw); 2386 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 2387 E1000_STATUS_LU); 2388 break; 2389 2390 case e1000_media_type_internal_serdes: 2391 e1000_check_for_link(hw); 2392 link_check = hw->mac.serdes_has_link; 2393 break; 2394 2395 /* VF device is type_unknown */ 2396 case e1000_media_type_unknown: 2397 eth_igbvf_link_update(hw); 2398 link_check = !hw->mac.get_link_status; 2399 break; 2400 2401 default: 2402 break; 2403 } 2404 if (link_check || wait_to_complete == 0) 2405 break; 2406 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL); 2407 } 2408 memset(&link, 0, sizeof(link)); 2409 2410 /* Now we check if a transition has happened */ 2411 if (link_check) { 2412 uint16_t duplex, speed; 2413 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 2414 link.link_duplex = (duplex == FULL_DUPLEX) ? 2415 ETH_LINK_FULL_DUPLEX : 2416 ETH_LINK_HALF_DUPLEX; 2417 link.link_speed = speed; 2418 link.link_status = ETH_LINK_UP; 2419 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2420 ETH_LINK_SPEED_FIXED); 2421 } else if (!link_check) { 2422 link.link_speed = 0; 2423 link.link_duplex = ETH_LINK_HALF_DUPLEX; 2424 link.link_status = ETH_LINK_DOWN; 2425 link.link_autoneg = ETH_LINK_FIXED; 2426 } 2427 2428 return rte_eth_linkstatus_set(dev, &link); 2429 } 2430 2431 /* 2432 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit. 2433 * For ASF and Pass Through versions of f/w this means 2434 * that the driver is loaded. 2435 */ 2436 static void 2437 igb_hw_control_acquire(struct e1000_hw *hw) 2438 { 2439 uint32_t ctrl_ext; 2440 2441 /* Let firmware know the driver has taken over */ 2442 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2443 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2444 } 2445 2446 /* 2447 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit. 2448 * For ASF and Pass Through versions of f/w this means that the 2449 * driver is no longer loaded. 2450 */ 2451 static void 2452 igb_hw_control_release(struct e1000_hw *hw) 2453 { 2454 uint32_t ctrl_ext; 2455 2456 /* Let firmware taken over control of h/w */ 2457 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2458 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 2459 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2460 } 2461 2462 /* 2463 * Bit of a misnomer, what this really means is 2464 * to enable OS management of the system... aka 2465 * to disable special hardware management features. 2466 */ 2467 static void 2468 igb_init_manageability(struct e1000_hw *hw) 2469 { 2470 if (e1000_enable_mng_pass_thru(hw)) { 2471 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H); 2472 uint32_t manc = E1000_READ_REG(hw, E1000_MANC); 2473 2474 /* disable hardware interception of ARP */ 2475 manc &= ~(E1000_MANC_ARP_EN); 2476 2477 /* enable receiving management packets to the host */ 2478 manc |= E1000_MANC_EN_MNG2HOST; 2479 manc2h |= 1 << 5; /* Mng Port 623 */ 2480 manc2h |= 1 << 6; /* Mng Port 664 */ 2481 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h); 2482 E1000_WRITE_REG(hw, E1000_MANC, manc); 2483 } 2484 } 2485 2486 static void 2487 igb_release_manageability(struct e1000_hw *hw) 2488 { 2489 if (e1000_enable_mng_pass_thru(hw)) { 2490 uint32_t manc = E1000_READ_REG(hw, E1000_MANC); 2491 2492 manc |= E1000_MANC_ARP_EN; 2493 manc &= ~E1000_MANC_EN_MNG2HOST; 2494 2495 E1000_WRITE_REG(hw, E1000_MANC, manc); 2496 } 2497 } 2498 2499 static int 2500 eth_igb_promiscuous_enable(struct rte_eth_dev *dev) 2501 { 2502 struct e1000_hw *hw = 2503 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2504 uint32_t rctl; 2505 2506 rctl = E1000_READ_REG(hw, E1000_RCTL); 2507 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2508 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2509 2510 return 0; 2511 } 2512 2513 static int 2514 eth_igb_promiscuous_disable(struct rte_eth_dev *dev) 2515 { 2516 struct e1000_hw *hw = 2517 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2518 uint32_t rctl; 2519 2520 rctl = E1000_READ_REG(hw, E1000_RCTL); 2521 rctl &= (~E1000_RCTL_UPE); 2522 if (dev->data->all_multicast == 1) 2523 rctl |= E1000_RCTL_MPE; 2524 else 2525 rctl &= (~E1000_RCTL_MPE); 2526 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2527 2528 return 0; 2529 } 2530 2531 static int 2532 eth_igb_allmulticast_enable(struct rte_eth_dev *dev) 2533 { 2534 struct e1000_hw *hw = 2535 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2536 uint32_t rctl; 2537 2538 rctl = E1000_READ_REG(hw, E1000_RCTL); 2539 rctl |= E1000_RCTL_MPE; 2540 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2541 2542 return 0; 2543 } 2544 2545 static int 2546 eth_igb_allmulticast_disable(struct rte_eth_dev *dev) 2547 { 2548 struct e1000_hw *hw = 2549 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2550 uint32_t rctl; 2551 2552 if (dev->data->promiscuous == 1) 2553 return 0; /* must remain in all_multicast mode */ 2554 rctl = E1000_READ_REG(hw, E1000_RCTL); 2555 rctl &= (~E1000_RCTL_MPE); 2556 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2557 2558 return 0; 2559 } 2560 2561 static int 2562 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 2563 { 2564 struct e1000_hw *hw = 2565 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2566 struct e1000_vfta * shadow_vfta = 2567 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 2568 uint32_t vfta; 2569 uint32_t vid_idx; 2570 uint32_t vid_bit; 2571 2572 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) & 2573 E1000_VFTA_ENTRY_MASK); 2574 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK)); 2575 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx); 2576 if (on) 2577 vfta |= vid_bit; 2578 else 2579 vfta &= ~vid_bit; 2580 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta); 2581 2582 /* update local VFTA copy */ 2583 shadow_vfta->vfta[vid_idx] = vfta; 2584 2585 return 0; 2586 } 2587 2588 static int 2589 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, 2590 enum rte_vlan_type vlan_type, 2591 uint16_t tpid) 2592 { 2593 struct e1000_hw *hw = 2594 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2595 uint32_t reg, qinq; 2596 2597 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT); 2598 qinq &= E1000_CTRL_EXT_EXT_VLAN; 2599 2600 /* only outer TPID of double VLAN can be configured*/ 2601 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) { 2602 reg = E1000_READ_REG(hw, E1000_VET); 2603 reg = (reg & (~E1000_VET_VET_EXT)) | 2604 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT); 2605 E1000_WRITE_REG(hw, E1000_VET, reg); 2606 2607 return 0; 2608 } 2609 2610 /* all other TPID values are read-only*/ 2611 PMD_DRV_LOG(ERR, "Not supported"); 2612 2613 return -ENOTSUP; 2614 } 2615 2616 static void 2617 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev) 2618 { 2619 struct e1000_hw *hw = 2620 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2621 uint32_t reg; 2622 2623 /* Filter Table Disable */ 2624 reg = E1000_READ_REG(hw, E1000_RCTL); 2625 reg &= ~E1000_RCTL_CFIEN; 2626 reg &= ~E1000_RCTL_VFE; 2627 E1000_WRITE_REG(hw, E1000_RCTL, reg); 2628 } 2629 2630 static void 2631 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2632 { 2633 struct e1000_hw *hw = 2634 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2635 struct e1000_vfta * shadow_vfta = 2636 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 2637 uint32_t reg; 2638 int i; 2639 2640 /* Filter Table Enable, CFI not used for packet acceptance */ 2641 reg = E1000_READ_REG(hw, E1000_RCTL); 2642 reg &= ~E1000_RCTL_CFIEN; 2643 reg |= E1000_RCTL_VFE; 2644 E1000_WRITE_REG(hw, E1000_RCTL, reg); 2645 2646 /* restore VFTA table */ 2647 for (i = 0; i < IGB_VFTA_SIZE; i++) 2648 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]); 2649 } 2650 2651 static void 2652 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev) 2653 { 2654 struct e1000_hw *hw = 2655 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2656 uint32_t reg; 2657 2658 /* VLAN Mode Disable */ 2659 reg = E1000_READ_REG(hw, E1000_CTRL); 2660 reg &= ~E1000_CTRL_VME; 2661 E1000_WRITE_REG(hw, E1000_CTRL, reg); 2662 } 2663 2664 static void 2665 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev) 2666 { 2667 struct e1000_hw *hw = 2668 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2669 uint32_t reg; 2670 2671 /* VLAN Mode Enable */ 2672 reg = E1000_READ_REG(hw, E1000_CTRL); 2673 reg |= E1000_CTRL_VME; 2674 E1000_WRITE_REG(hw, E1000_CTRL, reg); 2675 } 2676 2677 static void 2678 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2679 { 2680 struct e1000_hw *hw = 2681 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2682 uint32_t reg; 2683 2684 /* CTRL_EXT: Extended VLAN */ 2685 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2686 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN; 2687 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2688 2689 /* Update maximum packet length */ 2690 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 2691 E1000_WRITE_REG(hw, E1000_RLPML, 2692 dev->data->dev_conf.rxmode.max_rx_pkt_len + 2693 VLAN_TAG_SIZE); 2694 } 2695 2696 static void 2697 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2698 { 2699 struct e1000_hw *hw = 2700 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2701 uint32_t reg; 2702 2703 /* CTRL_EXT: Extended VLAN */ 2704 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2705 reg |= E1000_CTRL_EXT_EXTEND_VLAN; 2706 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2707 2708 /* Update maximum packet length */ 2709 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 2710 E1000_WRITE_REG(hw, E1000_RLPML, 2711 dev->data->dev_conf.rxmode.max_rx_pkt_len + 2712 2 * VLAN_TAG_SIZE); 2713 } 2714 2715 static int 2716 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2717 { 2718 struct rte_eth_rxmode *rxmode; 2719 2720 rxmode = &dev->data->dev_conf.rxmode; 2721 if(mask & ETH_VLAN_STRIP_MASK){ 2722 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2723 igb_vlan_hw_strip_enable(dev); 2724 else 2725 igb_vlan_hw_strip_disable(dev); 2726 } 2727 2728 if(mask & ETH_VLAN_FILTER_MASK){ 2729 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2730 igb_vlan_hw_filter_enable(dev); 2731 else 2732 igb_vlan_hw_filter_disable(dev); 2733 } 2734 2735 if(mask & ETH_VLAN_EXTEND_MASK){ 2736 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2737 igb_vlan_hw_extend_enable(dev); 2738 else 2739 igb_vlan_hw_extend_disable(dev); 2740 } 2741 2742 return 0; 2743 } 2744 2745 2746 /** 2747 * It enables the interrupt mask and then enable the interrupt. 2748 * 2749 * @param dev 2750 * Pointer to struct rte_eth_dev. 2751 * @param on 2752 * Enable or Disable 2753 * 2754 * @return 2755 * - On success, zero. 2756 * - On failure, a negative value. 2757 */ 2758 static int 2759 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 2760 { 2761 struct e1000_interrupt *intr = 2762 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2763 2764 if (on) 2765 intr->mask |= E1000_ICR_LSC; 2766 else 2767 intr->mask &= ~E1000_ICR_LSC; 2768 2769 return 0; 2770 } 2771 2772 /* It clears the interrupt causes and enables the interrupt. 2773 * It will be called once only during nic initialized. 2774 * 2775 * @param dev 2776 * Pointer to struct rte_eth_dev. 2777 * 2778 * @return 2779 * - On success, zero. 2780 * - On failure, a negative value. 2781 */ 2782 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev) 2783 { 2784 uint32_t mask, regval; 2785 int ret; 2786 struct e1000_hw *hw = 2787 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2789 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2790 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0; 2791 struct rte_eth_dev_info dev_info; 2792 2793 memset(&dev_info, 0, sizeof(dev_info)); 2794 ret = eth_igb_infos_get(dev, &dev_info); 2795 if (ret != 0) 2796 return ret; 2797 2798 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift; 2799 regval = E1000_READ_REG(hw, E1000_EIMS); 2800 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); 2801 2802 return 0; 2803 } 2804 2805 /* 2806 * It reads ICR and gets interrupt causes, check it and set a bit flag 2807 * to update link status. 2808 * 2809 * @param dev 2810 * Pointer to struct rte_eth_dev. 2811 * 2812 * @return 2813 * - On success, zero. 2814 * - On failure, a negative value. 2815 */ 2816 static int 2817 eth_igb_interrupt_get_status(struct rte_eth_dev *dev) 2818 { 2819 uint32_t icr; 2820 struct e1000_hw *hw = 2821 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2822 struct e1000_interrupt *intr = 2823 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2824 2825 igb_intr_disable(dev); 2826 2827 /* read-on-clear nic registers here */ 2828 icr = E1000_READ_REG(hw, E1000_ICR); 2829 2830 intr->flags = 0; 2831 if (icr & E1000_ICR_LSC) { 2832 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE; 2833 } 2834 2835 if (icr & E1000_ICR_VMMB) 2836 intr->flags |= E1000_FLAG_MAILBOX; 2837 2838 return 0; 2839 } 2840 2841 /* 2842 * It executes link_update after knowing an interrupt is prsent. 2843 * 2844 * @param dev 2845 * Pointer to struct rte_eth_dev. 2846 * 2847 * @return 2848 * - On success, zero. 2849 * - On failure, a negative value. 2850 */ 2851 static int 2852 eth_igb_interrupt_action(struct rte_eth_dev *dev, 2853 struct rte_intr_handle *intr_handle) 2854 { 2855 struct e1000_hw *hw = 2856 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2857 struct e1000_interrupt *intr = 2858 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2859 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2860 struct rte_eth_link link; 2861 int ret; 2862 2863 if (intr->flags & E1000_FLAG_MAILBOX) { 2864 igb_pf_mbx_process(dev); 2865 intr->flags &= ~E1000_FLAG_MAILBOX; 2866 } 2867 2868 igb_intr_enable(dev); 2869 rte_intr_ack(intr_handle); 2870 2871 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) { 2872 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE; 2873 2874 /* set get_link_status to check register later */ 2875 hw->mac.get_link_status = 1; 2876 ret = eth_igb_link_update(dev, 0); 2877 2878 /* check if link has changed */ 2879 if (ret < 0) 2880 return 0; 2881 2882 rte_eth_linkstatus_get(dev, &link); 2883 if (link.link_status) { 2884 PMD_INIT_LOG(INFO, 2885 " Port %d: Link Up - speed %u Mbps - %s", 2886 dev->data->port_id, 2887 (unsigned)link.link_speed, 2888 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 2889 "full-duplex" : "half-duplex"); 2890 } else { 2891 PMD_INIT_LOG(INFO, " Port %d: Link Down", 2892 dev->data->port_id); 2893 } 2894 2895 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 2896 pci_dev->addr.domain, 2897 pci_dev->addr.bus, 2898 pci_dev->addr.devid, 2899 pci_dev->addr.function); 2900 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2901 } 2902 2903 return 0; 2904 } 2905 2906 /** 2907 * Interrupt handler which shall be registered at first. 2908 * 2909 * @param handle 2910 * Pointer to interrupt handle. 2911 * @param param 2912 * The address of parameter (struct rte_eth_dev *) regsitered before. 2913 * 2914 * @return 2915 * void 2916 */ 2917 static void 2918 eth_igb_interrupt_handler(void *param) 2919 { 2920 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2921 2922 eth_igb_interrupt_get_status(dev); 2923 eth_igb_interrupt_action(dev, dev->intr_handle); 2924 } 2925 2926 static int 2927 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev) 2928 { 2929 uint32_t eicr; 2930 struct e1000_hw *hw = 2931 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2932 struct e1000_interrupt *intr = 2933 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2934 2935 igbvf_intr_disable(hw); 2936 2937 /* read-on-clear nic registers here */ 2938 eicr = E1000_READ_REG(hw, E1000_EICR); 2939 intr->flags = 0; 2940 2941 if (eicr == E1000_VTIVAR_MISC_MAILBOX) 2942 intr->flags |= E1000_FLAG_MAILBOX; 2943 2944 return 0; 2945 } 2946 2947 void igbvf_mbx_process(struct rte_eth_dev *dev) 2948 { 2949 struct e1000_hw *hw = 2950 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2951 struct e1000_mbx_info *mbx = &hw->mbx; 2952 u32 in_msg = 0; 2953 2954 /* peek the message first */ 2955 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0)); 2956 2957 /* PF reset VF event */ 2958 if (in_msg == E1000_PF_CONTROL_MSG) { 2959 /* dummy mbx read to ack pf */ 2960 if (mbx->ops.read(hw, &in_msg, 1, 0)) 2961 return; 2962 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 2963 NULL); 2964 } 2965 } 2966 2967 static int 2968 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle) 2969 { 2970 struct e1000_interrupt *intr = 2971 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2972 2973 if (intr->flags & E1000_FLAG_MAILBOX) { 2974 igbvf_mbx_process(dev); 2975 intr->flags &= ~E1000_FLAG_MAILBOX; 2976 } 2977 2978 igbvf_intr_enable(dev); 2979 rte_intr_ack(intr_handle); 2980 2981 return 0; 2982 } 2983 2984 static void 2985 eth_igbvf_interrupt_handler(void *param) 2986 { 2987 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2988 2989 eth_igbvf_interrupt_get_status(dev); 2990 eth_igbvf_interrupt_action(dev, dev->intr_handle); 2991 } 2992 2993 static int 2994 eth_igb_led_on(struct rte_eth_dev *dev) 2995 { 2996 struct e1000_hw *hw; 2997 2998 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2999 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP; 3000 } 3001 3002 static int 3003 eth_igb_led_off(struct rte_eth_dev *dev) 3004 { 3005 struct e1000_hw *hw; 3006 3007 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3008 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP; 3009 } 3010 3011 static int 3012 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3013 { 3014 struct e1000_hw *hw; 3015 uint32_t ctrl; 3016 int tx_pause; 3017 int rx_pause; 3018 3019 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3020 fc_conf->pause_time = hw->fc.pause_time; 3021 fc_conf->high_water = hw->fc.high_water; 3022 fc_conf->low_water = hw->fc.low_water; 3023 fc_conf->send_xon = hw->fc.send_xon; 3024 fc_conf->autoneg = hw->mac.autoneg; 3025 3026 /* 3027 * Return rx_pause and tx_pause status according to actual setting of 3028 * the TFCE and RFCE bits in the CTRL register. 3029 */ 3030 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3031 if (ctrl & E1000_CTRL_TFCE) 3032 tx_pause = 1; 3033 else 3034 tx_pause = 0; 3035 3036 if (ctrl & E1000_CTRL_RFCE) 3037 rx_pause = 1; 3038 else 3039 rx_pause = 0; 3040 3041 if (rx_pause && tx_pause) 3042 fc_conf->mode = RTE_FC_FULL; 3043 else if (rx_pause) 3044 fc_conf->mode = RTE_FC_RX_PAUSE; 3045 else if (tx_pause) 3046 fc_conf->mode = RTE_FC_TX_PAUSE; 3047 else 3048 fc_conf->mode = RTE_FC_NONE; 3049 3050 return 0; 3051 } 3052 3053 static int 3054 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3055 { 3056 struct e1000_hw *hw; 3057 int err; 3058 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = { 3059 e1000_fc_none, 3060 e1000_fc_rx_pause, 3061 e1000_fc_tx_pause, 3062 e1000_fc_full 3063 }; 3064 uint32_t rx_buf_size; 3065 uint32_t max_high_water; 3066 uint32_t rctl; 3067 uint32_t ctrl; 3068 3069 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3070 if (fc_conf->autoneg != hw->mac.autoneg) 3071 return -ENOTSUP; 3072 rx_buf_size = igb_get_rx_buffer_size(hw); 3073 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3074 3075 /* At least reserve one Ethernet frame for watermark */ 3076 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN; 3077 if ((fc_conf->high_water > max_high_water) || 3078 (fc_conf->high_water < fc_conf->low_water)) { 3079 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value"); 3080 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water); 3081 return -EINVAL; 3082 } 3083 3084 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode]; 3085 hw->fc.pause_time = fc_conf->pause_time; 3086 hw->fc.high_water = fc_conf->high_water; 3087 hw->fc.low_water = fc_conf->low_water; 3088 hw->fc.send_xon = fc_conf->send_xon; 3089 3090 err = e1000_setup_link_generic(hw); 3091 if (err == E1000_SUCCESS) { 3092 3093 /* check if we want to forward MAC frames - driver doesn't have native 3094 * capability to do that, so we'll write the registers ourselves */ 3095 3096 rctl = E1000_READ_REG(hw, E1000_RCTL); 3097 3098 /* set or clear MFLCN.PMCF bit depending on configuration */ 3099 if (fc_conf->mac_ctrl_frame_fwd != 0) 3100 rctl |= E1000_RCTL_PMCF; 3101 else 3102 rctl &= ~E1000_RCTL_PMCF; 3103 3104 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3105 3106 /* 3107 * check if we want to change flow control mode - driver doesn't have native 3108 * capability to do that, so we'll write the registers ourselves 3109 */ 3110 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3111 3112 /* 3113 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending 3114 * on configuration 3115 */ 3116 switch (fc_conf->mode) { 3117 case RTE_FC_NONE: 3118 ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE; 3119 break; 3120 case RTE_FC_RX_PAUSE: 3121 ctrl |= E1000_CTRL_RFCE; 3122 ctrl &= ~E1000_CTRL_TFCE; 3123 break; 3124 case RTE_FC_TX_PAUSE: 3125 ctrl |= E1000_CTRL_TFCE; 3126 ctrl &= ~E1000_CTRL_RFCE; 3127 break; 3128 case RTE_FC_FULL: 3129 ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE; 3130 break; 3131 default: 3132 PMD_INIT_LOG(ERR, "invalid flow control mode"); 3133 return -EINVAL; 3134 } 3135 3136 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3137 3138 E1000_WRITE_FLUSH(hw); 3139 3140 return 0; 3141 } 3142 3143 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err); 3144 return -EIO; 3145 } 3146 3147 #define E1000_RAH_POOLSEL_SHIFT (18) 3148 static int 3149 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 3150 uint32_t index, uint32_t pool) 3151 { 3152 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3153 uint32_t rah; 3154 3155 e1000_rar_set(hw, mac_addr->addr_bytes, index); 3156 rah = E1000_READ_REG(hw, E1000_RAH(index)); 3157 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool)); 3158 E1000_WRITE_REG(hw, E1000_RAH(index), rah); 3159 return 0; 3160 } 3161 3162 static void 3163 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index) 3164 { 3165 uint8_t addr[RTE_ETHER_ADDR_LEN]; 3166 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3167 3168 memset(addr, 0, sizeof(addr)); 3169 3170 e1000_rar_set(hw, addr, index); 3171 } 3172 3173 static int 3174 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev, 3175 struct rte_ether_addr *addr) 3176 { 3177 eth_igb_rar_clear(dev, 0); 3178 eth_igb_rar_set(dev, (void *)addr, 0, 0); 3179 3180 return 0; 3181 } 3182 /* 3183 * Virtual Function operations 3184 */ 3185 static void 3186 igbvf_intr_disable(struct e1000_hw *hw) 3187 { 3188 PMD_INIT_FUNC_TRACE(); 3189 3190 /* Clear interrupt mask to stop from interrupts being generated */ 3191 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF); 3192 3193 E1000_WRITE_FLUSH(hw); 3194 } 3195 3196 static void 3197 igbvf_stop_adapter(struct rte_eth_dev *dev) 3198 { 3199 u32 reg_val; 3200 u16 i; 3201 struct rte_eth_dev_info dev_info; 3202 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3203 int ret; 3204 3205 memset(&dev_info, 0, sizeof(dev_info)); 3206 ret = eth_igbvf_infos_get(dev, &dev_info); 3207 if (ret != 0) 3208 return; 3209 3210 /* Clear interrupt mask to stop from interrupts being generated */ 3211 igbvf_intr_disable(hw); 3212 3213 /* Clear any pending interrupts, flush previous writes */ 3214 E1000_READ_REG(hw, E1000_EICR); 3215 3216 /* Disable the transmit unit. Each queue must be disabled. */ 3217 for (i = 0; i < dev_info.max_tx_queues; i++) 3218 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH); 3219 3220 /* Disable the receive unit by stopping each queue */ 3221 for (i = 0; i < dev_info.max_rx_queues; i++) { 3222 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3223 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE; 3224 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val); 3225 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE) 3226 ; 3227 } 3228 3229 /* flush all queues disables */ 3230 E1000_WRITE_FLUSH(hw); 3231 msec_delay(2); 3232 } 3233 3234 static int eth_igbvf_link_update(struct e1000_hw *hw) 3235 { 3236 struct e1000_mbx_info *mbx = &hw->mbx; 3237 struct e1000_mac_info *mac = &hw->mac; 3238 int ret_val = E1000_SUCCESS; 3239 3240 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf"); 3241 3242 /* 3243 * We only want to run this if there has been a rst asserted. 3244 * in this case that could mean a link change, device reset, 3245 * or a virtual function reset 3246 */ 3247 3248 /* If we were hit with a reset or timeout drop the link */ 3249 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout) 3250 mac->get_link_status = TRUE; 3251 3252 if (!mac->get_link_status) 3253 goto out; 3254 3255 /* if link status is down no point in checking to see if pf is up */ 3256 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) 3257 goto out; 3258 3259 /* if we passed all the tests above then the link is up and we no 3260 * longer need to check for link */ 3261 mac->get_link_status = FALSE; 3262 3263 out: 3264 return ret_val; 3265 } 3266 3267 3268 static int 3269 igbvf_dev_configure(struct rte_eth_dev *dev) 3270 { 3271 struct rte_eth_conf* conf = &dev->data->dev_conf; 3272 3273 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 3274 dev->data->port_id); 3275 3276 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 3277 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 3278 3279 /* 3280 * VF has no ability to enable/disable HW CRC 3281 * Keep the persistent behavior the same as Host PF 3282 */ 3283 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC 3284 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 3285 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 3286 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 3287 } 3288 #else 3289 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 3290 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 3291 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 3292 } 3293 #endif 3294 3295 return 0; 3296 } 3297 3298 static int 3299 igbvf_dev_start(struct rte_eth_dev *dev) 3300 { 3301 struct e1000_hw *hw = 3302 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3303 struct e1000_adapter *adapter = 3304 E1000_DEV_PRIVATE(dev->data->dev_private); 3305 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3306 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3307 int ret; 3308 uint32_t intr_vector = 0; 3309 3310 PMD_INIT_FUNC_TRACE(); 3311 3312 hw->mac.ops.reset_hw(hw); 3313 adapter->stopped = 0; 3314 3315 /* Set all vfta */ 3316 igbvf_set_vfta_all(dev,1); 3317 3318 eth_igbvf_tx_init(dev); 3319 3320 /* This can fail when allocating mbufs for descriptor rings */ 3321 ret = eth_igbvf_rx_init(dev); 3322 if (ret) { 3323 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 3324 igb_dev_clear_queues(dev); 3325 return ret; 3326 } 3327 3328 /* check and configure queue intr-vector mapping */ 3329 if (rte_intr_cap_multiple(intr_handle) && 3330 dev->data->dev_conf.intr_conf.rxq) { 3331 intr_vector = dev->data->nb_rx_queues; 3332 ret = rte_intr_efd_enable(intr_handle, intr_vector); 3333 if (ret) 3334 return ret; 3335 } 3336 3337 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 3338 intr_handle->intr_vec = 3339 rte_zmalloc("intr_vec", 3340 dev->data->nb_rx_queues * sizeof(int), 0); 3341 if (!intr_handle->intr_vec) { 3342 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 3343 " intr_vec", dev->data->nb_rx_queues); 3344 return -ENOMEM; 3345 } 3346 } 3347 3348 eth_igbvf_configure_msix_intr(dev); 3349 3350 /* enable uio/vfio intr/eventfd mapping */ 3351 rte_intr_enable(intr_handle); 3352 3353 /* resume enabled intr since hw reset */ 3354 igbvf_intr_enable(dev); 3355 3356 return 0; 3357 } 3358 3359 static int 3360 igbvf_dev_stop(struct rte_eth_dev *dev) 3361 { 3362 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3363 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3364 struct e1000_adapter *adapter = 3365 E1000_DEV_PRIVATE(dev->data->dev_private); 3366 3367 if (adapter->stopped) 3368 return 0; 3369 3370 PMD_INIT_FUNC_TRACE(); 3371 3372 igbvf_stop_adapter(dev); 3373 3374 /* 3375 * Clear what we set, but we still keep shadow_vfta to 3376 * restore after device starts 3377 */ 3378 igbvf_set_vfta_all(dev,0); 3379 3380 igb_dev_clear_queues(dev); 3381 3382 /* disable intr eventfd mapping */ 3383 rte_intr_disable(intr_handle); 3384 3385 /* Clean datapath event and queue/vec mapping */ 3386 rte_intr_efd_disable(intr_handle); 3387 if (intr_handle->intr_vec) { 3388 rte_free(intr_handle->intr_vec); 3389 intr_handle->intr_vec = NULL; 3390 } 3391 3392 adapter->stopped = true; 3393 dev->data->dev_started = 0; 3394 3395 return 0; 3396 } 3397 3398 static int 3399 igbvf_dev_close(struct rte_eth_dev *dev) 3400 { 3401 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3402 struct rte_ether_addr addr; 3403 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3404 int ret; 3405 3406 PMD_INIT_FUNC_TRACE(); 3407 3408 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3409 return 0; 3410 3411 e1000_reset_hw(hw); 3412 3413 ret = igbvf_dev_stop(dev); 3414 if (ret != 0) 3415 return ret; 3416 3417 igb_dev_free_queues(dev); 3418 3419 /** 3420 * reprogram the RAR with a zero mac address, 3421 * to ensure that the VF traffic goes to the PF 3422 * after stop, close and detach of the VF. 3423 **/ 3424 3425 memset(&addr, 0, sizeof(addr)); 3426 igbvf_default_mac_addr_set(dev, &addr); 3427 3428 rte_intr_callback_unregister(&pci_dev->intr_handle, 3429 eth_igbvf_interrupt_handler, 3430 (void *)dev); 3431 3432 return 0; 3433 } 3434 3435 static int 3436 igbvf_promiscuous_enable(struct rte_eth_dev *dev) 3437 { 3438 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3439 3440 /* Set both unicast and multicast promisc */ 3441 e1000_promisc_set_vf(hw, e1000_promisc_enabled); 3442 3443 return 0; 3444 } 3445 3446 static int 3447 igbvf_promiscuous_disable(struct rte_eth_dev *dev) 3448 { 3449 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3450 3451 /* If in allmulticast mode leave multicast promisc */ 3452 if (dev->data->all_multicast == 1) 3453 e1000_promisc_set_vf(hw, e1000_promisc_multicast); 3454 else 3455 e1000_promisc_set_vf(hw, e1000_promisc_disabled); 3456 3457 return 0; 3458 } 3459 3460 static int 3461 igbvf_allmulticast_enable(struct rte_eth_dev *dev) 3462 { 3463 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3464 3465 /* In promiscuous mode multicast promisc already set */ 3466 if (dev->data->promiscuous == 0) 3467 e1000_promisc_set_vf(hw, e1000_promisc_multicast); 3468 3469 return 0; 3470 } 3471 3472 static int 3473 igbvf_allmulticast_disable(struct rte_eth_dev *dev) 3474 { 3475 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3476 3477 /* In promiscuous mode leave multicast promisc enabled */ 3478 if (dev->data->promiscuous == 0) 3479 e1000_promisc_set_vf(hw, e1000_promisc_disabled); 3480 3481 return 0; 3482 } 3483 3484 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on) 3485 { 3486 struct e1000_mbx_info *mbx = &hw->mbx; 3487 uint32_t msgbuf[2]; 3488 s32 err; 3489 3490 /* After set vlan, vlan strip will also be enabled in igb driver*/ 3491 msgbuf[0] = E1000_VF_SET_VLAN; 3492 msgbuf[1] = vid; 3493 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */ 3494 if (on) 3495 msgbuf[0] |= E1000_VF_SET_VLAN_ADD; 3496 3497 err = mbx->ops.write_posted(hw, msgbuf, 2, 0); 3498 if (err) 3499 goto mbx_err; 3500 3501 err = mbx->ops.read_posted(hw, msgbuf, 2, 0); 3502 if (err) 3503 goto mbx_err; 3504 3505 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS; 3506 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK)) 3507 err = -EINVAL; 3508 3509 mbx_err: 3510 return err; 3511 } 3512 3513 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on) 3514 { 3515 struct e1000_hw *hw = 3516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3517 struct e1000_vfta * shadow_vfta = 3518 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 3519 int i = 0, j = 0, vfta = 0, mask = 1; 3520 3521 for (i = 0; i < IGB_VFTA_SIZE; i++){ 3522 vfta = shadow_vfta->vfta[i]; 3523 if(vfta){ 3524 mask = 1; 3525 for (j = 0; j < 32; j++){ 3526 if(vfta & mask) 3527 igbvf_set_vfta(hw, 3528 (uint16_t)((i<<5)+j), on); 3529 mask<<=1; 3530 } 3531 } 3532 } 3533 3534 } 3535 3536 static int 3537 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3538 { 3539 struct e1000_hw *hw = 3540 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3541 struct e1000_vfta * shadow_vfta = 3542 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 3543 uint32_t vid_idx = 0; 3544 uint32_t vid_bit = 0; 3545 int ret = 0; 3546 3547 PMD_INIT_FUNC_TRACE(); 3548 3549 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/ 3550 ret = igbvf_set_vfta(hw, vlan_id, !!on); 3551 if(ret){ 3552 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 3553 return ret; 3554 } 3555 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 3556 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 3557 3558 /*Save what we set and retore it after device reset*/ 3559 if (on) 3560 shadow_vfta->vfta[vid_idx] |= vid_bit; 3561 else 3562 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 3563 3564 return 0; 3565 } 3566 3567 static int 3568 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 3569 { 3570 struct e1000_hw *hw = 3571 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3572 3573 /* index is not used by rar_set() */ 3574 hw->mac.ops.rar_set(hw, (void *)addr, 0); 3575 return 0; 3576 } 3577 3578 3579 static int 3580 eth_igb_rss_reta_update(struct rte_eth_dev *dev, 3581 struct rte_eth_rss_reta_entry64 *reta_conf, 3582 uint16_t reta_size) 3583 { 3584 uint8_t i, j, mask; 3585 uint32_t reta, r; 3586 uint16_t idx, shift; 3587 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3588 3589 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3590 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3591 "(%d) doesn't match the number hardware can supported " 3592 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3593 return -EINVAL; 3594 } 3595 3596 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) { 3597 idx = i / RTE_RETA_GROUP_SIZE; 3598 shift = i % RTE_RETA_GROUP_SIZE; 3599 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 3600 IGB_4_BIT_MASK); 3601 if (!mask) 3602 continue; 3603 if (mask == IGB_4_BIT_MASK) 3604 r = 0; 3605 else 3606 r = E1000_READ_REG(hw, E1000_RETA(i >> 2)); 3607 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) { 3608 if (mask & (0x1 << j)) 3609 reta |= reta_conf[idx].reta[shift + j] << 3610 (CHAR_BIT * j); 3611 else 3612 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j)); 3613 } 3614 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3615 } 3616 3617 return 0; 3618 } 3619 3620 static int 3621 eth_igb_rss_reta_query(struct rte_eth_dev *dev, 3622 struct rte_eth_rss_reta_entry64 *reta_conf, 3623 uint16_t reta_size) 3624 { 3625 uint8_t i, j, mask; 3626 uint32_t reta; 3627 uint16_t idx, shift; 3628 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3629 3630 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3631 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3632 "(%d) doesn't match the number hardware can supported " 3633 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3634 return -EINVAL; 3635 } 3636 3637 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) { 3638 idx = i / RTE_RETA_GROUP_SIZE; 3639 shift = i % RTE_RETA_GROUP_SIZE; 3640 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 3641 IGB_4_BIT_MASK); 3642 if (!mask) 3643 continue; 3644 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2)); 3645 for (j = 0; j < IGB_4_BIT_WIDTH; j++) { 3646 if (mask & (0x1 << j)) 3647 reta_conf[idx].reta[shift + j] = 3648 ((reta >> (CHAR_BIT * j)) & 3649 IGB_8_BIT_MASK); 3650 } 3651 } 3652 3653 return 0; 3654 } 3655 3656 int 3657 eth_igb_syn_filter_set(struct rte_eth_dev *dev, 3658 struct rte_eth_syn_filter *filter, 3659 bool add) 3660 { 3661 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3662 struct e1000_filter_info *filter_info = 3663 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3664 uint32_t synqf, rfctl; 3665 3666 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM) 3667 return -EINVAL; 3668 3669 synqf = E1000_READ_REG(hw, E1000_SYNQF(0)); 3670 3671 if (add) { 3672 if (synqf & E1000_SYN_FILTER_ENABLE) 3673 return -EINVAL; 3674 3675 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) & 3676 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE); 3677 3678 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3679 if (filter->hig_pri) 3680 rfctl |= E1000_RFCTL_SYNQFP; 3681 else 3682 rfctl &= ~E1000_RFCTL_SYNQFP; 3683 3684 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3685 } else { 3686 if (!(synqf & E1000_SYN_FILTER_ENABLE)) 3687 return -ENOENT; 3688 synqf = 0; 3689 } 3690 3691 filter_info->syn_info = synqf; 3692 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf); 3693 E1000_WRITE_FLUSH(hw); 3694 return 0; 3695 } 3696 3697 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/ 3698 static inline int 3699 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter, 3700 struct e1000_2tuple_filter_info *filter_info) 3701 { 3702 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM) 3703 return -EINVAL; 3704 if (filter->priority > E1000_2TUPLE_MAX_PRI) 3705 return -EINVAL; /* filter index is out of range. */ 3706 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK) 3707 return -EINVAL; /* flags is invalid. */ 3708 3709 switch (filter->dst_port_mask) { 3710 case UINT16_MAX: 3711 filter_info->dst_port_mask = 0; 3712 filter_info->dst_port = filter->dst_port; 3713 break; 3714 case 0: 3715 filter_info->dst_port_mask = 1; 3716 break; 3717 default: 3718 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 3719 return -EINVAL; 3720 } 3721 3722 switch (filter->proto_mask) { 3723 case UINT8_MAX: 3724 filter_info->proto_mask = 0; 3725 filter_info->proto = filter->proto; 3726 break; 3727 case 0: 3728 filter_info->proto_mask = 1; 3729 break; 3730 default: 3731 PMD_DRV_LOG(ERR, "invalid protocol mask."); 3732 return -EINVAL; 3733 } 3734 3735 filter_info->priority = (uint8_t)filter->priority; 3736 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) 3737 filter_info->tcp_flags = filter->tcp_flags; 3738 else 3739 filter_info->tcp_flags = 0; 3740 3741 return 0; 3742 } 3743 3744 static inline struct e1000_2tuple_filter * 3745 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list, 3746 struct e1000_2tuple_filter_info *key) 3747 { 3748 struct e1000_2tuple_filter *it; 3749 3750 TAILQ_FOREACH(it, filter_list, entries) { 3751 if (memcmp(key, &it->filter_info, 3752 sizeof(struct e1000_2tuple_filter_info)) == 0) { 3753 return it; 3754 } 3755 } 3756 return NULL; 3757 } 3758 3759 /* inject a igb 2tuple filter to HW */ 3760 static inline void 3761 igb_inject_2uple_filter(struct rte_eth_dev *dev, 3762 struct e1000_2tuple_filter *filter) 3763 { 3764 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3765 uint32_t ttqf = E1000_TTQF_DISABLE_MASK; 3766 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP; 3767 int i; 3768 3769 i = filter->index; 3770 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT); 3771 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */ 3772 imir |= E1000_IMIR_PORT_BP; 3773 else 3774 imir &= ~E1000_IMIR_PORT_BP; 3775 3776 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT; 3777 3778 ttqf |= E1000_TTQF_QUEUE_ENABLE; 3779 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT); 3780 ttqf |= (uint32_t)(filter->filter_info.proto & 3781 E1000_TTQF_PROTOCOL_MASK); 3782 if (filter->filter_info.proto_mask == 0) 3783 ttqf &= ~E1000_TTQF_MASK_ENABLE; 3784 3785 /* tcp flags bits setting. */ 3786 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) { 3787 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG) 3788 imir_ext |= E1000_IMIREXT_CTRL_URG; 3789 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG) 3790 imir_ext |= E1000_IMIREXT_CTRL_ACK; 3791 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG) 3792 imir_ext |= E1000_IMIREXT_CTRL_PSH; 3793 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG) 3794 imir_ext |= E1000_IMIREXT_CTRL_RST; 3795 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG) 3796 imir_ext |= E1000_IMIREXT_CTRL_SYN; 3797 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG) 3798 imir_ext |= E1000_IMIREXT_CTRL_FIN; 3799 } else { 3800 imir_ext |= E1000_IMIREXT_CTRL_BP; 3801 } 3802 E1000_WRITE_REG(hw, E1000_IMIR(i), imir); 3803 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf); 3804 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext); 3805 } 3806 3807 /* 3808 * igb_add_2tuple_filter - add a 2tuple filter 3809 * 3810 * @param 3811 * dev: Pointer to struct rte_eth_dev. 3812 * ntuple_filter: ponter to the filter that will be added. 3813 * 3814 * @return 3815 * - On success, zero. 3816 * - On failure, a negative value. 3817 */ 3818 static int 3819 igb_add_2tuple_filter(struct rte_eth_dev *dev, 3820 struct rte_eth_ntuple_filter *ntuple_filter) 3821 { 3822 struct e1000_filter_info *filter_info = 3823 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3824 struct e1000_2tuple_filter *filter; 3825 int i, ret; 3826 3827 filter = rte_zmalloc("e1000_2tuple_filter", 3828 sizeof(struct e1000_2tuple_filter), 0); 3829 if (filter == NULL) 3830 return -ENOMEM; 3831 3832 ret = ntuple_filter_to_2tuple(ntuple_filter, 3833 &filter->filter_info); 3834 if (ret < 0) { 3835 rte_free(filter); 3836 return ret; 3837 } 3838 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list, 3839 &filter->filter_info) != NULL) { 3840 PMD_DRV_LOG(ERR, "filter exists."); 3841 rte_free(filter); 3842 return -EEXIST; 3843 } 3844 filter->queue = ntuple_filter->queue; 3845 3846 /* 3847 * look for an unused 2tuple filter index, 3848 * and insert the filter to list. 3849 */ 3850 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) { 3851 if (!(filter_info->twotuple_mask & (1 << i))) { 3852 filter_info->twotuple_mask |= 1 << i; 3853 filter->index = i; 3854 TAILQ_INSERT_TAIL(&filter_info->twotuple_list, 3855 filter, 3856 entries); 3857 break; 3858 } 3859 } 3860 if (i >= E1000_MAX_TTQF_FILTERS) { 3861 PMD_DRV_LOG(ERR, "2tuple filters are full."); 3862 rte_free(filter); 3863 return -ENOSYS; 3864 } 3865 3866 igb_inject_2uple_filter(dev, filter); 3867 return 0; 3868 } 3869 3870 int 3871 igb_delete_2tuple_filter(struct rte_eth_dev *dev, 3872 struct e1000_2tuple_filter *filter) 3873 { 3874 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3875 struct e1000_filter_info *filter_info = 3876 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3877 3878 filter_info->twotuple_mask &= ~(1 << filter->index); 3879 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries); 3880 rte_free(filter); 3881 3882 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK); 3883 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0); 3884 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0); 3885 return 0; 3886 } 3887 3888 /* 3889 * igb_remove_2tuple_filter - remove a 2tuple filter 3890 * 3891 * @param 3892 * dev: Pointer to struct rte_eth_dev. 3893 * ntuple_filter: ponter to the filter that will be removed. 3894 * 3895 * @return 3896 * - On success, zero. 3897 * - On failure, a negative value. 3898 */ 3899 static int 3900 igb_remove_2tuple_filter(struct rte_eth_dev *dev, 3901 struct rte_eth_ntuple_filter *ntuple_filter) 3902 { 3903 struct e1000_filter_info *filter_info = 3904 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3905 struct e1000_2tuple_filter_info filter_2tuple; 3906 struct e1000_2tuple_filter *filter; 3907 int ret; 3908 3909 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info)); 3910 ret = ntuple_filter_to_2tuple(ntuple_filter, 3911 &filter_2tuple); 3912 if (ret < 0) 3913 return ret; 3914 3915 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list, 3916 &filter_2tuple); 3917 if (filter == NULL) { 3918 PMD_DRV_LOG(ERR, "filter doesn't exist."); 3919 return -ENOENT; 3920 } 3921 3922 igb_delete_2tuple_filter(dev, filter); 3923 3924 return 0; 3925 } 3926 3927 /* inject a igb flex filter to HW */ 3928 static inline void 3929 igb_inject_flex_filter(struct rte_eth_dev *dev, 3930 struct e1000_flex_filter *filter) 3931 { 3932 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3933 uint32_t wufc, queueing; 3934 uint32_t reg_off; 3935 uint8_t i, j = 0; 3936 3937 wufc = E1000_READ_REG(hw, E1000_WUFC); 3938 if (filter->index < E1000_MAX_FHFT) 3939 reg_off = E1000_FHFT(filter->index); 3940 else 3941 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT); 3942 3943 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ | 3944 (E1000_WUFC_FLX0 << filter->index)); 3945 queueing = filter->filter_info.len | 3946 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) | 3947 (filter->filter_info.priority << 3948 E1000_FHFT_QUEUEING_PRIO_SHIFT); 3949 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, 3950 queueing); 3951 3952 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) { 3953 E1000_WRITE_REG(hw, reg_off, 3954 filter->filter_info.dwords[j]); 3955 reg_off += sizeof(uint32_t); 3956 E1000_WRITE_REG(hw, reg_off, 3957 filter->filter_info.dwords[++j]); 3958 reg_off += sizeof(uint32_t); 3959 E1000_WRITE_REG(hw, reg_off, 3960 (uint32_t)filter->filter_info.mask[i]); 3961 reg_off += sizeof(uint32_t) * 2; 3962 ++j; 3963 } 3964 } 3965 3966 static inline struct e1000_flex_filter * 3967 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list, 3968 struct e1000_flex_filter_info *key) 3969 { 3970 struct e1000_flex_filter *it; 3971 3972 TAILQ_FOREACH(it, filter_list, entries) { 3973 if (memcmp(key, &it->filter_info, 3974 sizeof(struct e1000_flex_filter_info)) == 0) 3975 return it; 3976 } 3977 3978 return NULL; 3979 } 3980 3981 /* remove a flex byte filter 3982 * @param 3983 * dev: Pointer to struct rte_eth_dev. 3984 * filter: the pointer of the filter will be removed. 3985 */ 3986 void 3987 igb_remove_flex_filter(struct rte_eth_dev *dev, 3988 struct e1000_flex_filter *filter) 3989 { 3990 struct e1000_filter_info *filter_info = 3991 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3992 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3993 uint32_t wufc, i; 3994 uint32_t reg_off; 3995 3996 wufc = E1000_READ_REG(hw, E1000_WUFC); 3997 if (filter->index < E1000_MAX_FHFT) 3998 reg_off = E1000_FHFT(filter->index); 3999 else 4000 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT); 4001 4002 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++) 4003 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0); 4004 4005 E1000_WRITE_REG(hw, E1000_WUFC, wufc & 4006 (~(E1000_WUFC_FLX0 << filter->index))); 4007 4008 filter_info->flex_mask &= ~(1 << filter->index); 4009 TAILQ_REMOVE(&filter_info->flex_list, filter, entries); 4010 rte_free(filter); 4011 } 4012 4013 int 4014 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev, 4015 struct igb_flex_filter *filter, 4016 bool add) 4017 { 4018 struct e1000_filter_info *filter_info = 4019 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4020 struct e1000_flex_filter *flex_filter, *it; 4021 uint32_t mask; 4022 uint8_t shift, i; 4023 4024 flex_filter = rte_zmalloc("e1000_flex_filter", 4025 sizeof(struct e1000_flex_filter), 0); 4026 if (flex_filter == NULL) 4027 return -ENOMEM; 4028 4029 flex_filter->filter_info.len = filter->len; 4030 flex_filter->filter_info.priority = filter->priority; 4031 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len); 4032 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) { 4033 mask = 0; 4034 /* reverse bits in flex filter's mask*/ 4035 for (shift = 0; shift < CHAR_BIT; shift++) { 4036 if (filter->mask[i] & (0x01 << shift)) 4037 mask |= (0x80 >> shift); 4038 } 4039 flex_filter->filter_info.mask[i] = mask; 4040 } 4041 4042 it = eth_igb_flex_filter_lookup(&filter_info->flex_list, 4043 &flex_filter->filter_info); 4044 if (it == NULL && !add) { 4045 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4046 rte_free(flex_filter); 4047 return -ENOENT; 4048 } 4049 if (it != NULL && add) { 4050 PMD_DRV_LOG(ERR, "filter exists."); 4051 rte_free(flex_filter); 4052 return -EEXIST; 4053 } 4054 4055 if (add) { 4056 flex_filter->queue = filter->queue; 4057 /* 4058 * look for an unused flex filter index 4059 * and insert the filter into the list. 4060 */ 4061 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) { 4062 if (!(filter_info->flex_mask & (1 << i))) { 4063 filter_info->flex_mask |= 1 << i; 4064 flex_filter->index = i; 4065 TAILQ_INSERT_TAIL(&filter_info->flex_list, 4066 flex_filter, 4067 entries); 4068 break; 4069 } 4070 } 4071 if (i >= E1000_MAX_FLEX_FILTERS) { 4072 PMD_DRV_LOG(ERR, "flex filters are full."); 4073 rte_free(flex_filter); 4074 return -ENOSYS; 4075 } 4076 4077 igb_inject_flex_filter(dev, flex_filter); 4078 4079 } else { 4080 igb_remove_flex_filter(dev, it); 4081 rte_free(flex_filter); 4082 } 4083 4084 return 0; 4085 } 4086 4087 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/ 4088 static inline int 4089 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter, 4090 struct e1000_5tuple_filter_info *filter_info) 4091 { 4092 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576) 4093 return -EINVAL; 4094 if (filter->priority > E1000_2TUPLE_MAX_PRI) 4095 return -EINVAL; /* filter index is out of range. */ 4096 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK) 4097 return -EINVAL; /* flags is invalid. */ 4098 4099 switch (filter->dst_ip_mask) { 4100 case UINT32_MAX: 4101 filter_info->dst_ip_mask = 0; 4102 filter_info->dst_ip = filter->dst_ip; 4103 break; 4104 case 0: 4105 filter_info->dst_ip_mask = 1; 4106 break; 4107 default: 4108 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 4109 return -EINVAL; 4110 } 4111 4112 switch (filter->src_ip_mask) { 4113 case UINT32_MAX: 4114 filter_info->src_ip_mask = 0; 4115 filter_info->src_ip = filter->src_ip; 4116 break; 4117 case 0: 4118 filter_info->src_ip_mask = 1; 4119 break; 4120 default: 4121 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 4122 return -EINVAL; 4123 } 4124 4125 switch (filter->dst_port_mask) { 4126 case UINT16_MAX: 4127 filter_info->dst_port_mask = 0; 4128 filter_info->dst_port = filter->dst_port; 4129 break; 4130 case 0: 4131 filter_info->dst_port_mask = 1; 4132 break; 4133 default: 4134 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 4135 return -EINVAL; 4136 } 4137 4138 switch (filter->src_port_mask) { 4139 case UINT16_MAX: 4140 filter_info->src_port_mask = 0; 4141 filter_info->src_port = filter->src_port; 4142 break; 4143 case 0: 4144 filter_info->src_port_mask = 1; 4145 break; 4146 default: 4147 PMD_DRV_LOG(ERR, "invalid src_port mask."); 4148 return -EINVAL; 4149 } 4150 4151 switch (filter->proto_mask) { 4152 case UINT8_MAX: 4153 filter_info->proto_mask = 0; 4154 filter_info->proto = filter->proto; 4155 break; 4156 case 0: 4157 filter_info->proto_mask = 1; 4158 break; 4159 default: 4160 PMD_DRV_LOG(ERR, "invalid protocol mask."); 4161 return -EINVAL; 4162 } 4163 4164 filter_info->priority = (uint8_t)filter->priority; 4165 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) 4166 filter_info->tcp_flags = filter->tcp_flags; 4167 else 4168 filter_info->tcp_flags = 0; 4169 4170 return 0; 4171 } 4172 4173 static inline struct e1000_5tuple_filter * 4174 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list, 4175 struct e1000_5tuple_filter_info *key) 4176 { 4177 struct e1000_5tuple_filter *it; 4178 4179 TAILQ_FOREACH(it, filter_list, entries) { 4180 if (memcmp(key, &it->filter_info, 4181 sizeof(struct e1000_5tuple_filter_info)) == 0) { 4182 return it; 4183 } 4184 } 4185 return NULL; 4186 } 4187 4188 /* inject a igb 5-tuple filter to HW */ 4189 static inline void 4190 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev, 4191 struct e1000_5tuple_filter *filter) 4192 { 4193 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4194 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK; 4195 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP; 4196 uint8_t i; 4197 4198 i = filter->index; 4199 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK; 4200 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */ 4201 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP; 4202 if (filter->filter_info.dst_ip_mask == 0) 4203 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP; 4204 if (filter->filter_info.src_port_mask == 0) 4205 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 4206 if (filter->filter_info.proto_mask == 0) 4207 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; 4208 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) & 4209 E1000_FTQF_QUEUE_MASK; 4210 ftqf |= E1000_FTQF_QUEUE_ENABLE; 4211 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf); 4212 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip); 4213 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip); 4214 4215 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT; 4216 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf); 4217 4218 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT); 4219 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */ 4220 imir |= E1000_IMIR_PORT_BP; 4221 else 4222 imir &= ~E1000_IMIR_PORT_BP; 4223 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT; 4224 4225 /* tcp flags bits setting. */ 4226 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) { 4227 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG) 4228 imir_ext |= E1000_IMIREXT_CTRL_URG; 4229 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG) 4230 imir_ext |= E1000_IMIREXT_CTRL_ACK; 4231 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG) 4232 imir_ext |= E1000_IMIREXT_CTRL_PSH; 4233 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG) 4234 imir_ext |= E1000_IMIREXT_CTRL_RST; 4235 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG) 4236 imir_ext |= E1000_IMIREXT_CTRL_SYN; 4237 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG) 4238 imir_ext |= E1000_IMIREXT_CTRL_FIN; 4239 } else { 4240 imir_ext |= E1000_IMIREXT_CTRL_BP; 4241 } 4242 E1000_WRITE_REG(hw, E1000_IMIR(i), imir); 4243 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext); 4244 } 4245 4246 /* 4247 * igb_add_5tuple_filter_82576 - add a 5tuple filter 4248 * 4249 * @param 4250 * dev: Pointer to struct rte_eth_dev. 4251 * ntuple_filter: ponter to the filter that will be added. 4252 * 4253 * @return 4254 * - On success, zero. 4255 * - On failure, a negative value. 4256 */ 4257 static int 4258 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev, 4259 struct rte_eth_ntuple_filter *ntuple_filter) 4260 { 4261 struct e1000_filter_info *filter_info = 4262 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4263 struct e1000_5tuple_filter *filter; 4264 uint8_t i; 4265 int ret; 4266 4267 filter = rte_zmalloc("e1000_5tuple_filter", 4268 sizeof(struct e1000_5tuple_filter), 0); 4269 if (filter == NULL) 4270 return -ENOMEM; 4271 4272 ret = ntuple_filter_to_5tuple_82576(ntuple_filter, 4273 &filter->filter_info); 4274 if (ret < 0) { 4275 rte_free(filter); 4276 return ret; 4277 } 4278 4279 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list, 4280 &filter->filter_info) != NULL) { 4281 PMD_DRV_LOG(ERR, "filter exists."); 4282 rte_free(filter); 4283 return -EEXIST; 4284 } 4285 filter->queue = ntuple_filter->queue; 4286 4287 /* 4288 * look for an unused 5tuple filter index, 4289 * and insert the filter to list. 4290 */ 4291 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) { 4292 if (!(filter_info->fivetuple_mask & (1 << i))) { 4293 filter_info->fivetuple_mask |= 1 << i; 4294 filter->index = i; 4295 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 4296 filter, 4297 entries); 4298 break; 4299 } 4300 } 4301 if (i >= E1000_MAX_FTQF_FILTERS) { 4302 PMD_DRV_LOG(ERR, "5tuple filters are full."); 4303 rte_free(filter); 4304 return -ENOSYS; 4305 } 4306 4307 igb_inject_5tuple_filter_82576(dev, filter); 4308 return 0; 4309 } 4310 4311 int 4312 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev, 4313 struct e1000_5tuple_filter *filter) 4314 { 4315 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4316 struct e1000_filter_info *filter_info = 4317 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4318 4319 filter_info->fivetuple_mask &= ~(1 << filter->index); 4320 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 4321 rte_free(filter); 4322 4323 E1000_WRITE_REG(hw, E1000_FTQF(filter->index), 4324 E1000_FTQF_VF_BP | E1000_FTQF_MASK); 4325 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0); 4326 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0); 4327 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0); 4328 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0); 4329 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0); 4330 return 0; 4331 } 4332 4333 /* 4334 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter 4335 * 4336 * @param 4337 * dev: Pointer to struct rte_eth_dev. 4338 * ntuple_filter: ponter to the filter that will be removed. 4339 * 4340 * @return 4341 * - On success, zero. 4342 * - On failure, a negative value. 4343 */ 4344 static int 4345 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev, 4346 struct rte_eth_ntuple_filter *ntuple_filter) 4347 { 4348 struct e1000_filter_info *filter_info = 4349 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4350 struct e1000_5tuple_filter_info filter_5tuple; 4351 struct e1000_5tuple_filter *filter; 4352 int ret; 4353 4354 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info)); 4355 ret = ntuple_filter_to_5tuple_82576(ntuple_filter, 4356 &filter_5tuple); 4357 if (ret < 0) 4358 return ret; 4359 4360 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list, 4361 &filter_5tuple); 4362 if (filter == NULL) { 4363 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4364 return -ENOENT; 4365 } 4366 4367 igb_delete_5tuple_filter_82576(dev, filter); 4368 4369 return 0; 4370 } 4371 4372 static int 4373 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 4374 { 4375 uint32_t rctl; 4376 struct e1000_hw *hw; 4377 struct rte_eth_dev_info dev_info; 4378 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD; 4379 int ret; 4380 4381 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4382 4383 #ifdef RTE_LIBRTE_82571_SUPPORT 4384 /* XXX: not bigger than max_rx_pktlen */ 4385 if (hw->mac.type == e1000_82571) 4386 return -ENOTSUP; 4387 #endif 4388 ret = eth_igb_infos_get(dev, &dev_info); 4389 if (ret != 0) 4390 return ret; 4391 4392 /* check that mtu is within the allowed range */ 4393 if (mtu < RTE_ETHER_MIN_MTU || 4394 frame_size > dev_info.max_rx_pktlen) 4395 return -EINVAL; 4396 4397 /* refuse mtu that requires the support of scattered packets when this 4398 * feature has not been enabled before. */ 4399 if (!dev->data->scattered_rx && 4400 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) 4401 return -EINVAL; 4402 4403 rctl = E1000_READ_REG(hw, E1000_RCTL); 4404 4405 /* switch to jumbo mode if needed */ 4406 if (frame_size > E1000_ETH_MAX_LEN) { 4407 dev->data->dev_conf.rxmode.offloads |= 4408 DEV_RX_OFFLOAD_JUMBO_FRAME; 4409 rctl |= E1000_RCTL_LPE; 4410 } else { 4411 dev->data->dev_conf.rxmode.offloads &= 4412 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 4413 rctl &= ~E1000_RCTL_LPE; 4414 } 4415 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4416 4417 /* update max frame size */ 4418 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 4419 4420 E1000_WRITE_REG(hw, E1000_RLPML, 4421 dev->data->dev_conf.rxmode.max_rx_pkt_len); 4422 4423 return 0; 4424 } 4425 4426 /* 4427 * igb_add_del_ntuple_filter - add or delete a ntuple filter 4428 * 4429 * @param 4430 * dev: Pointer to struct rte_eth_dev. 4431 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 4432 * add: if true, add filter, if false, remove filter 4433 * 4434 * @return 4435 * - On success, zero. 4436 * - On failure, a negative value. 4437 */ 4438 int 4439 igb_add_del_ntuple_filter(struct rte_eth_dev *dev, 4440 struct rte_eth_ntuple_filter *ntuple_filter, 4441 bool add) 4442 { 4443 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4444 int ret; 4445 4446 switch (ntuple_filter->flags) { 4447 case RTE_5TUPLE_FLAGS: 4448 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG): 4449 if (hw->mac.type != e1000_82576) 4450 return -ENOTSUP; 4451 if (add) 4452 ret = igb_add_5tuple_filter_82576(dev, 4453 ntuple_filter); 4454 else 4455 ret = igb_remove_5tuple_filter_82576(dev, 4456 ntuple_filter); 4457 break; 4458 case RTE_2TUPLE_FLAGS: 4459 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG): 4460 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 && 4461 hw->mac.type != e1000_i210 && 4462 hw->mac.type != e1000_i211) 4463 return -ENOTSUP; 4464 if (add) 4465 ret = igb_add_2tuple_filter(dev, ntuple_filter); 4466 else 4467 ret = igb_remove_2tuple_filter(dev, ntuple_filter); 4468 break; 4469 default: 4470 ret = -EINVAL; 4471 break; 4472 } 4473 4474 return ret; 4475 } 4476 4477 static inline int 4478 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info, 4479 uint16_t ethertype) 4480 { 4481 int i; 4482 4483 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) { 4484 if (filter_info->ethertype_filters[i].ethertype == ethertype && 4485 (filter_info->ethertype_mask & (1 << i))) 4486 return i; 4487 } 4488 return -1; 4489 } 4490 4491 static inline int 4492 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info, 4493 uint16_t ethertype, uint32_t etqf) 4494 { 4495 int i; 4496 4497 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) { 4498 if (!(filter_info->ethertype_mask & (1 << i))) { 4499 filter_info->ethertype_mask |= 1 << i; 4500 filter_info->ethertype_filters[i].ethertype = ethertype; 4501 filter_info->ethertype_filters[i].etqf = etqf; 4502 return i; 4503 } 4504 } 4505 return -1; 4506 } 4507 4508 int 4509 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info, 4510 uint8_t idx) 4511 { 4512 if (idx >= E1000_MAX_ETQF_FILTERS) 4513 return -1; 4514 filter_info->ethertype_mask &= ~(1 << idx); 4515 filter_info->ethertype_filters[idx].ethertype = 0; 4516 filter_info->ethertype_filters[idx].etqf = 0; 4517 return idx; 4518 } 4519 4520 4521 int 4522 igb_add_del_ethertype_filter(struct rte_eth_dev *dev, 4523 struct rte_eth_ethertype_filter *filter, 4524 bool add) 4525 { 4526 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4527 struct e1000_filter_info *filter_info = 4528 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4529 uint32_t etqf = 0; 4530 int ret; 4531 4532 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 4533 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 4534 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 4535 " ethertype filter.", filter->ether_type); 4536 return -EINVAL; 4537 } 4538 4539 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 4540 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 4541 return -EINVAL; 4542 } 4543 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 4544 PMD_DRV_LOG(ERR, "drop option is unsupported."); 4545 return -EINVAL; 4546 } 4547 4548 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type); 4549 if (ret >= 0 && add) { 4550 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 4551 filter->ether_type); 4552 return -EEXIST; 4553 } 4554 if (ret < 0 && !add) { 4555 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 4556 filter->ether_type); 4557 return -ENOENT; 4558 } 4559 4560 if (add) { 4561 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE; 4562 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE); 4563 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT; 4564 ret = igb_ethertype_filter_insert(filter_info, 4565 filter->ether_type, etqf); 4566 if (ret < 0) { 4567 PMD_DRV_LOG(ERR, "ethertype filters are full."); 4568 return -ENOSYS; 4569 } 4570 } else { 4571 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret); 4572 if (ret < 0) 4573 return -ENOSYS; 4574 } 4575 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf); 4576 E1000_WRITE_FLUSH(hw); 4577 4578 return 0; 4579 } 4580 4581 static int 4582 eth_igb_filter_ctrl(struct rte_eth_dev *dev __rte_unused, 4583 enum rte_filter_type filter_type, 4584 enum rte_filter_op filter_op, 4585 void *arg) 4586 { 4587 int ret = 0; 4588 4589 switch (filter_type) { 4590 case RTE_ETH_FILTER_GENERIC: 4591 if (filter_op != RTE_ETH_FILTER_GET) 4592 return -EINVAL; 4593 *(const void **)arg = &igb_flow_ops; 4594 break; 4595 default: 4596 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 4597 filter_type); 4598 break; 4599 } 4600 4601 return ret; 4602 } 4603 4604 static int 4605 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev, 4606 struct rte_ether_addr *mc_addr_set, 4607 uint32_t nb_mc_addr) 4608 { 4609 struct e1000_hw *hw; 4610 4611 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4612 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr); 4613 return 0; 4614 } 4615 4616 static uint64_t 4617 igb_read_systime_cyclecounter(struct rte_eth_dev *dev) 4618 { 4619 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4620 uint64_t systime_cycles; 4621 4622 switch (hw->mac.type) { 4623 case e1000_i210: 4624 case e1000_i211: 4625 /* 4626 * Need to read System Time Residue Register to be able 4627 * to read the other two registers. 4628 */ 4629 E1000_READ_REG(hw, E1000_SYSTIMR); 4630 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 4631 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML); 4632 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH) 4633 * NSEC_PER_SEC; 4634 break; 4635 case e1000_82580: 4636 case e1000_i350: 4637 case e1000_i354: 4638 /* 4639 * Need to read System Time Residue Register to be able 4640 * to read the other two registers. 4641 */ 4642 E1000_READ_REG(hw, E1000_SYSTIMR); 4643 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML); 4644 /* Only the 8 LSB are valid. */ 4645 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH) 4646 & 0xff) << 32; 4647 break; 4648 default: 4649 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML); 4650 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH) 4651 << 32; 4652 break; 4653 } 4654 4655 return systime_cycles; 4656 } 4657 4658 static uint64_t 4659 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4660 { 4661 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4662 uint64_t rx_tstamp_cycles; 4663 4664 switch (hw->mac.type) { 4665 case e1000_i210: 4666 case e1000_i211: 4667 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 4668 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL); 4669 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH) 4670 * NSEC_PER_SEC; 4671 break; 4672 case e1000_82580: 4673 case e1000_i350: 4674 case e1000_i354: 4675 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL); 4676 /* Only the 8 LSB are valid. */ 4677 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH) 4678 & 0xff) << 32; 4679 break; 4680 default: 4681 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL); 4682 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH) 4683 << 32; 4684 break; 4685 } 4686 4687 return rx_tstamp_cycles; 4688 } 4689 4690 static uint64_t 4691 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4692 { 4693 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4694 uint64_t tx_tstamp_cycles; 4695 4696 switch (hw->mac.type) { 4697 case e1000_i210: 4698 case e1000_i211: 4699 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 4700 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL); 4701 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH) 4702 * NSEC_PER_SEC; 4703 break; 4704 case e1000_82580: 4705 case e1000_i350: 4706 case e1000_i354: 4707 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL); 4708 /* Only the 8 LSB are valid. */ 4709 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH) 4710 & 0xff) << 32; 4711 break; 4712 default: 4713 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL); 4714 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH) 4715 << 32; 4716 break; 4717 } 4718 4719 return tx_tstamp_cycles; 4720 } 4721 4722 static void 4723 igb_start_timecounters(struct rte_eth_dev *dev) 4724 { 4725 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4726 struct e1000_adapter *adapter = dev->data->dev_private; 4727 uint32_t incval = 1; 4728 uint32_t shift = 0; 4729 uint64_t mask = E1000_CYCLECOUNTER_MASK; 4730 4731 switch (hw->mac.type) { 4732 case e1000_82580: 4733 case e1000_i350: 4734 case e1000_i354: 4735 /* 32 LSB bits + 8 MSB bits = 40 bits */ 4736 mask = (1ULL << 40) - 1; 4737 /* fall-through */ 4738 case e1000_i210: 4739 case e1000_i211: 4740 /* 4741 * Start incrementing the register 4742 * used to timestamp PTP packets. 4743 */ 4744 E1000_WRITE_REG(hw, E1000_TIMINCA, incval); 4745 break; 4746 case e1000_82576: 4747 incval = E1000_INCVALUE_82576; 4748 shift = IGB_82576_TSYNC_SHIFT; 4749 E1000_WRITE_REG(hw, E1000_TIMINCA, 4750 E1000_INCPERIOD_82576 | incval); 4751 break; 4752 default: 4753 /* Not supported */ 4754 return; 4755 } 4756 4757 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 4758 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4759 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4760 4761 adapter->systime_tc.cc_mask = mask; 4762 adapter->systime_tc.cc_shift = shift; 4763 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 4764 4765 adapter->rx_tstamp_tc.cc_mask = mask; 4766 adapter->rx_tstamp_tc.cc_shift = shift; 4767 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4768 4769 adapter->tx_tstamp_tc.cc_mask = mask; 4770 adapter->tx_tstamp_tc.cc_shift = shift; 4771 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4772 } 4773 4774 static int 4775 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 4776 { 4777 struct e1000_adapter *adapter = dev->data->dev_private; 4778 4779 adapter->systime_tc.nsec += delta; 4780 adapter->rx_tstamp_tc.nsec += delta; 4781 adapter->tx_tstamp_tc.nsec += delta; 4782 4783 return 0; 4784 } 4785 4786 static int 4787 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 4788 { 4789 uint64_t ns; 4790 struct e1000_adapter *adapter = dev->data->dev_private; 4791 4792 ns = rte_timespec_to_ns(ts); 4793 4794 /* Set the timecounters to a new value. */ 4795 adapter->systime_tc.nsec = ns; 4796 adapter->rx_tstamp_tc.nsec = ns; 4797 adapter->tx_tstamp_tc.nsec = ns; 4798 4799 return 0; 4800 } 4801 4802 static int 4803 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 4804 { 4805 uint64_t ns, systime_cycles; 4806 struct e1000_adapter *adapter = dev->data->dev_private; 4807 4808 systime_cycles = igb_read_systime_cyclecounter(dev); 4809 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 4810 *ts = rte_ns_to_timespec(ns); 4811 4812 return 0; 4813 } 4814 4815 static int 4816 igb_timesync_enable(struct rte_eth_dev *dev) 4817 { 4818 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4819 uint32_t tsync_ctl; 4820 uint32_t tsauxc; 4821 4822 /* Stop the timesync system time. */ 4823 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0); 4824 /* Reset the timesync system time value. */ 4825 switch (hw->mac.type) { 4826 case e1000_82580: 4827 case e1000_i350: 4828 case e1000_i354: 4829 case e1000_i210: 4830 case e1000_i211: 4831 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0); 4832 /* fall-through */ 4833 case e1000_82576: 4834 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0); 4835 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0); 4836 break; 4837 default: 4838 /* Not supported. */ 4839 return -ENOTSUP; 4840 } 4841 4842 /* Enable system time for it isn't on by default. */ 4843 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC); 4844 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME; 4845 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc); 4846 4847 igb_start_timecounters(dev); 4848 4849 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4850 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 4851 (RTE_ETHER_TYPE_1588 | 4852 E1000_ETQF_FILTER_ENABLE | 4853 E1000_ETQF_1588)); 4854 4855 /* Enable timestamping of received PTP packets. */ 4856 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); 4857 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED; 4858 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl); 4859 4860 /* Enable Timestamping of transmitted PTP packets. */ 4861 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); 4862 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED; 4863 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl); 4864 4865 return 0; 4866 } 4867 4868 static int 4869 igb_timesync_disable(struct rte_eth_dev *dev) 4870 { 4871 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4872 uint32_t tsync_ctl; 4873 4874 /* Disable timestamping of transmitted PTP packets. */ 4875 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); 4876 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED; 4877 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl); 4878 4879 /* Disable timestamping of received PTP packets. */ 4880 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); 4881 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED; 4882 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl); 4883 4884 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4885 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0); 4886 4887 /* Stop incrementating the System Time registers. */ 4888 E1000_WRITE_REG(hw, E1000_TIMINCA, 0); 4889 4890 return 0; 4891 } 4892 4893 static int 4894 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 4895 struct timespec *timestamp, 4896 uint32_t flags __rte_unused) 4897 { 4898 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4899 struct e1000_adapter *adapter = dev->data->dev_private; 4900 uint32_t tsync_rxctl; 4901 uint64_t rx_tstamp_cycles; 4902 uint64_t ns; 4903 4904 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); 4905 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0) 4906 return -EINVAL; 4907 4908 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev); 4909 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 4910 *timestamp = rte_ns_to_timespec(ns); 4911 4912 return 0; 4913 } 4914 4915 static int 4916 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 4917 struct timespec *timestamp) 4918 { 4919 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4920 struct e1000_adapter *adapter = dev->data->dev_private; 4921 uint32_t tsync_txctl; 4922 uint64_t tx_tstamp_cycles; 4923 uint64_t ns; 4924 4925 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); 4926 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0) 4927 return -EINVAL; 4928 4929 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev); 4930 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 4931 *timestamp = rte_ns_to_timespec(ns); 4932 4933 return 0; 4934 } 4935 4936 static int 4937 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused) 4938 { 4939 int count = 0; 4940 int g_ind = 0; 4941 const struct reg_info *reg_group; 4942 4943 while ((reg_group = igb_regs[g_ind++])) 4944 count += igb_reg_group_count(reg_group); 4945 4946 return count; 4947 } 4948 4949 static int 4950 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 4951 { 4952 int count = 0; 4953 int g_ind = 0; 4954 const struct reg_info *reg_group; 4955 4956 while ((reg_group = igbvf_regs[g_ind++])) 4957 count += igb_reg_group_count(reg_group); 4958 4959 return count; 4960 } 4961 4962 static int 4963 eth_igb_get_regs(struct rte_eth_dev *dev, 4964 struct rte_dev_reg_info *regs) 4965 { 4966 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4967 uint32_t *data = regs->data; 4968 int g_ind = 0; 4969 int count = 0; 4970 const struct reg_info *reg_group; 4971 4972 if (data == NULL) { 4973 regs->length = eth_igb_get_reg_length(dev); 4974 regs->width = sizeof(uint32_t); 4975 return 0; 4976 } 4977 4978 /* Support only full register dump */ 4979 if ((regs->length == 0) || 4980 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) { 4981 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 4982 hw->device_id; 4983 while ((reg_group = igb_regs[g_ind++])) 4984 count += igb_read_regs_group(dev, &data[count], 4985 reg_group); 4986 return 0; 4987 } 4988 4989 return -ENOTSUP; 4990 } 4991 4992 static int 4993 igbvf_get_regs(struct rte_eth_dev *dev, 4994 struct rte_dev_reg_info *regs) 4995 { 4996 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4997 uint32_t *data = regs->data; 4998 int g_ind = 0; 4999 int count = 0; 5000 const struct reg_info *reg_group; 5001 5002 if (data == NULL) { 5003 regs->length = igbvf_get_reg_length(dev); 5004 regs->width = sizeof(uint32_t); 5005 return 0; 5006 } 5007 5008 /* Support only full register dump */ 5009 if ((regs->length == 0) || 5010 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) { 5011 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 5012 hw->device_id; 5013 while ((reg_group = igbvf_regs[g_ind++])) 5014 count += igb_read_regs_group(dev, &data[count], 5015 reg_group); 5016 return 0; 5017 } 5018 5019 return -ENOTSUP; 5020 } 5021 5022 static int 5023 eth_igb_get_eeprom_length(struct rte_eth_dev *dev) 5024 { 5025 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5026 5027 /* Return unit is byte count */ 5028 return hw->nvm.word_size * 2; 5029 } 5030 5031 static int 5032 eth_igb_get_eeprom(struct rte_eth_dev *dev, 5033 struct rte_dev_eeprom_info *in_eeprom) 5034 { 5035 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5036 struct e1000_nvm_info *nvm = &hw->nvm; 5037 uint16_t *data = in_eeprom->data; 5038 int first, length; 5039 5040 first = in_eeprom->offset >> 1; 5041 length = in_eeprom->length >> 1; 5042 if ((first >= hw->nvm.word_size) || 5043 ((first + length) >= hw->nvm.word_size)) 5044 return -EINVAL; 5045 5046 in_eeprom->magic = hw->vendor_id | 5047 ((uint32_t)hw->device_id << 16); 5048 5049 if ((nvm->ops.read) == NULL) 5050 return -ENOTSUP; 5051 5052 return nvm->ops.read(hw, first, length, data); 5053 } 5054 5055 static int 5056 eth_igb_set_eeprom(struct rte_eth_dev *dev, 5057 struct rte_dev_eeprom_info *in_eeprom) 5058 { 5059 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5060 struct e1000_nvm_info *nvm = &hw->nvm; 5061 uint16_t *data = in_eeprom->data; 5062 int first, length; 5063 5064 first = in_eeprom->offset >> 1; 5065 length = in_eeprom->length >> 1; 5066 if ((first >= hw->nvm.word_size) || 5067 ((first + length) >= hw->nvm.word_size)) 5068 return -EINVAL; 5069 5070 in_eeprom->magic = (uint32_t)hw->vendor_id | 5071 ((uint32_t)hw->device_id << 16); 5072 5073 if ((nvm->ops.write) == NULL) 5074 return -ENOTSUP; 5075 return nvm->ops.write(hw, first, length, data); 5076 } 5077 5078 static int 5079 eth_igb_get_module_info(struct rte_eth_dev *dev, 5080 struct rte_eth_dev_module_info *modinfo) 5081 { 5082 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5083 5084 uint32_t status = 0; 5085 uint16_t sff8472_rev, addr_mode; 5086 bool page_swap = false; 5087 5088 if (hw->phy.media_type == e1000_media_type_copper || 5089 hw->phy.media_type == e1000_media_type_unknown) 5090 return -EOPNOTSUPP; 5091 5092 /* Check whether we support SFF-8472 or not */ 5093 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 5094 if (status) 5095 return -EIO; 5096 5097 /* addressing mode is not supported */ 5098 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 5099 if (status) 5100 return -EIO; 5101 5102 /* addressing mode is not supported */ 5103 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 5104 PMD_DRV_LOG(ERR, 5105 "Address change required to access page 0xA2, " 5106 "but not supported. Please report the module " 5107 "type to the driver maintainers.\n"); 5108 page_swap = true; 5109 } 5110 5111 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 5112 /* We have an SFP, but it does not support SFF-8472 */ 5113 modinfo->type = RTE_ETH_MODULE_SFF_8079; 5114 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 5115 } else { 5116 /* We have an SFP which supports a revision of SFF-8472 */ 5117 modinfo->type = RTE_ETH_MODULE_SFF_8472; 5118 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 5119 } 5120 5121 return 0; 5122 } 5123 5124 static int 5125 eth_igb_get_module_eeprom(struct rte_eth_dev *dev, 5126 struct rte_dev_eeprom_info *info) 5127 { 5128 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5129 5130 uint32_t status = 0; 5131 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1]; 5132 u16 first_word, last_word; 5133 int i = 0; 5134 5135 if (info->length == 0) 5136 return -EINVAL; 5137 5138 first_word = info->offset >> 1; 5139 last_word = (info->offset + info->length - 1) >> 1; 5140 5141 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 5142 for (i = 0; i < last_word - first_word + 1; i++) { 5143 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2, 5144 &dataword[i]); 5145 if (status) { 5146 /* Error occurred while reading module */ 5147 return -EIO; 5148 } 5149 5150 dataword[i] = rte_be_to_cpu_16(dataword[i]); 5151 } 5152 5153 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length); 5154 5155 return 0; 5156 } 5157 5158 static int 5159 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5160 { 5161 struct e1000_hw *hw = 5162 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5163 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5164 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5165 uint32_t vec = E1000_MISC_VEC_ID; 5166 5167 if (rte_intr_allow_others(intr_handle)) 5168 vec = E1000_RX_VEC_START; 5169 5170 uint32_t mask = 1 << (queue_id + vec); 5171 5172 E1000_WRITE_REG(hw, E1000_EIMC, mask); 5173 E1000_WRITE_FLUSH(hw); 5174 5175 return 0; 5176 } 5177 5178 static int 5179 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5180 { 5181 struct e1000_hw *hw = 5182 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5183 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5184 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5185 uint32_t vec = E1000_MISC_VEC_ID; 5186 5187 if (rte_intr_allow_others(intr_handle)) 5188 vec = E1000_RX_VEC_START; 5189 5190 uint32_t mask = 1 << (queue_id + vec); 5191 uint32_t regval; 5192 5193 regval = E1000_READ_REG(hw, E1000_EIMS); 5194 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); 5195 E1000_WRITE_FLUSH(hw); 5196 5197 rte_intr_ack(intr_handle); 5198 5199 return 0; 5200 } 5201 5202 static void 5203 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector, 5204 uint8_t index, uint8_t offset) 5205 { 5206 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 5207 5208 /* clear bits */ 5209 val &= ~((uint32_t)0xFF << offset); 5210 5211 /* write vector and valid bit */ 5212 val |= (msix_vector | E1000_IVAR_VALID) << offset; 5213 5214 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val); 5215 } 5216 5217 static void 5218 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction, 5219 uint8_t queue, uint8_t msix_vector) 5220 { 5221 uint32_t tmp = 0; 5222 5223 if (hw->mac.type == e1000_82575) { 5224 if (direction == 0) 5225 tmp = E1000_EICR_RX_QUEUE0 << queue; 5226 else if (direction == 1) 5227 tmp = E1000_EICR_TX_QUEUE0 << queue; 5228 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp); 5229 } else if (hw->mac.type == e1000_82576) { 5230 if ((direction == 0) || (direction == 1)) 5231 eth_igb_write_ivar(hw, msix_vector, queue & 0x7, 5232 ((queue & 0x8) << 1) + 5233 8 * direction); 5234 } else if ((hw->mac.type == e1000_82580) || 5235 (hw->mac.type == e1000_i350) || 5236 (hw->mac.type == e1000_i354) || 5237 (hw->mac.type == e1000_i210) || 5238 (hw->mac.type == e1000_i211)) { 5239 if ((direction == 0) || (direction == 1)) 5240 eth_igb_write_ivar(hw, msix_vector, 5241 queue >> 1, 5242 ((queue & 0x1) << 4) + 5243 8 * direction); 5244 } 5245 } 5246 5247 /* Sets up the hardware to generate MSI-X interrupts properly 5248 * @hw 5249 * board private structure 5250 */ 5251 static void 5252 eth_igb_configure_msix_intr(struct rte_eth_dev *dev) 5253 { 5254 int queue_id; 5255 uint32_t tmpval, regval, intr_mask; 5256 struct e1000_hw *hw = 5257 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5258 uint32_t vec = E1000_MISC_VEC_ID; 5259 uint32_t base = E1000_MISC_VEC_ID; 5260 uint32_t misc_shift = 0; 5261 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5262 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5263 5264 /* won't configure msix register if no mapping is done 5265 * between intr vector and event fd 5266 */ 5267 if (!rte_intr_dp_is_en(intr_handle)) 5268 return; 5269 5270 if (rte_intr_allow_others(intr_handle)) { 5271 vec = base = E1000_RX_VEC_START; 5272 misc_shift = 1; 5273 } 5274 5275 /* set interrupt vector for other causes */ 5276 if (hw->mac.type == e1000_82575) { 5277 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT); 5278 /* enable MSI-X PBA support */ 5279 tmpval |= E1000_CTRL_EXT_PBA_CLR; 5280 5281 /* Auto-Mask interrupts upon ICR read */ 5282 tmpval |= E1000_CTRL_EXT_EIAME; 5283 tmpval |= E1000_CTRL_EXT_IRCA; 5284 5285 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval); 5286 5287 /* enable msix_other interrupt */ 5288 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER); 5289 regval = E1000_READ_REG(hw, E1000_EIAC); 5290 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER); 5291 regval = E1000_READ_REG(hw, E1000_EIAM); 5292 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER); 5293 } else if ((hw->mac.type == e1000_82576) || 5294 (hw->mac.type == e1000_82580) || 5295 (hw->mac.type == e1000_i350) || 5296 (hw->mac.type == e1000_i354) || 5297 (hw->mac.type == e1000_i210) || 5298 (hw->mac.type == e1000_i211)) { 5299 /* turn on MSI-X capability first */ 5300 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE | 5301 E1000_GPIE_PBA | E1000_GPIE_EIAME | 5302 E1000_GPIE_NSICR); 5303 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << 5304 misc_shift; 5305 5306 if (dev->data->dev_conf.intr_conf.lsc != 0) 5307 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC); 5308 5309 regval = E1000_READ_REG(hw, E1000_EIAC); 5310 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask); 5311 5312 /* enable msix_other interrupt */ 5313 regval = E1000_READ_REG(hw, E1000_EIMS); 5314 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); 5315 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8; 5316 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval); 5317 } 5318 5319 /* use EIAM to auto-mask when MSI-X interrupt 5320 * is asserted, this saves a register write for every interrupt 5321 */ 5322 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << 5323 misc_shift; 5324 5325 if (dev->data->dev_conf.intr_conf.lsc != 0) 5326 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC); 5327 5328 regval = E1000_READ_REG(hw, E1000_EIAM); 5329 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask); 5330 5331 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) { 5332 eth_igb_assign_msix_vector(hw, 0, queue_id, vec); 5333 intr_handle->intr_vec[queue_id] = vec; 5334 if (vec < base + intr_handle->nb_efd - 1) 5335 vec++; 5336 } 5337 5338 E1000_WRITE_FLUSH(hw); 5339 } 5340 5341 /* restore n-tuple filter */ 5342 static inline void 5343 igb_ntuple_filter_restore(struct rte_eth_dev *dev) 5344 { 5345 struct e1000_filter_info *filter_info = 5346 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5347 struct e1000_5tuple_filter *p_5tuple; 5348 struct e1000_2tuple_filter *p_2tuple; 5349 5350 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) { 5351 igb_inject_5tuple_filter_82576(dev, p_5tuple); 5352 } 5353 5354 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) { 5355 igb_inject_2uple_filter(dev, p_2tuple); 5356 } 5357 } 5358 5359 /* restore SYN filter */ 5360 static inline void 5361 igb_syn_filter_restore(struct rte_eth_dev *dev) 5362 { 5363 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5364 struct e1000_filter_info *filter_info = 5365 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5366 uint32_t synqf; 5367 5368 synqf = filter_info->syn_info; 5369 5370 if (synqf & E1000_SYN_FILTER_ENABLE) { 5371 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf); 5372 E1000_WRITE_FLUSH(hw); 5373 } 5374 } 5375 5376 /* restore ethernet type filter */ 5377 static inline void 5378 igb_ethertype_filter_restore(struct rte_eth_dev *dev) 5379 { 5380 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5381 struct e1000_filter_info *filter_info = 5382 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5383 int i; 5384 5385 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) { 5386 if (filter_info->ethertype_mask & (1 << i)) { 5387 E1000_WRITE_REG(hw, E1000_ETQF(i), 5388 filter_info->ethertype_filters[i].etqf); 5389 E1000_WRITE_FLUSH(hw); 5390 } 5391 } 5392 } 5393 5394 /* restore flex byte filter */ 5395 static inline void 5396 igb_flex_filter_restore(struct rte_eth_dev *dev) 5397 { 5398 struct e1000_filter_info *filter_info = 5399 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5400 struct e1000_flex_filter *flex_filter; 5401 5402 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) { 5403 igb_inject_flex_filter(dev, flex_filter); 5404 } 5405 } 5406 5407 /* restore rss filter */ 5408 static inline void 5409 igb_rss_filter_restore(struct rte_eth_dev *dev) 5410 { 5411 struct e1000_filter_info *filter_info = 5412 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5413 5414 if (filter_info->rss_info.conf.queue_num) 5415 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE); 5416 } 5417 5418 /* restore all types filter */ 5419 static int 5420 igb_filter_restore(struct rte_eth_dev *dev) 5421 { 5422 igb_ntuple_filter_restore(dev); 5423 igb_ethertype_filter_restore(dev); 5424 igb_syn_filter_restore(dev); 5425 igb_flex_filter_restore(dev); 5426 igb_rss_filter_restore(dev); 5427 5428 return 0; 5429 } 5430 5431 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd); 5432 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map); 5433 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci"); 5434 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd); 5435 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map); 5436 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci"); 5437 5438 /* see e1000_logs.c */ 5439 RTE_INIT(e1000_init_log) 5440 { 5441 e1000_igb_init_log(); 5442 } 5443