1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #include "cn9k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
8
9 #define CN9K_DUAL_WS_NB_WS 2
10 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
11
12 #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
13 deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
14
15 #define CN9K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
16 enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
17
18 static int
cn9k_sso_hws_link(void * arg,void * port,uint16_t * map,uint16_t nb_link)19 cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
20 {
21 struct cnxk_sso_evdev *dev = arg;
22 struct cn9k_sso_hws_dual *dws;
23 struct cn9k_sso_hws *ws;
24 int rc;
25
26 if (dev->dual_ws) {
27 dws = port;
28 rc = roc_sso_hws_link(&dev->sso,
29 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,
30 nb_link);
31 rc |= roc_sso_hws_link(&dev->sso,
32 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
33 map, nb_link);
34 } else {
35 ws = port;
36 rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
37 }
38
39 return rc;
40 }
41
42 static int
cn9k_sso_hws_unlink(void * arg,void * port,uint16_t * map,uint16_t nb_link)43 cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
44 {
45 struct cnxk_sso_evdev *dev = arg;
46 struct cn9k_sso_hws_dual *dws;
47 struct cn9k_sso_hws *ws;
48 int rc;
49
50 if (dev->dual_ws) {
51 dws = port;
52 rc = roc_sso_hws_unlink(&dev->sso,
53 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),
54 map, nb_link);
55 rc |= roc_sso_hws_unlink(&dev->sso,
56 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),
57 map, nb_link);
58 } else {
59 ws = port;
60 rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
61 }
62
63 return rc;
64 }
65
66 static void
cn9k_sso_hws_setup(void * arg,void * hws,uintptr_t grp_base)67 cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
68 {
69 struct cnxk_sso_evdev *dev = arg;
70 struct cn9k_sso_hws_dual *dws;
71 struct cn9k_sso_hws *ws;
72 uint64_t val;
73
74 /* Set get_work tmo for HWS */
75 val = NSEC2USEC(dev->deq_tmo_ns);
76 val = val ? val - 1 : 0;
77 if (dev->dual_ws) {
78 dws = hws;
79 dws->grp_base = grp_base;
80 dws->fc_mem = (uint64_t *)dev->fc_iova;
81 dws->xaq_lmt = dev->xaq_lmt;
82
83 plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);
84 plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);
85 } else {
86 ws = hws;
87 ws->grp_base = grp_base;
88 ws->fc_mem = (uint64_t *)dev->fc_iova;
89 ws->xaq_lmt = dev->xaq_lmt;
90
91 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
92 }
93 }
94
95 static void
cn9k_sso_hws_release(void * arg,void * hws)96 cn9k_sso_hws_release(void *arg, void *hws)
97 {
98 struct cnxk_sso_evdev *dev = arg;
99 struct cn9k_sso_hws_dual *dws;
100 struct cn9k_sso_hws *ws;
101 uint16_t i;
102
103 if (dev->dual_ws) {
104 dws = hws;
105 for (i = 0; i < dev->nb_event_queues; i++) {
106 roc_sso_hws_unlink(&dev->sso,
107 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), &i, 1);
108 roc_sso_hws_unlink(&dev->sso,
109 CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), &i, 1);
110 }
111 memset(dws, 0, sizeof(*dws));
112 } else {
113 ws = hws;
114 for (i = 0; i < dev->nb_event_queues; i++)
115 roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);
116 memset(ws, 0, sizeof(*ws));
117 }
118 }
119
120 static int
cn9k_sso_hws_flush_events(void * hws,uint8_t queue_id,uintptr_t base,cnxk_handle_event_t fn,void * arg)121 cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
122 cnxk_handle_event_t fn, void *arg)
123 {
124 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);
125 uint64_t retry = CNXK_SSO_FLUSH_RETRY_MAX;
126 struct cnxk_timesync_info *tstamp;
127 struct cn9k_sso_hws_dual *dws;
128 struct cn9k_sso_hws *ws;
129 uint64_t cq_ds_cnt = 1;
130 uint64_t aq_cnt = 1;
131 uint64_t ds_cnt = 1;
132 struct rte_event ev;
133 uintptr_t ws_base;
134 uint64_t val, req;
135 void *lookup_mem;
136
137 plt_write64(0, base + SSO_LF_GGRP_QCTL);
138
139 req = queue_id; /* GGRP ID */
140 req |= BIT_ULL(18); /* Grouped */
141 req |= BIT_ULL(16); /* WAIT */
142
143 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
144 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
145 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
146 cq_ds_cnt &= 0x3FFF3FFF0000;
147
148 if (dev->dual_ws) {
149 dws = hws;
150 ws_base = dws->base[0];
151 lookup_mem = dws->lookup_mem;
152 tstamp = dws->tstamp;
153 } else {
154 ws = hws;
155 ws_base = ws->base;
156 lookup_mem = ws->lookup_mem;
157 tstamp = ws->tstamp;
158 }
159
160 while (aq_cnt || cq_ds_cnt || ds_cnt) {
161 plt_write64(req, ws_base + SSOW_LF_GWS_OP_GET_WORK0);
162 cn9k_sso_hws_get_work_empty(ws_base, &ev, dev->rx_offloads,
163 lookup_mem, tstamp);
164 if (fn != NULL && ev.u64 != 0)
165 fn(arg, ev);
166 if (ev.sched_type != SSO_TT_EMPTY)
167 cnxk_sso_hws_swtag_flush(ws_base);
168 else if (retry-- == 0)
169 break;
170 do {
171 val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE);
172 } while (val & BIT_ULL(56));
173 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
174 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
175 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
176 /* Extract cq and ds count */
177 cq_ds_cnt &= 0x3FFF3FFF0000;
178 }
179
180 if (aq_cnt || cq_ds_cnt || ds_cnt)
181 return -EAGAIN;
182
183 plt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL);
184
185 return 0;
186 }
187
188 static void
cn9k_sso_hws_reset(void * arg,void * hws)189 cn9k_sso_hws_reset(void *arg, void *hws)
190 {
191 struct cnxk_sso_evdev *dev = arg;
192 struct cn9k_sso_hws_dual *dws;
193 struct cn9k_sso_hws *ws;
194 uint64_t pend_state;
195 uint8_t pend_tt;
196 uintptr_t base;
197 bool is_pend;
198 uint64_t tag;
199 uint8_t i;
200
201 dws = hws;
202 ws = hws;
203 for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {
204 base = dev->dual_ws ? dws->base[i] : ws->base;
205 is_pend = false;
206 /* Work in WQE0 is always consumed, unless its a SWTAG. */
207 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
208 if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) ||
209 (dev->dual_ws ? (dws->swtag_req && i == !dws->vws) :
210 ws->swtag_req))
211 is_pend = true;
212 /* Wait till getwork/swtp/waitw/desched completes. */
213 do {
214 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
215 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
216 BIT_ULL(56)));
217
218 tag = plt_read64(base + SSOW_LF_GWS_TAG);
219 pend_tt = (tag >> 32) & 0x3;
220 if (is_pend && pend_tt != SSO_TT_EMPTY) { /* Work was pending */
221 if (pend_tt == SSO_TT_ATOMIC ||
222 pend_tt == SSO_TT_ORDERED)
223 cnxk_sso_hws_swtag_untag(
224 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
225 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
226 }
227
228 /* Wait for desched to complete. */
229 do {
230 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
231 } while (pend_state & BIT_ULL(58));
232
233 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
234 }
235
236 if (dev->dual_ws)
237 dws->swtag_req = 0;
238 else
239 ws->swtag_req = 0;
240 }
241
242 void
cn9k_sso_set_rsrc(void * arg)243 cn9k_sso_set_rsrc(void *arg)
244 {
245 struct cnxk_sso_evdev *dev = arg;
246
247 if (dev->dual_ws)
248 dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS;
249 else
250 dev->max_event_ports = dev->sso.max_hws;
251 dev->max_event_queues =
252 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
253 RTE_EVENT_MAX_QUEUES_PER_DEV :
254 dev->sso.max_hwgrp;
255 }
256
257 static int
cn9k_sso_rsrc_init(void * arg,uint8_t hws,uint8_t hwgrp)258 cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
259 {
260 struct cnxk_sso_evdev *dev = arg;
261
262 if (dev->dual_ws)
263 hws = hws * CN9K_DUAL_WS_NB_WS;
264
265 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
266 }
267
268 static int
cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev * event_dev)269 cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
270 {
271 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
272 int i;
273
274 if (dev->tx_adptr_data == NULL)
275 return 0;
276
277 for (i = 0; i < dev->nb_event_ports; i++) {
278 if (dev->dual_ws) {
279 struct cn9k_sso_hws_dual *dws =
280 event_dev->data->ports[i];
281 void *ws_cookie;
282
283 ws_cookie = cnxk_sso_hws_get_cookie(dws);
284 ws_cookie = rte_realloc_socket(
285 ws_cookie,
286 sizeof(struct cnxk_sso_hws_cookie) +
287 sizeof(struct cn9k_sso_hws_dual) +
288 dev->tx_adptr_data_sz,
289 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
290 if (ws_cookie == NULL)
291 return -ENOMEM;
292 dws = RTE_PTR_ADD(ws_cookie,
293 sizeof(struct cnxk_sso_hws_cookie));
294 memcpy(&dws->tx_adptr_data, dev->tx_adptr_data,
295 dev->tx_adptr_data_sz);
296 event_dev->data->ports[i] = dws;
297 } else {
298 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
299 void *ws_cookie;
300
301 ws_cookie = cnxk_sso_hws_get_cookie(ws);
302 ws_cookie = rte_realloc_socket(
303 ws_cookie,
304 sizeof(struct cnxk_sso_hws_cookie) +
305 sizeof(struct cn9k_sso_hws_dual) +
306 dev->tx_adptr_data_sz,
307 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
308 if (ws_cookie == NULL)
309 return -ENOMEM;
310 ws = RTE_PTR_ADD(ws_cookie,
311 sizeof(struct cnxk_sso_hws_cookie));
312 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
313 dev->tx_adptr_data_sz);
314 event_dev->data->ports[i] = ws;
315 }
316 }
317 rte_mb();
318
319 return 0;
320 }
321
322 static void
cn9k_sso_fp_fns_set(struct rte_eventdev * event_dev)323 cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
324 {
325 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
326 /* Single WS modes */
327 const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
328 #define R(name, flags)[flags] = cn9k_sso_hws_deq_##name,
329 NIX_RX_FASTPATH_MODES
330 #undef R
331 };
332
333 const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
334 #define R(name, flags)[flags] = cn9k_sso_hws_deq_burst_##name,
335 NIX_RX_FASTPATH_MODES
336 #undef R
337 };
338
339 const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
340 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_##name,
341 NIX_RX_FASTPATH_MODES
342 #undef R
343 };
344
345 const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
346 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_burst_##name,
347 NIX_RX_FASTPATH_MODES
348 #undef R
349 };
350
351 const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
352 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_##name,
353 NIX_RX_FASTPATH_MODES
354 #undef R
355 };
356
357 const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
358 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_burst_##name,
359 NIX_RX_FASTPATH_MODES
360 #undef R
361 };
362
363 const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
364 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_##name,
365 NIX_RX_FASTPATH_MODES
366 #undef R
367 };
368
369 const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
370 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_burst_##name,
371 NIX_RX_FASTPATH_MODES
372 #undef R
373 };
374
375 const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
376 #define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_##name,
377 NIX_RX_FASTPATH_MODES
378 #undef R
379 };
380
381 const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
382 #define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_burst_##name,
383 NIX_RX_FASTPATH_MODES
384 #undef R
385 };
386
387 const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
388 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_##name,
389 NIX_RX_FASTPATH_MODES
390 #undef R
391 };
392
393 const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
394 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
395 NIX_RX_FASTPATH_MODES
396 #undef R
397 };
398
399 const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
400 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_##name,
401 NIX_RX_FASTPATH_MODES
402 #undef R
403 };
404
405 const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
406 #define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_burst_##name,
407 NIX_RX_FASTPATH_MODES
408 #undef R
409 };
410
411 const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
412 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_##name,
413 NIX_RX_FASTPATH_MODES
414 #undef R
415 };
416
417 const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
418 #define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_burst_##name,
419 NIX_RX_FASTPATH_MODES
420 #undef R
421 };
422
423 /* Dual WS modes */
424 const event_dequeue_t sso_hws_dual_deq[NIX_RX_OFFLOAD_MAX] = {
425 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_##name,
426 NIX_RX_FASTPATH_MODES
427 #undef R
428 };
429
430 const event_dequeue_burst_t sso_hws_dual_deq_burst[NIX_RX_OFFLOAD_MAX] = {
431 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_burst_##name,
432 NIX_RX_FASTPATH_MODES
433 #undef R
434 };
435
436 const event_dequeue_t sso_hws_dual_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
437 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_##name,
438 NIX_RX_FASTPATH_MODES
439 #undef R
440 };
441
442 const event_dequeue_burst_t sso_hws_dual_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
443 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
444 NIX_RX_FASTPATH_MODES
445 #undef R
446 };
447
448 const event_dequeue_t sso_hws_dual_deq_ca[NIX_RX_OFFLOAD_MAX] = {
449 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_##name,
450 NIX_RX_FASTPATH_MODES
451 #undef R
452 };
453
454 const event_dequeue_burst_t sso_hws_dual_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
455 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_burst_##name,
456 NIX_RX_FASTPATH_MODES
457 #undef R
458 };
459
460 const event_dequeue_t sso_hws_dual_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
461 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_##name,
462 NIX_RX_FASTPATH_MODES
463 #undef R
464 };
465
466 const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
467 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_burst_##name,
468 NIX_RX_FASTPATH_MODES
469 #undef R
470 };
471
472 const event_dequeue_t sso_hws_dual_deq_seg[NIX_RX_OFFLOAD_MAX] = {
473 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_##name,
474 NIX_RX_FASTPATH_MODES
475 #undef R
476 };
477
478 const event_dequeue_burst_t sso_hws_dual_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
479 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_burst_##name,
480 NIX_RX_FASTPATH_MODES
481 #undef R
482 };
483
484 const event_dequeue_t sso_hws_dual_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
485 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
486 NIX_RX_FASTPATH_MODES
487 #undef R
488 };
489
490 const event_dequeue_burst_t sso_hws_dual_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
491 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
492 NIX_RX_FASTPATH_MODES
493 #undef R
494 };
495
496 const event_dequeue_t sso_hws_dual_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
497 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_##name,
498 NIX_RX_FASTPATH_MODES
499 #undef R
500 };
501
502 const event_dequeue_burst_t sso_hws_dual_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
503 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
504 NIX_RX_FASTPATH_MODES
505 #undef R
506 };
507
508 const event_dequeue_t sso_hws_dual_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
509 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_##name,
510 NIX_RX_FASTPATH_MODES
511 #undef R
512 };
513
514 const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
515 #define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_burst_##name,
516 NIX_RX_FASTPATH_MODES
517 #undef R
518 };
519
520 /* Tx modes */
521 const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
522 #define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_##name,
523 NIX_TX_FASTPATH_MODES
524 #undef T
525 };
526
527 const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
528 #define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_seg_##name,
529 NIX_TX_FASTPATH_MODES
530 #undef T
531 };
532
533 const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
534 #define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_##name,
535 NIX_TX_FASTPATH_MODES
536 #undef T
537 };
538
539 const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
540 #define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_seg_##name,
541 NIX_TX_FASTPATH_MODES
542 #undef T
543 };
544
545 event_dev->enqueue = cn9k_sso_hws_enq;
546 event_dev->enqueue_burst = cn9k_sso_hws_enq_burst;
547 event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;
548 event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;
549 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
550 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_seg);
551 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
552 sso_hws_deq_seg_burst);
553 if (dev->is_timeout_deq) {
554 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
555 sso_hws_deq_tmo_seg);
556 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
557 sso_hws_deq_tmo_seg_burst);
558 }
559 if (dev->is_ca_internal_port) {
560 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
561 sso_hws_deq_ca_seg);
562 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
563 sso_hws_deq_ca_seg_burst);
564 }
565
566 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
567 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
568 sso_hws_deq_tmo_ca_seg);
569 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
570 sso_hws_deq_tmo_ca_seg_burst);
571 }
572 } else {
573 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
574 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
575 sso_hws_deq_burst);
576 if (dev->is_timeout_deq) {
577 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
578 sso_hws_deq_tmo);
579 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
580 sso_hws_deq_tmo_burst);
581 }
582 if (dev->is_ca_internal_port) {
583 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
584 sso_hws_deq_ca);
585 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
586 sso_hws_deq_ca_burst);
587 }
588
589 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
590 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
591 sso_hws_deq_tmo_ca);
592 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
593 sso_hws_deq_tmo_ca_burst);
594 }
595 }
596 event_dev->ca_enqueue = cn9k_sso_hws_ca_enq;
597
598 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
599 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
600 sso_hws_tx_adptr_enq_seg);
601 else
602 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
603 sso_hws_tx_adptr_enq);
604
605 if (dev->dual_ws) {
606 event_dev->enqueue = cn9k_sso_hws_dual_enq;
607 event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst;
608 event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;
609 event_dev->enqueue_forward_burst =
610 cn9k_sso_hws_dual_enq_fwd_burst;
611 event_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;
612
613 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
614 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
615 sso_hws_dual_deq_seg);
616 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
617 sso_hws_dual_deq_seg_burst);
618 if (dev->is_timeout_deq) {
619 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
620 sso_hws_dual_deq_tmo_seg);
621 CN9K_SET_EVDEV_DEQ_OP(
622 dev, event_dev->dequeue_burst,
623 sso_hws_dual_deq_tmo_seg_burst);
624 }
625 if (dev->is_ca_internal_port) {
626 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
627 sso_hws_dual_deq_ca_seg);
628 CN9K_SET_EVDEV_DEQ_OP(
629 dev, event_dev->dequeue_burst,
630 sso_hws_dual_deq_ca_seg_burst);
631 }
632 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
633 CN9K_SET_EVDEV_DEQ_OP(
634 dev, event_dev->dequeue,
635 sso_hws_dual_deq_tmo_ca_seg);
636 CN9K_SET_EVDEV_DEQ_OP(
637 dev, event_dev->dequeue_burst,
638 sso_hws_dual_deq_tmo_ca_seg_burst);
639 }
640 } else {
641 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
642 sso_hws_dual_deq);
643 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
644 sso_hws_dual_deq_burst);
645 if (dev->is_timeout_deq) {
646 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
647 sso_hws_dual_deq_tmo);
648 CN9K_SET_EVDEV_DEQ_OP(
649 dev, event_dev->dequeue_burst,
650 sso_hws_dual_deq_tmo_burst);
651 }
652 if (dev->is_ca_internal_port) {
653 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
654 sso_hws_dual_deq_ca);
655 CN9K_SET_EVDEV_DEQ_OP(
656 dev, event_dev->dequeue_burst,
657 sso_hws_dual_deq_ca_burst);
658 }
659 if (dev->is_ca_internal_port && dev->is_timeout_deq) {
660 CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
661 sso_hws_dual_deq_tmo_ca);
662 CN9K_SET_EVDEV_DEQ_OP(
663 dev, event_dev->dequeue_burst,
664 sso_hws_dual_deq_tmo_ca_burst);
665 }
666 }
667
668 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
669 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
670 sso_hws_dual_tx_adptr_enq_seg);
671 else
672 CN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
673 sso_hws_dual_tx_adptr_enq);
674 }
675
676 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
677 rte_mb();
678 }
679
680 static void *
cn9k_sso_init_hws_mem(void * arg,uint8_t port_id)681 cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
682 {
683 struct cnxk_sso_evdev *dev = arg;
684 struct cn9k_sso_hws_dual *dws;
685 struct cn9k_sso_hws *ws;
686 void *data;
687
688 if (dev->dual_ws) {
689 dws = rte_zmalloc("cn9k_dual_ws",
690 sizeof(struct cn9k_sso_hws_dual) +
691 RTE_CACHE_LINE_SIZE,
692 RTE_CACHE_LINE_SIZE);
693 if (dws == NULL) {
694 plt_err("Failed to alloc memory for port=%d", port_id);
695 return NULL;
696 }
697
698 dws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie));
699 dws->base[0] = roc_sso_hws_base_get(
700 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0));
701 dws->base[1] = roc_sso_hws_base_get(
702 &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1));
703 dws->hws_id = port_id;
704 dws->swtag_req = 0;
705 dws->vws = 0;
706 if (dev->deq_tmo_ns)
707 dws->gw_wdata = BIT_ULL(16);
708 dws->gw_wdata |= 1;
709
710 data = dws;
711 } else {
712 /* Allocate event port memory */
713 ws = rte_zmalloc("cn9k_ws",
714 sizeof(struct cn9k_sso_hws) +
715 RTE_CACHE_LINE_SIZE,
716 RTE_CACHE_LINE_SIZE);
717 if (ws == NULL) {
718 plt_err("Failed to alloc memory for port=%d", port_id);
719 return NULL;
720 }
721
722 /* First cache line is reserved for cookie */
723 ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie));
724 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
725 ws->hws_id = port_id;
726 ws->swtag_req = 0;
727 if (dev->deq_tmo_ns)
728 ws->gw_wdata = BIT_ULL(16);
729 ws->gw_wdata |= 1;
730
731 data = ws;
732 }
733
734 return data;
735 }
736
737 static void
cn9k_sso_info_get(struct rte_eventdev * event_dev,struct rte_event_dev_info * dev_info)738 cn9k_sso_info_get(struct rte_eventdev *event_dev,
739 struct rte_event_dev_info *dev_info)
740 {
741 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
742
743 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD);
744 cnxk_sso_info_get(dev, dev_info);
745 }
746
747 static int
cn9k_sso_dev_configure(const struct rte_eventdev * event_dev)748 cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)
749 {
750 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
751 int rc;
752
753 rc = cnxk_sso_dev_validate(event_dev);
754 if (rc < 0) {
755 plt_err("Invalid event device configuration");
756 return -EINVAL;
757 }
758
759 rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues);
760 if (rc < 0) {
761 plt_err("Failed to initialize SSO resources");
762 return -ENODEV;
763 }
764
765 rc = cnxk_sso_xaq_allocate(dev);
766 if (rc < 0)
767 goto cnxk_rsrc_fini;
768
769 rc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem,
770 cn9k_sso_hws_setup);
771 if (rc < 0)
772 goto cnxk_rsrc_fini;
773
774 /* Restore any prior port-queue mapping. */
775 cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link);
776
777 dev->configured = 1;
778 rte_mb();
779
780 return 0;
781 cnxk_rsrc_fini:
782 roc_sso_rsrc_fini(&dev->sso);
783 dev->nb_event_ports = 0;
784 return rc;
785 }
786
787 static int
cn9k_sso_port_setup(struct rte_eventdev * event_dev,uint8_t port_id,const struct rte_event_port_conf * port_conf)788 cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
789 const struct rte_event_port_conf *port_conf)
790 {
791
792 RTE_SET_USED(port_conf);
793 return cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup);
794 }
795
796 static void
cn9k_sso_port_release(void * port)797 cn9k_sso_port_release(void *port)
798 {
799 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
800 struct cnxk_sso_evdev *dev;
801
802 if (port == NULL)
803 return;
804
805 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
806 if (!gws_cookie->configured)
807 goto free;
808
809 cn9k_sso_hws_release(dev, port);
810 memset(gws_cookie, 0, sizeof(*gws_cookie));
811 free:
812 rte_free(gws_cookie);
813 }
814
815 static void
cn9k_sso_port_quiesce(struct rte_eventdev * event_dev,void * port,rte_eventdev_port_flush_t flush_cb,void * args)816 cn9k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port,
817 rte_eventdev_port_flush_t flush_cb, void *args)
818 {
819 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
820 struct cn9k_sso_hws_dual *dws;
821 struct cn9k_sso_hws *ws;
822 struct rte_event ev;
823 uintptr_t base;
824 uint64_t ptag;
825 bool is_pend;
826 uint8_t i;
827
828 dws = port;
829 ws = port;
830 for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {
831 base = dev->dual_ws ? dws->base[i] : ws->base;
832 is_pend = false;
833 /* Work in WQE0 is always consumed, unless its a SWTAG. */
834 ptag = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
835 if (ptag & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) ||
836 (dev->dual_ws ? (dws->swtag_req && i == !dws->vws) :
837 ws->swtag_req))
838 is_pend = true;
839 /* Wait till getwork/swtp/waitw/desched completes. */
840 do {
841 ptag = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
842 } while (ptag & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
843 BIT_ULL(56)));
844
845 cn9k_sso_hws_get_work_empty(
846 base, &ev, dev->rx_offloads,
847 dev->dual_ws ? dws->lookup_mem : ws->lookup_mem,
848 dev->dual_ws ? dws->tstamp : ws->tstamp);
849 if (is_pend && ev.u64) {
850 if (flush_cb)
851 flush_cb(event_dev->data->dev_id, ev, args);
852 cnxk_sso_hws_swtag_flush(ws->base);
853 }
854 }
855 }
856
857 static int
cn9k_sso_port_link(struct rte_eventdev * event_dev,void * port,const uint8_t queues[],const uint8_t priorities[],uint16_t nb_links)858 cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,
859 const uint8_t queues[], const uint8_t priorities[],
860 uint16_t nb_links)
861 {
862 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
863 uint16_t hwgrp_ids[nb_links];
864 uint16_t link;
865
866 RTE_SET_USED(priorities);
867 for (link = 0; link < nb_links; link++)
868 hwgrp_ids[link] = queues[link];
869 nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
870
871 return (int)nb_links;
872 }
873
874 static int
cn9k_sso_port_unlink(struct rte_eventdev * event_dev,void * port,uint8_t queues[],uint16_t nb_unlinks)875 cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
876 uint8_t queues[], uint16_t nb_unlinks)
877 {
878 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
879 uint16_t hwgrp_ids[nb_unlinks];
880 uint16_t unlink;
881
882 for (unlink = 0; unlink < nb_unlinks; unlink++)
883 hwgrp_ids[unlink] = queues[unlink];
884 nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
885
886 return (int)nb_unlinks;
887 }
888
889 static int
cn9k_sso_start(struct rte_eventdev * event_dev)890 cn9k_sso_start(struct rte_eventdev *event_dev)
891 {
892 int rc;
893
894 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
895 if (rc < 0)
896 return rc;
897
898 rc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset,
899 cn9k_sso_hws_flush_events);
900 if (rc < 0)
901 return rc;
902
903 cn9k_sso_fp_fns_set(event_dev);
904
905 return rc;
906 }
907
908 static void
cn9k_sso_stop(struct rte_eventdev * event_dev)909 cn9k_sso_stop(struct rte_eventdev *event_dev)
910 {
911 cnxk_sso_stop(event_dev, cn9k_sso_hws_reset, cn9k_sso_hws_flush_events);
912 }
913
914 static int
cn9k_sso_close(struct rte_eventdev * event_dev)915 cn9k_sso_close(struct rte_eventdev *event_dev)
916 {
917 return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink);
918 }
919
920 static int
cn9k_sso_selftest(void)921 cn9k_sso_selftest(void)
922 {
923 return cnxk_sso_selftest(RTE_STR(event_cn9k));
924 }
925
926 static int
cn9k_sso_rx_adapter_caps_get(const struct rte_eventdev * event_dev,const struct rte_eth_dev * eth_dev,uint32_t * caps)927 cn9k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
928 const struct rte_eth_dev *eth_dev, uint32_t *caps)
929 {
930 int rc;
931
932 RTE_SET_USED(event_dev);
933 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 9);
934 if (rc)
935 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
936 else
937 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
938 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
939 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
940
941 return 0;
942 }
943
944 static void
cn9k_sso_set_priv_mem(const struct rte_eventdev * event_dev,void * lookup_mem,void * tstmp_info)945 cn9k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
946 void *tstmp_info)
947 {
948 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
949 int i;
950
951 for (i = 0; i < dev->nb_event_ports; i++) {
952 if (dev->dual_ws) {
953 struct cn9k_sso_hws_dual *dws =
954 event_dev->data->ports[i];
955 dws->lookup_mem = lookup_mem;
956 dws->tstamp = tstmp_info;
957 } else {
958 struct cn9k_sso_hws *ws = event_dev->data->ports[i];
959 ws->lookup_mem = lookup_mem;
960 ws->tstamp = tstmp_info;
961 }
962 }
963 }
964
965 static int
cn9k_sso_rx_adapter_queue_add(const struct rte_eventdev * event_dev,const struct rte_eth_dev * eth_dev,int32_t rx_queue_id,const struct rte_event_eth_rx_adapter_queue_conf * queue_conf)966 cn9k_sso_rx_adapter_queue_add(
967 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
968 int32_t rx_queue_id,
969 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
970 {
971 struct cn9k_eth_rxq *rxq;
972 void *lookup_mem;
973 void *tstmp_info;
974 int rc;
975
976 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
977 if (rc)
978 return -EINVAL;
979
980 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
981 queue_conf);
982 if (rc)
983 return -EINVAL;
984
985 rxq = eth_dev->data->rx_queues[0];
986 lookup_mem = rxq->lookup_mem;
987 tstmp_info = rxq->tstamp;
988 cn9k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
989 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
990
991 return 0;
992 }
993
994 static int
cn9k_sso_rx_adapter_queue_del(const struct rte_eventdev * event_dev,const struct rte_eth_dev * eth_dev,int32_t rx_queue_id)995 cn9k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
996 const struct rte_eth_dev *eth_dev,
997 int32_t rx_queue_id)
998 {
999 int rc;
1000
1001 rc = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
1002 if (rc)
1003 return -EINVAL;
1004
1005 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
1006 }
1007
1008 static int
cn9k_sso_tx_adapter_caps_get(const struct rte_eventdev * dev,const struct rte_eth_dev * eth_dev,uint32_t * caps)1009 cn9k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
1010 const struct rte_eth_dev *eth_dev, uint32_t *caps)
1011 {
1012 int ret;
1013
1014 RTE_SET_USED(dev);
1015 ret = strncmp(eth_dev->device->driver->name, "net_cn9k", 8);
1016 if (ret)
1017 *caps = 0;
1018 else
1019 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;
1020
1021 return 0;
1022 }
1023
1024 static void
cn9k_sso_txq_fc_update(const struct rte_eth_dev * eth_dev,int32_t tx_queue_id)1025 cn9k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id)
1026 {
1027 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
1028 struct cn9k_eth_txq *txq;
1029 struct roc_nix_sq *sq;
1030 int i;
1031
1032 if (tx_queue_id < 0) {
1033 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1034 cn9k_sso_txq_fc_update(eth_dev, i);
1035 } else {
1036 uint16_t sqes_per_sqb;
1037
1038 sq = &cnxk_eth_dev->sqs[tx_queue_id];
1039 txq = eth_dev->data->tx_queues[tx_queue_id];
1040 sqes_per_sqb = 1U << txq->sqes_per_sqb_log2;
1041 sq->nb_sqb_bufs_adj =
1042 sq->nb_sqb_bufs -
1043 RTE_ALIGN_MUL_CEIL(sq->nb_sqb_bufs, sqes_per_sqb) /
1044 sqes_per_sqb;
1045 if (cnxk_eth_dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
1046 sq->nb_sqb_bufs_adj -= (cnxk_eth_dev->outb.nb_desc /
1047 (sqes_per_sqb - 1));
1048 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;
1049 txq->nb_sqb_bufs_adj = (70 * txq->nb_sqb_bufs_adj) / 100;
1050 }
1051 }
1052
1053 static int
cn9k_sso_tx_adapter_queue_add(uint8_t id,const struct rte_eventdev * event_dev,const struct rte_eth_dev * eth_dev,int32_t tx_queue_id)1054 cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
1055 const struct rte_eth_dev *eth_dev,
1056 int32_t tx_queue_id)
1057 {
1058 struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
1059 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1060 uint64_t tx_offloads;
1061 int rc;
1062
1063 RTE_SET_USED(id);
1064 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
1065 if (rc < 0)
1066 return rc;
1067
1068 /* Can't enable tstamp if all the ports don't have it enabled. */
1069 tx_offloads = cnxk_eth_dev->tx_offload_flags;
1070 if (dev->tx_adptr_configured) {
1071 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
1072 uint8_t tstmp_ena =
1073 !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
1074
1075 if (tstmp_ena && !tstmp_req)
1076 dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
1077 else if (!tstmp_ena && tstmp_req)
1078 tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
1079 }
1080
1081 dev->tx_offloads |= tx_offloads;
1082 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id);
1083 rc = cn9k_sso_updt_tx_adptr_data(event_dev);
1084 if (rc < 0)
1085 return rc;
1086 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1087 dev->tx_adptr_configured = 1;
1088
1089 return 0;
1090 }
1091
1092 static int
cn9k_sso_tx_adapter_queue_del(uint8_t id,const struct rte_eventdev * event_dev,const struct rte_eth_dev * eth_dev,int32_t tx_queue_id)1093 cn9k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
1094 const struct rte_eth_dev *eth_dev,
1095 int32_t tx_queue_id)
1096 {
1097 int rc;
1098
1099 RTE_SET_USED(id);
1100 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
1101 if (rc < 0)
1102 return rc;
1103 cn9k_sso_txq_fc_update(eth_dev, tx_queue_id);
1104 return cn9k_sso_updt_tx_adptr_data(event_dev);
1105 }
1106
1107 static int
cn9k_crypto_adapter_caps_get(const struct rte_eventdev * event_dev,const struct rte_cryptodev * cdev,uint32_t * caps)1108 cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
1109 const struct rte_cryptodev *cdev, uint32_t *caps)
1110 {
1111 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1112 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1113
1114 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
1115 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
1116
1117 return 0;
1118 }
1119
1120 static int
cn9k_crypto_adapter_qp_add(const struct rte_eventdev * event_dev,const struct rte_cryptodev * cdev,int32_t queue_pair_id,const struct rte_event * event)1121 cn9k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
1122 const struct rte_cryptodev *cdev,
1123 int32_t queue_pair_id, const struct rte_event *event)
1124 {
1125 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1126
1127 RTE_SET_USED(event);
1128
1129 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1130 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1131
1132 dev->is_ca_internal_port = 1;
1133 cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
1134
1135 return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
1136 }
1137
1138 static int
cn9k_crypto_adapter_qp_del(const struct rte_eventdev * event_dev,const struct rte_cryptodev * cdev,int32_t queue_pair_id)1139 cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
1140 const struct rte_cryptodev *cdev,
1141 int32_t queue_pair_id)
1142 {
1143 CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k");
1144 CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k");
1145
1146 return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
1147 }
1148
1149 static struct eventdev_ops cn9k_sso_dev_ops = {
1150 .dev_infos_get = cn9k_sso_info_get,
1151 .dev_configure = cn9k_sso_dev_configure,
1152
1153 .queue_def_conf = cnxk_sso_queue_def_conf,
1154 .queue_setup = cnxk_sso_queue_setup,
1155 .queue_release = cnxk_sso_queue_release,
1156 .queue_attr_get = cnxk_sso_queue_attribute_get,
1157 .queue_attr_set = cnxk_sso_queue_attribute_set,
1158
1159 .port_def_conf = cnxk_sso_port_def_conf,
1160 .port_setup = cn9k_sso_port_setup,
1161 .port_release = cn9k_sso_port_release,
1162 .port_quiesce = cn9k_sso_port_quiesce,
1163 .port_link = cn9k_sso_port_link,
1164 .port_unlink = cn9k_sso_port_unlink,
1165 .timeout_ticks = cnxk_sso_timeout_ticks,
1166
1167 .eth_rx_adapter_caps_get = cn9k_sso_rx_adapter_caps_get,
1168 .eth_rx_adapter_queue_add = cn9k_sso_rx_adapter_queue_add,
1169 .eth_rx_adapter_queue_del = cn9k_sso_rx_adapter_queue_del,
1170 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
1171 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
1172
1173 .eth_tx_adapter_caps_get = cn9k_sso_tx_adapter_caps_get,
1174 .eth_tx_adapter_queue_add = cn9k_sso_tx_adapter_queue_add,
1175 .eth_tx_adapter_queue_del = cn9k_sso_tx_adapter_queue_del,
1176
1177 .timer_adapter_caps_get = cnxk_tim_caps_get,
1178
1179 .crypto_adapter_caps_get = cn9k_crypto_adapter_caps_get,
1180 .crypto_adapter_queue_pair_add = cn9k_crypto_adapter_qp_add,
1181 .crypto_adapter_queue_pair_del = cn9k_crypto_adapter_qp_del,
1182
1183 .dump = cnxk_sso_dump,
1184 .dev_start = cn9k_sso_start,
1185 .dev_stop = cn9k_sso_stop,
1186 .dev_close = cn9k_sso_close,
1187 .dev_selftest = cn9k_sso_selftest,
1188 };
1189
1190 static int
cn9k_sso_init(struct rte_eventdev * event_dev)1191 cn9k_sso_init(struct rte_eventdev *event_dev)
1192 {
1193 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
1194 int rc;
1195
1196 if (RTE_CACHE_LINE_SIZE != 128) {
1197 plt_err("Driver not compiled for CN9K");
1198 return -EFAULT;
1199 }
1200
1201 rc = roc_plt_init();
1202 if (rc < 0) {
1203 plt_err("Failed to initialize platform model");
1204 return rc;
1205 }
1206
1207 event_dev->dev_ops = &cn9k_sso_dev_ops;
1208 /* For secondary processes, the primary has done all the work */
1209 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1210 cn9k_sso_fp_fns_set(event_dev);
1211 return 0;
1212 }
1213
1214 rc = cnxk_sso_init(event_dev);
1215 if (rc < 0)
1216 return rc;
1217
1218 cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
1219 if (!dev->max_event_ports || !dev->max_event_queues) {
1220 plt_err("Not enough eventdev resource queues=%d ports=%d",
1221 dev->max_event_queues, dev->max_event_ports);
1222 cnxk_sso_fini(event_dev);
1223 return -ENODEV;
1224 }
1225
1226 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1227 event_dev->data->name, dev->max_event_queues,
1228 dev->max_event_ports);
1229
1230 return 0;
1231 }
1232
1233 static int
cn9k_sso_probe(struct rte_pci_driver * pci_drv,struct rte_pci_device * pci_dev)1234 cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1235 {
1236 return rte_event_pmd_pci_probe(
1237 pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init);
1238 }
1239
1240 static const struct rte_pci_id cn9k_pci_sso_map[] = {
1241 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1242 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1243 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1244 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1245 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
1246 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1247 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1248 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1249 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1250 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
1251 {
1252 .vendor_id = 0,
1253 },
1254 };
1255
1256 static struct rte_pci_driver cn9k_pci_sso = {
1257 .id_table = cn9k_pci_sso_map,
1258 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1259 .probe = cn9k_sso_probe,
1260 .remove = cnxk_sso_remove,
1261 };
1262
1263 RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);
1264 RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);
1265 RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
1266 RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
1267 CNXK_SSO_GGRP_QOS "=<string>"
1268 CNXK_SSO_FORCE_BP "=1"
1269 CN9K_SSO_SINGLE_WS "=1"
1270 CNXK_TIM_DISABLE_NPA "=1"
1271 CNXK_TIM_CHNK_SLOTS "=<int>"
1272 CNXK_TIM_RINGS_LMT "=<int>"
1273 CNXK_TIM_STATS_ENA "=1");
1274