1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_PLATFORM_H_ 6 #define _ROC_PLATFORM_H_ 7 8 #include <rte_alarm.h> 9 #include <rte_bitmap.h> 10 #include <rte_bus_pci.h> 11 #include <rte_byteorder.h> 12 #include <rte_common.h> 13 #include <rte_cycles.h> 14 #include <rte_ether.h> 15 #include <rte_interrupts.h> 16 #include <rte_io.h> 17 #include <rte_log.h> 18 #include <rte_malloc.h> 19 #include <rte_memzone.h> 20 #include <rte_pci.h> 21 #include <rte_spinlock.h> 22 #include <rte_string_fns.h> 23 #include <rte_tailq.h> 24 #include <rte_telemetry.h> 25 26 #include "roc_bits.h" 27 28 #if defined(__ARM_FEATURE_SVE) 29 #define PLT_CPU_FEATURE_PREAMBLE \ 30 ".arch_extension crc\n" \ 31 ".arch_extension lse\n" \ 32 ".arch_extension sve\n" 33 #else 34 #define PLT_CPU_FEATURE_PREAMBLE \ 35 ".arch_extension crc\n" \ 36 ".arch_extension lse\n" 37 #endif 38 39 #define PLT_ASSERT RTE_ASSERT 40 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE 41 #define PLT_STD_C11 RTE_STD_C11 42 #define PLT_PTR_ADD RTE_PTR_ADD 43 #define PLT_PTR_DIFF RTE_PTR_DIFF 44 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID 45 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET 46 #define PLT_MIN RTE_MIN 47 #define PLT_MAX RTE_MAX 48 #define PLT_DIM RTE_DIM 49 #define PLT_SET_USED RTE_SET_USED 50 #define PLT_SWAP RTE_SWAP 51 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) 52 #define PLT_ALIGN RTE_ALIGN 53 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL 54 #define PLT_MODEL_MZ_NAME "roc_model_mz" 55 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE 56 #define BITMASK_ULL GENMASK_ULL 57 #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL 58 #define PLT_INIT RTE_INIT 59 #define PLT_TAILQ_FOREACH_SAFE RTE_TAILQ_FOREACH_SAFE 60 61 #ifndef PLT_ETHER_ADDR_LEN 62 #define PLT_ETHER_ADDR_LEN RTE_ETHER_ADDR_LEN 63 #endif 64 /** Divide ceil */ 65 #define PLT_DIV_CEIL(x, y) \ 66 ({ \ 67 __typeof(x) __x = x; \ 68 __typeof(y) __y = y; \ 69 (__x + __y - 1) / __y; \ 70 }) 71 72 #define __plt_cache_aligned __rte_cache_aligned 73 #define __plt_always_inline __rte_always_inline 74 #define __plt_packed __rte_packed 75 #define __plt_unused __rte_unused 76 #define __roc_api __rte_internal 77 #define plt_iova_t rte_iova_t 78 79 #define plt_pci_addr rte_pci_addr 80 #define plt_pci_device rte_pci_device 81 #define plt_pci_read_config rte_pci_read_config 82 #define plt_pci_find_ext_capability rte_pci_find_ext_capability 83 84 #define plt_log2_u32 rte_log2_u32 85 #define plt_cpu_to_be_16 rte_cpu_to_be_16 86 #define plt_be_to_cpu_16 rte_be_to_cpu_16 87 #define plt_cpu_to_be_32 rte_cpu_to_be_32 88 #define plt_be_to_cpu_32 rte_be_to_cpu_32 89 #define plt_cpu_to_be_64 rte_cpu_to_be_64 90 #define plt_be_to_cpu_64 rte_be_to_cpu_64 91 92 #define plt_aligned __rte_aligned 93 #define plt_align32pow2 rte_align32pow2 94 #define plt_align32prevpow2 rte_align32prevpow2 95 96 #define plt_bitmap rte_bitmap 97 #define plt_bitmap_init rte_bitmap_init 98 #define plt_bitmap_reset rte_bitmap_reset 99 #define plt_bitmap_free rte_bitmap_free 100 #define plt_bitmap_clear rte_bitmap_clear 101 #define plt_bitmap_set rte_bitmap_set 102 #define plt_bitmap_get rte_bitmap_get 103 #define plt_bitmap_scan_init __rte_bitmap_scan_init 104 #define plt_bitmap_scan rte_bitmap_scan 105 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint 106 107 #define plt_spinlock_t rte_spinlock_t 108 #define plt_spinlock_init rte_spinlock_init 109 #define plt_spinlock_lock rte_spinlock_lock 110 #define plt_spinlock_unlock rte_spinlock_unlock 111 112 #define plt_intr_callback_register rte_intr_callback_register 113 #define plt_intr_callback_unregister rte_intr_callback_unregister 114 #define plt_intr_disable rte_intr_disable 115 #define plt_thread_is_intr rte_thread_is_intr 116 #define plt_intr_callback_fn rte_intr_callback_fn 117 118 #define plt_intr_efd_counter_size_get rte_intr_efd_counter_size_get 119 #define plt_intr_efd_counter_size_set rte_intr_efd_counter_size_set 120 #define plt_intr_vec_list_index_get rte_intr_vec_list_index_get 121 #define plt_intr_vec_list_index_set rte_intr_vec_list_index_set 122 #define plt_intr_vec_list_alloc rte_intr_vec_list_alloc 123 #define plt_intr_vec_list_free rte_intr_vec_list_free 124 #define plt_intr_fd_set rte_intr_fd_set 125 #define plt_intr_fd_get rte_intr_fd_get 126 #define plt_intr_dev_fd_get rte_intr_dev_fd_get 127 #define plt_intr_dev_fd_set rte_intr_dev_fd_set 128 #define plt_intr_type_get rte_intr_type_get 129 #define plt_intr_type_set rte_intr_type_set 130 #define plt_intr_instance_alloc rte_intr_instance_alloc 131 #define plt_intr_instance_dup rte_intr_instance_dup 132 #define plt_intr_instance_free rte_intr_instance_free 133 #define plt_intr_event_list_update rte_intr_event_list_update 134 #define plt_intr_max_intr_get rte_intr_max_intr_get 135 #define plt_intr_max_intr_set rte_intr_max_intr_set 136 #define plt_intr_nb_efd_get rte_intr_nb_efd_get 137 #define plt_intr_nb_efd_set rte_intr_nb_efd_set 138 #define plt_intr_nb_intr_get rte_intr_nb_intr_get 139 #define plt_intr_nb_intr_set rte_intr_nb_intr_set 140 #define plt_intr_efds_index_get rte_intr_efds_index_get 141 #define plt_intr_efds_index_set rte_intr_efds_index_set 142 #define plt_intr_elist_index_get rte_intr_elist_index_get 143 #define plt_intr_elist_index_set rte_intr_elist_index_set 144 145 #define plt_alarm_set rte_eal_alarm_set 146 #define plt_alarm_cancel rte_eal_alarm_cancel 147 148 #define plt_intr_handle rte_intr_handle 149 150 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) 151 #define plt_free rte_free 152 153 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 154 #define plt_write64(val, addr) \ 155 rte_write64_relaxed((val), (volatile void *)(addr)) 156 157 #define plt_wmb() rte_wmb() 158 #define plt_rmb() rte_rmb() 159 #define plt_io_wmb() rte_io_wmb() 160 #define plt_io_rmb() rte_io_rmb() 161 #define plt_atomic_thread_fence rte_atomic_thread_fence 162 163 #define plt_mmap mmap 164 #define PLT_PROT_READ PROT_READ 165 #define PLT_PROT_WRITE PROT_WRITE 166 #define PLT_MAP_SHARED MAP_SHARED 167 168 #define plt_memzone rte_memzone 169 #define plt_memzone_lookup rte_memzone_lookup 170 #define plt_memzone_reserve_cache_align(name, sz) \ 171 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) 172 #define plt_memzone_free rte_memzone_free 173 #define plt_memzone_reserve_aligned(name, len, flags, align) \ 174 rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) 175 176 #define plt_tsc_hz rte_get_tsc_hz 177 #define plt_delay_ms rte_delay_ms 178 #define plt_delay_us rte_delay_us 179 180 #define plt_lcore_id rte_lcore_id 181 182 #define plt_strlcpy rte_strlcpy 183 184 #define PLT_TEL_INT_VAL RTE_TEL_INT_VAL 185 #define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL 186 #define plt_tel_data rte_tel_data 187 #define plt_tel_data_start_array rte_tel_data_start_array 188 #define plt_tel_data_add_array_int rte_tel_data_add_array_int 189 #define plt_tel_data_add_array_string rte_tel_data_add_array_string 190 #define plt_tel_data_start_dict rte_tel_data_start_dict 191 #define plt_tel_data_add_dict_int rte_tel_data_add_dict_int 192 #define plt_tel_data_add_dict_ptr(d, n, v) \ 193 rte_tel_data_add_dict_u64(d, n, (uint64_t)v) 194 #define plt_tel_data_add_dict_string rte_tel_data_add_dict_string 195 #define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_u64 196 #define plt_telemetry_register_cmd rte_telemetry_register_cmd 197 198 /* Log */ 199 extern int cnxk_logtype_base; 200 extern int cnxk_logtype_mbox; 201 extern int cnxk_logtype_cpt; 202 extern int cnxk_logtype_npa; 203 extern int cnxk_logtype_nix; 204 extern int cnxk_logtype_npc; 205 extern int cnxk_logtype_sso; 206 extern int cnxk_logtype_tim; 207 extern int cnxk_logtype_tm; 208 extern int cnxk_logtype_ree; 209 210 #define plt_err(fmt, args...) \ 211 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 212 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 213 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args) 214 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 215 #define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__) 216 #define plt_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__) 217 218 /** 219 * Log debug message if given subsystem logging is enabled. 220 */ 221 #define plt_dbg(subsystem, fmt, args...) \ 222 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \ 223 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \ 224 ##args) 225 226 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) 227 #define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) 228 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) 229 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) 230 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) 231 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) 232 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) 233 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) 234 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) 235 #define plt_ree_dbg(fmt, ...) plt_dbg(ree, fmt, ##__VA_ARGS__) 236 237 /* Datapath logs */ 238 #define plt_dp_err(fmt, args...) \ 239 RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 240 #define plt_dp_info(fmt, args...) \ 241 RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 242 243 #ifdef __cplusplus 244 #define CNXK_PCI_ID(subsystem_dev, dev) \ 245 { \ 246 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ 247 (subsystem_dev), \ 248 } 249 #else 250 #define CNXK_PCI_ID(subsystem_dev, dev) \ 251 { \ 252 .class_id = RTE_CLASS_ANY_ID, \ 253 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ 254 .subsystem_vendor_id = RTE_PCI_ANY_ID, \ 255 .subsystem_device_id = (subsystem_dev), \ 256 } 257 #endif 258 259 __rte_internal 260 int roc_plt_init(void); 261 262 /* Init callbacks */ 263 typedef int (*roc_plt_init_cb_t)(void); 264 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); 265 266 static inline const void * 267 plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align) 268 { 269 /* To ensure returned memory is physically contiguous, bounding 270 * the start and end address in 2M range. 271 */ 272 return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 273 RTE_MEMZONE_IOVA_CONTIG, 274 align, RTE_PGSIZE_2M); 275 } 276 277 #endif /* _ROC_PLATFORM_H_ */ 278