1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #ifndef _ROC_PLATFORM_H_
6 #define _ROC_PLATFORM_H_
7
8 #include <rte_alarm.h>
9 #include <rte_bitmap.h>
10 #include <rte_bus_pci.h>
11 #include <rte_byteorder.h>
12 #include <rte_common.h>
13 #include <rte_cycles.h>
14 #include <rte_ether.h>
15 #include <rte_interrupts.h>
16 #include <rte_io.h>
17 #include <rte_lcore.h>
18 #include <rte_log.h>
19 #include <rte_malloc.h>
20 #include <rte_memzone.h>
21 #include <rte_pci.h>
22 #include <rte_spinlock.h>
23 #include <rte_string_fns.h>
24 #include <rte_tailq.h>
25 #include <rte_telemetry.h>
26
27 #include "roc_bits.h"
28
29 #if defined(__ARM_FEATURE_SVE)
30 #define PLT_CPU_FEATURE_PREAMBLE \
31 ".arch_extension crc\n" \
32 ".arch_extension lse\n" \
33 ".arch_extension sve\n"
34 #else
35 #define PLT_CPU_FEATURE_PREAMBLE \
36 ".arch_extension crc\n" \
37 ".arch_extension lse\n"
38 #endif
39
40 #define PLT_ASSERT RTE_ASSERT
41 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE
42 #define PLT_STD_C11 RTE_STD_C11
43 #define PLT_PTR_ADD RTE_PTR_ADD
44 #define PLT_PTR_DIFF RTE_PTR_DIFF
45 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID
46 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET
47 #define PLT_MIN RTE_MIN
48 #define PLT_MAX RTE_MAX
49 #define PLT_DIM RTE_DIM
50 #define PLT_SET_USED RTE_SET_USED
51 #define PLT_SWAP RTE_SWAP
52 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s)
53 #define PLT_ALIGN RTE_ALIGN
54 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL
55 #define PLT_MODEL_MZ_NAME "roc_model_mz"
56 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE
57 #define BITMASK_ULL GENMASK_ULL
58 #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL
59 #define PLT_INIT RTE_INIT
60 #define PLT_MAX_ETHPORTS RTE_MAX_ETHPORTS
61 #define PLT_TAILQ_FOREACH_SAFE RTE_TAILQ_FOREACH_SAFE
62
63 #ifndef PLT_ETHER_ADDR_LEN
64 #define PLT_ETHER_ADDR_LEN RTE_ETHER_ADDR_LEN
65 #endif
66
67 /* Cast to specific datatypes */
68 #define PLT_PTR_CAST(val) ((void *)(val))
69 #define PLT_U64_CAST(val) ((uint64_t)(val))
70 #define PLT_U32_CAST(val) ((uint32_t)(val))
71 #define PLT_U16_CAST(val) ((uint16_t)(val))
72
73 /** Divide ceil */
74 #define PLT_DIV_CEIL(x, y) \
75 ({ \
76 __typeof(x) __x = x; \
77 __typeof(y) __y = y; \
78 (__x + __y - 1) / __y; \
79 })
80
81 #define __plt_cache_aligned __rte_cache_aligned
82 #define __plt_always_inline __rte_always_inline
83 #define __plt_packed __rte_packed
84 #define __plt_unused __rte_unused
85 #define __roc_api __rte_internal
86 #define plt_iova_t rte_iova_t
87
88 #define plt_pci_addr rte_pci_addr
89 #define plt_pci_device rte_pci_device
90 #define plt_pci_read_config rte_pci_read_config
91 #define plt_pci_find_ext_capability rte_pci_find_ext_capability
92
93 #define plt_log2_u32 rte_log2_u32
94 #define plt_cpu_to_be_16 rte_cpu_to_be_16
95 #define plt_be_to_cpu_16 rte_be_to_cpu_16
96 #define plt_cpu_to_be_32 rte_cpu_to_be_32
97 #define plt_be_to_cpu_32 rte_be_to_cpu_32
98 #define plt_cpu_to_be_64 rte_cpu_to_be_64
99 #define plt_be_to_cpu_64 rte_be_to_cpu_64
100
101 #define __plt_aligned __rte_aligned
102 #define plt_align32pow2 rte_align32pow2
103 #define plt_align32prevpow2 rte_align32prevpow2
104
105 #define plt_bitmap rte_bitmap
106 #define plt_bitmap_init rte_bitmap_init
107 #define plt_bitmap_reset rte_bitmap_reset
108 #define plt_bitmap_free rte_bitmap_free
109 #define plt_bitmap_clear rte_bitmap_clear
110 #define plt_bitmap_set rte_bitmap_set
111 #define plt_bitmap_get rte_bitmap_get
112 #define plt_bitmap_scan_init __rte_bitmap_scan_init
113 #define plt_bitmap_scan rte_bitmap_scan
114 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint
115
116 #define plt_spinlock_t rte_spinlock_t
117 #define plt_spinlock_init rte_spinlock_init
118 #define plt_spinlock_lock rte_spinlock_lock
119 #define plt_spinlock_unlock rte_spinlock_unlock
120
121 #define plt_intr_callback_register rte_intr_callback_register
122 #define plt_intr_callback_unregister rte_intr_callback_unregister
123 #define plt_intr_disable rte_intr_disable
124 #define plt_thread_is_intr rte_thread_is_intr
125 #define plt_intr_callback_fn rte_intr_callback_fn
126 #define plt_ctrl_thread_create rte_ctrl_thread_create
127
128 #define plt_intr_efd_counter_size_get rte_intr_efd_counter_size_get
129 #define plt_intr_efd_counter_size_set rte_intr_efd_counter_size_set
130 #define plt_intr_vec_list_index_get rte_intr_vec_list_index_get
131 #define plt_intr_vec_list_index_set rte_intr_vec_list_index_set
132 #define plt_intr_vec_list_alloc rte_intr_vec_list_alloc
133 #define plt_intr_vec_list_free rte_intr_vec_list_free
134 #define plt_intr_fd_set rte_intr_fd_set
135 #define plt_intr_fd_get rte_intr_fd_get
136 #define plt_intr_dev_fd_get rte_intr_dev_fd_get
137 #define plt_intr_dev_fd_set rte_intr_dev_fd_set
138 #define plt_intr_type_get rte_intr_type_get
139 #define plt_intr_type_set rte_intr_type_set
140 #define plt_intr_instance_alloc rte_intr_instance_alloc
141 #define plt_intr_instance_dup rte_intr_instance_dup
142 #define plt_intr_instance_free rte_intr_instance_free
143 #define plt_intr_event_list_update rte_intr_event_list_update
144 #define plt_intr_max_intr_get rte_intr_max_intr_get
145 #define plt_intr_max_intr_set rte_intr_max_intr_set
146 #define plt_intr_nb_efd_get rte_intr_nb_efd_get
147 #define plt_intr_nb_efd_set rte_intr_nb_efd_set
148 #define plt_intr_nb_intr_get rte_intr_nb_intr_get
149 #define plt_intr_nb_intr_set rte_intr_nb_intr_set
150 #define plt_intr_efds_index_get rte_intr_efds_index_get
151 #define plt_intr_efds_index_set rte_intr_efds_index_set
152 #define plt_intr_elist_index_get rte_intr_elist_index_get
153 #define plt_intr_elist_index_set rte_intr_elist_index_set
154
155 #define plt_alarm_set rte_eal_alarm_set
156 #define plt_alarm_cancel rte_eal_alarm_cancel
157
158 #define plt_intr_handle rte_intr_handle
159
160 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align)
161 #define plt_realloc rte_realloc
162 #define plt_free rte_free
163
164 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr))
165 #define plt_write64(val, addr) \
166 rte_write64_relaxed((val), (volatile void *)(addr))
167
168 #define plt_wmb() rte_wmb()
169 #define plt_rmb() rte_rmb()
170 #define plt_io_wmb() rte_io_wmb()
171 #define plt_io_rmb() rte_io_rmb()
172 #define plt_atomic_thread_fence rte_atomic_thread_fence
173
174 #define plt_mmap mmap
175 #define PLT_PROT_READ PROT_READ
176 #define PLT_PROT_WRITE PROT_WRITE
177 #define PLT_MAP_SHARED MAP_SHARED
178
179 #define plt_memzone rte_memzone
180 #define plt_memzone_lookup rte_memzone_lookup
181 #define plt_memzone_reserve_cache_align(name, sz) \
182 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE)
183 #define plt_memzone_free rte_memzone_free
184 #define plt_memzone_reserve_aligned(name, len, flags, align) \
185 rte_memzone_reserve_aligned((name), (len), 0, (flags), (align))
186
187 #define plt_tsc_hz rte_get_tsc_hz
188 #define plt_tsc_cycles rte_get_tsc_cycles
189 #define plt_delay_ms rte_delay_ms
190 #define plt_delay_us rte_delay_us
191
192 #define plt_lcore_id rte_lcore_id
193
194 #define plt_strlcpy rte_strlcpy
195
196 #define PLT_TEL_INT_VAL RTE_TEL_INT_VAL
197 #define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL
198 #define plt_tel_data rte_tel_data
199 #define plt_tel_data_start_array rte_tel_data_start_array
200 #define plt_tel_data_add_array_int rte_tel_data_add_array_int
201 #define plt_tel_data_add_array_string rte_tel_data_add_array_string
202 #define plt_tel_data_start_dict rte_tel_data_start_dict
203 #define plt_tel_data_add_dict_int rte_tel_data_add_dict_int
204 #define plt_tel_data_add_dict_ptr(d, n, v) \
205 rte_tel_data_add_dict_u64(d, n, (uint64_t)v)
206 #define plt_tel_data_add_dict_string rte_tel_data_add_dict_string
207 #define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_u64
208 #define plt_telemetry_register_cmd rte_telemetry_register_cmd
209
210 /* Log */
211 extern int cnxk_logtype_base;
212 extern int cnxk_logtype_mbox;
213 extern int cnxk_logtype_cpt;
214 extern int cnxk_logtype_npa;
215 extern int cnxk_logtype_nix;
216 extern int cnxk_logtype_npc;
217 extern int cnxk_logtype_sso;
218 extern int cnxk_logtype_tim;
219 extern int cnxk_logtype_tm;
220 extern int cnxk_logtype_ree;
221
222 #define plt_err(fmt, args...) \
223 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
224 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args)
225 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args)
226 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args)
227 #define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
228 #define plt_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__)
229
230 /**
231 * Log debug message if given subsystem logging is enabled.
232 */
233 #define plt_dbg(subsystem, fmt, args...) \
234 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \
235 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \
236 ##args)
237
238 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__)
239 #define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__)
240 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__)
241 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__)
242 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__)
243 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__)
244 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__)
245 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__)
246 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__)
247 #define plt_ree_dbg(fmt, ...) plt_dbg(ree, fmt, ##__VA_ARGS__)
248
249 /* Datapath logs */
250 #define plt_dp_err(fmt, args...) \
251 RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
252 #define plt_dp_info(fmt, args...) \
253 RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
254
255 #ifdef __cplusplus
256 #define CNXK_PCI_ID(subsystem_dev, dev) \
257 { \
258 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \
259 (subsystem_dev), \
260 }
261 #else
262 #define CNXK_PCI_ID(subsystem_dev, dev) \
263 { \
264 .class_id = RTE_CLASS_ANY_ID, \
265 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \
266 .subsystem_vendor_id = RTE_PCI_ANY_ID, \
267 .subsystem_device_id = (subsystem_dev), \
268 }
269 #endif
270
271 __rte_internal
272 int roc_plt_init(void);
273
274 /* Init callbacks */
275 typedef int (*roc_plt_init_cb_t)(void);
276 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb);
277
278 static inline const void *
plt_lmt_region_reserve_aligned(const char * name,size_t len,uint32_t align)279 plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align)
280 {
281 /* To ensure returned memory is physically contiguous, bounding
282 * the start and end address in 2M range.
283 */
284 return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY,
285 RTE_MEMZONE_IOVA_CONTIG,
286 align, RTE_PGSIZE_2M);
287 }
288
289 #endif /* _ROC_PLATFORM_H_ */
290