1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_PLATFORM_H_ 6 #define _ROC_PLATFORM_H_ 7 8 #include <rte_alarm.h> 9 #include <rte_bitmap.h> 10 #include <rte_bus_pci.h> 11 #include <rte_byteorder.h> 12 #include <rte_common.h> 13 #include <rte_cycles.h> 14 #include <rte_ether.h> 15 #include <rte_interrupts.h> 16 #include <rte_io.h> 17 #include <rte_lcore.h> 18 #include <rte_log.h> 19 #include <rte_malloc.h> 20 #include <rte_memzone.h> 21 #include <rte_pci.h> 22 #include <rte_spinlock.h> 23 #include <rte_string_fns.h> 24 #include <rte_tailq.h> 25 #include <rte_telemetry.h> 26 27 #include "roc_bits.h" 28 29 #if defined(__ARM_FEATURE_SVE) 30 #define PLT_CPU_FEATURE_PREAMBLE \ 31 ".arch_extension crc\n" \ 32 ".arch_extension lse\n" \ 33 ".arch_extension sve\n" 34 #else 35 #define PLT_CPU_FEATURE_PREAMBLE \ 36 ".arch_extension crc\n" \ 37 ".arch_extension lse\n" 38 #endif 39 40 #define PLT_ASSERT RTE_ASSERT 41 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE 42 #define PLT_STD_C11 RTE_STD_C11 43 #define PLT_PTR_ADD RTE_PTR_ADD 44 #define PLT_PTR_DIFF RTE_PTR_DIFF 45 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID 46 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET 47 #define PLT_MIN RTE_MIN 48 #define PLT_MAX RTE_MAX 49 #define PLT_DIM RTE_DIM 50 #define PLT_SET_USED RTE_SET_USED 51 #define PLT_SWAP RTE_SWAP 52 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) 53 #define PLT_ALIGN RTE_ALIGN 54 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL 55 #define PLT_MODEL_MZ_NAME "roc_model_mz" 56 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE 57 #define BITMASK_ULL GENMASK_ULL 58 #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL 59 #define PLT_INIT RTE_INIT 60 #define PLT_MAX_ETHPORTS RTE_MAX_ETHPORTS 61 #define PLT_TAILQ_FOREACH_SAFE RTE_TAILQ_FOREACH_SAFE 62 63 #ifndef PLT_ETHER_ADDR_LEN 64 #define PLT_ETHER_ADDR_LEN RTE_ETHER_ADDR_LEN 65 #endif 66 /** Divide ceil */ 67 #define PLT_DIV_CEIL(x, y) \ 68 ({ \ 69 __typeof(x) __x = x; \ 70 __typeof(y) __y = y; \ 71 (__x + __y - 1) / __y; \ 72 }) 73 74 #define __plt_cache_aligned __rte_cache_aligned 75 #define __plt_always_inline __rte_always_inline 76 #define __plt_packed __rte_packed 77 #define __plt_unused __rte_unused 78 #define __roc_api __rte_internal 79 #define plt_iova_t rte_iova_t 80 81 #define plt_pci_addr rte_pci_addr 82 #define plt_pci_device rte_pci_device 83 #define plt_pci_read_config rte_pci_read_config 84 #define plt_pci_find_ext_capability rte_pci_find_ext_capability 85 86 #define plt_log2_u32 rte_log2_u32 87 #define plt_cpu_to_be_16 rte_cpu_to_be_16 88 #define plt_be_to_cpu_16 rte_be_to_cpu_16 89 #define plt_cpu_to_be_32 rte_cpu_to_be_32 90 #define plt_be_to_cpu_32 rte_be_to_cpu_32 91 #define plt_cpu_to_be_64 rte_cpu_to_be_64 92 #define plt_be_to_cpu_64 rte_be_to_cpu_64 93 94 #define plt_aligned __rte_aligned 95 #define plt_align32pow2 rte_align32pow2 96 #define plt_align32prevpow2 rte_align32prevpow2 97 98 #define plt_bitmap rte_bitmap 99 #define plt_bitmap_init rte_bitmap_init 100 #define plt_bitmap_reset rte_bitmap_reset 101 #define plt_bitmap_free rte_bitmap_free 102 #define plt_bitmap_clear rte_bitmap_clear 103 #define plt_bitmap_set rte_bitmap_set 104 #define plt_bitmap_get rte_bitmap_get 105 #define plt_bitmap_scan_init __rte_bitmap_scan_init 106 #define plt_bitmap_scan rte_bitmap_scan 107 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint 108 109 #define plt_spinlock_t rte_spinlock_t 110 #define plt_spinlock_init rte_spinlock_init 111 #define plt_spinlock_lock rte_spinlock_lock 112 #define plt_spinlock_unlock rte_spinlock_unlock 113 114 #define plt_intr_callback_register rte_intr_callback_register 115 #define plt_intr_callback_unregister rte_intr_callback_unregister 116 #define plt_intr_disable rte_intr_disable 117 #define plt_thread_is_intr rte_thread_is_intr 118 #define plt_intr_callback_fn rte_intr_callback_fn 119 #define plt_ctrl_thread_create rte_ctrl_thread_create 120 121 #define plt_intr_efd_counter_size_get rte_intr_efd_counter_size_get 122 #define plt_intr_efd_counter_size_set rte_intr_efd_counter_size_set 123 #define plt_intr_vec_list_index_get rte_intr_vec_list_index_get 124 #define plt_intr_vec_list_index_set rte_intr_vec_list_index_set 125 #define plt_intr_vec_list_alloc rte_intr_vec_list_alloc 126 #define plt_intr_vec_list_free rte_intr_vec_list_free 127 #define plt_intr_fd_set rte_intr_fd_set 128 #define plt_intr_fd_get rte_intr_fd_get 129 #define plt_intr_dev_fd_get rte_intr_dev_fd_get 130 #define plt_intr_dev_fd_set rte_intr_dev_fd_set 131 #define plt_intr_type_get rte_intr_type_get 132 #define plt_intr_type_set rte_intr_type_set 133 #define plt_intr_instance_alloc rte_intr_instance_alloc 134 #define plt_intr_instance_dup rte_intr_instance_dup 135 #define plt_intr_instance_free rte_intr_instance_free 136 #define plt_intr_event_list_update rte_intr_event_list_update 137 #define plt_intr_max_intr_get rte_intr_max_intr_get 138 #define plt_intr_max_intr_set rte_intr_max_intr_set 139 #define plt_intr_nb_efd_get rte_intr_nb_efd_get 140 #define plt_intr_nb_efd_set rte_intr_nb_efd_set 141 #define plt_intr_nb_intr_get rte_intr_nb_intr_get 142 #define plt_intr_nb_intr_set rte_intr_nb_intr_set 143 #define plt_intr_efds_index_get rte_intr_efds_index_get 144 #define plt_intr_efds_index_set rte_intr_efds_index_set 145 #define plt_intr_elist_index_get rte_intr_elist_index_get 146 #define plt_intr_elist_index_set rte_intr_elist_index_set 147 148 #define plt_alarm_set rte_eal_alarm_set 149 #define plt_alarm_cancel rte_eal_alarm_cancel 150 151 #define plt_intr_handle rte_intr_handle 152 153 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) 154 #define plt_realloc rte_realloc 155 #define plt_free rte_free 156 157 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 158 #define plt_write64(val, addr) \ 159 rte_write64_relaxed((val), (volatile void *)(addr)) 160 161 #define plt_wmb() rte_wmb() 162 #define plt_rmb() rte_rmb() 163 #define plt_io_wmb() rte_io_wmb() 164 #define plt_io_rmb() rte_io_rmb() 165 #define plt_atomic_thread_fence rte_atomic_thread_fence 166 167 #define plt_mmap mmap 168 #define PLT_PROT_READ PROT_READ 169 #define PLT_PROT_WRITE PROT_WRITE 170 #define PLT_MAP_SHARED MAP_SHARED 171 172 #define plt_memzone rte_memzone 173 #define plt_memzone_lookup rte_memzone_lookup 174 #define plt_memzone_reserve_cache_align(name, sz) \ 175 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) 176 #define plt_memzone_free rte_memzone_free 177 #define plt_memzone_reserve_aligned(name, len, flags, align) \ 178 rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) 179 180 #define plt_tsc_hz rte_get_tsc_hz 181 #define plt_delay_ms rte_delay_ms 182 #define plt_delay_us rte_delay_us 183 184 #define plt_lcore_id rte_lcore_id 185 186 #define plt_strlcpy rte_strlcpy 187 188 #define PLT_TEL_INT_VAL RTE_TEL_INT_VAL 189 #define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL 190 #define plt_tel_data rte_tel_data 191 #define plt_tel_data_start_array rte_tel_data_start_array 192 #define plt_tel_data_add_array_int rte_tel_data_add_array_int 193 #define plt_tel_data_add_array_string rte_tel_data_add_array_string 194 #define plt_tel_data_start_dict rte_tel_data_start_dict 195 #define plt_tel_data_add_dict_int rte_tel_data_add_dict_int 196 #define plt_tel_data_add_dict_ptr(d, n, v) \ 197 rte_tel_data_add_dict_u64(d, n, (uint64_t)v) 198 #define plt_tel_data_add_dict_string rte_tel_data_add_dict_string 199 #define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_u64 200 #define plt_telemetry_register_cmd rte_telemetry_register_cmd 201 202 /* Log */ 203 extern int cnxk_logtype_base; 204 extern int cnxk_logtype_mbox; 205 extern int cnxk_logtype_cpt; 206 extern int cnxk_logtype_npa; 207 extern int cnxk_logtype_nix; 208 extern int cnxk_logtype_npc; 209 extern int cnxk_logtype_sso; 210 extern int cnxk_logtype_tim; 211 extern int cnxk_logtype_tm; 212 extern int cnxk_logtype_ree; 213 214 #define plt_err(fmt, args...) \ 215 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 216 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 217 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args) 218 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 219 #define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__) 220 #define plt_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__) 221 222 /** 223 * Log debug message if given subsystem logging is enabled. 224 */ 225 #define plt_dbg(subsystem, fmt, args...) \ 226 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \ 227 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \ 228 ##args) 229 230 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) 231 #define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) 232 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) 233 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) 234 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) 235 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) 236 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) 237 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) 238 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) 239 #define plt_ree_dbg(fmt, ...) plt_dbg(ree, fmt, ##__VA_ARGS__) 240 241 /* Datapath logs */ 242 #define plt_dp_err(fmt, args...) \ 243 RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 244 #define plt_dp_info(fmt, args...) \ 245 RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 246 247 #ifdef __cplusplus 248 #define CNXK_PCI_ID(subsystem_dev, dev) \ 249 { \ 250 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ 251 (subsystem_dev), \ 252 } 253 #else 254 #define CNXK_PCI_ID(subsystem_dev, dev) \ 255 { \ 256 .class_id = RTE_CLASS_ANY_ID, \ 257 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ 258 .subsystem_vendor_id = RTE_PCI_ANY_ID, \ 259 .subsystem_device_id = (subsystem_dev), \ 260 } 261 #endif 262 263 __rte_internal 264 int roc_plt_init(void); 265 266 /* Init callbacks */ 267 typedef int (*roc_plt_init_cb_t)(void); 268 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); 269 270 static inline const void * 271 plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align) 272 { 273 /* To ensure returned memory is physically contiguous, bounding 274 * the start and end address in 2M range. 275 */ 276 return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 277 RTE_MEMZONE_IOVA_CONTIG, 278 align, RTE_PGSIZE_2M); 279 } 280 281 #endif /* _ROC_PLATFORM_H_ */ 282