1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_PLATFORM_H_ 6 #define _ROC_PLATFORM_H_ 7 8 #include <rte_alarm.h> 9 #include <rte_bitmap.h> 10 #include <rte_bus_pci.h> 11 #include <rte_byteorder.h> 12 #include <rte_common.h> 13 #include <rte_cycles.h> 14 #include <rte_interrupts.h> 15 #include <rte_io.h> 16 #include <rte_log.h> 17 #include <rte_malloc.h> 18 #include <rte_memzone.h> 19 #include <rte_pci.h> 20 #include <rte_spinlock.h> 21 #include <rte_string_fns.h> 22 23 #include "roc_bits.h" 24 25 #if defined(__ARM_FEATURE_SVE) 26 #define PLT_CPU_FEATURE_PREAMBLE \ 27 ".arch_extension crc\n" \ 28 ".arch_extension lse\n" \ 29 ".arch_extension sve\n" 30 #else 31 #define PLT_CPU_FEATURE_PREAMBLE \ 32 ".arch_extension crc\n" \ 33 ".arch_extension lse\n" 34 #endif 35 36 #define PLT_ASSERT RTE_ASSERT 37 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE 38 #define PLT_STD_C11 RTE_STD_C11 39 #define PLT_PTR_ADD RTE_PTR_ADD 40 #define PLT_PTR_DIFF RTE_PTR_DIFF 41 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID 42 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET 43 #define PLT_MIN RTE_MIN 44 #define PLT_MAX RTE_MAX 45 #define PLT_DIM RTE_DIM 46 #define PLT_SET_USED RTE_SET_USED 47 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) 48 #define PLT_ALIGN RTE_ALIGN 49 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL 50 #define PLT_MODEL_MZ_NAME "roc_model_mz" 51 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE 52 #define BITMASK_ULL GENMASK_ULL 53 #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL 54 55 /** Divide ceil */ 56 #define PLT_DIV_CEIL(x, y) \ 57 ({ \ 58 __typeof(x) __x = x; \ 59 __typeof(y) __y = y; \ 60 (__x + __y - 1) / __y; \ 61 }) 62 63 #define __plt_cache_aligned __rte_cache_aligned 64 #define __plt_always_inline __rte_always_inline 65 #define __plt_packed __rte_packed 66 #define __roc_api __rte_internal 67 #define plt_iova_t rte_iova_t 68 69 #define plt_pci_device rte_pci_device 70 #define plt_pci_read_config rte_pci_read_config 71 #define plt_pci_find_ext_capability rte_pci_find_ext_capability 72 73 #define plt_log2_u32 rte_log2_u32 74 #define plt_cpu_to_be_16 rte_cpu_to_be_16 75 #define plt_be_to_cpu_16 rte_be_to_cpu_16 76 #define plt_cpu_to_be_32 rte_cpu_to_be_32 77 #define plt_be_to_cpu_32 rte_be_to_cpu_32 78 #define plt_cpu_to_be_64 rte_cpu_to_be_64 79 #define plt_be_to_cpu_64 rte_be_to_cpu_64 80 81 #define plt_align32pow2 rte_align32pow2 82 #define plt_align32prevpow2 rte_align32prevpow2 83 84 #define plt_bitmap rte_bitmap 85 #define plt_bitmap_init rte_bitmap_init 86 #define plt_bitmap_reset rte_bitmap_reset 87 #define plt_bitmap_free rte_bitmap_free 88 #define plt_bitmap_clear rte_bitmap_clear 89 #define plt_bitmap_set rte_bitmap_set 90 #define plt_bitmap_get rte_bitmap_get 91 #define plt_bitmap_scan_init __rte_bitmap_scan_init 92 #define plt_bitmap_scan rte_bitmap_scan 93 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint 94 95 #define plt_spinlock_t rte_spinlock_t 96 #define plt_spinlock_init rte_spinlock_init 97 #define plt_spinlock_lock rte_spinlock_lock 98 #define plt_spinlock_unlock rte_spinlock_unlock 99 100 #define plt_intr_callback_register rte_intr_callback_register 101 #define plt_intr_callback_unregister rte_intr_callback_unregister 102 #define plt_intr_disable rte_intr_disable 103 #define plt_thread_is_intr rte_thread_is_intr 104 #define plt_intr_callback_fn rte_intr_callback_fn 105 106 #define plt_alarm_set rte_eal_alarm_set 107 #define plt_alarm_cancel rte_eal_alarm_cancel 108 109 #define plt_intr_handle rte_intr_handle 110 111 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) 112 #define plt_free rte_free 113 114 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 115 #define plt_write64(val, addr) \ 116 rte_write64_relaxed((val), (volatile void *)(addr)) 117 118 #define plt_wmb() rte_wmb() 119 #define plt_rmb() rte_rmb() 120 #define plt_io_wmb() rte_io_wmb() 121 #define plt_io_rmb() rte_io_rmb() 122 #define plt_atomic_thread_fence rte_atomic_thread_fence 123 124 #define plt_mmap mmap 125 #define PLT_PROT_READ PROT_READ 126 #define PLT_PROT_WRITE PROT_WRITE 127 #define PLT_MAP_SHARED MAP_SHARED 128 129 #define plt_memzone rte_memzone 130 #define plt_memzone_lookup rte_memzone_lookup 131 #define plt_memzone_reserve_cache_align(name, sz) \ 132 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) 133 #define plt_memzone_free rte_memzone_free 134 #define plt_memzone_reserve_aligned(name, len, flags, align) \ 135 rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) 136 137 #define plt_tsc_hz rte_get_tsc_hz 138 #define plt_delay_ms rte_delay_ms 139 #define plt_delay_us rte_delay_us 140 141 #define plt_lcore_id rte_lcore_id 142 143 #define plt_strlcpy rte_strlcpy 144 145 /* Log */ 146 extern int cnxk_logtype_base; 147 extern int cnxk_logtype_mbox; 148 extern int cnxk_logtype_cpt; 149 extern int cnxk_logtype_npa; 150 extern int cnxk_logtype_nix; 151 extern int cnxk_logtype_npc; 152 extern int cnxk_logtype_sso; 153 extern int cnxk_logtype_tim; 154 extern int cnxk_logtype_tm; 155 156 #define plt_err(fmt, args...) \ 157 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 158 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 159 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args) 160 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 161 162 /** 163 * Log debug message if given subsystem logging is enabled. 164 */ 165 #define plt_dbg(subsystem, fmt, args...) \ 166 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \ 167 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \ 168 ##args) 169 170 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) 171 #define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) 172 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) 173 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) 174 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) 175 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) 176 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) 177 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) 178 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) 179 180 /* Datapath logs */ 181 #define plt_dp_err(fmt, args...) \ 182 RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 183 #define plt_dp_info(fmt, args...) \ 184 RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 185 186 #ifdef __cplusplus 187 #define CNXK_PCI_ID(subsystem_dev, dev) \ 188 { \ 189 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ 190 (subsystem_dev), \ 191 } 192 #else 193 #define CNXK_PCI_ID(subsystem_dev, dev) \ 194 { \ 195 .class_id = RTE_CLASS_ANY_ID, \ 196 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ 197 .subsystem_vendor_id = RTE_PCI_ANY_ID, \ 198 .subsystem_device_id = (subsystem_dev), \ 199 } 200 #endif 201 202 __rte_internal 203 int roc_plt_init(void); 204 205 /* Init callbacks */ 206 typedef int (*roc_plt_init_cb_t)(void); 207 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); 208 209 static inline const void * 210 plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align) 211 { 212 /* To ensure returned memory is physically contiguous, bounding 213 * the start and end address in 2M range. 214 */ 215 return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 216 RTE_MEMZONE_IOVA_CONTIG, 217 align, RTE_PGSIZE_2M); 218 } 219 220 #endif /* _ROC_PLATFORM_H_ */ 221