1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_PLATFORM_H_ 6 #define _ROC_PLATFORM_H_ 7 8 #include <rte_alarm.h> 9 #include <rte_bitmap.h> 10 #include <rte_bus_pci.h> 11 #include <rte_byteorder.h> 12 #include <rte_common.h> 13 #include <rte_cycles.h> 14 #include <rte_interrupts.h> 15 #include <rte_io.h> 16 #include <rte_log.h> 17 #include <rte_malloc.h> 18 #include <rte_memzone.h> 19 #include <rte_pci.h> 20 #include <rte_spinlock.h> 21 #include <rte_string_fns.h> 22 23 #include "roc_bits.h" 24 25 #if defined(__ARM_FEATURE_SVE) 26 #define PLT_CPU_FEATURE_PREAMBLE \ 27 ".arch_extension crc\n" \ 28 ".arch_extension lse\n" \ 29 ".arch_extension sve\n" 30 #else 31 #define PLT_CPU_FEATURE_PREAMBLE \ 32 ".arch_extension crc\n" \ 33 ".arch_extension lse\n" 34 #endif 35 36 #define PLT_ASSERT RTE_ASSERT 37 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE 38 #define PLT_STD_C11 RTE_STD_C11 39 #define PLT_PTR_ADD RTE_PTR_ADD 40 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID 41 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET 42 #define PLT_MIN RTE_MIN 43 #define PLT_MAX RTE_MAX 44 #define PLT_DIM RTE_DIM 45 #define PLT_SET_USED RTE_SET_USED 46 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) 47 #define PLT_ALIGN RTE_ALIGN 48 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL 49 #define PLT_MODEL_MZ_NAME "roc_model_mz" 50 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE 51 #define BITMASK_ULL GENMASK_ULL 52 53 /** Divide ceil */ 54 #define PLT_DIV_CEIL(x, y) \ 55 ({ \ 56 __typeof(x) __x = x; \ 57 __typeof(y) __y = y; \ 58 (__x + __y - 1) / __y; \ 59 }) 60 61 #define __plt_cache_aligned __rte_cache_aligned 62 #define __plt_always_inline __rte_always_inline 63 #define __plt_packed __rte_packed 64 #define __roc_api __rte_internal 65 #define plt_iova_t rte_iova_t 66 67 #define plt_pci_device rte_pci_device 68 #define plt_pci_read_config rte_pci_read_config 69 #define plt_pci_find_ext_capability rte_pci_find_ext_capability 70 71 #define plt_log2_u32 rte_log2_u32 72 #define plt_cpu_to_be_16 rte_cpu_to_be_16 73 #define plt_be_to_cpu_16 rte_be_to_cpu_16 74 #define plt_cpu_to_be_32 rte_cpu_to_be_32 75 #define plt_be_to_cpu_32 rte_be_to_cpu_32 76 #define plt_cpu_to_be_64 rte_cpu_to_be_64 77 #define plt_be_to_cpu_64 rte_be_to_cpu_64 78 79 #define plt_align32prevpow2 rte_align32prevpow2 80 81 #define plt_bitmap rte_bitmap 82 #define plt_bitmap_init rte_bitmap_init 83 #define plt_bitmap_reset rte_bitmap_reset 84 #define plt_bitmap_free rte_bitmap_free 85 #define plt_bitmap_clear rte_bitmap_clear 86 #define plt_bitmap_set rte_bitmap_set 87 #define plt_bitmap_get rte_bitmap_get 88 #define plt_bitmap_scan_init __rte_bitmap_scan_init 89 #define plt_bitmap_scan rte_bitmap_scan 90 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint 91 92 #define plt_spinlock_t rte_spinlock_t 93 #define plt_spinlock_init rte_spinlock_init 94 #define plt_spinlock_lock rte_spinlock_lock 95 #define plt_spinlock_unlock rte_spinlock_unlock 96 97 #define plt_intr_callback_register rte_intr_callback_register 98 #define plt_intr_callback_unregister rte_intr_callback_unregister 99 #define plt_intr_disable rte_intr_disable 100 #define plt_thread_is_intr rte_thread_is_intr 101 #define plt_intr_callback_fn rte_intr_callback_fn 102 103 #define plt_alarm_set rte_eal_alarm_set 104 #define plt_alarm_cancel rte_eal_alarm_cancel 105 106 #define plt_intr_handle rte_intr_handle 107 108 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) 109 #define plt_free rte_free 110 111 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 112 #define plt_write64(val, addr) \ 113 rte_write64_relaxed((val), (volatile void *)(addr)) 114 115 #define plt_wmb() rte_wmb() 116 #define plt_rmb() rte_rmb() 117 #define plt_io_wmb() rte_io_wmb() 118 #define plt_io_rmb() rte_io_rmb() 119 120 #define plt_mmap mmap 121 #define PLT_PROT_READ PROT_READ 122 #define PLT_PROT_WRITE PROT_WRITE 123 #define PLT_MAP_SHARED MAP_SHARED 124 125 #define plt_memzone rte_memzone 126 #define plt_memzone_lookup rte_memzone_lookup 127 #define plt_memzone_reserve_cache_align(name, sz) \ 128 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) 129 #define plt_memzone_free rte_memzone_free 130 131 #define plt_tsc_hz rte_get_tsc_hz 132 #define plt_delay_ms rte_delay_ms 133 #define plt_delay_us rte_delay_us 134 135 #define plt_lcore_id rte_lcore_id 136 137 #define plt_strlcpy rte_strlcpy 138 139 /* Log */ 140 extern int cnxk_logtype_base; 141 extern int cnxk_logtype_mbox; 142 extern int cnxk_logtype_npa; 143 extern int cnxk_logtype_nix; 144 extern int cnxk_logtype_npc; 145 extern int cnxk_logtype_sso; 146 extern int cnxk_logtype_tim; 147 extern int cnxk_logtype_tm; 148 149 #define plt_err(fmt, args...) \ 150 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 151 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 152 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args) 153 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 154 155 /** 156 * Log debug message if given subsystem logging is enabled. 157 */ 158 #define plt_dbg(subsystem, fmt, args...) \ 159 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \ 160 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \ 161 ##args) 162 163 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) 164 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) 165 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) 166 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) 167 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) 168 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) 169 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) 170 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) 171 172 #ifdef __cplusplus 173 #define CNXK_PCI_ID(subsystem_dev, dev) \ 174 { \ 175 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ 176 (subsystem_dev), \ 177 } 178 #else 179 #define CNXK_PCI_ID(subsystem_dev, dev) \ 180 { \ 181 .class_id = RTE_CLASS_ANY_ID, \ 182 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ 183 .subsystem_vendor_id = RTE_PCI_ANY_ID, \ 184 .subsystem_device_id = (subsystem_dev), \ 185 } 186 #endif 187 188 __rte_internal 189 int roc_plt_init(void); 190 191 /* Init callbacks */ 192 typedef int (*roc_plt_init_cb_t)(void); 193 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); 194 195 #endif /* _ROC_PLATFORM_H_ */ 196