1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_PLATFORM_H_ 6 #define _ROC_PLATFORM_H_ 7 8 #include <rte_alarm.h> 9 #include <rte_bitmap.h> 10 #include <rte_bus_pci.h> 11 #include <rte_byteorder.h> 12 #include <rte_common.h> 13 #include <rte_cycles.h> 14 #include <rte_interrupts.h> 15 #include <rte_io.h> 16 #include <rte_log.h> 17 #include <rte_malloc.h> 18 #include <rte_memzone.h> 19 #include <rte_pci.h> 20 #include <rte_spinlock.h> 21 #include <rte_string_fns.h> 22 #include <rte_telemetry.h> 23 24 #include "roc_bits.h" 25 26 #if defined(__ARM_FEATURE_SVE) 27 #define PLT_CPU_FEATURE_PREAMBLE \ 28 ".arch_extension crc\n" \ 29 ".arch_extension lse\n" \ 30 ".arch_extension sve\n" 31 #else 32 #define PLT_CPU_FEATURE_PREAMBLE \ 33 ".arch_extension crc\n" \ 34 ".arch_extension lse\n" 35 #endif 36 37 #define PLT_ASSERT RTE_ASSERT 38 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE 39 #define PLT_STD_C11 RTE_STD_C11 40 #define PLT_PTR_ADD RTE_PTR_ADD 41 #define PLT_PTR_DIFF RTE_PTR_DIFF 42 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID 43 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET 44 #define PLT_MIN RTE_MIN 45 #define PLT_MAX RTE_MAX 46 #define PLT_DIM RTE_DIM 47 #define PLT_SET_USED RTE_SET_USED 48 #define PLT_SWAP RTE_SWAP 49 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) 50 #define PLT_ALIGN RTE_ALIGN 51 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL 52 #define PLT_MODEL_MZ_NAME "roc_model_mz" 53 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE 54 #define BITMASK_ULL GENMASK_ULL 55 #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL 56 #define PLT_INIT RTE_INIT 57 58 /** Divide ceil */ 59 #define PLT_DIV_CEIL(x, y) \ 60 ({ \ 61 __typeof(x) __x = x; \ 62 __typeof(y) __y = y; \ 63 (__x + __y - 1) / __y; \ 64 }) 65 66 #define __plt_cache_aligned __rte_cache_aligned 67 #define __plt_always_inline __rte_always_inline 68 #define __plt_packed __rte_packed 69 #define __plt_unused __rte_unused 70 #define __roc_api __rte_internal 71 #define plt_iova_t rte_iova_t 72 73 #define plt_pci_addr rte_pci_addr 74 #define plt_pci_device rte_pci_device 75 #define plt_pci_read_config rte_pci_read_config 76 #define plt_pci_find_ext_capability rte_pci_find_ext_capability 77 78 #define plt_log2_u32 rte_log2_u32 79 #define plt_cpu_to_be_16 rte_cpu_to_be_16 80 #define plt_be_to_cpu_16 rte_be_to_cpu_16 81 #define plt_cpu_to_be_32 rte_cpu_to_be_32 82 #define plt_be_to_cpu_32 rte_be_to_cpu_32 83 #define plt_cpu_to_be_64 rte_cpu_to_be_64 84 #define plt_be_to_cpu_64 rte_be_to_cpu_64 85 86 #define plt_align32pow2 rte_align32pow2 87 #define plt_align32prevpow2 rte_align32prevpow2 88 89 #define plt_bitmap rte_bitmap 90 #define plt_bitmap_init rte_bitmap_init 91 #define plt_bitmap_reset rte_bitmap_reset 92 #define plt_bitmap_free rte_bitmap_free 93 #define plt_bitmap_clear rte_bitmap_clear 94 #define plt_bitmap_set rte_bitmap_set 95 #define plt_bitmap_get rte_bitmap_get 96 #define plt_bitmap_scan_init __rte_bitmap_scan_init 97 #define plt_bitmap_scan rte_bitmap_scan 98 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint 99 100 #define plt_spinlock_t rte_spinlock_t 101 #define plt_spinlock_init rte_spinlock_init 102 #define plt_spinlock_lock rte_spinlock_lock 103 #define plt_spinlock_unlock rte_spinlock_unlock 104 105 #define plt_intr_callback_register rte_intr_callback_register 106 #define plt_intr_callback_unregister rte_intr_callback_unregister 107 #define plt_intr_disable rte_intr_disable 108 #define plt_thread_is_intr rte_thread_is_intr 109 #define plt_intr_callback_fn rte_intr_callback_fn 110 111 #define plt_intr_efd_counter_size_get rte_intr_efd_counter_size_get 112 #define plt_intr_efd_counter_size_set rte_intr_efd_counter_size_set 113 #define plt_intr_vec_list_index_get rte_intr_vec_list_index_get 114 #define plt_intr_vec_list_index_set rte_intr_vec_list_index_set 115 #define plt_intr_vec_list_alloc rte_intr_vec_list_alloc 116 #define plt_intr_vec_list_free rte_intr_vec_list_free 117 #define plt_intr_fd_set rte_intr_fd_set 118 #define plt_intr_fd_get rte_intr_fd_get 119 #define plt_intr_dev_fd_get rte_intr_dev_fd_get 120 #define plt_intr_dev_fd_set rte_intr_dev_fd_set 121 #define plt_intr_type_get rte_intr_type_get 122 #define plt_intr_type_set rte_intr_type_set 123 #define plt_intr_instance_alloc rte_intr_instance_alloc 124 #define plt_intr_instance_dup rte_intr_instance_dup 125 #define plt_intr_instance_free rte_intr_instance_free 126 #define plt_intr_event_list_update rte_intr_event_list_update 127 #define plt_intr_max_intr_get rte_intr_max_intr_get 128 #define plt_intr_max_intr_set rte_intr_max_intr_set 129 #define plt_intr_nb_efd_get rte_intr_nb_efd_get 130 #define plt_intr_nb_efd_set rte_intr_nb_efd_set 131 #define plt_intr_nb_intr_get rte_intr_nb_intr_get 132 #define plt_intr_nb_intr_set rte_intr_nb_intr_set 133 #define plt_intr_efds_index_get rte_intr_efds_index_get 134 #define plt_intr_efds_index_set rte_intr_efds_index_set 135 #define plt_intr_elist_index_get rte_intr_elist_index_get 136 #define plt_intr_elist_index_set rte_intr_elist_index_set 137 138 #define plt_alarm_set rte_eal_alarm_set 139 #define plt_alarm_cancel rte_eal_alarm_cancel 140 141 #define plt_intr_handle rte_intr_handle 142 143 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) 144 #define plt_free rte_free 145 146 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 147 #define plt_write64(val, addr) \ 148 rte_write64_relaxed((val), (volatile void *)(addr)) 149 150 #define plt_wmb() rte_wmb() 151 #define plt_rmb() rte_rmb() 152 #define plt_io_wmb() rte_io_wmb() 153 #define plt_io_rmb() rte_io_rmb() 154 #define plt_atomic_thread_fence rte_atomic_thread_fence 155 156 #define plt_mmap mmap 157 #define PLT_PROT_READ PROT_READ 158 #define PLT_PROT_WRITE PROT_WRITE 159 #define PLT_MAP_SHARED MAP_SHARED 160 161 #define plt_memzone rte_memzone 162 #define plt_memzone_lookup rte_memzone_lookup 163 #define plt_memzone_reserve_cache_align(name, sz) \ 164 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) 165 #define plt_memzone_free rte_memzone_free 166 #define plt_memzone_reserve_aligned(name, len, flags, align) \ 167 rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) 168 169 #define plt_tsc_hz rte_get_tsc_hz 170 #define plt_delay_ms rte_delay_ms 171 #define plt_delay_us rte_delay_us 172 173 #define plt_lcore_id rte_lcore_id 174 175 #define plt_strlcpy rte_strlcpy 176 177 #define PLT_TEL_INT_VAL RTE_TEL_INT_VAL 178 #define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL 179 #define plt_tel_data rte_tel_data 180 #define plt_tel_data_start_array rte_tel_data_start_array 181 #define plt_tel_data_add_array_int rte_tel_data_add_array_int 182 #define plt_tel_data_add_array_string rte_tel_data_add_array_string 183 #define plt_tel_data_start_dict rte_tel_data_start_dict 184 #define plt_tel_data_add_dict_int rte_tel_data_add_dict_int 185 #define plt_tel_data_add_dict_ptr(d, n, v) \ 186 rte_tel_data_add_dict_u64(d, n, (uint64_t)v) 187 #define plt_tel_data_add_dict_string rte_tel_data_add_dict_string 188 #define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_u64 189 #define plt_telemetry_register_cmd rte_telemetry_register_cmd 190 191 /* Log */ 192 extern int cnxk_logtype_base; 193 extern int cnxk_logtype_mbox; 194 extern int cnxk_logtype_cpt; 195 extern int cnxk_logtype_npa; 196 extern int cnxk_logtype_nix; 197 extern int cnxk_logtype_npc; 198 extern int cnxk_logtype_sso; 199 extern int cnxk_logtype_tim; 200 extern int cnxk_logtype_tm; 201 extern int cnxk_logtype_ree; 202 203 #define plt_err(fmt, args...) \ 204 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 205 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 206 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args) 207 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 208 #define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__) 209 210 /** 211 * Log debug message if given subsystem logging is enabled. 212 */ 213 #define plt_dbg(subsystem, fmt, args...) \ 214 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \ 215 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \ 216 ##args) 217 218 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) 219 #define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) 220 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) 221 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) 222 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) 223 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) 224 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) 225 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) 226 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) 227 #define plt_ree_dbg(fmt, ...) plt_dbg(ree, fmt, ##__VA_ARGS__) 228 229 /* Datapath logs */ 230 #define plt_dp_err(fmt, args...) \ 231 RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 232 #define plt_dp_info(fmt, args...) \ 233 RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 234 235 #ifdef __cplusplus 236 #define CNXK_PCI_ID(subsystem_dev, dev) \ 237 { \ 238 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ 239 (subsystem_dev), \ 240 } 241 #else 242 #define CNXK_PCI_ID(subsystem_dev, dev) \ 243 { \ 244 .class_id = RTE_CLASS_ANY_ID, \ 245 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ 246 .subsystem_vendor_id = RTE_PCI_ANY_ID, \ 247 .subsystem_device_id = (subsystem_dev), \ 248 } 249 #endif 250 251 __rte_internal 252 int roc_plt_init(void); 253 254 /* Init callbacks */ 255 typedef int (*roc_plt_init_cb_t)(void); 256 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); 257 258 static inline const void * 259 plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align) 260 { 261 /* To ensure returned memory is physically contiguous, bounding 262 * the start and end address in 2M range. 263 */ 264 return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 265 RTE_MEMZONE_IOVA_CONTIG, 266 align, RTE_PGSIZE_2M); 267 } 268 269 #endif /* _ROC_PLATFORM_H_ */ 270