1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_PLATFORM_H_ 6 #define _ROC_PLATFORM_H_ 7 8 #include <rte_alarm.h> 9 #include <rte_bitmap.h> 10 #include <rte_bus_pci.h> 11 #include <rte_byteorder.h> 12 #include <rte_common.h> 13 #include <rte_cycles.h> 14 #include <rte_interrupts.h> 15 #include <rte_io.h> 16 #include <rte_log.h> 17 #include <rte_malloc.h> 18 #include <rte_memzone.h> 19 #include <rte_pci.h> 20 #include <rte_spinlock.h> 21 #include <rte_string_fns.h> 22 #include <rte_telemetry.h> 23 24 #include "roc_bits.h" 25 26 #if defined(__ARM_FEATURE_SVE) 27 #define PLT_CPU_FEATURE_PREAMBLE \ 28 ".arch_extension crc\n" \ 29 ".arch_extension lse\n" \ 30 ".arch_extension sve\n" 31 #else 32 #define PLT_CPU_FEATURE_PREAMBLE \ 33 ".arch_extension crc\n" \ 34 ".arch_extension lse\n" 35 #endif 36 37 #define PLT_ASSERT RTE_ASSERT 38 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE 39 #define PLT_STD_C11 RTE_STD_C11 40 #define PLT_PTR_ADD RTE_PTR_ADD 41 #define PLT_PTR_DIFF RTE_PTR_DIFF 42 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID 43 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET 44 #define PLT_MIN RTE_MIN 45 #define PLT_MAX RTE_MAX 46 #define PLT_DIM RTE_DIM 47 #define PLT_SET_USED RTE_SET_USED 48 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) 49 #define PLT_ALIGN RTE_ALIGN 50 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL 51 #define PLT_MODEL_MZ_NAME "roc_model_mz" 52 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE 53 #define BITMASK_ULL GENMASK_ULL 54 #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL 55 #define PLT_INIT RTE_INIT 56 57 /** Divide ceil */ 58 #define PLT_DIV_CEIL(x, y) \ 59 ({ \ 60 __typeof(x) __x = x; \ 61 __typeof(y) __y = y; \ 62 (__x + __y - 1) / __y; \ 63 }) 64 65 #define __plt_cache_aligned __rte_cache_aligned 66 #define __plt_always_inline __rte_always_inline 67 #define __plt_packed __rte_packed 68 #define __plt_unused __rte_unused 69 #define __roc_api __rte_internal 70 #define plt_iova_t rte_iova_t 71 72 #define plt_pci_device rte_pci_device 73 #define plt_pci_read_config rte_pci_read_config 74 #define plt_pci_find_ext_capability rte_pci_find_ext_capability 75 76 #define plt_log2_u32 rte_log2_u32 77 #define plt_cpu_to_be_16 rte_cpu_to_be_16 78 #define plt_be_to_cpu_16 rte_be_to_cpu_16 79 #define plt_cpu_to_be_32 rte_cpu_to_be_32 80 #define plt_be_to_cpu_32 rte_be_to_cpu_32 81 #define plt_cpu_to_be_64 rte_cpu_to_be_64 82 #define plt_be_to_cpu_64 rte_be_to_cpu_64 83 84 #define plt_align32pow2 rte_align32pow2 85 #define plt_align32prevpow2 rte_align32prevpow2 86 87 #define plt_bitmap rte_bitmap 88 #define plt_bitmap_init rte_bitmap_init 89 #define plt_bitmap_reset rte_bitmap_reset 90 #define plt_bitmap_free rte_bitmap_free 91 #define plt_bitmap_clear rte_bitmap_clear 92 #define plt_bitmap_set rte_bitmap_set 93 #define plt_bitmap_get rte_bitmap_get 94 #define plt_bitmap_scan_init __rte_bitmap_scan_init 95 #define plt_bitmap_scan rte_bitmap_scan 96 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint 97 98 #define plt_spinlock_t rte_spinlock_t 99 #define plt_spinlock_init rte_spinlock_init 100 #define plt_spinlock_lock rte_spinlock_lock 101 #define plt_spinlock_unlock rte_spinlock_unlock 102 103 #define plt_intr_callback_register rte_intr_callback_register 104 #define plt_intr_callback_unregister rte_intr_callback_unregister 105 #define plt_intr_disable rte_intr_disable 106 #define plt_thread_is_intr rte_thread_is_intr 107 #define plt_intr_callback_fn rte_intr_callback_fn 108 109 #define plt_alarm_set rte_eal_alarm_set 110 #define plt_alarm_cancel rte_eal_alarm_cancel 111 112 #define plt_intr_handle rte_intr_handle 113 114 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) 115 #define plt_free rte_free 116 117 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 118 #define plt_write64(val, addr) \ 119 rte_write64_relaxed((val), (volatile void *)(addr)) 120 121 #define plt_wmb() rte_wmb() 122 #define plt_rmb() rte_rmb() 123 #define plt_io_wmb() rte_io_wmb() 124 #define plt_io_rmb() rte_io_rmb() 125 #define plt_atomic_thread_fence rte_atomic_thread_fence 126 127 #define plt_mmap mmap 128 #define PLT_PROT_READ PROT_READ 129 #define PLT_PROT_WRITE PROT_WRITE 130 #define PLT_MAP_SHARED MAP_SHARED 131 132 #define plt_memzone rte_memzone 133 #define plt_memzone_lookup rte_memzone_lookup 134 #define plt_memzone_reserve_cache_align(name, sz) \ 135 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) 136 #define plt_memzone_free rte_memzone_free 137 #define plt_memzone_reserve_aligned(name, len, flags, align) \ 138 rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) 139 140 #define plt_tsc_hz rte_get_tsc_hz 141 #define plt_delay_ms rte_delay_ms 142 #define plt_delay_us rte_delay_us 143 144 #define plt_lcore_id rte_lcore_id 145 146 #define plt_strlcpy rte_strlcpy 147 148 #define PLT_TEL_INT_VAL RTE_TEL_INT_VAL 149 #define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL 150 #define plt_tel_data rte_tel_data 151 #define plt_tel_data_start_array rte_tel_data_start_array 152 #define plt_tel_data_add_array_int rte_tel_data_add_array_int 153 #define plt_tel_data_add_array_string rte_tel_data_add_array_string 154 #define plt_tel_data_start_dict rte_tel_data_start_dict 155 #define plt_tel_data_add_dict_int rte_tel_data_add_dict_int 156 #define plt_tel_data_add_dict_ptr(d, n, v) \ 157 rte_tel_data_add_dict_u64(d, n, (uint64_t)v) 158 #define plt_tel_data_add_dict_string rte_tel_data_add_dict_string 159 #define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_u64 160 #define plt_telemetry_register_cmd rte_telemetry_register_cmd 161 162 /* Log */ 163 extern int cnxk_logtype_base; 164 extern int cnxk_logtype_mbox; 165 extern int cnxk_logtype_cpt; 166 extern int cnxk_logtype_npa; 167 extern int cnxk_logtype_nix; 168 extern int cnxk_logtype_npc; 169 extern int cnxk_logtype_sso; 170 extern int cnxk_logtype_tim; 171 extern int cnxk_logtype_tm; 172 173 #define plt_err(fmt, args...) \ 174 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 175 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 176 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args) 177 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 178 #define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__) 179 180 /** 181 * Log debug message if given subsystem logging is enabled. 182 */ 183 #define plt_dbg(subsystem, fmt, args...) \ 184 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \ 185 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \ 186 ##args) 187 188 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) 189 #define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) 190 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) 191 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) 192 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) 193 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) 194 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) 195 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) 196 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) 197 198 /* Datapath logs */ 199 #define plt_dp_err(fmt, args...) \ 200 RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 201 #define plt_dp_info(fmt, args...) \ 202 RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 203 204 #ifdef __cplusplus 205 #define CNXK_PCI_ID(subsystem_dev, dev) \ 206 { \ 207 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ 208 (subsystem_dev), \ 209 } 210 #else 211 #define CNXK_PCI_ID(subsystem_dev, dev) \ 212 { \ 213 .class_id = RTE_CLASS_ANY_ID, \ 214 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ 215 .subsystem_vendor_id = RTE_PCI_ANY_ID, \ 216 .subsystem_device_id = (subsystem_dev), \ 217 } 218 #endif 219 220 __rte_internal 221 int roc_plt_init(void); 222 223 /* Init callbacks */ 224 typedef int (*roc_plt_init_cb_t)(void); 225 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); 226 227 static inline const void * 228 plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align) 229 { 230 /* To ensure returned memory is physically contiguous, bounding 231 * the start and end address in 2M range. 232 */ 233 return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 234 RTE_MEMZONE_IOVA_CONTIG, 235 align, RTE_PGSIZE_2M); 236 } 237 238 #endif /* _ROC_PLATFORM_H_ */ 239