1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_PLATFORM_H_ 6 #define _ROC_PLATFORM_H_ 7 8 #include <rte_alarm.h> 9 #include <rte_bitmap.h> 10 #include <rte_bus_pci.h> 11 #include <rte_byteorder.h> 12 #include <rte_common.h> 13 #include <rte_cycles.h> 14 #include <rte_interrupts.h> 15 #include <rte_io.h> 16 #include <rte_log.h> 17 #include <rte_malloc.h> 18 #include <rte_memzone.h> 19 #include <rte_pci.h> 20 #include <rte_spinlock.h> 21 #include <rte_string_fns.h> 22 #include <rte_telemetry.h> 23 24 #include "roc_bits.h" 25 26 #if defined(__ARM_FEATURE_SVE) 27 #define PLT_CPU_FEATURE_PREAMBLE \ 28 ".arch_extension crc\n" \ 29 ".arch_extension lse\n" \ 30 ".arch_extension sve\n" 31 #else 32 #define PLT_CPU_FEATURE_PREAMBLE \ 33 ".arch_extension crc\n" \ 34 ".arch_extension lse\n" 35 #endif 36 37 #define PLT_ASSERT RTE_ASSERT 38 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE 39 #define PLT_STD_C11 RTE_STD_C11 40 #define PLT_PTR_ADD RTE_PTR_ADD 41 #define PLT_PTR_DIFF RTE_PTR_DIFF 42 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID 43 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET 44 #define PLT_MIN RTE_MIN 45 #define PLT_MAX RTE_MAX 46 #define PLT_DIM RTE_DIM 47 #define PLT_SET_USED RTE_SET_USED 48 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) 49 #define PLT_ALIGN RTE_ALIGN 50 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL 51 #define PLT_MODEL_MZ_NAME "roc_model_mz" 52 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE 53 #define BITMASK_ULL GENMASK_ULL 54 #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL 55 #define PLT_INIT RTE_INIT 56 57 /** Divide ceil */ 58 #define PLT_DIV_CEIL(x, y) \ 59 ({ \ 60 __typeof(x) __x = x; \ 61 __typeof(y) __y = y; \ 62 (__x + __y - 1) / __y; \ 63 }) 64 65 #define __plt_cache_aligned __rte_cache_aligned 66 #define __plt_always_inline __rte_always_inline 67 #define __plt_packed __rte_packed 68 #define __plt_unused __rte_unused 69 #define __roc_api __rte_internal 70 #define plt_iova_t rte_iova_t 71 72 #define plt_pci_addr rte_pci_addr 73 #define plt_pci_device rte_pci_device 74 #define plt_pci_read_config rte_pci_read_config 75 #define plt_pci_find_ext_capability rte_pci_find_ext_capability 76 77 #define plt_log2_u32 rte_log2_u32 78 #define plt_cpu_to_be_16 rte_cpu_to_be_16 79 #define plt_be_to_cpu_16 rte_be_to_cpu_16 80 #define plt_cpu_to_be_32 rte_cpu_to_be_32 81 #define plt_be_to_cpu_32 rte_be_to_cpu_32 82 #define plt_cpu_to_be_64 rte_cpu_to_be_64 83 #define plt_be_to_cpu_64 rte_be_to_cpu_64 84 85 #define plt_align32pow2 rte_align32pow2 86 #define plt_align32prevpow2 rte_align32prevpow2 87 88 #define plt_bitmap rte_bitmap 89 #define plt_bitmap_init rte_bitmap_init 90 #define plt_bitmap_reset rte_bitmap_reset 91 #define plt_bitmap_free rte_bitmap_free 92 #define plt_bitmap_clear rte_bitmap_clear 93 #define plt_bitmap_set rte_bitmap_set 94 #define plt_bitmap_get rte_bitmap_get 95 #define plt_bitmap_scan_init __rte_bitmap_scan_init 96 #define plt_bitmap_scan rte_bitmap_scan 97 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint 98 99 #define plt_spinlock_t rte_spinlock_t 100 #define plt_spinlock_init rte_spinlock_init 101 #define plt_spinlock_lock rte_spinlock_lock 102 #define plt_spinlock_unlock rte_spinlock_unlock 103 104 #define plt_intr_callback_register rte_intr_callback_register 105 #define plt_intr_callback_unregister rte_intr_callback_unregister 106 #define plt_intr_disable rte_intr_disable 107 #define plt_thread_is_intr rte_thread_is_intr 108 #define plt_intr_callback_fn rte_intr_callback_fn 109 110 #define plt_intr_efd_counter_size_get rte_intr_efd_counter_size_get 111 #define plt_intr_efd_counter_size_set rte_intr_efd_counter_size_set 112 #define plt_intr_vec_list_index_get rte_intr_vec_list_index_get 113 #define plt_intr_vec_list_index_set rte_intr_vec_list_index_set 114 #define plt_intr_vec_list_alloc rte_intr_vec_list_alloc 115 #define plt_intr_vec_list_free rte_intr_vec_list_free 116 #define plt_intr_fd_set rte_intr_fd_set 117 #define plt_intr_fd_get rte_intr_fd_get 118 #define plt_intr_dev_fd_get rte_intr_dev_fd_get 119 #define plt_intr_dev_fd_set rte_intr_dev_fd_set 120 #define plt_intr_type_get rte_intr_type_get 121 #define plt_intr_type_set rte_intr_type_set 122 #define plt_intr_instance_alloc rte_intr_instance_alloc 123 #define plt_intr_instance_dup rte_intr_instance_dup 124 #define plt_intr_instance_free rte_intr_instance_free 125 #define plt_intr_event_list_update rte_intr_event_list_update 126 #define plt_intr_max_intr_get rte_intr_max_intr_get 127 #define plt_intr_max_intr_set rte_intr_max_intr_set 128 #define plt_intr_nb_efd_get rte_intr_nb_efd_get 129 #define plt_intr_nb_efd_set rte_intr_nb_efd_set 130 #define plt_intr_nb_intr_get rte_intr_nb_intr_get 131 #define plt_intr_nb_intr_set rte_intr_nb_intr_set 132 #define plt_intr_efds_index_get rte_intr_efds_index_get 133 #define plt_intr_efds_index_set rte_intr_efds_index_set 134 #define plt_intr_elist_index_get rte_intr_elist_index_get 135 #define plt_intr_elist_index_set rte_intr_elist_index_set 136 137 #define plt_alarm_set rte_eal_alarm_set 138 #define plt_alarm_cancel rte_eal_alarm_cancel 139 140 #define plt_intr_handle rte_intr_handle 141 142 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) 143 #define plt_free rte_free 144 145 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 146 #define plt_write64(val, addr) \ 147 rte_write64_relaxed((val), (volatile void *)(addr)) 148 149 #define plt_wmb() rte_wmb() 150 #define plt_rmb() rte_rmb() 151 #define plt_io_wmb() rte_io_wmb() 152 #define plt_io_rmb() rte_io_rmb() 153 #define plt_atomic_thread_fence rte_atomic_thread_fence 154 155 #define plt_mmap mmap 156 #define PLT_PROT_READ PROT_READ 157 #define PLT_PROT_WRITE PROT_WRITE 158 #define PLT_MAP_SHARED MAP_SHARED 159 160 #define plt_memzone rte_memzone 161 #define plt_memzone_lookup rte_memzone_lookup 162 #define plt_memzone_reserve_cache_align(name, sz) \ 163 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) 164 #define plt_memzone_free rte_memzone_free 165 #define plt_memzone_reserve_aligned(name, len, flags, align) \ 166 rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) 167 168 #define plt_tsc_hz rte_get_tsc_hz 169 #define plt_delay_ms rte_delay_ms 170 #define plt_delay_us rte_delay_us 171 172 #define plt_lcore_id rte_lcore_id 173 174 #define plt_strlcpy rte_strlcpy 175 176 #define PLT_TEL_INT_VAL RTE_TEL_INT_VAL 177 #define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL 178 #define plt_tel_data rte_tel_data 179 #define plt_tel_data_start_array rte_tel_data_start_array 180 #define plt_tel_data_add_array_int rte_tel_data_add_array_int 181 #define plt_tel_data_add_array_string rte_tel_data_add_array_string 182 #define plt_tel_data_start_dict rte_tel_data_start_dict 183 #define plt_tel_data_add_dict_int rte_tel_data_add_dict_int 184 #define plt_tel_data_add_dict_ptr(d, n, v) \ 185 rte_tel_data_add_dict_u64(d, n, (uint64_t)v) 186 #define plt_tel_data_add_dict_string rte_tel_data_add_dict_string 187 #define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_u64 188 #define plt_telemetry_register_cmd rte_telemetry_register_cmd 189 190 /* Log */ 191 extern int cnxk_logtype_base; 192 extern int cnxk_logtype_mbox; 193 extern int cnxk_logtype_cpt; 194 extern int cnxk_logtype_npa; 195 extern int cnxk_logtype_nix; 196 extern int cnxk_logtype_npc; 197 extern int cnxk_logtype_sso; 198 extern int cnxk_logtype_tim; 199 extern int cnxk_logtype_tm; 200 201 #define plt_err(fmt, args...) \ 202 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 203 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 204 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args) 205 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) 206 #define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__) 207 208 /** 209 * Log debug message if given subsystem logging is enabled. 210 */ 211 #define plt_dbg(subsystem, fmt, args...) \ 212 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \ 213 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \ 214 ##args) 215 216 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) 217 #define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) 218 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) 219 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) 220 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) 221 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) 222 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) 223 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) 224 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) 225 226 /* Datapath logs */ 227 #define plt_dp_err(fmt, args...) \ 228 RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 229 #define plt_dp_info(fmt, args...) \ 230 RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) 231 232 #ifdef __cplusplus 233 #define CNXK_PCI_ID(subsystem_dev, dev) \ 234 { \ 235 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ 236 (subsystem_dev), \ 237 } 238 #else 239 #define CNXK_PCI_ID(subsystem_dev, dev) \ 240 { \ 241 .class_id = RTE_CLASS_ANY_ID, \ 242 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ 243 .subsystem_vendor_id = RTE_PCI_ANY_ID, \ 244 .subsystem_device_id = (subsystem_dev), \ 245 } 246 #endif 247 248 __rte_internal 249 int roc_plt_init(void); 250 251 /* Init callbacks */ 252 typedef int (*roc_plt_init_cb_t)(void); 253 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); 254 255 static inline const void * 256 plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align) 257 { 258 /* To ensure returned memory is physically contiguous, bounding 259 * the start and end address in 2M range. 260 */ 261 return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 262 RTE_MEMZONE_IOVA_CONTIG, 263 align, RTE_PGSIZE_2M); 264 } 265 266 #endif /* _ROC_PLATFORM_H_ */ 267