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Searched refs:prefers (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Dlsr-insns-2.ll5 ; OPT checks that LSR prefers less instructions to less registers.
20 ; LLC checks that LSR prefers less instructions to less registers.
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davoid_complex_am.ll5 ; Therefore, LSR currently prefers to fold as much computation as possible
H A Dcode_placement_ext_tsp.ll45 ; Test that the algorithm prefers many fallthroughs even in the presence of
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dwiden_switch.ll6 ; X86 prefers i32 over i16 for address calculation.
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfreeze.ll73 %a = select i1 %f, i32 %x, i32 32 ; prefers %f to be false
74 %b = or i1 %f, %y ; prefers %f to be true
85 %a = select i1 %f, i32 %x, i32 32 ; prefers %f to be false
86 %b = select i1 %f, i1 true, i1 %y ; prefers %f to be true
/llvm-project-15.0.7/llvm/test/DebugInfo/COFF/
H A Dfpo-realign-vframe.ll10 ; variables. Instead, our CodeView output prefers to use the VFRAME virtual
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dframe-14.ll152 ; object being at offset 1048576 (1 << 20). The backend prefers to create
H A Dframe-16.ll146 ; object being at offset 1048576 (1 << 20). The backend prefers to create
/llvm-project-15.0.7/llvm/docs/
H A DCMakePrimer.rst194 This is not true of macros, and it is for this reason LLVM prefers functions
H A DMyFirstTypoFix.rst489 single commit. LLVM prefers commits to match the code that was
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dframe-access.ll238 ; 24 bytes callee-saved area for AAPCS as codegen prefers an even number of GPRs spilled
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td1625 // occurs because SimplifyDemandedBits prefers srl over sra.
/llvm-project-15.0.7/llvm/lib/Target/
H A DREADME.txt1717 LLVM prefers comparisons with zero over non-zero in general, but in this
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td1177 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrSSE.td2297 /// There are no patterns here because isel prefers integer versions for SSE2
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx9_dasm_all.txt10086 # SP3 prefers to decode instructions with imm=1 and soffset_en=1 to the
10577 # SP3 prefers to decode instructions with imm=1 and soffset_en=1 to the