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/llvm-project-15.0.7/clang/test/Sema/
H A Dext_vector_components.c13 float4 vec4, vec4_2, *vec4p; in test() local
22 vec2 = vec4.s01; // legal, shorten in test()
23 vec2 = vec4.S01; // legal, shorten in test()
25 vec3 = vec4.xyz; // legal, shorten in test()
27 f = vec4.xy.x; // legal, shorten in test()
35 vec4 = (float4){ 1,2,3,4 }; in test()
38 vec4.x = vec16.sf; in test()
39 vec4.x = vec16.sF; in test()
63 vec4 = (float4){ 1,2,3,4 }; in test()
65 vec4.r = vec16.sf; in test()
[all …]
H A Dext_vector_casts.c18 float4 vec4, vec4_2; in test() local
26 vec4 += vec3; // expected-error {{cannot convert between vector values of different size}} in test()
28 vec4 = 5.0f; in test()
29 vec4 = (float4)5.0f; in test()
30 vec4 = (float4)5; in test()
31 vec4 = (float4)vec4_3; in test()
42 …vec4 = (float4)vec2; // expected-error {{invalid conversion between ext-vector type 'float4' (vect… in test()
46 vec4 /= 5.2f; in test()
47 …vec4 %= 4; // expected-error {{invalid operands to binary expression ('float4' (vector of 4 'float… in test()
49 …ivec4 += vec4; // expected-error {{cannot convert between vector values of different size ('int4' … in test()
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dext-vector.c21 float4 vec4, vec4_2; variable
31 vec2 = vec4.xy; // shorten in test2()
33 vec4 = vec4.yyyy; // splat in test2()
312 vec4_2 = vec4.abgr + vec4; in test_rgba()
315 vec2 = vec4.rg; in test_rgba()
317 vec2_2 = vec4.ba; in test_rgba()
319 f = vec4.b; in test_rgba()
333 vec4.rgb = vec4.bgr; in test_rgba()
337 vec4.b = vec16.sb; in test_rgba()
H A Dvector.c15 typedef float vec4 __attribute__((vector_size(16))); typedef
17 void test3 ( vec4* a, char b, float c ) { in test3()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dreduction.ll11 define half @reduction_fadd_v4f16(<4 x half> %vec4) {
14 %bin.rdx = fadd <4 x half> %vec4, %rdx.shuf
31 define half @reduction_fsub_v4f16(<4 x half> %vec4) {
34 %bin.rdx = fsub <4 x half> %vec4, %rdx.shuf
56 %bin.rdx = fsub nsz <4 x half> %vec4, %rdx.shuf
71 define half @reduction_fmul_half4(<4 x half> %vec4) {
74 %bin.rdx = fmul <4 x half> %vec4, %rdx.shuf
88 define i16 @reduction_v4i16(<4 x i16> %vec4) {
91 %bin.rdx = add <4 x i16> %vec4, %rdx.shuf
197 define i16 @reduction_min_v4i16(<4 x i16> %vec4) {
[all …]
H A Dscalar_to_vector.v8i16.ll80 …%val.4.vec4.i32 = shufflevector <2 x i32> %in, <2 x i32> %in, <4 x i32> <i32 0, i32 1, i32 2, i32 …
81 %val.5.vec8.i16 = bitcast <4 x i32> %val.4.vec4.i32 to <8 x i16>
162 …%val.4.vec4.float = shufflevector <2 x float> %in, <2 x float> %in, <4 x i32> <i32 0, i32 1, i32 2…
163 %val.5.vec8.half = bitcast <4 x float> %val.4.vec4.float to <8 x half>
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dvector-extract-elt.ll13 %vec4 = sext <4 x i16> %vec3 to <4 x i32>
14 %elt0 = extractelement <4 x i32> %vec4, i32 0
15 %elt1 = extractelement <4 x i32> %vec4, i32 1
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A DInsertElement-inseltpoison.ll22 %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
23 ret <4 x i64> %vec4
33 %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
H A DInsertElement.ll22 %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
23 ret <4 x i64> %vec4
33 %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll282 %elt0 = extractelement <4 x i16> %vec4, i64 0
283 %elt1 = extractelement <4 x i16> %vec4, i64 1
284 %elt2 = extractelement <4 x i16> %vec4, i64 2
285 %elt3 = extractelement <4 x i16> %vec4, i64 3
496 %elt0 = extractelement <4 x i16> %vec4, i64 0
497 %elt1 = extractelement <4 x i16> %vec4, i64 1
498 %elt2 = extractelement <4 x i16> %vec4, i64 2
499 %elt3 = extractelement <4 x i16> %vec4, i64 3
532 %elt0 = extractelement <4 x i16> %vec4, i64 0
533 %elt1 = extractelement <4 x i16> %vec4, i64 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvec_loadsingles.ll49 %vec4 = insertelement <4 x float> %vec2, float %c, i32 2
52 %vec6 = insertelement <4 x float> %vec4, float %d, i32 3
79 %vec4 = insertelement <8 x float> %vec2, float %c, i32 2
82 %vec6 = insertelement <8 x float> %vec4, float %d, i32 3
116 %vec4 = insertelement <4 x double> %vec2, double %c, i32 2
119 %vec6 = insertelement <4 x double> %vec4, double %d, i32 3
H A Dvector-interleaved-load-i64-stride-6.ll11 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
89 %strided.vec4 = shufflevector <12 x i64> %wide.vec, <12 x i64> poison, <2 x i32> <i32 4, i32 10>
96 store <2 x i64> %strided.vec4, ptr %out.vec4, align 32
102 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
284 …%strided.vec4 = shufflevector <24 x i64> %wide.vec, <24 x i64> poison, <4 x i32> <i32 4, i32 10, i…
291 store <4 x i64> %strided.vec4, ptr %out.vec4, align 32
297 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
669 …%strided.vec4 = shufflevector <48 x i64> %wide.vec, <48 x i64> poison, <8 x i32> <i32 4, i32 10, i…
676 store <8 x i64> %strided.vec4, ptr %out.vec4, align 32
H A Dvector-interleaved-store-i64-stride-6.ll105 %in.vec4 = load <2 x i64>, ptr %in.vecptr4, align 32
110 …%concat45 = shufflevector <2 x i64> %in.vec4, <2 x i64> %in.vec5, <4 x i32> <i32 0, i32 1, i32 2, …
292 %in.vec4 = load <4 x i64>, ptr %in.vecptr4, align 32
297 …%concat45 = shufflevector <4 x i64> %in.vec4, <4 x i64> %in.vec5, <8 x i32> <i32 0, i32 1, i32 2, …
696 %in.vec4 = load <8 x i64>, ptr %in.vecptr4, align 32
701 …%concat45 = shufflevector <8 x i64> %in.vec4, <8 x i64> %in.vec5, <16 x i32> <i32 0, i32 1, i32 2,…
H A Dvector-interleaved-load-i32-stride-6.ll11 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
130 %strided.vec4 = shufflevector <12 x i32> %wide.vec, <12 x i32> poison, <2 x i32> <i32 4, i32 10>
137 store <2 x i32> %strided.vec4, ptr %out.vec4, align 32
143 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
342 …%strided.vec4 = shufflevector <24 x i32> %wide.vec, <24 x i32> poison, <4 x i32> <i32 4, i32 10, i…
349 store <4 x i32> %strided.vec4, ptr %out.vec4, align 32
355 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
866 …%strided.vec4 = shufflevector <48 x i32> %wide.vec, <48 x i32> poison, <8 x i32> <i32 4, i32 10, i…
873 store <8 x i32> %strided.vec4, ptr %out.vec4, align 32
879 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
[all …]
H A Dvector-interleaved-load-i8-stride-6.ll11 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
115 %strided.vec4 = shufflevector <12 x i8> %wide.vec, <12 x i8> poison, <2 x i32> <i32 4, i32 10>
122 store <2 x i8> %strided.vec4, ptr %out.vec4, align 32
128 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
300 …%strided.vec4 = shufflevector <24 x i8> %wide.vec, <24 x i8> poison, <4 x i32> <i32 4, i32 10, i32…
307 store <4 x i8> %strided.vec4, ptr %out.vec4, align 32
313 …vec, ptr %out.vec0, ptr %out.vec1, ptr %out.vec2, ptr %out.vec3, ptr %out.vec4, ptr %out.vec5) nou…
594 …%strided.vec4 = shufflevector <48 x i8> %wide.vec, <48 x i8> poison, <8 x i32> <i32 4, i32 10, i32…
601 store <8 x i8> %strided.vec4, ptr %out.vec4, align 32
1266 store <16 x i8> %strided.vec4, ptr %out.vec4, align 32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvldm-liveness.ll24 %vec4 = insertelement <4 x float> %vec3, float %val2, i32 3
26 ret <4 x float> %vec4
H A DlowerMUL-newload.ll157 %vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8
158 %3 = sext <4 x i16> %vec4 to <4 x i32>
232 %vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8
233 %3 = sext <4 x i16> %vec4 to <4 x i32>
H A Dfp16-vld.ll27 define dso_local void @vec4(half* nocapture readonly %V, i32 %N) local_unnamed_addr #0 {
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dbool_cast.cl10 int4 vec4 = (int4)t;
16 // CHECK: store <4 x i32> {{%.*}}, <4 x i32>* %vec4, align 16
H A DvectorLoadStore.cl8 // Check for optimized vec3 load/store which treats vec3 as vec4.
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dreferences.cpp145 __attribute((vector_size(16))) typedef int vec4; in test10() typedef
148 vec4 v; in test10()
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dreferences.cpp60 __attribute((vector_size(16))) typedef int vec4; in test_scalar() typedef
61 f((vec4){1,2,3,4}[0]); in test_scalar()
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dinsert-shuffle.ll54 %vec4 = insertelement <2 x float> %vec3, float %add54, i32 1
56 %ins2 = insertvalue { <2 x float>, <2 x float> } %ins1, <2 x float> %vec4, 1
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-cc-ext-vec-abi.ll9 …@vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <…
13 %add2 = add <4 x i32> %add1, %vec4
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A DlowerMUL-newload.ll327 %vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8
328 %3 = sext <4 x i16> %vec4 to <4 x i32>
397 %vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8
398 %3 = sext <4 x i16> %vec4 to <4 x i32>

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