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/llvm-project-15.0.7/clang/test/OpenMP/
H A Dopenmp_attribute_parsing.cpp22 [[omp::sequence(directive)]]; // expected-error {{expected '('}}
23 [[omp::sequence(sequence)]]; // expected-error {{expected '('}}
24 [[omp::sequence(omp::directive)]]; // expected-error {{expected '('}}
25 [[omp::sequence(omp::sequence)]]; // expected-error {{expected '('}}
30 [[omp::sequence(directive(), sequence())]]; // expected-error {{expected an OpenMP directive}} expe…
31 [[omp::sequence(omp::directive(), sequence())]]; // expected-error {{expected an OpenMP directive}}…
37 [[omp::sequence( // expected-note {{to match this '('}}
40 [[omp::sequence( // expected-note {{to match this '('}}
41 sequence(
58 [[omp::sequence(sequence(unknown))]]; // expected-error {{expected an OpenMP 'directive' or 'sequen…
[all …]
H A Dteams_distribute_parallel_for_simd_num_teams_messages_attr.cpp17 [[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams(C)))]] in tmain()
19 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams(T)))]] /… in tmain()
21 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams))]] // e… in tmain()
23 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams()))]] //… in tmain()
27 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams(argc + k… in tmain()
31 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams(S1)))]] … in tmain()
35 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams(-10u)))]] in tmain()
45 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams))]] // e… in main()
48 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams ()))]] /… in main()
54 …[[omp::sequence(directive(target), directive(teams distribute parallel for simd num_teams (argc + … in main()
[all …]
/llvm-project-15.0.7/mlir/test/python/dialects/
H A Dtransform_structured_ext.py21 sequence = transform.SequenceOp()
22 with InsertionPoint(sequence.body):
32 sequence = transform.SequenceOp()
33 with InsertionPoint(sequence.body):
43 sequence = transform.SequenceOp()
44 with InsertionPoint(sequence.body):
46 sequence.bodyTarget,
59 sequence = transform.SequenceOp()
73 sequence = transform.SequenceOp()
76 sequence.bodyTarget,
[all …]
H A Dtransform.py21 with InsertionPoint(sequence.body):
22 transform.YieldOp([sequence.bodyTarget])
32 sequence = transform.SequenceOp()
33 with InsertionPoint(sequence.body):
34 nested = transform.SequenceOp(sequence.bodyTarget)
61 with InsertionPoint(sequence.body):
77 sequence = transform.SequenceOp()
78 with InsertionPoint(sequence.body):
89 sequence = transform.SequenceOp()
90 with InsertionPoint(sequence.body):
[all …]
H A Dtransform_loop_ext.py21 sequence = transform.SequenceOp()
22 with InsertionPoint(sequence.body):
32 sequence = transform.SequenceOp()
33 with InsertionPoint(sequence.body):
43 sequence = transform.SequenceOp()
44 with InsertionPoint(sequence.body):
45 loop.LoopPeelOp(sequence.bodyTarget)
53 sequence = transform.SequenceOp()
54 with InsertionPoint(sequence.body):
65 sequence = transform.SequenceOp()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVCallingConv.td33 (sequence "X%u", 3, 9),
34 (sequence "X%u", 10, 11),
35 (sequence "X%u", 12, 17),
36 (sequence "X%u", 18, 27),
41 (sequence "X%u", 3, 9),
42 (sequence "X%u", 10, 11),
43 (sequence "X%u", 12, 17),
44 (sequence "X%u", 18, 27),
45 (sequence "X%u", 28, 31),
46 (sequence "F%u_F", 0, 7),
[all …]
H A DRISCVRegisterInfo.td127 (sequence "X%u", 10, 17),
128 (sequence "X%u", 5, 7),
129 (sequence "X%u", 28, 31),
130 (sequence "X%u", 8, 9),
131 (sequence "X%u", 18, 27),
132 (sequence "X%u", 0, 4)
159 (sequence "X%u", 8, 9)
169 (sequence "X%u", 6, 7),
171 (sequence "X%u", 28, 31)
246 (sequence "F%u_F", 8, 9)
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Transform/
H A Dops.mlir3 // CHECK: transform.sequence
5 transform.sequence {
7 // CHECK: sequence %{{.+}}
9 sequence %arg0 {
19 sequence %arg0 {
26 transform.sequence {
37 // CHECK: sequence %[[V]]
38 // CHECK: sequence %[[V]]
39 transform.sequence {
45 transform.sequence %0 {
[all …]
H A Dops-invalid.mlir4 transform.sequence {
10 transform.sequence {
13 transform.sequence {
21 transform.sequence {
42 transform.sequence {
53 transform.sequence {
57 transform.sequence {
99 transform.sequence {
111 transform.sequence {
126 transform.sequence {
[all …]
H A Dcheck-use-after-free.mlir20 transform.sequence %0 {
49 transform.sequence %0 {
58 transform.sequence {
65 transform.sequence %0 attributes { ord = 2 } {
68 transform.sequence %0 attributes { ord = 3 } {
75 transform.sequence %0 attributes { ord = 4 } {
80 transform.sequence %0 attributes { ord = 5 } {
90 transform.sequence {
97 transform.sequence %0 attributes { ord = 2 } {
100 transform.sequence %0 attributes { ord = 3 } {
[all …]
H A Dtest-interpreter.mlir31 transform.sequence {
33 sequence %arg0 {
50 transform.sequence {
53 sequence %0 {
62 transform.sequence {
64 %0 = sequence %arg0 {
77 sequence %arg0 {
123 transform.sequence %arg0 {
148 transform.sequence %arg0 {
336 transform.sequence {
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.td59 def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 4))>;
60 def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 4))>;
63 def Float16Regs : NVPTXRegClass<[f16], 16, (add (sequence "H%u", 0, 4))>;
64 def Float16x2Regs : NVPTXRegClass<[v2f16], 32, (add (sequence "HH%u", 0, 4))>;
65 def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
66 def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 4))>;
67 def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 4))>;
68 def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 4))>;
69 def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>;
70 def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td13 def CSR_I32 : CalleeSavedRegs<(add R8, R15, (sequence "R%u", 4, 7),
14 (sequence "R%u", 9, 11), (sequence "R%u", 16, 17), R28)>;
17 (sequence "F%u_64", 8, 15))>;
22 (sequence "R%u", 0, 3),
23 (sequence "R%u", 4, 7),
24 (sequence "R%u", 9, 13),
25 (sequence "R%u", 16, 31))>;
28 (sequence "F%u_32", 0, 15))>;
30 (sequence "F%u_64", 0, 15))>;
33 (sequence "F%u_32", 16, 31))>;
[all …]
H A DCSKYRegisterInfo.td94 [(add (sequence "R%u", 0, 31)), (add (sequence "R%u", 1, 32))],
153 (add (sequence "R%u", 0, 3), (sequence "R%u", 12, 13),
154 (sequence "R%u", 18, 25), R15, (sequence "R%u", 4, 11),
155 (sequence "R%u", 16, 17), (sequence "R%u", 26, 27), R28,
163 (add (sequence "R%u", 0, 3), (sequence "R%u", 12, 13), R15,
164 (sequence "R%u", 4, 11), R14)> {
171 (add (sequence "R%u", 0, 7))> {
192 (add (sequence "F%u_32", 0, 31))>;
194 (add (sequence "F%u_32", 0, 15))>;
205 (add (sequence "F%u_128", 0, 31))>;
[all …]
/llvm-project-15.0.7/flang/test/Semantics/
H A Dresolve31.f9051 sequence
53 sequence ! not a fatal error
60 sequence
64 sequence
71 sequence
77 sequence
81 sequence
94 sequence
/llvm-project-15.0.7/lldb/source/Symbol/
H A DLineTable.cpp29 for (const auto &sequence : sequences) { in LineTable() local
74 assert(sequence != nullptr); in AppendLineEntryToSequence()
106 assert(sequence != nullptr); in InsertSequence()
408 LineSequenceImpl sequence; in LinkLineTable() local
451 if (!sequence.m_entries.empty() && in LinkLineTable()
460 sequence.m_entries.push_back(sequence.m_entries.back()); in LinkLineTable()
470 line_table_up->InsertSequence(&sequence); in LinkLineTable()
471 sequence.Clear(); in LinkLineTable()
478 sequence.m_entries.push_back(entry); in LinkLineTable()
484 if (!sequence.m_entries.empty() && in LinkLineTable()
[all …]
/llvm-project-15.0.7/llvm/bindings/python/llvm/tests/
H A Dtest_disassembler.py12 sequence = '\x67\xe3\x81' # jcxz -127
17 count, s = disassembler.get_instruction(sequence)
26 sequence = '\x67\xe3\x81\x01\xc7' # jcxz -127; addl %eax, %edi
30 instructions = list(disassembler.get_instructions(sequence))
37 sequence = '\x10\x40\x2d\xe9'
42 count, s = disassembler.get_instruction(sequence)
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td99 (add (sequence "R%uL", 0, 5),
100 (sequence "R%uL", 15, 6)),
103 (add (sequence "R%uH", 0, 5),
104 (sequence "R%uH", 15, 6)),
107 (add (sequence "R%uD", 0, 5),
108 (sequence "R%uD", 15, 6)),
115 (add (sequence "R%uL", 0, 5),
116 (sequence "R%uH", 0, 5),
268 (add (sequence "F%uS", 0, 7),
276 (add (sequence "F%uD", 0, 7),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.td79 (sequence "PMCR%u", 0, 3),
171 (add (sequence "SW%u", 0, 7),
172 (sequence "SW%u", 34, 63),
175 (add (sequence "SX%u", 0, 7),
176 (sequence "SX%u", 34, 63),
179 (add (sequence "SF%u", 0, 7),
180 (sequence "SF%u", 34, 63),
183 (add (sequence "Q%u", 0, 3),
184 (sequence "Q%u", 17, 31),
185 (sequence "Q%u", 4, 16))>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td136 (sequence "VGPR%u", 56, 63),
137 (sequence "VGPR%u", 72, 79),
138 (sequence "VGPR%u", 88, 95),
139 (sequence "VGPR%u", 104, 111),
140 (sequence "VGPR%u", 120, 127),
141 (sequence "VGPR%u", 136, 143),
152 (sequence "AGPR%u", 32, 255)
156 (sequence "SGPR%u", 30, 105)
160 (add (sequence "SGPR%u", 4, 31), (sequence "SGPR%u", 64, 105))
222 (sequence "VGPR%u", 0, 255)
[all …]
H A DR600RegisterInfo.td153 (add (sequence "ArrayBase%u", 448, 480))> {
178 (add (sequence "KC0_%u_X", 128, 159))>;
181 (add (sequence "KC0_%u_Y", 128, 159))>;
184 (add (sequence "KC0_%u_Z", 128, 159))>;
187 (add (sequence "KC0_%u_W", 128, 159))>;
194 (add (sequence "KC1_%u_X", 160, 191))>;
197 (add (sequence "KC1_%u_Y", 160, 191))>;
200 (add (sequence "KC1_%u_Z", 160, 191))>;
203 (add (sequence "KC1_%u_W", 160, 191))>;
215 (add (sequence "T%u_Y", 0, 127))>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCallingConv.td366 (sequence "S%u", 7, 0))> {
367 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
371 (sequence "S%u", 7, 0))>;
375 (sequence "S%u", 7, 0))>;
379 (sequence "S%u_64", 7, 0))>;
386 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
387 (sequence "D%u", 15, 10))>;
395 def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
396 (sequence "S%u", 7, 0),
397 (sequence "V%u", 1, 0),
[all …]
/llvm-project-15.0.7/flang/test/Lower/
H A Dassociate-construct.f9075 associate (s => sequence(size(a)))
77 associate(t => sequence(n))
91 function sequence(n) function
92 integer sequence(n) local
93 sequence = [(i,i=1,n)]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dit-nv.s4 @ CHECK-ERRS: error: unpredictable IT predicate sequence
6 @ CHECK-ERRS: error: unpredictable IT predicate sequence
8 @ CHECK-ERRS: error: unpredictable IT predicate sequence
10 @ CHECK-ERRS: error: unpredictable IT predicate sequence
12 @ CHECK-ERRS: error: unpredictable IT predicate sequence
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtransform-ops-invalid.mlir3 transform.sequence {
11 transform.sequence {
19 transform.sequence {
27 transform.sequence {
35 transform.sequence {

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