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Searched refs:getRepRegClassFor (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.h60 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
H A DMipsSEISelLowering.cpp302 MipsSETargetLowering::getRepRegClassFor(MVT VT) const { in getRepRegClassFor() function in MipsSETargetLowering
306 return TargetLowering::getRepRegClassFor(VT); in getRepRegClassFor()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp348 RegClass = TLI->getRepRegClassFor(VT)->getID(); in GetCostForDef()
2135 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in MayReduceRegPressure()
2166 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff()
2181 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff()
2289 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in unscheduledNode()
2301 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in unscheduledNode()
2310 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in unscheduledNode()
2329 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in unscheduledNode()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h767 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
H A DSystemZISelLowering.cpp5875 if (getRepRegClassFor(MVT::f128) == &SystemZ::VR128BitRegClass) { in LowerOperationWrapper()
5882 assert(getRepRegClassFor(MVT::f128) == &SystemZ::FP128BitRegClass && in LowerOperationWrapper()
9041 SystemZTargetLowering::getRepRegClassFor(MVT VT) const { in getRepRegClassFor() function in SystemZTargetLowering
9044 return TargetLowering::getRepRegClassFor(VT); in getRepRegClassFor()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h916 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor() function