Home
last modified time | relevance | path

Searched refs:getNumAllocatableRegs (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp163 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
205 unsigned NAllocatableRegs = getNumAllocatableRegs(RC); in computePSetLimit()
H A DRegAllocEvictionAdvisor.cpp234 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in canEvictInterferenceBasedOnCost()
235 RegClassInfo.getNumAllocatableRegs( in canEvictInterferenceBasedOnCost()
H A DMLRegallocEvictAdvisor.cpp573 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in loadInterferenceFeatures()
574 RegClassInfo.getNumAllocatableRegs( in loadInterferenceFeatures()
H A DRegAllocGreedy.cpp309 (2 * RegClassInfo.getNumAllocatableRegs(&RC)); in enqueue()
1227 return RCI.getNumAllocatableRegs(ConstrainedRC); in getNumAllocatableRegsForConstraints()
1260 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
H A DMachineScheduler.cpp2944 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h95 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() function
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp51 Context->RegClassInfo->getNumAllocatableRegs(&AMDGPU::SGPR_32RegClass); in initialize()
53 Context->RegClassInfo->getNumAllocatableRegs(&AMDGPU::VGPR_32RegClass); in initialize()