Searched refs:chips (Results 1 – 15 of 15) sorted by relevance
1 ; Intel chips with slow unaligned memory accesses15 ; Intel chips with fast unaligned memory accesses27 ; AMD chips with slow unaligned memory accesses39 ; AMD chips with fast unaligned memory accesses53 ; Other chips with slow unaligned memory accesses58 ; Slow chips use 4-byte stores. Fast chips with SSE or later use something other than 4-byte stores.
12 ; chips where it makes sense to transform the general case blendv to 2 bit-ops. That should be
12 This should use fiadd on chips where it is profitable:
104 … "64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)",1566 // be good for modern chips without enabling instruction set encodings past the1573 // knobs which need to be tuned differently for AMD chips, we might consider
19 on the ARMv6 and ARMv7 architectures and may be inapplicable to older chips.
20 system, cross-compiling from an x86_64 host (most Intel and AMD chips
89 * `PowerPC Compiler Writer's Guide <http://www.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20…
457 of a specific sub-architecture, for example only to Intel chips that support ``AVX2``.
104 - Fixed background-indexing priority for M1 chips.
184 ; on 16 bank LDS chips.
10 // Functional units across Mips chips sets. Based on GCC/Mips backend files.
513 // register. On some Intel chips, different parts of a GPR can be stored in
149 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
228 low-precision inference chips, and arbitrary precision integers are useful
764 // Note that cyclone does not fuse AES instructions, but newer apple chips do