Home
last modified time | relevance | path

Searched refs:RegUnitSetOrder (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.h599 std::vector<unsigned> RegUnitSetOrder; variable
779 return RegUnitSetOrder[Order]; in getRegSetIDAt()
783 return RegUnitSets[RegUnitSetOrder[Order]]; in getRegSetAt()
H A DCodeGenRegisters.cpp2173 RegUnitSetOrder.reserve(RegUnitSets.size()); in computeDerivedInfo()
2175 RegUnitSetOrder.push_back(Idx); in computeDerivedInfo()
2177 llvm::stable_sort(RegUnitSetOrder, [this](unsigned ID1, unsigned ID2) { in computeDerivedInfo()
2182 RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx; in computeDerivedInfo()